Light-emitting display device

Abstract

A light emitting display device includes: a substrate including a display area in which a plurality of sub-pixels are disposed; a light emitting diode in a sub-pixel among the plurality of sub-pixels, the light emitting diode including an anode electrode, a light emitting layer on the anode electrode, and a cathode electrode on the light emitting layer; a photoresistor disposed in the sub-pixel and positioned under the light emitting diode; a sensing transistor having a drain electrode connected to the photoresistor and a gate electrode connected to the gate line; and a sense line connected to a source electrode of the sense transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0117542, filed in Korea on August 30, 2024, which is incorporated herein by reference in its entirety for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure relates to light-emitting display devices. Background Technology

[0004] Recently, flat panel display devices with excellent characteristics such as thinness, lightweight and low power consumption have been widely developed and applied in various fields.

[0005] In flat panel display devices, light-emitting display devices equipped with light-emitting elements such as light-emitting diodes emit light when charge is injected into the light-emitting layer formed between the anode and cathode, and electrons and holes pair up and then annihilate.

[0006] During or after manufacturing, light-emitting display devices may have dark or bright spots for various reasons, and such light-emitting defects are usually detected by visual inspection. However, there are cases where light-emitting defects are shipped without being detected by visual inspection, and dark spots, in particular, are not easily visible, making defect detection difficult.

[0007] After a display device with unexpected light emission defects is manufactured, shipped, and delivered to a customer, it is difficult to identify information about the defective condition of the product.

[0008] However, from the perspective of product development and quality improvement, defect information is very important, and information about the condition of the product after it has been delivered to the customer is needed. Summary of the Invention

[0009] The advantage of this disclosure is that it provides a light-emitting display device that can easily identify the light-emitting state of a light-emitting diode and effectively detect light-emitting defects.

[0010] Additional features and advantages of this disclosure will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of this disclosure. These and other advantages of this disclosure will be realized and obtained through the written description of this disclosure and the claims, as well as the structures particularly pointed out in the accompanying drawings.

[0011] To achieve these and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a light emitting display apparatus includes a substrate including a display area in which a plurality of sub-pixels are disposed; a light emitting diode in a sub-pixel among the plurality of sub-pixels, the light emitting diode including an anode electrode, a light emitting layer on the anode electrode, and a cathode electrode on the light emitting layer; a photoresistor disposed in the sub-pixel and positioned below the light emitting diode; a sensing transistor having a drain electrode connected to the photoresistor and a gate electrode connected to a gate line; and a sensing line connected to a source electrode of the sensing transistor.

[0012] In another aspect, a light emitting display apparatus includes a substrate including a display area in which a plurality of sub-pixels are disposed; a plurality of light emitting diodes each disposed in a respective sub-pixel among the plurality of sub-pixels and including an anode electrode, a light emitting layer on the anode electrode, and a cathode electrode on the light emitting layer; a plurality of photoresistors each overlapping a light emitting area of the respective sub-pixel and positioned in a light emitting direction of the light emitting diode disposed in the respective sub-pixel; a sensing line receiving light sensing signals respectively generated by the plurality of photoresistors; and a plurality of sensing transistors each connecting a respective photoresistor among the plurality of photoresistors to the sensing line, wherein the light sensing signals for the plurality of sub-pixels are sequentially output to the sensing line in units of row lines by the plurality of sensing transistors.

[0013] In yet another aspect, a light emitting display apparatus includes a display area and a non-display area, in the display area, a plurality of sub-pixels arranged along a plurality of row lines and a plurality of column lines, each sub-pixel among the plurality of sub-pixels including a first transistor; a light emitting diode; a driving transistor having a first electrode connected to a high potential voltage power line, a second electrode connected to an anode of the light emitting diode, and a gate electrode coupled to the first transistor; a second transistor coupled to the second electrode of the driving transistor; and a photoresistor connected to the high potential voltage power line.

[0014] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings:

[0016] Figure 1is a view schematically showing a light emitting display device according to an embodiment of the present disclosure;

[0017] Figure 2 is a view schematically showing a circuit structure of a sub-pixel of a light emitting display device according to an embodiment of the present disclosure;

[0018] Figure 3 is a view showing a light sensing operation when a display panel is driven to emit light according to an embodiment of the present disclosure;

[0019] Figure 4 is a view showing a light sensing operation when a display panel is driven to emit light according to an embodiment of the present disclosure; Figure 3 is a waveform chart of a gate signal and a light sensing signal when a display panel is driven to emit light according to an embodiment of the present disclosure;

[0020] Figure 5 is a view showing a light sensing signal detected when a sub-pixel arranged in a column line of a display panel normally emits light according to an embodiment of the present disclosure;

[0021] Figure 6 is a view showing a light sensing signal detected when one of the sub-pixels arranged in a column line of a display panel has a dark spot defect according to an embodiment of the present disclosure;

[0022] Figure 7 is a view showing a light sensing signal detected when one of the sub-pixels arranged in a column line of a display panel has a bright spot defect according to an embodiment of the present disclosure;

[0023] Figure 8 is a plan view schematically showing a sub-pixel of a light emitting display device according to an embodiment of the present disclosure;

[0024] Figure 9 is a cross-sectional view taken along line IX-IX’ of Figure 8 ;

[0025] Figure 10 is a cross-sectional view taken along line X-X’ of Figure 8 ; and

[0026] Figure 11 is a plan view schematically showing a case where a photoresistor of a display panel is formed in a maze structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only these embodiments make this disclosure complete. This disclosure is provided to fully inform those skilled in the art of this disclosure of its scope, and this disclosure may be defined by the scope of the claims.

[0028] The shapes, dimensions, scales, angles, numbers, etc., disclosed in the accompanying drawings used to illustrate embodiments of this disclosure are illustrative and are not limited to the matters shown. Throughout the specification, the same reference numerals refer to the same parts.

[0029] Furthermore, in describing this disclosure, if it is determined that a detailed description of the relevant known technology unnecessarily obscures the subject matter of this disclosure, its detailed description may be omitted. When words such as "comprising," "including," "having," or "containing" are used in this disclosure, additional parts may be added unless "only" is used. When a component is referred to as a singular, the plural case is included unless specifically described.

[0030] When interpreting a component, it is interpreted as including the allowance range, even if there is no separate explicit description.

[0031] When describing positional relationships, for example, when the positional relationship between two parts is described as "on," "above," "above," "below," "next to," "under," etc., one or more other parts may be located between the two parts, unless "exactly" or "directly" is used.

[0032] When describing time relationships, such as when time priorities are described as "after", "following", "before", etc., discontinuous situations can be included unless "immediately" or "right away" is used.

[0033] In describing the components of this disclosure, terms such as first, second, etc., may be used. These terms are used only to distinguish these components from other components, and the nature, order, or number of components is not limited by these terms.

[0034] The various features of the various embodiments of this disclosure may be connected or combined with each other in part or in whole, and may be interlocked and driven in different technical ways, and the various embodiments may be implemented independently of each other or together in a related relationship.

[0035] In the following description, embodiments of the present disclosure are illustrated with reference to the accompanying drawings. Furthermore, in the following embodiments, the same or similar reference numerals are assigned to the same or similar components, and their detailed descriptions may be omitted.

[0036] Figure 1 This is a schematic view illustrating a light-emitting display device according to an embodiment of the present disclosure. Figure 2 This is a schematic view illustrating the circuit structure of a sub-pixel of a light-emitting display device according to an embodiment of the present disclosure.

[0037] Before a detailed description, the light-emitting display device 10 according to embodiments of this disclosure may include all types of display devices that include self-emissive elements such as light-emitting diodes (LEDs) to display images.

[0038] In this embodiment, for ease of explanation, an organic light-emitting display device is used as an example of the light-emitting display device 10.

[0039] Reference Figure 1 and Figure 2 The light-emitting display device 10 (or its light-emitting display panel) of this embodiment may include a display panel (or light-emitting display panel) 100 defining a display area AA for displaying images and a non-display area NA arranged around the display area AA, as well as a panel driving circuit 400. The non-display area NA does not display images.

[0040] In the display area AA of the display panel 100, multiple sub-pixels SP arranged along multiple row lines (or horizontal lines) and multiple column lines (or vertical lines) can be formed on the substrate 101.

[0041] In addition, multiple gate lines GL extending in the row direction (or horizontal direction or first direction) and multiple data lines DL extending in the column direction (or vertical direction or second direction) can be formed on the substrate 101.

[0042] During normal operation for displaying an image, multiple gate lines GL can be scanned sequentially in units of row lines (or horizontal time intervals) to be applied with gate signals. Additionally, during the scan period when the gate lines GL are applied with their respective gate signals, data signals DI for displaying the image can be applied to each data line DL and input to each sub-pixel SP.

[0043] Such gate signals and data signals DI can be output from the panel driver circuit 400 and provided to the display panel 100.

[0044] Simultaneously, a power line PL can be formed on the substrate 101 to transmit a high-potential voltage (or a first driving voltage) VDD to the sub-pixel SP. A reference line RL can be formed on the substrate 101, which transmits a sensing voltage for compensating the characteristics of the driving transistor Td (e.g., threshold voltage and / or mobility compensation) and also provides a reference voltage to the sub-pixel SP.

[0045] Furthermore, in this embodiment, multiple sensing lines (or light-emitting sensing lines) SL extending along the column direction can be formed on the substrate 101. For example, the sensing lines SL can extend parallel to the data lines DL in each column line.

[0046] As described below, the sensing line SL can transmit a light sensing signal (or light emission sensing signal) SD generated by sensing light emitted from the sub-pixel SP to detect the light emission state (or illumination state) when light is emitted from the light-emitting diode OD arranged in each sub-pixel SP of the corresponding column line. The light sensing signal SD can be provided to the panel driving circuit 400.

[0047] In this regard, each sub-pixel SP can be equipped with a photoresistor PR, which is an optoelectronic element that receives light generated from the corresponding light-emitting diode OD and generates a light sensing signal SD of a magnitude (or value) corresponding to the amount of light received (or the amount of incident light).

[0048] A photoresistor PR can be, for example, a variable resistor formed using photoelectric materials, and its resistance changes due to the photoelectric effect. This photoresistor PR can have the characteristic that its resistance decreases as the amount of received light increases, and its resistance increases as the amount of received light decreases.

[0049] Therefore, the resistance value of the photoresistor PR can change according to the light emission state of the corresponding sub-pixel SP, and the photosensitive signal SD, which is the current flowing through the photoresistor PR, can change according to the change in resistance value.

[0050] Therefore, when the LED OD emits light normally, the current in the normal emission state flows through the photoresistor PR and is generated as the photosensing signal SD. When the LED OD emits abnormal light that is dimmer than its normal emission (or the LED OD emits light at a low emission level), the low current in the corresponding low emission state flows through the photoresistor PR and is generated as the photosensing signal SD. When the LED OD emits abnormal light that is brighter than its normal emission (or the LED OD emits light at a high emission level), the high current in the corresponding high emission state flows through the photoresistor PR and is generated as the photosensing signal SD. When the sub-pixel SP has a defect in a dark spot and is actually in a non-emitting state, no current flows through the photoresistor PR, and therefore the photosensing signal SD can actually be in an off-level state.

[0051] As described above, a light sensing signal SD can be generated and output by sensing the light emission state of a light-emitting diode OD via a photoresistor PR disposed in a sub-pixel SP, and such a light sensing signal SD can be applied to a sensing line SL.

[0052] Therefore, for example, the generated light sensing signal SD from each of the sub-pixels SP arranged in the corresponding column lines can be output sequentially (or continuously) to the sensing line SL in row line units.

[0053] In other words, in each column line, the light sensing signal SD that senses the light emission state of the sub-pixel SP of each row line can be sequentially output to the sensing line SL, and therefore, the light sensing signals SD generated from all the row lines of the corresponding column line can be sequentially applied to the sensing line SL and provided to the panel driving circuit 400.

[0054] In this case, for example, the panel driving circuit 400 can use the input light sensing signal SD to check the light emission state of the sub-pixel SP and identify and detect sub-pixels SP with light emission defects.

[0055] As described above, the photosensing method for checking the luminous state of subpixel SP and detecting luminous defects of subpixel SP using a photoresistor PR is described in more detail below.

[0056] The plurality of subpixels SP arranged in the display panel 100 may include subpixels SP of different colors, which constitute pixels as units for displaying color images. In this regard, the plurality of subpixels SP may include subpixels SP that display a first color, a second color, and a third color respectively, for example, red, green, and blue subpixels SP, but are not limited thereto.

[0057] Each sub-pixel SP may include a light-emitting diode OD, a plurality of transistors for driving the light-emitting diode OD, and at least one capacitor.

[0058] Meanwhile, in this embodiment, for ease of explanation, as shown in the example Figure 2 The sub-pixel SP shown is configured with a 3T1C structure consisting of three transistors T1, T2, and Td, and a capacitor Cst, as an example.

[0059] Reference Figure 2 Describe the subpixel SP. Also, for ease of explanation, Figure 2 Subpixels SP are shown arranged along a column line of the display panel 100. Additionally, as an example, subpixels (SP: SP(1), SP(2), and SP(3)) located in three consecutive rows within the column line are shown, for example, the first row line, the second row line, and the third row line.

[0060] Additionally, in the following description, the terms source electrode and drain electrode of a transistor are used to distinguish the two electrodes connected to the semiconductor layer, and these terms may be used interchangeably in some cases.

[0061] The sub-pixel SP may include a first transistor T1 and a second transistor T2 as switching transistors, a driving transistor Td, a storage capacitor Cst, and a light-emitting diode OD. The first transistor T1 may be a data supply transistor, and the second transistor T2 may be a driving characteristic sensing transistor.

[0062] The first transistor T1, the second transistor T2, the driving transistor Td, and the storage capacitor Cst can constitute a pixel driving circuit for driving the light-emitting diode OD during image display operation. In other words, the first transistor T1, the second transistor T2, the driving transistor Td, and the storage capacitor Cst can form a pixel driving circuit for performing normal driving to display an image through the light-emitting display device 10.

[0063] Furthermore, in this embodiment, as described above, a photoresistor PR can be formed that senses the light generated from the light-emitting diode OD in each sub-pixel SP and generates a light sensing signal SD as a current of magnitude corresponding to the amount of light received.

[0064] A photoresistor PR can be positioned in the light emission (or light output) direction of the light-emitting diode OD to receive light generated from the OD. For example, when the OD is a bottom-emitting type, the photoresistor PR can be located below the OD, and when the OD is a top-emitting type, the photoresistor PR can be located above the OD. In this embodiment, a bottom-emitting OD is used as an example, and therefore the photoresistor PR can be formed below the OD. More specifically, the photoresistor PR can be positioned below the OD, corresponding to (or overlapping with) the light-emitting area of ​​the sub-pixel SP.

[0065] The photoresistor PR can be formed of, for example, optoelectronic materials and has the characteristic that its resistance changes due to the photoelectric effect. In this respect, for example, when the sub-pixel SP has a dark spot defect and is therefore in a non-emissive state due to the dark spot defect, the photoresistor PR changes to a very high resistance value, so that virtually no current flows. When the sub-pixel SP is in a normal emissive state, the photoresistor PR has a corresponding normal resistance value, allowing normal current to flow. When the sub-pixel SP has a bright spot defect and is therefore in a high emissive state, the photoresistor PR changes to a very low resistance value, allowing a high current, higher than the normal current, to flow.

[0066] As described above, in this embodiment, a photoresistor PR can be formed inside the sub-pixel SP. The photoresistor PR can sense the light emission state of the sub-pixel SP and generate a light sensing signal SD for determining whether the sub-pixel SP is emitting light normally or abnormally.

[0067] Additionally, a sensing transistor Ts can be formed, which is a switching transistor connected between the photoresistor PR of each sub-pixel SP and the sensing line SL, and switches the output of the photoresistor PR to be on / off.

[0068] For example, the sensing transistor Ts can operate when the sub-pixel SP is normally driven to display an image.

[0069] For example, a sensing transistor Ts can be driven such that its on-state (or scanning) section overlaps with the emission section of the sub-pixel SP where the photoresistor PR connected to the sensing transistor Ts is located.

[0070] In this respect, sensing transistors Ts can be arranged in each column line, and the sensing transistors Ts are respectively connected to the sub-pixels SP arranged in the row lines of that column line. These sensing transistors Ts (as well as the first transistor T1 and the second transistor T2) can be sequentially scanned and driven in one direction, for example, from the top row line to the bottom row line. Therefore, in each column line, the photoresistor PR and the sensing line SL can be sequentially connected on a row line basis.

[0071] In this embodiment, the sensing transistor Ts can be disposed in a sub-pixel SP located further back (or lower) than the row line in which the photoresistor PR connected to the sensing transistor Ts is disposed. In other words, the sensing transistor Ts can be connected to the photoresistor PR disposed in a sub-pixel SP located further forward (or higher) than the row line in which the sensing transistor Ts is disposed.

[0072] In this regard, refer to Figure 2 For example, a photoresistor PR disposed in a sub-pixel SP(1) of the first row can be connected to a sensing transistor Ts disposed in a sub-pixel SP(2) of the second row. Similarly, a photoresistor PR disposed in a sub-pixel SP(2) of the second row can be connected to a sensing transistor Ts disposed in a sub-pixel SP(3) of the third row. In this way, a photoresistor PR disposed in each row can be connected to a sensing transistor Ts disposed in the next row.

[0073] The electrical connections of the components arranged in the sub-pixel SP will be described in more detail.

[0074] The first transistor T1 can be connected to the corresponding gate line GL and data line DL. In this respect, the drain electrode (or source electrode) of the first transistor T1 can be connected to the data line DL, and the gate electrode of the first transistor T1 can be connected to the gate line GL.

[0075] The driving transistor Td may have a gate electrode connected to the source electrode of the first transistor T1, a drain electrode (or source electrode) connected to the power line PL to receive a high potential voltage VDD, and a source electrode (or drain electrode) connected to the anode electrode of the light-emitting diode OD.

[0076] The second transistor T2 can be connected to the corresponding gate line GL and reference line RL. In this respect, the drain electrode (or source electrode) of the second transistor T2 can be connected to the reference line RL, the gate electrode of the second transistor T2 can be connected to the gate line GL, and the source electrode (or drain electrode) of the second transistor T2 can be connected to node N between the driving transistor Td and the light-emitting diode OD. In other words, the source electrode of the second transistor T2 can be connected to the source electrode of the driving transistor Td and the anode electrode of the light-emitting diode OD.

[0077] Therefore, in this embodiment, the example is taken where the second transistor T2 and the first transistor T1 in the sub-pixel SP are connected to the same gate line GL and receive the same gate signal. As another example, the second transistor T2 can be configured to be connected to a different gate line GL than the gate line GL connected to the first transistor T1.

[0078] The cathode of a light-emitting diode (LED) OD can receive a low-potential voltage (or a second driving voltage) VSS. The low-potential voltage VSS is a voltage lower than the high-potential voltage VDD and may include the ground voltage.

[0079] The storage capacitor Cst can be connected between the gate electrode and the source electrode of the driving transistor Td.

[0080] With the above configuration, when operating in the display mode for displaying images, when a gate signal is applied through the gate line GL, the first transistor T1 can be turned on and the data signal DI can be input to the sub-pixel SP, so that the data signal DI can be applied to the gate electrode of the driving transistor Td. At this time, the second transistor T2 can be turned on, and a reference voltage can be applied to the source electrode of the driving transistor Td. Therefore, the data signal DI and the reference voltage can be applied to the two electrodes of the storage capacitor Cst, so that the data signal DI can be stored in the storage capacitor Cst.

[0081] Then, when the gate signal is not applied to the gate line GL and is in the off state, the first transistor T1 and the second transistor T2 can be turned off, the driving transistor Td can be turned on, and the emission current (or driving current) corresponding to the applied data signal DI can flow to the light-emitting diode OD through the driving transistor Td. Therefore, light corresponding to the emission current during the emission segment can be generated and output from the light-emitting diode OD.

[0082] Simultaneously, when operating in compensation mode to compensate the driving transistor Td, a sensed data signal can be applied to the sub-pixel SP, and a sensed voltage can be provided to the reference line RL via the second transistor T2. Based on the sensed voltage, the data signal DI used for image display can be compensated, and the compensated data signal DI can be applied to the sub-pixel SP to compensate the driving transistor Td.

[0083] The photoresistor PR and sensing transistor Ts used to sense the emission state of sub-pixel SP are described.

[0084] The photoresistor PR can be configured to connect, for example, a power line PL and a sensing transistor Ts arranged in a sub-pixel (SP) of the next row.

[0085] In this respect, the photoresistor PR can be connected to the power line PL at one end (or the first end or the input end) and receive a high potential voltage VDD. The photoresistor PR can be connected to the drain electrode (or source electrode) of the sensing transistor Ts at the other end (or the second end or the output end).

[0086] Additionally, the sensing transistor Ts can be configured to connect, for example, a photoresistor PR arranged in a sub-pixel SP in the previous row and a sensing line SL.

[0087] In this respect, the sensing transistor Ts can have a source electrode (or drain electrode) connected to the sensing line SL.

[0088] Furthermore, the gate electrode of the sensing transistor Ts can be connected to, for example, a gate line GL arranged in the corresponding row line. Therefore, the sensing transistor Ts can be connected to the gate line GL to which the first transistor T1 of the corresponding sub-pixel SP is connected, and can receive the same gate signal as the first transistor T1.

[0089] As another example, the sensing transistor Ts can be configured to be connected to a gate line GL (or sensing gate line) that is different from the gate line to which the first transistor T1 is connected, and can receive different gate signals.

[0090] When the sensing transistor Ts is connected to the gate line GL and is driven, during the on-phase of the sensing transistor Ts (i.e., the scanning phase of the gate line GL), the photoresistor PR of the sub-pixel SP of the previous row connected to the sensing transistor Ts and the sensing line SL can be electrically connected through the sensing transistor Ts.

[0091] Therefore, when the photoresistor PR and the sensing line SL are connected through the sensing transistor Ts, the light sensing signal SD flowing through the photoresistor PR can be transmitted to the sensing line SL through the sensing transistor Ts.

[0092] For example, when the sub-pixel SP(1) of the first row line is scanned in the corresponding horizontal time period and the gate signal is applied to the gate line GL(1) and the data signal DI is input, the light-emitting diode OD can operate during the emission segment of the first row line to generate light.

[0093] Therefore, during the emission segment of the first row, light can be sensed by the photoresistor PR in the corresponding sub-pixel SP(1) to generate a light sensing signal SD.

[0094] Simultaneously, when the sub-pixel SP(2) of the second row line is scanned in the corresponding horizontal period and the gate signal is applied to the gate line GL(2), the sensing transistor Ts can be turned on. Therefore, during the scanning period of the second row line, the photoresistor PR of the sub-pixel SP(1) of the first row line connected to the sensing transistor Ts and the sensing line SL can be electrically connected to each other through the sensing transistor Ts.

[0095] Therefore, when the sensing transistor Ts is turned on, the photosensitive signal SD detected by the photoresistor PR of the sub-pixel SP(1) of the first row can be output to the sensing line SL through the sensing transistor Ts.

[0096] Similarly, when the sensing transistor Ts of the third row is turned on, the photosensitive signal SD detected by the photoresistor PR of the sub-pixel SP(2) of the second row can be output to the sensing line SL through the sensing transistor Ts.

[0097] As described above, during the scanning segment of a row line where a sensing transistor Ts is provided, the light sensing signal SD generated by the photoresistor PR of the sub-pixel SP of the previous row line can be output to the sensing line SL through the sensing transistor Ts.

[0098] Therefore, when the row lines arranged in each column line are driven sequentially, the light sensing signal SD that senses the light emission state of the sub-pixel SP on a row line basis can be sequentially output to the sensing line SL, so that the light sensing signal SD generated in all the row lines arranged in each column line can be provided to the sensing line SL.

[0099] Further reference Figure 3 and Figure 4 The light-emitting operation of the light-emitting diode OD and the light-sensing operation of the photoresistor PR and the sensing transistor Ts are described in more detail. Figure 3 This is a view illustrating the light sensing operation when the display panel is driven to emit light according to an embodiment of the present disclosure, and Figure 4 It shows when Figure 3 The waveforms of the gate signal and the light sensing signal when the display panel is driven to emit light.

[0100] Before a detailed description, in this embodiment, for ease of explanation, the first row line to the third row line, the gate signals (Vg: Vg(1), Vg(2), Vg(3)) driving the first row line to the third row line, and the light sensing signals (SD: SD(1), SD(2), SD(3)) sensed from the first row line to the third row line are shown by way of example.

[0101] Furthermore, the example illustrates a scenario where gate signals Vg are sequentially applied to row lines, and the on-state segments of gate signals Vg applied to adjacent row lines overlap. In other words, the example illustrates a scenario where the on-state segment of the gate signal Vg of the current row line overlaps with the on-state segment of the gate signal Vg of the next row line.

[0102] Combination Figure 1 and Figure 2 For reference Figure 3 and Figure 4 The first row line is scanned such that the first gate signal Vg(1) can be applied to the first gate line GL(1) during the horizontal period, and the corresponding data signal DI can be input to the sub-pixel SP(1). Therefore, the data signal DI can be provided to the gate electrode of the driving transistor Td and stored in the storage capacitor Cst.

[0103] When the first gate signal Vg(1) becomes off, the driving transistor Td can be turned on during the emission segment, and the emission current Id corresponding to the data signal DI can be generated and provided to the light-emitting diode OD through the driving transistor Td. Therefore, the light-emitting diode OD can generate and output light L corresponding to the emission current Id.

[0104] Furthermore, when the light-emitting diode OD emits light L, the light L can be sensed by the photoresistor PR in the corresponding sub-pixel SP(1), and a corresponding light sensing signal SD can be generated, namely the first light sensing signal SD(1).

[0105] Next, the second row line is scanned so that the second gate signal Vg(2) can be applied to the second gate line GL(2) during the horizontal time period, and the corresponding data signal DI can be input to the sub-pixel SP(2). Therefore, the data signal DI can be provided to the gate electrode of the driving transistor Td and stored in the storage capacitor Cst.

[0106] When the second gate signal Vg(2) becomes off, the driving transistor Td can be turned on during the emission segment, and the emission current Id corresponding to the data signal DI can be generated and provided to the light-emitting diode OD through the driving transistor Td, and thus the light-emitting diode OD can generate and output light L corresponding to the emission current Id.

[0107] Furthermore, when the light-emitting diode OD emits light L, the light L can be sensed by the photoresistor PR in the corresponding sub-pixel SP(2), and a corresponding light sensing signal SD can be generated, namely the second light sensing signal SD(2).

[0108] Meanwhile, during the scan segment when the second gate signal Vg(2) is applied, the sensing transistor Ts disposed in the corresponding sub-pixel SP(2) can be turned on. Therefore, by turning on the sensing transistor Ts, the photoresistor PR of the sub-pixel SP(1) of the first row line connected to the sensing transistor Ts can be electrically connected to the sensing line SL.

[0109] Therefore, the light sensing signal SD(1) generated by the photoresistor PR in the emission section of the sub-pixel SP(1) of the first row line can be output and applied to the sensing line SL through the sensing transistor Ts in the on state set in the sub-pixel SP(2) of the second row line.

[0110] Next, the third row line is scanned so that the third gate signal Vg(3) can be applied to the third gate line GL(3) during the horizontal time period, and the corresponding data signal DI can be input to the sub-pixel SP(3). Therefore, the data signal DI can be provided to the gate electrode of the driving transistor Td and stored in the storage capacitor Cst.

[0111] When the third gate signal Vg(3) becomes off, the driving transistor Td can be turned on during the emission segment, and the emission current Id corresponding to the data signal DI can be generated and provided to the light-emitting diode OD through the driving transistor Td, and thus the light-emitting diode OD can generate and output light L corresponding to the emission current Id.

[0112] Furthermore, when the light-emitting diode OD emits light L, the light L can be sensed by the photoresistor PR in the corresponding sub-pixel SP(3), and a corresponding light sensing signal SD can be generated, namely the third light sensing signal SD(3).

[0113] Meanwhile, during the scan segment when the third gate signal Vg(3) is applied, the sensing transistor Ts disposed in the corresponding sub-pixel SP(3) can be turned on. Therefore, by turning on the sensing transistor Ts, the photoresistor PR of the sub-pixel SP(2) of the second row line connected to the sensing transistor Ts can be electrically connected to the sensing line SL.

[0114] Therefore, the photosensitive signal SD(2) generated by the photoresistor PR in the emission section of the sub-pixel SP(2) of the second row can be output and applied to the sensing line SL through the sensing transistor Ts in the on state of the sub-pixel SP(3) of the third row.

[0115] Similar to the above, the photosensitive signal SD(3) generated by the photoresistor PR in the emission section of the sub-pixel SP(3) of the third row can be output and applied to the sensing line SL through the sensing transistor Ts in the on state of the sub-pixel SP of the fourth row.

[0116] In the manner described above, when the row lines arranged in each column line are driven sequentially during a frame, the light sensing signal SD that senses the luminous state of the sub-pixel SP on a row line basis can be sequentially output to the sensing line SL, so that the light sensing signal SD generated in all the row lines arranged in the column line can be provided to the sensing line SL.

[0117] By checking the state of the light sensing signal SD output to the sensing line SL in the manner described above, the light emission state of each sub-pixel SP can be checked, and sub-pixels SP with light emission defects can be identified and detected.

[0118] This will be further referenced Figures 5 to 7 To describe. Figure 5 This is a view showing a light-sensing signal detected when sub-pixels arranged in the column lines of a display panel emit light normally, according to an embodiment of the present disclosure. Figure 6 This is a view showing a light-sensing signal detected when one of the sub-pixels arranged in the column lines of a display panel has a dark spot defect, according to an embodiment of the present disclosure. Figure 7 This is a view showing a light-sensing signal detected when one of the sub-pixels arranged in the column lines of a display panel has a bright spot defect, according to an embodiment of the present disclosure.

[0119] First, combined Figures 1 to 4 For reference Figure 5 When all the sub-pixels SP arranged in the column lines of the display panel 100 emit light normally, a light sensing signal SD with a normal current level can be generated by the photoresistor PR set in each of the sub-pixels SP and output to the sensing line SL.

[0120] In this case, such as Figure 5 As shown, the light sensing signal SD applied to the sensing line SL during a frame can have a substantially constant normal level. By checking the level of this light sensing signal SD, it can be confirmed that all sub-pixels SP are in a normal luminous state.

[0121] Next, combined Figures 1 to 4 For reference Figure 6 When one of the sub-pixels SP arranged in the column line of the display panel 100 is defective in the dark spot DP and does not emit light abnormally, the current does not flow through the photoresistor PR set in the sub-pixel SP with the dark spot DP, so that the corresponding light sensing signal SD can have a turn-off level.

[0122] In this case, such as Figure 6As shown, the light sensing signal SD applied to the sensing line (SL) during a frame can have an off level state during the sensing segment of the row line where the sub-pixel SP with dark spot DP is located. By checking the level state of the light sensing signal SD, the sub-pixel SP with dark spot DP can be detected.

[0123] Next, combined Figures 1 to 4 For reference Figure 7 When one of the sub-pixels SP arranged in the column lines of the display panel 100 has a defect in the bright spot BP and emits abnormally bright light, an overcurrent higher than normal current flows through the photoresistor PR set in the sub-pixel SP with the bright spot BP, causing the corresponding light sensing signal SD to have an overlevel higher than normal level.

[0124] In this case, such as Figure 7 As shown, the light sensing signal SD applied to the sensing line SL during a frame has an over-level state during the sensing segment of the row line where the sub-pixel SP with the bright spot BP is located. By examining the level state of the light sensing signal SD, the sub-pixel SP with the bright spot BP can be detected.

[0125] Therefore, by checking the state of the light sensing signal SD output to the sensing line SL, the light emission state of each sub-pixel SP can be checked, and sub-pixels SP with light emission defects can be identified and detected.

[0126] As described above, according to this embodiment, a photoresistor PR can be formed to sense the light emission state of the light-emitting diode OD in the sensing sub-pixel SP and generate a corresponding light sensing signal SD, and the light sensing signal SD of the sub-pixel SP can be output to the sensing line SD through the sensing transistor Ts on a row-line basis.

[0127] Therefore, by checking the state of the light sensing signal SD output to the sensing line SL, the light emission state of each sub-pixel SP can be checked, and sub-pixels SP with light emission defects such as dark spots or bright spots can be identified and detected.

[0128] Therefore, the luminous state of a light-emitting diode (OD) can be easily identified, and luminous defects can be effectively detected.

[0129] The following describes an example of the structure of a light-emitting display device for checking the light emission state and detecting light emission defects according to this embodiment.

[0130] Figure 8 This is a schematic plan view of a sub-pixel of a light-emitting display device according to an embodiment of the present disclosure. Figure 9 It is along Figure 8The cross-sectional view is taken from line IX-IX', and the cross-sectional structure of the light-emitting diode, driving transistor and photoresistor of the sub-pixel is shown. Figure 10 It is along Figure 8 The cross-sectional view is taken from line X-X', and the cross-sectional structure of the sensing transistor and photoresistor is shown.

[0131] Before going into detail, for ease of explanation, Figure 8 The image shows sub-pixels (SP: SP(1), SP(2), and SP(3)) located in three consecutive rows (e.g., the first row, the second row, and the third row) in the column line as an example.

[0132] Reference Figures 1 to 7 as well as Figures 8 to 10 On the substrate 101 of the display panel 100 in this embodiment, a first transistor T1 and a second transistor T2 disposed in the driving circuit region of the sub-pixel SP, as well as a driving transistor Td, and a light-emitting diode OD located on transistors T1, T2 and Td and disposed in the light-emitting region, can be formed.

[0133] The light-emitting diode (OD) can be configured, for example, as a bottom-emitting type. In this case, light can pass through the anode electrode AE ​​of the OD and be emitted downwards.

[0134] In each sub-pixel SP, a photoresistor PR can be formed below the light-emitting diode OD and overlapping with the light-emitting area, receiving light emitted from the light-emitting diode OD and outputting it downwards. The photoresistor PR can be formed to have substantially transparent properties to achieve downward emission from the light-emitting diode OD.

[0135] Additionally, a sensing transistor Ts connected between the photoresistor PR and the sensing line SL can be formed on the substrate 101.

[0136] The sensing transistor Ts can be located in the sub-pixel SP of the row line following the row line in which the photoresistor PR connected to the sensing transistor Ts is located. For example, the sensing transistor Ts connected to the photoresistor PR of the sub-pixel SP of the nth row line can be located in the sub-pixel SP of the (n+1)th row line.

[0137] The substrate 101 can be, for example, a glass substrate or a plastic substrate with insulating properties. As another example, the substrate 101 can be a silicon wafer. In this embodiment, for ease of explanation, the case where the substrate 101 is formed of a glass substrate or a plastic substrate is used as an example.

[0138] The first transistor T1 may include a source electrode (or first source electrode) S1, a drain electrode (or first drain electrode) D1, a gate electrode (or first gate electrode) G1, and a semiconductor layer (or first semiconductor layer) SL1.

[0139] The second transistor T2 may include a source electrode (or a second source electrode) S2, a drain electrode (or a second drain electrode) D2, a gate electrode (or a second gate electrode) G2, and a semiconductor layer (or a second semiconductor layer) SL2.

[0140] The driving transistor Td may include a source electrode (or a third source electrode) Sd, a drain electrode (or a third drain electrode) Dd, a gate electrode (or a third gate electrode) Gd, and a semiconductor layer (or a third semiconductor layer) SLd.

[0141] The sensing transistor Ts may include a source electrode (or a fourth source electrode) Ss, a drain electrode (or a fourth drain electrode) Ds, a gate electrode (or a fourth gate electrode) Gs, and a semiconductor layer (or a fourth semiconductor layer) SLs.

[0142] For example, regarding the stacked structure of transistors T1, T2, Td, and Ts, the drain electrode D1 of the first transistor T1 and the source electrode S2 of the second transistor T2 can be formed on the substrate 101, and a buffer layer 105 made of insulating material can be formed on such electrodes D1 and S2. Simultaneously, the data line DL can be formed in the same layer as such electrodes D1 and S2. Furthermore, the first line PL1, which is part of the power line PL, can be formed in the same layer as such electrodes D1 and S2.

[0143] The buffer layer 105 may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), but is not limited thereto.

[0144] On the buffer layer 105, semiconductor layers SL1, SL2, SLd, and SLs can be formed for a first transistor T1, a second transistor T2, a driving transistor Td, and a sensing transistor Ts. Each of such semiconductor layers SL1, SL2, SLd, and SLs may include a channel region in the middle and source and drain regions on both sides thereof.

[0145] Furthermore, the photoresistor PR can be formed from the same material as the semiconductor layers SL1, SL2, SLd and SLs and in the same layer as the semiconductor layers SL1, SL2, SLd and SLs, but is not limited thereto.

[0146] The semiconductor layers SL1, SL2, SLd, and SLs, as well as the photoresistor PR, can be formed from, for example, polycrystalline silicon, amorphous silicon, or oxide semiconductors. In this embodiment, an example is taken where the semiconductor layers SL1, SL2, SLd, and SLs, as well as the photoresistor PR, are formed from oxide semiconductors such as IGZO.

[0147] Oxide semiconductors are photoelectric materials that generate electron-hole pairs through the photoelectric effect when exposed to light. Therefore, since the photoresistor PR is formed of oxide semiconductor, it can receive light generated from the light-emitting diode OD and generate a corresponding current, i.e., the photosensing signal SD.

[0148] A gate insulating layer 110 may be formed on the semiconductor layers SL1, SL2, SLd and SLs and the photoresistor PR. The gate insulating layer 110 may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), but is not limited thereto.

[0149] On the gate insulating layer 110, the gate electrodes G1, G2, Gd, and Gs of the first transistor T1, the second transistor T2, the driving transistor Td, and the sensing transistor Ts can be formed. Furthermore, the source electrode S1 of the first transistor T1, the drain electrode D2 of the second transistor T2, and the source electrode Sd and drain electrode Dd of the driving transistor Td can be formed in the same layer as the gate electrodes G1, G2, Gd, and Gs. Simultaneously, the gate line GL can be formed in the same layer as the gate electrodes G1, G2, Gd, and Gs. Additionally, the reference line RL and the second line PL2, which is part of the power line PL, can be formed in the same layer as the gate electrodes G1, G2, Gd, and Gs.

[0150] The source electrode S1 of the first transistor T1 and the gate electrode Gd of the driving transistor Td can be formed integrally.

[0151] The power line PL may include a first line PL1 and a second line PL2 connected to each other, and the first line PL1 may be formed to cross the gate line GL. The second line PL2 may contact the first line PL1 below it, for example, through a contact hole CHp connected to the first line PL1, and such a contact hole CHp may be formed in the buffer layer 105 and the gate insulating layer 110.

[0152] In addition, the drain electrode D1 of the first transistor T1 can, for example, contact the drain region of the corresponding semiconductor layer SL1 through the contact hole CHd1 formed in the buffer layer 105.

[0153] The source electrode S2 of the second transistor T2 can, for example, contact the source region of the corresponding semiconductor layer SL2 through a contact hole CHs2 formed in the buffer layer 105. The drain electrode D2 of the second transistor T2 can, for example, contact the drain region of the corresponding semiconductor layer SL2 through a contact hole CHd2 formed in the gate insulating layer 115.

[0154] The source electrode S1 of the first transistor T1 can, for example, contact the source region of the corresponding semiconductor layer SL1 through a contact hole CHs1 formed in the gate insulating layer 110. The source electrode Sd and drain electrode Dd of the driving transistor Td can, for example, contact the source region and drain region of the corresponding semiconductor layer SLd through respective contact holes CHsd and CHdd formed in the gate insulating layer 110.

[0155] The drain electrode Dd of the driving transistor Td can be integrally formed with, for example, the second line PL2 of the power line PL.

[0156] Meanwhile, the source electrode Ss of the sensing transistor Ts can, for example, contact the source region of the corresponding semiconductor layer SLs through a contact hole CHss formed in the buffer layer 105 or the gate insulating layer 110.

[0157] In this regard, this embodiment takes the case where the source electrode Ss of the sensing transistor Ts is formed in different layers according to the row lines as an example. For example, the source electrode Ss of the sensing transistor Ts located in the second row line can be formed in the same layer as the data line DL, and in this case, the source electrode Ss can contact the corresponding semiconductor layer SLs through the contact hole CHss formed in the buffer layer 105. Alternatively, the source electrode Ss of the sensing transistor Ts located in the third row line can be formed in the same layer as the gate line GL, and in this case, the source electrode Ss can contact the corresponding semiconductor layer SLs through the contact hole CHss formed in the gate insulating layer 110. Therefore, the stacking positions of the source electrodes Ts of the sensing transistor Ts can alternate along the column lines. Alternatively, the source electrodes Ss of the sensing transistor Ts arranged along the column lines can be formed in the same layer.

[0158] In this embodiment, an example is taken where the planar position of the sensing transistor Ts varies depending on the row line. (Refer to...) Figure 8 For example, the sensing transistors Ts in the second row can be located to the right of the corresponding sub-pixel (SP) where the power line PL is arranged, and the sensing transistors Ts in the third row can be located to the left of the corresponding sub-pixel SP where the data line DL is arranged. Therefore, the positions of the sensing transistors Ts can alternate along the column lines. Alternatively, the sensing transistors Ts arranged in the column lines can be positioned in the same direction.

[0159] Meanwhile, for example, the connection pattern CON connecting the source electrode Ss of the sensing transistor Ts and the sensing line SL can be formed in the same layer as the gate electrodes G1, G2, Gd and Gs.

[0160] For example, the connection pattern CON of the source electrode Ss of the sensing transistor Ts in the second row line can have one end that contacts the sensing line SL through a contact hole CHo1 formed in the gate insulating layer 110 and the buffer layer 105, and the other end that contacts the source electrode Ss of the sensing transistor Ts through a contact hole CHo2 formed in the gate insulating layer 110 and the buffer layer 105. Additionally, the connection pattern CON of the source electrode Ss of the sensing transistor Ts in the third row line can be integrally formed with the source electrode Ss, and can have one end that contacts the sensing line SL through a contact hole CHo1 formed in the gate insulating layer 110 and the buffer layer 105.

[0161] Meanwhile, for example, the first contact pattern CP1 and the second contact pattern CP2 can be formed in the same layer as the gate electrodes G1, G2, Gd and Gs.

[0162] The first contact pattern CP1 can connect, for example, a power line PL (e.g., the first line PL1 of the power line PL) and a photoresistor PR, and thus a high potential voltage VDD can be input from the power line PL to the photoresistor PR. One end of the first contact pattern CP1 can contact the first line PL1 of the power line PL, for example, through a contact hole CHc1 formed in the buffer layer 105 and the gate insulating layer 110, and the other end of the first contact pattern CP1 can contact the photoresistor PR, for example, through a contact hole CHc2 formed in the gate insulating layer 110.

[0163] The second contact pattern CP2 can, for example, contact the photoresistor PR and the connecting line CL, and thus can output the light sensing signal SD generated in the photoresistor PR to the connecting line CL. One end of the second contact pattern CP2 can, for example, contact the photoresistor PR through a contact hole CHc3 formed in the gate insulating layer 110, and the other end of the second contact pattern CP2 can, for example, contact the connecting line CL through a contact hole CHc4 formed in the passivation layer 115 and the planarization layer 120 on the second contact pattern CP2.

[0164] At least one insulating layer may be formed on the transistors T1, T2, Td, and Ts configured as described above. In this embodiment, a passivation layer 115 and a planarization layer 120 may be formed on the transistors T1, T2, Td, and Ts as an example.

[0165] The passivation layer 115 can be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) or an organic insulating material such as photoacrylic acid or benzocyclobutene. The planarization layer 120 can be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) or an organic insulating material such as photoacrylic acid or benzocyclobutene.

[0166] On the planarization layer 120, an anode electrode AE ​​can be formed for each sub-pixel SP. When using a bottom-emitting light-emitting display device 10, the anode electrode AE ​​may include a transparent conductive layer formed of a transparent conductive material such as ITO or IZO.

[0167] The anode electrode AE ​​can contact the source electrode Sd of the driving transistor Td, for example, through a contact hole Cha formed in the planarization layer 120 and the passivation layer 115. Furthermore, this contact hole Cha can penetrate the source electrode Sd of the driving transistor Td and be formed in the gate insulating layer 110 and the buffer layer 105, and through the contact hole Cha formed in this way, the anode electrode AE ​​can contact the source electrode Sd of the driving transistor Td and the source electrode S2 of the second transistor T2.

[0168] Meanwhile, the connecting line CL that connects the photoresistor PR and the corresponding sensing transistor Ts can, for example, be formed in the same layer as the anode electrode AE.

[0169] In this respect, one end (or the first end) of the connecting line CL can be connected to the second contact pattern CP2 connected to the photoresistor PR, and the other end (or the second end) of the connecting line CL can be connected to the drain electrode Ds of the sensing transistor Ts. For example, as described above, one end of the connecting line CL can contact the second contact pattern CP2 through the contact hole CHc4 formed in the planarization layer 120 and the passivation layer 115. In addition, the drain electrode Ds of the sensing transistor Ts can be integrally formed with the connecting line CL, and in this case, the drain electrode Ds can contact the drain region of the corresponding semiconductor layer SLs, for example, through the contact hole CHds formed in the planarization layer 120, the passivation layer 115 and the gate insulating layer 110.

[0170] In this embodiment, similar to the position of the sensing transistor Ts described above, an example is taken where the planar position of the connecting line CL is formed differently depending on the row line. In this regard, refer to... Figure 8For example, the connection line CL connecting to the sensing transistor Ts in the second row can be positioned to overlap with the power line PL on the right side, and the connection line CL connecting to the sensing transistor Ts in the third row can be positioned to the left of the data line DL. Therefore, the positions of the connection lines CL connecting to the sensing transistor Ts along the column lines can be alternated. Alternatively, the connection lines CL arranged along the column lines can be positioned in the same direction.

[0171] On the planarization layer 120 and the anode electrode AE, a dam 130 may be formed along the boundary of each sub-pixel SP. The dam 130 may include an opening OP that exposes the anode electrode AE, and the dam 130 may cover the edge of the anode electrode AE. The opening OP of the dam 130 may define the light-emitting area of ​​the sub-pixel SP. In this case, the area in the sub-pixel SP where the dam 130 is formed can be considered a non-light-emitting area.

[0172] A light-emitting layer EL can be formed on the anode electrode AE. The light-emitting layer EL may include a light-emitting material (e.g., an organic light-emitting material) that generates colored light or emits white light for its sub-pixels SP.

[0173] A cathode electrode CE can be formed on the light-emitting layer EL. For example, the cathode electrode CE can be formed continuously across the entire display area AA to correspond to all sub-pixels SP.

[0174] When using a bottom-emitting light-emitting display device 10, the cathode electrode CE may include, for example, a reflective layer formed of a metal with high reflectivity, such as Ag.

[0175] As described above, in each sub-pixel SP, a light-emitting diode OD consisting of an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE can be formed in the light-emitting area.

[0176] In the structure described above, when the light-emitting diode OD of the sub-pixel SP emits light, the corresponding photoresistor PR can receive the light and generate a light sensing signal SD corresponding to the amount of light received. The light sensing signal SD can be output to the sensing line SL through the sensing transistor Ts connected to the photoresistor PR.

[0177] Meanwhile, since the photoresistor PR in this embodiment is positioned in the light-emitting direction corresponding to the light-emitting diode OD, the photoresistor PR can be formed into a labyrinth structure (or mesh structure) to ensure sufficient light output by reducing light loss caused by the photoresistor PR. This will be further referred to... Figure 11 Describe it. Figure 11 This is a schematic plan view illustrating a case where the photoresistors of a display panel are formed into a maze structure according to an embodiment of the present disclosure.

[0178] Reference Figure 11 A photoresistor PR formed from optoelectronic materials can be formed into an irregularly shaped labyrinth structure. For example, when viewed in a plane, the photoresistor PR can be composed of multiple irregularly shaped rather than linear grooves (or labyrinth grooves) GR and partition walls SW surrounding the multiple grooves GR.

[0179] In this regard, the separator SW formed of optoelectronic material can be used essentially as a photoresistor PR, and can have a substantially continuous and integral connection within the photoresistor PR in order to transmit the current generated by the photoelectric effect.

[0180] Additionally, the multiple grooves GR defined by the partition wall SW can essentially serve as openings, for example, exposing the buffer layer 105, which is formed beneath it. The grooves GR can be arranged dispersedly within the photoresistor PR, and more preferably, the grooves GR can be irregularly dispersed.

[0181] Furthermore, the multiple slots GR can have irregular shapes, and the shapes of the multiple slots GR can be different from each other. The area occupied by the multiple slots GR of the photoresistor (PR) can, for example, be greater than 0% and less than 50% of the total area of ​​the photoresistor PR, but is not limited thereto.

[0182] Therefore, the photoresistor PR can have an irregularly shaped labyrinth structure with grooves GR dispersed within it, which reduces the loss of light passing through the photoresistor PR. Furthermore, the irregular shape of the photoresistor GR can produce a scattering effect on the light passing through it, thus improving optical efficiency.

[0183] As described above, according to the embodiments of the present disclosure, a photoresistor can be formed to sense the light emission state of the light-emitting diode in the sensing sub-pixel and generate a corresponding light sensing signal, and the light sensing signal generated in this way can be output to the sensing line in row line units through the sensing transistor.

[0184] Therefore, by checking the state of the light sensing signal output to the sensing line, the light emission state of each sub-pixel can be checked, and sub-pixels with light emission defects such as dark spots or bright spots can be identified and detected.

[0185] Therefore, the luminous state of a light-emitting diode can be easily identified, and luminous defects can be effectively detected.

[0186] Because the luminous state of LEDs can be easily identified in this way, luminous defect information can be identified not only by the manufacturer but also after delivery to the customer, and can be effectively used for product development and quality improvement.

[0187] It will be apparent to those skilled in the art that various modifications and variations may be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover such modifications and variations, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display device comprising: a substrate including a display region in which a plurality of subpixels are provided; a light-emitting diode in a subpixel among the plurality of subpixels, the light-emitting diode including an anode electrode, a light-emitting layer over the anode electrode, and a cathode electrode over the light-emitting layer; a photoresistor provided in the subpixel and positioned below the light-emitting diode; a sensing transistor having a drain electrode connected to the photoresistor and a gate electrode connected to a gate line; and a sensing line connected to a source electrode of the sensing transistor. The photoresistor includes a photoelectric material.

2. The light-emitting display device according to claim 1, wherein The photoelectric material is an oxide semiconductor.

3. The light-emitting display device according to claim 2, wherein The sensing transistor is provided in another subpixel in a next line after a line of the subpixel among the plurality of subpixels in which the photoresistor is provided, and the sensing transistor is connected to a gate line of the next line.

4. The light-emitting display device according to claim 1, wherein The photoresistor is connected to a power line that transmits a high potential voltage.

5. The light-emitting display device according to claim 1, wherein 6. The light-emitting display device according to claim 5, further comprising a connection line connecting the photoresistor to the sensing transistor, the connection line being formed in the same layer as the anode electrode. wherein 7. The light-emitting display device according to claim 6, further comprising a first contact pattern and a second contact pattern formed in the same layer as the gate line, the first contact pattern being in contact with the power line and the photoresistor, and the second contact pattern being in contact with the connection line and the photoresistor. wherein Semiconductor layers of the photoresistor and the sensing transistor are formed of an oxide semiconductor in the same layer.

8. The light-emitting display device according to claim 1, wherein The photoresistor has an irregularly shaped labyrinth structure.

9. The light-emitting display device according to claim 1, wherein The photoresistor includes a plurality of grooves having an irregular shape and arranged in a dispersed manner within the photoresistor.

10. The light-emitting display device according to claim 9, wherein An area occupied by the plurality of grooves is greater than 0% and less than 50% of a total area of the photoresistor.

11. The light-emitting display device according to claim 10, wherein 12. A light-emitting display device comprising: a substrate including a display region in which a plurality of subpixels are provided; a plurality of light-emitting diodes each provided in a respective subpixel among the plurality of subpixels and including an anode electrode, a light-emitting layer over the anode electrode, and a cathode electrode over the light-emitting layer; a plurality of photoresistors each overlapping with a light-emitting region of the respective subpixel and positioned in a light-emitting direction of a light-emitting diode provided in the respective subpixel; a sensing line that receives light-sensing signals respectively generated by the plurality of photoresistors; and a plurality of sensing transistors each connecting a respective photoresistor among the plurality of photoresistors to the sensing line, wherein light-sensing signals for the plurality of subpixels are sequentially output to the sensing line in units of a line by the plurality of sensing transistors. The plurality of photoresistors include an oxide semiconductor. The plurality of photoresistors receive a high potential voltage.

13. The light-emitting display device according to claim 12, wherein ​ 14. The light-emitting display device according to claim 12, wherein ​ 15. The light-emitting display device according to claim 12, wherein Each of the plurality of photoresistors includes a plurality of slots having an irregular shape and arranged in a dispersed manner within the photoresistor.

16. The light-emitting display device according to claim 12, wherein Each sensing transistor is disposed in a sub-pixel of a next row line after a row line of a sub-pixel in which the corresponding photoresistor is disposed, and is connected to a gate line of the next row line.

17. A light emitting display device comprising a display area in which a plurality of sub-pixels arranged along a plurality of row lines and a plurality of column lines are disposed, each of the plurality of sub-pixels comprising: a first transistor; a light emitting diode; a drive transistor having a first electrode connected to a high potential voltage power line, a second electrode connected to an anode of the light emitting diode, and a gate electrode coupled to the first transistor; a second transistor coupled to the second electrode of the drive transistor; and a photoresistor connected to the high potential voltage power line.

18. The light emitting display device of claim 17, further comprising a plurality of sensing transistors each disposed in a sub-pixel of a next row line after a row line of a sub-pixel in which the photoresistor is disposed, connected to a gate line of the next row line, and configured to transmit a light sensing signal generated by the photoresistor to a sensing line. Each sub-pixel further comprises a capacitor connected between the gate electrode and the first or second electrode of the drive transistor.

19. The light-emitting display device according to claim 17, wherein The photoresistor comprises a photoelectric material.

20. The light-emitting display device according to claim 17, wherein The photoelectric material is an oxide semiconductor.

21. The light-emitting display device according to claim 20, wherein The cathode of the light emitting diode is connected to a low potential voltage power line.

22. The light-emitting display device according to claim 17, wherein ​

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