Semiconductor structure comprising variable resistance type memory and double capacitors and manufacturing method thereof

Abstract

A semiconductor structure including a resistive random access memory (RRAM) and a dual capacitor and a method of fabricating the same are provided, where the semiconductor structure including the RRAM and the dual capacitor includes a substrate on which an element region and a capacitor region beside the element region are defined. The variable resistance type memory is located in the element area, the variable resistance type memory comprises a variable resistance layer and a double-capacitor structure located in the capacitor area, and the double-capacitor structure comprises a lower capacitor structure and an upper capacitor structure. Wherein the material of a first high dielectric constant layer in the lower capacitor structure is the same as that of a variable resistance layer of the variable resistance type memory.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor structure integrating a variable resistive memory and a dual-capacitor structure, and a method for fabricating the same. Background Technology

[0002] Resistive random access memory (RRAM) offers advantages such as simple structure, low operating voltage, high operating speed, good durability, and compatibility with CMOS fabrication processes. RRAM is the most promising alternative to traditional flash memory, enabling the reduction of device size. RRAM is widely used in various devices, such as optical discs and non-volatile memory arrays.

[0003] RRAM cells store data within material layers capable of undergoing phase transitions. Within all or part of these layers, the material can initiate a phase transition, switching between high-resistance and low-resistance states. These different resistance states, once detected, can be represented as "0" or "1". In a typical RRAM cell, the data storage layer comprises an amorphous metal oxide. Applying a sufficient voltage creates a metal bridge across the data storage layer, resulting in a low-resistance state. This bridge can then be broken by applying a high-current-density pulse or otherwise decomposing or melting all or part of the metal structure, restoring the high-resistance state. When the data storage layer is then rapidly cooled, it transitions back to a low-resistance state.

[0004] As the area of ​​semiconductor devices becomes smaller and smaller, various devices with different functions are often combined on the same substrate to increase device density. In this process, how to effectively integrate various different devices is one of the research directions in this field. Summary of the Invention

[0005] This invention provides a semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor, comprising a substrate, on which a device region and a capacitor region are defined, adjacent to the device region, a resistive random access memory (RRAM) located within the device region, wherein the RRAM includes a variable resistance layer, and a dual capacitor structure is located within the capacitor region, wherein the dual capacitor structure includes a lower capacitor structure and an upper capacitor structure, wherein the material of a first high dielectric constant layer in the lower capacitor structure is the same as the material of the variable resistance layer of the RRAM.

[0006] The present invention also provides a method for fabricating a semiconductor structure including a resistive random access memory (RRAM) and a dual capacitor, comprising providing a substrate, defining a component region and a capacitor region on the substrate adjacent to the component region, forming a resistive random access memory within the component region, wherein the resistive random access memory includes a variable resistance layer, and forming a dual capacitor structure within the capacitor region, wherein the dual capacitor structure includes a lower capacitor structure and an upper capacitor structure, wherein the material of a first high dielectric constant layer in the lower capacitor structure is the same as the material of the variable resistance layer of the resistive random access memory.

[0007] This invention provides a semiconductor structure integrating RRAM and dual capacitors, as well as a method for fabricating the same. The dual capacitors are formed concurrently during the RRAM fabrication process, thus saving fabrication steps. Furthermore, contact structures can be formed simultaneously during fabrication to electrically connect the lower electrodes of the RRAM and the dual capacitors, eliminating the need for subsequent contact structures to connect the lower electrodes of the dual capacitors, further reducing fabrication steps. This invention effectively integrates RRAM and dual capacitors using existing fabrication processes, providing a stable and easily fabricated semiconductor integrated structure and its fabrication method. Attached Figure Description

[0008] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0009] Figures 1 to 7 This is a cross-sectional view of a semiconductor structure integrating a variable resistive memory and a dual-capacitor structure, as an embodiment of the present invention.

[0010] Symbol Explanation

[0011] 10: Mask layer

[0012] 12: Mask layer

[0013] 14: Mask layer

[0014] 16: Mask layer

[0015] 18: Fourth dielectric layer

[0016] 20: Conductive via

[0017] 24: First electrode layer (lower electrode)

[0018] 26: First high dielectric constant layer

[0019] 26A: Variable Resistance Layer

[0020] 26B: First insulating layer

[0021] 27: Barrier Layer

[0022] 27A: First Barrier Layer

[0023] 27B: First Barrier Layer

[0024] 28: Second electrode layer (middle electrode)

[0025] 29: Second High Dielectric Constant Layer

[0026] 30: Third electrode layer (upper electrode)

[0027] 32: Nitride layer

[0028] 34: Oxide layer

[0029] 36: Dielectric layer

[0030] 37: Mask layer

[0031] 38: Dielectric layer

[0032] C1: Lower capacitor structure

[0033] C2: Upper capacitor structure

[0034] DC: Dual capacitor structure

[0035] IMD1: First dielectric layer

[0036] IMD2: Second dielectric layer

[0037] IMD3: Third dielectric layer

[0038] M1: First metal layer

[0039] M2: Second metal layer

[0040] M3: Third metal layer

[0041] M4: Fourth Metal Layer

[0042] M5: Fifth Metal Layer

[0043] R1: Component Area

[0044] R2: Capacitor area

[0045] R3: Logical area

[0046] RRAM: Resistive Random Access Memory

[0047] S: Substrate

[0048] ST: Stepped outline

[0049] V1: Conductive via

[0050] V2: Conductive via

[0051] V3: Conductive via

[0052] V4: Conductive via

[0053] V5: Conductive Through Hole Detailed Implementation

[0054] To enable those skilled in the art to further understand the present invention, preferred embodiments of the invention are described below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings.

[0055] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0056] Although the present invention uses terms such as first, second, third, etc., to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0057] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, such as within 10%, 5%, 3%, 2%, 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate, meaning that the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0058] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0059] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details are within the scope of knowledge of those skilled in the art.

[0060] As described in the prior art, with the advancement of semiconductor technology, in order to reduce the space required for components and lower manufacturing costs, it is possible to integrate various different components onto the same substrate. In the semiconductor structure described below, a resistive random access memory (RRAM) and a dual-capacitor structure are integrated, as will be described in detail in the following paragraphs.

[0061] Please refer to Figures 1 to 7 , Figures 1 to 7 A cross-sectional view of a semiconductor structure integrating a variable resistive memory (hereinafter referred to as RRAM) and a dual-capacitor structure is illustrated according to an embodiment of the present invention. Figure 1 As shown, a substrate S is first provided, such as a silicon substrate or a material layer containing electronic components (such as transistors). Multiple layers are sequentially formed on the substrate S to... Figure 1 For example, it includes a mask layer 10, a first dielectric layer IMD1, a mask layer 12, a second dielectric layer IMD2, a mask layer 14, a third dielectric layer IMD3, a mask layer 16, and a fourth dielectric layer 18. The first dielectric layer IMD1, the second dielectric layer IMD2, the third dielectric layer IMD3, and the fourth dielectric layer 18 are made of, for example, silicon oxide, while the mask layers 10, 12, 14, and 16 are made of, for example, silicon nitride or silicon oxynitride, but the invention is not limited thereto. Furthermore, Figure 1 The number of mask layers and dielectric layers shown in the figure can also be adjusted according to actual needs. In other words, in other embodiments of the present invention, the semiconductor structure may also contain more or fewer mask layers and dielectric layers, and such variations are also within the scope of the present invention.

[0062] The mask layer 10 and the first dielectric layer IMD1 contain conductive vias V1 and a first metal layer M1; the mask layer 12 and the second dielectric layer IMD2 contain conductive vias V2 and a second metal layer M2; the mask layer 14 and the third dielectric layer IMD3 contain conductive vias V3 and a third metal layer M3; and the mask layer 16 and the fourth dielectric layer 18 contain conductive vias 20. The conductive vias V1, V2, and V3, as well as the first metal layer M1, second metal layer M2, and third metal layer M3, are made of materials with good conductivity, such as tungsten, cobalt, copper, aluminum, gold, and silver. The first metal layer M1, second metal layer M2, and third metal layer M3 are mainly used for electrically connecting components in the horizontal direction, that is, electrically connecting various electronic components in the same layer structure. The main function of the conductive vias V1, V2, V3, and V4 is to connect electronic components in the vertical direction (i.e., different layers). The technology regarding metal layers and conductive vias is existing technology in this field and will not be elaborated upon here.

[0063] also, Figure 1 The semiconductor element further includes a component region R1, a capacitor region R2, and a logic region R3, wherein the component region R1, capacitor region R2, and logic region R3 are distributed on the substrate. In subsequent steps, components such as RRAM will be formed in the component region R1, a dual-capacitor structure will be formed in the capacitor region R2 for storing charge, and logic circuits and connections to various electronic components will be formed in the logic region R3. In this embodiment, although the logic region R3 is located between the component region R1 and the capacitor region R2, the present invention is not limited to this arrangement; that is, the positions of the above three regions can be adjusted according to requirements. In addition, in this embodiment, the boundary between the component region R1 and the logic region R3, and the boundary between the capacitor region R2 and the logic region R3 are represented by dashed lines. The dashed lines may represent two regions that are directly adjacent to each other, or in other embodiments, they may represent two regions that are not directly adjacent to each other (that is, there may be other components such as blank areas in between). All of these variations are within the scope of the present invention.

[0064] like Figure 2As shown, a first electrode layer 24, a first high-dielectric-constant layer 26, a barrier layer 27, a second electrode layer 28, a second high-dielectric-constant layer 29, and a third electrode layer 30 are sequentially formed within the component area R1, the capacitor area R2, and the logic area R3. The materials of the first electrode layer 24, the second electrode layer 28, and the third electrode layer 30 are, for example, titanium, titanium nitride, tantalum, or tantalum nitride, but are not limited to these. The first electrode layer 24, the second electrode layer 28, and the third electrode layer 30 serve as electrode plates for the subsequently formed resistive random access memory (RRAM) and the dual-capacitor structure. More specifically, the first electrode layer 24 and the second electrode layer 28 can serve as the lower and upper electrodes of the RRAM, respectively, while the first electrode layer 24, the second electrode layer 28, and the third electrode layer 30 can serve as the bottom, middle, and upper electrodes of the subsequently formed dual-capacitor structure, respectively.

[0065] A first high-dielectric-constant layer 26 is formed between the first electrode layer 24 and the barrier layer 27. In subsequent steps, the first high-dielectric-constant layer 26 located in the element region R1 will serve as the variable resistance layer of the RRAM. Since the first high-dielectric-constant layer 26 is also formed in the capacitor region R2, it can also serve as the insulating layer of the lower capacitor structure in a dual-capacitor structure. In this embodiment, tantalum oxide (TaOx) is chosen as the material for the first high-dielectric-constant layer 26, but the invention is not limited thereto.

[0066] The barrier layer 27 can be made of metals such as ruthenium (Ru), platinum (Pt), or iridium (Ir). These metals are less likely to react with other substances during the fabrication process, and therefore can be used as an etch stop layer in the fabrication process. Furthermore, since oxygen vacancies migrate during RRAM driving, the barrier layer 27, positioned above the first high-dielectric-constant layer 26, can also prevent oxygen ions from migrating upwards and reacting with the metal. Additionally, oxides of the aforementioned metals, such as ruthenium oxide, platinum oxide, and iridium oxide, can also be used as the material for the barrier layer 27 in this invention, and these are also within the scope of this invention.

[0067] The second high dielectric constant layer 29 is made of a suitable high dielectric constant layer and can serve as an insulating layer for the upper capacitor structure in a dual capacitor structure. More specifically, in this embodiment, the second high dielectric constant layer 29 comprises a stacked structure of zirconium dioxide, aluminum oxide, and zirconium dioxide (also known as ZAZ). While zirconium dioxide has a high dielectric constant, it exhibits significant leakage current when used as an insulating layer for a capacitor. Therefore, the addition of aluminum oxide can reduce the overall leakage current of the stacked material. It is understood that the first high dielectric constant layer 26 and the second high dielectric constant layer 29 of the present invention may also contain other suitable high dielectric constant materials, such as those selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. The invention comprises the group consisting of lead zirconate titanate (SrBi₂Ta₂O₉, SBT), lead zirconate titanate (PbZrₓTi₁₁ₘO₃, PZT), barium strontium titanate (BaₓSr₁ₘTi₁ₘO₃, BST), or combinations thereof. However, the invention is not limited thereto.

[0068] like Figure 3 As shown, one or more patterning steps are performed to form an RRAM pattern in the component region R1 and a dual-capacitor structure in the capacitor region R2. More specifically, in Figure 3After the patterning step, a patterned first electrode layer 24, a first high dielectric constant layer 26, a barrier layer 27, and a second electrode layer 28 are left in the component region R1. These material layers together constitute the RRAM structure. As mentioned above, the first electrode layer 24 and the second electrode layer 28 serve as the lower and upper electrodes of the RRAM, respectively, while the first high dielectric constant layer 26 serves as the variable resistance layer of the RRAM. For ease of distinction, the first high dielectric constant layer 26 located in the component region R1 is defined here as the variable resistance layer 26A. It can be understood that the variable resistance layer 26A is part of the RRAM, and its material is the same as the first high dielectric constant layer 26 mentioned above.

[0069] Same reference Figure 3 After the patterning step, patterned first electrode layer 24, first high dielectric constant layer 26, barrier layer 27, second electrode layer 28, second high dielectric constant layer 29, and third electrode layer 30 are left in the capacitor region R2. These material layers constitute a dual-capacitor structure DC. More specifically, the dual-capacitor structure DC includes a lower capacitor structure C1 and an upper capacitor structure C2. The lower capacitor structure C1 includes a first electrode layer 24 as the lower electrode, a first high dielectric constant layer 26 as the insulating layer, and a barrier layer 27 and a second electrode layer 28 as the upper electrodes. The upper capacitor structure C2 includes a second electrode layer 28 as the lower electrode, a second high dielectric constant layer 29 as the insulating layer, and a third electrode layer 30 as the upper electrode. It is worth noting that the insulating layer in the lower capacitor structure C1 and the variable resistor layer 26A in the RRAM are formed simultaneously and are made of the same material. For ease of distinction, the insulating layer in the lower capacitor structure C1 is defined as the first insulating layer 26B. In addition, in order to facilitate the subsequent connection of wires to each electrode, it is preferable to design the area of ​​the upper capacitor structure C2 to be smaller than that of the upper capacitor structure C2, that is, to remove part of the second high dielectric constant layer 29 and the third electrode layer 30, so that the top surface of the second electrode layer 28 is partially exposed, and a stepped profile ST is formed in the cross-sectional view.

[0070] Similarly, apart from the first high dielectric constant layer 26, the first electrode layer 24, the barrier layer 27, and the second electrode layer 28 are formed in the device region R1 and the capacitor region R2, respectively. The material layers located in the device region R1 constitute part of the RRAM, while the material layers located in the capacitor region R2 constitute part of the dual-capacitor structure. For ease of distinction, the barrier layer 27 located in the device region R1 is defined as the first barrier layer 27A, while the barrier layer 27 located in the capacitor region R2 is defined as the second barrier layer 27B.

[0071] like Figure 4As shown, a nitride layer 32 is further formed within the component region R1, capacitor region R2, and logic region R3, covering each RRAM and the dual-capacitor structure. In this embodiment, the nitride layer 32 is made of silicon nitride. The nitride layer 32 can be used to protect the RRAM and the dual-capacitor structure.

[0072] like Figure 5 As shown, an oxide layer 34 is then formed to fill the gaps between each RRAM. Since the gap size between each RRAM is small, the oxide layer 34 can be formed by an atomic layer deposition (ALD) step, but the invention is not limited to this. Subsequently, the excess oxide layer 34 and nitride layer 32 are removed by an etch-back step. For example, the nitride layer 32 in logic region R3 is also completely removed.

[0073] like Figure 6 As shown, a dielectric layer 36 is then formed in the component region R1, capacitor region R2, and logic region R3. The dielectric layer 36 contains an ultra-low dielectric constant material (ULK), such as silicon carbide (SiCOH) or organosilicon glass (OSG), but the present invention is not limited thereto. After the dielectric layer 36 covers the RRAM in the component region R1 and the dual capacitor structure (C1, C2) in the capacitor region R2, a planarization step is performed, such as chemical mechanical polishing, to align the top surfaces of each dielectric layer 36 in the component region R1, capacitor region R2, and logic region R3.

[0074] like Figure 7 As shown, a mask layer 37 and a dielectric layer 38 are formed on the surface of dielectric layer 36. Then, multiple fourth metal layers M4, conductive vias V4, fifth metal layers M5, and conductive vias V5 are formed within the component region R1, capacitor region R2, and logic region R3. In component region R1, the fourth metal layer M4 is electrically connected to the second electrode layer (i.e., the top electrode of the RRAM) 28. In capacitor region R2, the fourth metal layer M4 is electrically connected to the second electrode layer 28 (i.e., the top electrode of the lower capacitor structure C1, or the bottom electrode of the upper capacitor structure C2). The upper electrode (third electrode layer 30) of the upper capacitor structure C2 in capacitor region R2 is connected to the conductive via V5, while the lower electrode (first electrode layer 24) of the lower capacitor structure C1 in capacitor region R2 is connected to the previously formed conductive via 20. The wiring structure in logic region R3 is connected to other circuit elements through the aforementioned fourth metal layers M4, conductive vias V4, fifth metal layers M5, and conductive vias V5. Thus, the semiconductor structure integrating RRAM and dual capacitors provided by this invention has been completed.

[0075] like Figure 7As shown, one feature of this invention is that the first electrode layer 24, the first high dielectric constant layer 26, the barrier layer 27, and the second electrode layer 28 are simultaneously formed in both the component region R1 and the capacitor region R2. After the patterning step, these material layers constitute the RRAM in the component region R1 and also constitute the lower capacitor structure C1 in the capacitor region R2. Therefore, the components in the two regions share a portion of the material layers, which can effectively reduce the number of manufacturing steps and improve production efficiency.

[0076] Another feature of the present invention is that, when forming the conductive via 20 for electrically connecting the RRAM, a portion of the conductive via 20 is also located within the capacitor region R2 (e.g., Figure 1 These conductive vias 20 formed within the capacitor region R2 can be directly electrically connected to the bottom electrode (i.e., the first electrode layer 24) of the subsequently formed lower capacitor structure C1. Therefore, when forming structures such as the fourth metal layer M4, conductive vias V4, and the fifth metal layer M5 in subsequent steps to connect the upper and middle electrodes of the dual capacitor structure, it is not necessary to connect to the bottom electrode by penetrating the electrode structure from above. This simplifies the manufacturing process, and the simplicity of this structure improves the stability of the product.

[0077] This invention proposes a semiconductor structure integrating RRAM and a dual-capacitor structure. The dual-capacitor structure DC consists of a lower capacitor structure C1 and an upper capacitor structure C2 connected in parallel. Compared to a single capacitor, the dual-capacitor structure can store more charge. In other embodiments of this invention, multi-layer capacitor structures may be formed, such as three, four, or more layers of capacitors connected in parallel, to further increase the amount of charge stored. Such variations are also within the scope of this invention.

[0078] Based on the above description and figures, the present invention provides a semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor, comprising a substrate S, on which a component region R1 and a capacitor region R2 are defined adjacent to the component region R1, wherein the resistive random access memory (RRAM) comprises a variable resistance layer 26A, and a dual capacitor structure DC is located within the capacitor region R2, wherein the dual capacitor structure DC comprises a lower capacitor structure C1 and an upper capacitor structure C2, wherein the material of a first high dielectric constant layer 26 in the lower capacitor structure C1 is the same as the material of the variable resistance layer 26A of the resistive random access memory (RRAM).

[0079] In some embodiments of the present invention, the dual-capacitor structure comprises, from bottom to top, a lower electrode (first electrode layer 24), a first high dielectric constant layer 26, a middle electrode (second electrode layer 28), a second high dielectric constant layer 29, and an upper electrode (third electrode layer 30). The lower electrode 24, the first high dielectric constant layer 26, and the middle electrode 28 constitute the lower capacitor structure C1, while the middle electrode 28, the second high dielectric constant layer 29, and the upper electrode 30 constitute the upper capacitor structure.

[0080] In some embodiments of the present invention, a first barrier layer 27A is further included on a variable resistance layer 26A in a variable resistive memory RRAM, and a second barrier layer 27B is included between a first high dielectric constant layer 26 and a middle electrode 28 in a dual capacitor structure DC.

[0081] In some embodiments of the present invention, the first barrier layer 27A and the second barrier layer 27B are made of the same material, wherein the material of the first barrier layer 27A and the second barrier layer 27B includes ruthenium, iridium or platinum.

[0082] In some embodiments of the present invention, the material of the second high dielectric constant layer 29 comprises a stacked layer of zirconium dioxide and aluminum oxide (ZAZ).

[0083] In some embodiments of the present invention, it further includes a first contact (conductive via 20 located in element region R1) located below and electrically connected to the variable resistive memory RRAM, and a second contact (conductive via 20 located in capacitor region R2) located below and electrically connected to the lower electrode 24 of the dual capacitor structure DC.

[0084] In some embodiments of the present invention, the first contact (conductive via 20 located in element region R1) and the second contact (conductive via 20 located in capacitor region R2) are made of the same material, and a top surface of the first contact and a top surface of the second contact are aligned in a horizontal direction.

[0085] In some embodiments of the present invention, in the dual-capacitor DC structure, the width of the lower electrode 24 is equal to the width of the middle electrode 28, while the width of the upper electrode 30 is smaller than the width of the middle electrode 28.

[0086] In some embodiments of the present invention, a third contact structure is further included (see reference). Figure 7The fourth metal layer M4 is located in the component area R1, a fourth contact (the fourth metal layer M4 is located in the capacitor area R2) and a fifth contact (the conductive via V5 is located in the capacitor area R2), wherein the third contact is electrically connected to a top surface of the variable resistive memory RRAM, the fourth contact is electrically connected to the middle electrode 28 in the dual capacitor structure DC, and the fifth contact is electrically connected to the upper electrode 30 in the dual capacitor structure DC.

[0087] In some embodiments of the invention, one top surface of the dual-capacitor structure DC is higher than one top surface of the variable resistive memory RRAM.

[0088] The present invention also provides a method for fabricating a semiconductor structure including a resistive random access memory (RRAM) and a dual capacitor, comprising providing a substrate S, on which a component region R1 and a capacitor region R2 are defined adjacent to the component region R1, forming a resistive random access memory (RRAM) within the component region R1, wherein the resistive random access memory (RRAM) includes a variable resistance layer 26A, and forming a dual capacitor structure DC within the capacitor region R2, wherein the dual capacitor structure DC includes a lower capacitor structure C1 and an upper capacitor structure C2, wherein the material of a first high dielectric constant layer 26 in the lower capacitor structure C1 is the same as the material of the variable resistance layer 26A of the resistive random access memory (RRAM).

[0089] In some embodiments of the present invention, the dual-capacitor structure comprises, from bottom to top, a lower electrode (first electrode layer 24), a first high dielectric constant layer 26, a middle electrode (second electrode layer 28), a second high dielectric constant layer 29, and an upper electrode (third electrode layer 30). The lower electrode 24, the first high dielectric constant layer 26, and the middle electrode 28 constitute the lower capacitor structure C1, while the middle electrode 28, the second high dielectric constant layer 29, and the upper electrode 30 constitute the upper capacitor structure.

[0090] In some embodiments of the present invention, it further includes forming a first barrier layer 27A on a variable resistance layer 26A in a variable resistive memory RRAM, and including a second barrier layer 27B between a first high dielectric constant layer 26 and a middle electrode 28 in a dual-capacitor structure DC.

[0091] In some embodiments of the present invention, the first barrier layer 27A and the second barrier layer 27B are made of the same material and are formed simultaneously, wherein the material of the first barrier layer 27A and the second barrier layer 27B includes ruthenium, iridium or platinum.

[0092] In some embodiments of the present invention, the material of the second high dielectric constant layer 29 comprises a stacked layer of zirconium dioxide and aluminum oxide (ZAZ).

[0093] In some embodiments of the present invention, it further includes a first contact (conductive via 20 located in element region R1) located below and electrically connected to the variable resistive memory RRAM, and a lower electrode 24 including a second contact (conductive via 20 located in capacitor region R2) located below and electrically connected to the dual capacitor structure DC.

[0094] In some embodiments of the present invention, the first contact (conductive via 20 located in element region R1) and the second contact (conductive via 20 located in capacitor region R2) are made of the same material and are formed at the same time, and a top surface of the first contact and a top surface of the second contact are aligned in a horizontal direction.

[0095] In some embodiments of the present invention, the method further includes forming a middle electrode material layer 28, a second high dielectric constant layer 29, and an upper electrode material layer 30 in the element region R1 and the capacitor region R2, performing an etching step to pattern and remove portions of the middle electrode material layer 28, the second high dielectric constant layer 29, and the upper electrode material layer 30. After the above steps, the remaining middle electrode material layer 28 in the capacitor region R2 is defined as the middle electrode 28, the remaining second high dielectric constant layer 29 is defined as the second high dielectric constant layer 29, and the remaining upper electrode material layer 30 is defined as the upper electrode 30, wherein the width of the middle electrode 28 is greater than the width of the upper electrode 30 (see reference). Figure 2 as well as Figure 3 ).

[0096] In some embodiments of the invention, the second high dielectric constant layer 29 and the upper electrode material layer 30 within the element region R1 are completely removed after the etching step.

[0097] In some embodiments of the present invention, a third contact structure is further included (see reference). Figure 7 The fourth metal layer M4 is located in the component area R1, a fourth contact (the fourth metal layer M4 is located in the capacitor area R2) and a fifth contact (the conductive via V5 is located in the capacitor area R2), wherein the third contact is electrically connected to a top surface of the variable resistive memory RRAM, the fourth contact is electrically connected to the middle electrode 28 in the dual capacitor structure DC, and the fifth contact is electrically connected to the upper electrode 30 in the dual capacitor structure DC.

[0098] In summary, this invention provides a semiconductor structure integrating RRAM and dual capacitors, as well as a method for fabricating the same. The dual capacitors are formed concurrently during the RRAM fabrication process, thus saving fabrication steps. Furthermore, contact structures can be formed simultaneously during fabrication to electrically connect the lower electrodes of the RRAM and the dual capacitors, eliminating the need for subsequent contact structures to connect the lower electrodes of the dual capacitors, further reducing fabrication steps. This invention effectively integrates RRAM and dual capacitors using existing fabrication processes, providing a stable and easily fabricated semiconductor integrated structure and its fabrication method.

[0099] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor, comprising: a substrate, wherein an element region and a capacitor region are defined on the substrate; a resistive random access memory (RRAM) located in the element region, wherein the RRAM comprises a variable resistance layer; and a dual capacitor structure located in the capacitor region, wherein the dual capacitor structure comprises a lower capacitor structure and an upper capacitor structure, and wherein a material of a first high-k layer in the lower capacitor structure is the same as a material of the variable resistance layer of the RRAM.

2. The semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor of claim 1, wherein the dual capacitor structure comprises, in order from bottom to top, a lower electrode, the first high-k layer, a middle electrode, a second high-k layer, and an upper electrode, wherein the lower electrode, the first high-k layer, and the middle electrode form the lower capacitor structure, and wherein the middle electrode, the second high-k layer, and the upper electrode form the upper capacitor structure.

3. The semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor of claim 2, further comprising a first barrier layer located on the variable resistance layer in the RRAM, and a second barrier layer located between the first high-k layer and the middle electrode in the dual capacitor structure.

4. The semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor of claim 3, wherein the first barrier layer and the second barrier layer have the same material, and wherein the material of the first barrier layer and the second barrier layer comprises Ru, Ir, or Pt.

5. The semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor of claim 2, wherein a material of the second high-k layer comprises a stack of zirconium dioxide and aluminum oxide (ZAZ).

6. The semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor of claim 2, further comprising a first contact located below the RRAM and electrically connected to the RRAM, and a second contact located below the dual capacitor structure and electrically connected to the lower electrode of the dual capacitor structure.

7. The semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor of claim 6, wherein the first contact and the second contact comprise the same material, and wherein a top surface of the first contact and a top surface of the second contact are aligned in a horizontal direction.

8. The semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor of claim 2, wherein in the dual capacitor structure, a width of the lower electrode is equal to a width of the middle electrode, and a width of the upper electrode is smaller than the width of the middle electrode.

9. The semiconductor structure comprising a resistive random access memory (RRAM) and a dual capacitor of claim 2, further comprising a third contact structure, a fourth contact, and a fifth contact, wherein the third contact is electrically connected to a top surface of the RRAM, the fourth contact is electrically connected to the middle electrode in the dual capacitor structure, and the fifth contact is electrically connected to the upper electrode in the dual capacitor structure. ​ ​ ​ 10. The semiconductor structure of claim 1, wherein a top surface of the dual-capacitor structure is higher than a top surface of the variable resistance memory.

11. A method of fabricating a semiconductor structure comprising a variable resistance memory (RRAM) and a dual-capacitor, comprising: providing a substrate having a device region and a capacitor region defined adjacent to the device region; forming a variable resistance memory in the device region, wherein the variable resistance memory comprises a variable resistance layer; and forming a dual-capacitor structure in the capacitor region, wherein the dual-capacitor structure comprises a lower capacitor structure and an upper capacitor structure, and wherein a material of a first high-k layer in the lower capacitor structure is the same as a material of the variable resistance layer of the variable resistance memory.

12. The method of claim 11, wherein the dual-capacitor structure comprises, in order from bottom to top, a lower electrode, the first high-k layer, a middle electrode, a second high-k layer, and an upper electrode, wherein the lower electrode, the first high-k layer, and the middle electrode form the lower capacitor structure, and wherein the middle electrode, the second high-k layer, and the upper electrode form the upper capacitor structure.

13. The method of claim 12, further comprising forming a first barrier layer on the variable resistance layer of the variable resistance memory and forming a second barrier layer between the first high-k layer and the middle electrode of the dual-capacitor structure.

14. The method of claim 13, wherein the first barrier layer and the second barrier layer are formed simultaneously and have the same material, and wherein the material of the first barrier layer and the second barrier layer comprises Ru, Ir, or Pt.

15. The method of claim 12, wherein the second high-k layer comprises a stack of zirconium dioxide and aluminum (ZAZ).

16. The method of claim 12, further comprising forming a first contact under the variable resistance memory and electrically connected to the variable resistance memory, and forming a second contact under the dual-capacitor structure and electrically connected to the lower electrode of the dual-capacitor structure.

17. The method of claim 16, wherein the first contact and the second contact comprise the same material and are formed simultaneously, and wherein a top surface of the first contact and a top surface of the second contact are aligned in a horizontal direction.

18. The method of claim 12, further comprising: forming a middle electrode material layer, a second high-k layer, and an upper electrode material layer in the device region and the capacitor region; and ​ ​ ​ ​ An etching step is performed to pattern and remove portions of the middle electrode material layer, the second high-k layer, and the upper electrode material layer. After the etching step, the remaining middle electrode material layer in the capacitor region defines the middle electrode, the remaining second high-k layer defines the second high-k layer, and the remaining upper electrode material layer defines the upper electrode. The width of the middle electrode is greater than the width of the upper electrode.

19. The method of claim 18, wherein after the etching step is performed, the second high-k layer and the upper electrode material layer in the element region are completely removed.

20. The method of claim 12, further comprising forming a third contact, a fourth contact, and a fifth contact, wherein the third contact electrically connects to a top surface of the variable resistance memory, the fourth contact electrically connects to the middle electrode in the dual capacitor structure, and the fifth contact electrically connects to the upper electrode in the dual capacitor structure.

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