Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a bottom electrode layer, a protective layer, an insulating layer, a top electrode layer, a first contact structure and a second contact structure. The bottom electrode layer comprises a first step structure, wherein the first step structure comprises a first step surface and a second step surface lower than the first step surface. The protective layer is arranged on the second step surface, the insulating layer is arranged on the first step surface, the top electrode layer is arranged on the insulating layer, the first contact structure is electrically connected with the bottom electrode layer, and the second contact structure is electrically connected with the top electrode layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and particularly to a semiconductor element comprising a metal-insulator-metal (MIM) structure and a method of fabricating the same. BACKGROUND

[0002] In the field of semiconductor, MIM structure is widely used in fabricating semiconductor elements. For example, MIM structure can constitute a capacitor element. The capacitor element using MIM structure has lower resistance and smaller parasitic capacitance, and has no problem of induced voltage shift in the depletion region. Therefore, MIM structure is one of the main structures of the capacitor element. With the popularization of the application of MIM structure, how to improve the semiconductor element comprising MIM structure and the method of fabricating the same has become the goal of the continuous efforts of the relevant industry. SUMMARY

[0003] According to an embodiment of the present application, a semiconductor element is provided, comprising a bottom electrode layer, a protection layer, an insulating layer, a top electrode layer, a first contact structure and a second contact structure. The bottom electrode layer comprises a first stepped structure, wherein the first stepped structure comprises a first step surface and a second step surface lower than the first step surface. The protection layer is disposed on the second step surface, the insulating layer is disposed on the first step surface, the top electrode layer is disposed on the insulating layer, the first contact structure is electrically connected with the bottom electrode layer, and the second contact structure is electrically connected with the top electrode layer.

[0004] According to another embodiment of the present application, a method of fabricating a semiconductor element is provided, comprising the following steps. A bottom electrode layer is formed, wherein the bottom electrode layer comprises a first stepped structure, and the first stepped structure comprises a first step surface and a second step surface lower than the first step surface. A protection layer is formed on the second step surface, an insulating layer is formed on the first step surface, a top electrode layer is formed on the insulating layer, a first contact structure is formed to be electrically connected with the bottom electrode layer, and a second contact structure is formed to be electrically connected with the top electrode layer.

[0005] Compared with the prior art, by comprising a stepped structure in the bottom electrode layer, the present application can provide a space for disposing the protection layer, on the one hand, the capacitance value provided by the MIM structure can not be affected, on the other hand, the etchant used for defining the top electrode layer can not contact the bottom electrode layer, so that the process window for defining the top electrode layer can be increased, thereby being beneficial to maintaining the performance of the semiconductor element and / or improving the production yield of the semiconductor element. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1, Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 This is a cross-sectional schematic diagram of the steps for fabricating a semiconductor device according to an embodiment of the present invention;

[0007] Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a cross-sectional schematic diagram of the steps for fabricating a semiconductor device according to another embodiment of the present invention;

[0008] Figure 13 This is a cross-sectional schematic diagram of the steps for manufacturing a semiconductor device according to another embodiment of the present invention;

[0009] Figure 14 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0010] Figure 15 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0011] Symbol Explanation

[0012] 10, 10a, 10b, 10c: Semiconductor components

[0013] 12: Base

[0014] 14: Dielectric layer

[0015] 16: Bottom electrode layer

[0016] 18,20: Insulation layer

[0017] 22, 23, 24: Protective layer

[0018] 28: Top electrode layer

[0019] 30, 32, 34, 36: Dielectric layers

[0020] 38, 40: Holes

[0021] 42: First contact structure

[0022] 44: Second contact structure

[0023] 46: Photoresist layer

[0024] 121,184,221,231,241,281,301,361,461: Top surface

[0025] 140, 160, 180: Stepped structure

[0026] 141, 161, 181: First-order surface

[0027] 142, 162, 182: Second-order surfaces

[0028] 143, 163, 183: Connecting surfaces

[0029] 203,462: Side surface

[0030] D1: Horizontal direction

[0031] D2: Vertical direction

[0032] HD: Spacing

[0033] SD1, SD2, SD3: Step Difference

[0034] T1, T11, T12, T21, T22, T23, T3, T41, T42, T5, T6: Thickness Detailed Implementation

[0035] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. To make the content of the present invention clearer and easier to understand, the following drawings are simplified schematic diagrams, and the elements therein may not be drawn to scale. Furthermore, the number and size of the elements in the drawings are merely illustrative and not intended to limit the present invention. Directional terms mentioned in the following embodiments, such as up, down, left, right, front, back, bottom, and top, are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention. In addition, in the following embodiments, the same or similar elements will be referred to by the same or similar reference numerals.

[0036] The following description of "the first feature is formed on or above the second feature" can refer to "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature" so that the first feature and the second feature are not in direct contact.

[0037] This invention uses terms such as "first," "second," etc., to describe elements, regions, layers, and / or sections. However, it should be understood that these terms are only used to distinguish one element, region, layer, and / or section from another, and do not inherently imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this invention, the first element, region, layer, and / or section discussed below may also be referred to as the second element, region, layer, and / or section. The terms used in the claims may not be the same as those in the description, and may be replaced by first, second, third… according to the order of the elements declared in the claims.

[0038] Please refer to Figures 1 to 7 This is a cross-sectional schematic diagram of the steps involved in fabricating a semiconductor device 10 according to an embodiment of the present invention. Figure 1 As shown, a dielectric layer 14 can be formed on the substrate 12 first. At this stage, the dielectric layer 14 has a uniform thickness T1. The thickness T1 can be, for example, 500 angstroms to 1000 angstroms, but is not limited thereto. In this invention, the thickness of an element can refer to the length of the element in the vertical direction D2, which can be, for example, perpendicular to the top surface 121 of the substrate 12. The substrate 12 may include a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. Although not shown in the figure, active (active) elements and / or passive (passive) elements, such as transistors, diodes, capacitors, inductors, resistors, etc., can be formed in the substrate 12 and the dielectric layer 14 as needed, but are not limited thereto. In addition, other films and semiconductor elements can be formed between the substrate 12 and the dielectric layer 14 as needed.

[0039] Next, as Figure 2 As shown, a portion of the dielectric layer 14 can be removed using semiconductor fabrication processes such as photolithography and etching to form a stepped structure 140 in the dielectric layer 14. The stepped structure 140 may include a first stepped surface 141, a connecting surface 143, and a second stepped surface 142 connected in sequence, wherein the second stepped surface 142 is lower than the first stepped surface 141, and the first stepped surface 141 and the second stepped surface 142 have a step difference SD1 in the vertical direction D2. Specifically, the portion of the dielectric layer 14 above the second stepped surface 142 is removed to form the stepped structure 140, resulting in the dielectric layer 14 having different thicknesses T11 and T12, wherein the portion of the dielectric layer 14 below the first stepped surface 141 has a thickness T11, and the portion of the dielectric layer 14 below the second stepped surface 142 has a thickness T12, and the thickness T11 is substantially equal to the thickness T1 (see [reference]). Figure 1Thickness T11 is greater than thickness T12, and thickness T11 is equal to the sum of thickness T12 and step difference SD1.

[0040] Next, as Figure 3 As shown, a bottom electrode layer 16 is formed on the dielectric layer 14, wherein the bottom electrode layer 16 conformally covers the dielectric layer 14 and includes a stepped structure 160. The stepped structure 160 may include a first stepped surface 161, a connecting surface 163, and a second stepped surface 162 connected in sequence, wherein the second stepped surface 162 is lower than the first stepped surface 161, and the first stepped surface 161 and the second stepped surface 162 have a step difference SD2 in the vertical direction D2. The step difference SD2 is substantially equal to the step difference SD1. The first stepped surface 161 is disposed above the first stepped surface 141, and the second stepped surface 162 is disposed above the second stepped surface 142. The bottom electrode layer 16 has different thicknesses T21, T22, and T23. The portion of the bottom electrode layer 16 located between the first step surface 141 and the first step surface 161 has a thickness T21; the portion of the bottom electrode layer 16 located between the second step surface 142 and the first step surface 161 has a thickness T22; and the portion of the bottom electrode layer 16 located between the second step surface 142 and the second step surface 162 has a thickness T23. Thickness T21 is substantially equal to thickness T23, and thickness T22 is greater than both thicknesses T21 and T23. Thickness T22 is equal to the sum of thickness T21 or T23 and the step difference SD2. According to one embodiment of the present invention, thickness T21 can be from 400 angstroms to 3000 angstroms, but is not limited thereto.

[0041] like Figure 3 As shown, an insulating layer 18 is formed on the bottom electrode layer 16, wherein the insulating layer 18 conformally covers the bottom electrode layer 16 and includes a stepped structure 180. The stepped structure 180 may include a first stepped surface 181, a connecting surface 183, and a second stepped surface 182 sequentially connected, wherein the second stepped surface 182 is lower than the first stepped surface 181, and the first stepped surface 181 and the second stepped surface 182 have a step difference SD3 in the vertical direction D2. The step difference SD3 is substantially equal to the step difference SD2.

[0042] Next, as Figure 4 As shown, a planarization process, such as chemical mechanical polishing (CMP), can be used to remove a portion of the insulating layer 18, giving the insulating layer 18 a flat top surface 184 and eliminating the stepped structure 180. Before performing the planarization process, a sacrificial insulating layer (not shown) can be formed on the insulating layer 18. The sacrificial insulating layer can increase the overall thickness of the insulating layer (i.e., the sum of the thicknesses of the insulating layer 18 and the sacrificial insulating layer), which helps improve the flatness of the top surface 184. The sacrificial insulating layer can be an oxide, such as silicon dioxide, but is not limited to this.

[0043] Next, a top electrode layer 28 and a dielectric layer 30 are formed sequentially on the insulating layer 18. The top electrode layer 28 has a flat top surface 281 following the surface morphology of the insulating layer 18, and the dielectric layer 30 has a flat top surface 301 following the surface morphology of the top electrode layer 28.

[0044] Next, as Figure 5 As shown, the size of the top electrode layer 28 is defined. A portion of the dielectric layer 30, the top electrode layer 28, and the insulating layer 18 can be removed using one or more semiconductor fabrication processes such as photolithography and etching. Of the remaining portion of the insulating layer 18, the portion covered by the top electrode layer 28 is the insulating layer 20, and the portion exposed by the top electrode layer 28 is the protective layer 22. That is, in this step, the protective layer 22 can be formed on the second surface 162, the insulating layer 20 can be formed on the first surface 161, and the top electrode layer 28 can be formed on the insulating layer 20. The insulating layer 20 is located between the top electrode layer 28 and the bottom electrode layer 16. The bottom electrode layer 16, the insulating layer 20, and the top electrode layer 28 can together constitute a MIM structure, which can serve as a capacitor element. The insulating layer 20 has different thicknesses T41 and T42. The portion of the insulating layer 20 between the first step surface 161 and the top electrode layer 28 has a thickness T41, and the portion of the insulating layer 20 between the second step surface 162 and the top electrode layer 28 has a thickness T42. The capacitance value provided by the MIM structure is mainly determined by the thickness T41. Therefore, unless otherwise specified below, the thickness of the insulating layer 20 refers to the thickness T41. The protective layer 22 is disposed on the second step surface 162 of the bottom electrode layer 16. The protective layer 22 prevents the etchant used in the etching process that defines the top electrode layer 28 from contacting the bottom electrode layer 16, thus preventing damage to the bottom electrode layer 16 when defining the top electrode layer 28. For example, it prevents the second step surface 162 of the bottom electrode layer 16 from becoming rough.

[0045] When the protective layer 22 is not provided on the bottom electrode layer 16, the etching depth needs to be precisely controlled when defining the top electrode layer 28. Over-etching may damage the bottom electrode layer 16, affecting the properties and production yield of the subsequently fabricated semiconductor device 10. In other words, the protective layer 22 increases the fabrication process window when defining the top electrode layer 28, which helps maintain the properties of the semiconductor device 10 (see [link to documentation]). Figure 7 This improves the performance and / or production yield of the semiconductor device 10. Furthermore, by including a stepped structure 160 in the bottom electrode layer 16, the present invention provides space for the protective layer 22 without increasing the thickness T41 of the insulating layer 20. That is, by including the stepped structure 160 in the bottom electrode layer 16, the protective layer 22 can be provided to protect the bottom electrode layer 16 without sacrificing the capacitance value provided by the MIM structure.

[0046] In this embodiment, the insulating layer 20 and the protective layer 22 are formed by removing a portion of the insulating layer 18. Therefore, the insulating layer 20 and the protective layer 22 are formed in the same step, and the insulating layer 20 and the protective layer 22 contain the same material. This simplifies the manufacturing process.

[0047] The protective layer 22 has a thickness T3, which may differ from the thickness T41 of the insulating layer 20. According to one embodiment of the invention, the ratio of the thickness T41 of the insulating layer 20 to the thickness T3 of the protective layer 22 may be greater than or equal to 4. For example, the thickness T41 of the insulating layer 20 may be 200 angstroms to 300 angstroms, or 225 angstroms to 265 angstroms. The thickness T3 of the protective layer 22 may be less than or equal to 75 angstroms, or less than or equal to 60 angstroms, or 10 angstroms to 50 angstroms.

[0048] In this embodiment, the top surface 221 of the protective layer 22 is flush with the first step surface 161, and the thickness T3 of the protective layer 22 is equal to the step difference SD2, but is not limited thereto. In other embodiments, the top surface 221 of the protective layer 22 may be lower than the first step surface 161 (i.e., the thickness T3 of the protective layer 22 may be less than the step difference SD2), which can also achieve protection of the bottom electrode layer 16 without sacrificing the capacitance value provided by the MIM structure. In this embodiment, the length of the insulating layer 20 in the horizontal direction D1 (not otherwise labeled) is greater than the length of the first step surface 161 in the horizontal direction D1 (not otherwise labeled), the side surface 203 of the insulating layer 20 and the connecting surface 163 are spaced apart by a distance HD in the horizontal direction D1, and the protective layer 22 and the insulating layer 20 overlap in the vertical direction D2, but are not limited thereto. In other embodiments, the length of the insulating layer 20 in the horizontal direction D1 (unspecified) may be equal to the length of the first-step surface 161 in the horizontal direction D1 (unspecified). In this case, the side surface 203 of the insulating layer 20 is flush with the connecting surface 163, the spacing distance HD is equal to 0, and the protective layer 22 and the insulating layer 20 do not overlap in the vertical direction D2. This part can be referred to. Figure 14 Related explanations.

[0049] Next, as Figure 6 As shown, a dielectric layer 32 can be deposited over the entire substrate 12 to cover the dielectric layer 30 and the protective layer 22. Next, the size of the bottom electrode layer 16 is defined, and a portion of the dielectric layer 32, the protective layer 22, the bottom electrode layer 16, and the dielectric layer 14 can be removed using one or more semiconductor fabrication processes such as photolithography and etching. Then, a dielectric layer 34 is deposited over the entire substrate 12 to cover the dielectric layer 32 and the substrate 12.

[0050] Next, as Figure 7As shown, forming a first contact structure 42 electrically connecting the bottom electrode layer 16 and forming a second contact structure 44 electrically connecting the top electrode layer 28 may include the following steps. First, a dielectric layer 36 may be deposited over the entire substrate 12 to cover the dielectric layer 34. Then, a planarization process is used to remove a portion of the dielectric layer 36, giving the dielectric layer 36 a flat top surface 361. Next, an insert fabrication process is performed. Semiconductor fabrication processes such as photolithography and etching can be used to remove a portion of the dielectric layers 36, 34, 32, and a portion of the protective layer 22 to form a hole 38 exposing the bottom electrode layer 16. Another semiconductor fabrication process, such as photolithography and etching, is used to remove a portion of the dielectric layers 36, 34, 32, and 30 to form a hole 40 exposing the top electrode layer 28. Conductive material is then filled into the holes 38 and 40, and a planarization process is used to form the first contact structure 42 and the second contact structure 44 within the dielectric layer 36. The first contact structure 42 is electrically connected to the bottom electrode layer 16, and the second contact structure 44 is electrically connected to the top electrode layer 28. At this point, the fabrication of the semiconductor element 10 is complete.

[0051] The dielectric layer 14 may be made of oxides such as silicon dioxide or tetraethoxysilane (TEOS), but is not limited thereto. The insulating layer 18 may be made of a high dielectric constant dielectric material, such as a dielectric material with a dielectric constant greater than or equal to 4, but is not limited thereto. The insulating layer 18 may be a composite structure formed by a single layer or multiple film layers. For example, the insulating layer 18 may contain nitrides, such as silicon nitride (SiN), silicon carbonitride (SiCN), or combinations thereof, but is not limited thereto. The bottom electrode layer 16 and the top electrode layer 28 may be a composite structure formed by a single layer or multiple film layers. The materials of the bottom electrode layer 16 and the top electrode layer 28 may each independently contain conductive materials, such as copper (Cu), chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), silver (Ag), alloys of the above materials, or combinations thereof, but are not limited thereto. The dielectric layers 30, 32, and 34 may each independently contain nitrides, such as silicon nitride (SiN) or silicon nitric nitride (SiCN), but are not limited to these. The dielectric layer 36 may contain oxides such as silicon dioxide or tetraethoxysilane, but is not limited to these. The conductive materials of the first contact structure 42 and the second contact structure 44 may be the same or different, and each may independently contain a barrier layer (not shown) and a metal layer (not shown). The barrier layer may contain titanium, tantalum, titanium nitride, tantalum nitride, nitrogen, or combinations thereof, and the metal layer may contain aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, or combinations thereof, but is not limited to these.

[0052] Please refer toFigure 7 This is a cross-sectional schematic diagram illustrating a semiconductor device 10 according to an embodiment of the present invention. The semiconductor device 10 includes a bottom electrode layer 16, a protective layer 22, an insulating layer 20, a top electrode layer 28, a first contact structure 42, and a second contact structure 44, and optionally includes dielectric layers 14, 30, 32, 34, and 36. The bottom electrode layer 16 includes a stepped structure 160, which includes a first stepped surface 161 and a second stepped surface 162, the second stepped surface 162 being lower than the first stepped surface 161. The protective layer 22 is disposed on the second stepped surface 162, the insulating layer 20 is disposed on the first stepped surface 161, the top electrode layer 28 is disposed on the insulating layer 20, the first contact structure 42 is electrically connected to the bottom electrode layer 16, and the second contact structure 44 is electrically connected to the top electrode layer 28. A dielectric layer 14 is disposed below the bottom electrode layer 16. The dielectric layer 14 includes a stepped structure 140, which includes a first stepped surface 141 and a second stepped surface 142. The second stepped surface 142 is lower than the first stepped surface 141. The first stepped surface 161 is disposed above the first stepped surface 141, and the second stepped surface 162 is disposed above the second stepped surface 142. The dielectric layer 14 has different thicknesses T11 and T12 (see...). Figure 2 ).

[0053] Figure 7 In this configuration, the top surface 221 of the protective layer 22 may be flush with the first step surface 161. The thickness T3 of the protective layer 22 may differ from the thickness T41 of the insulating layer 20; in this case, the thickness T3 is less than the thickness T41. The ratio of the thickness T41 of the insulating layer 20 to the thickness T3 of the protective layer 22 may be greater than or equal to 4. The protective layer 22 and the insulating layer 20 may contain the same material. Further details regarding the semiconductor element 10 are provided above and will not be repeated here.

[0054] Please refer to Figure 1 , Figure 2 , Figures 8 to 12 This is a cross-sectional schematic diagram of the steps for fabricating a semiconductor device 10a according to another embodiment of the present invention. Figure 1 As shown, a dielectric layer 14 can be formed on the substrate 12 first. Then, as... Figure 2 As shown, a portion of the dielectric layer 14 is removed to form a stepped structure 140 on the dielectric layer 14.

[0055] Next, as Figure 8As shown, a bottom electrode layer 16 is formed on the dielectric layer 14, wherein the bottom electrode layer 16 conformally covers the dielectric layer 14 and includes a stepped structure 160. The stepped structure 160 may include a first stepped surface 161, a connecting surface 163, and a second stepped surface 162 sequentially connected, wherein the second stepped surface 162 is lower than the first stepped surface 161, and the first stepped surface 161 and the second stepped surface 162 have a step difference SD2 in the vertical direction D2. Next, a photoresist layer 46 is formed on the first stepped surface 161, and a protective layer 23 is deposited all over the substrate 12 to cover the photoresist layer 46 and the bottom electrode layer 16. Figure 8 In this embodiment, the thickness T5 of the protective layer 23 is less than the step difference SD2, but it is not limited to this. In other embodiments, the thickness T5 of the protective layer 23 may be equal to the step difference SD2. For more information on this, please refer to [link / reference needed]. Figure 15 Related explanations.

[0056] Next, as Figure 9 As shown, the photoresist layer 46 and the protective layer 23 on the photoresist layer 46 are removed, leaving only the protective layer 23 on the second surface 162. For example, a planarization process such as CMP can be used to remove the protective layer 23 on the top surface 461 of the photoresist layer 46, and then the photoresist layer 46 can be dissolved with a solvent, thus removing the protective layer 23 on the side surface 462 of the photoresist layer 46 at the same time. Alternatively, a dry film photoresist can be used for the photoresist layer 46, and the protective layer 23 on the side surface 462 of the photoresist layer 46 can be removed by peeling off the photoresist layer 46. Thus, the first surface 161 is less likely to be scratched or damaged by the planarization process. However, the invention is not limited to this, and other methods can be used to obtain the desired result. Figure 9 The semiconductor structure shown.

[0057] For example, please also refer to Figure 2 , Figure 13 and Figure 9 , Figure 2 In the middle, after removing a portion of the dielectric layer 14 to form a stepped structure 140, it can be as follows: Figure 13 As shown, a bottom electrode layer 16 is formed on the dielectric layer 14. Next, the following steps can be omitted. Figure 8 In the step of forming the photoresist layer 46, a protective layer 23 is directly deposited over the entire substrate 12 to cover the bottom electrode layer 16. Then, the protective layer 23 located above the first step surface 161 is removed by a planarization process such as CMP. Figure 9 The semiconductor structure in the image eliminates the need for a photoresist layer 46, simplifying the fabrication process.

[0058] Next, as Figure 10As shown, an insulating layer 18 is formed on the bottom electrode layer 16. Then, a portion of the insulating layer 18 is removed using a planarization process, giving the insulating layer 18 a flat top surface 184. Next, a top electrode layer 28 and a dielectric layer 30 are sequentially formed on the insulating layer 18. The top electrode layer 28 has a flat top surface 281 following the surface morphology of the insulating layer 18, and the dielectric layer 30 has a flat top surface 301 following the surface morphology of the top electrode layer 28.

[0059] Next, as Figure 11 As shown, the size of the top electrode layer 28 is defined. A portion of the dielectric layer 30, top electrode layer 28, and insulating layer 18 can be removed using one or more semiconductor fabrication processes such as photolithography and etching. Of the remaining portion of the insulating layer 18, the part covered by the top electrode layer 28 is the insulating layer 20, and the part exposed by the top electrode layer 28 is the protective layer 22. The insulating layer 20 is located between the top electrode layer 28 and the bottom electrode layer 16. The bottom electrode layer 16, insulating layer 20, and top electrode layer 28 together constitute a MIM structure. The protective layer 22 is disposed above the protective layer 23. The protective layers 22 and 23 together constitute the protective layer 24, which is disposed on the second-level surface 162 of the bottom electrode layer 16. That is, in this step, the protective layer 24 can be formed on the second-level surface 162, the insulating layer 20 can be formed on the first-level surface 161, and the top electrode layer 28 can be formed on the insulating layer 20. The protective layer 24 prevents the etchant used in the etching process that defines the top electrode layer 28 from contacting the bottom electrode layer 16, thus preventing the bottom electrode layer 16 from being damaged when defining the top electrode layer 28. For example, it can prevent the second surface 162 of the bottom electrode layer 16 from becoming rough.

[0060] The material of the protective layer 23 can be selected to be more resistant to the aforementioned etchant. Preferably, the material of the protective layer 23 has a high etch selectivity with the material of the insulating layer 20 (i.e., insulating layer 18, protective layer 22), thereby further expanding the fabrication process window when defining the top electrode layer 28. For example, the etch selectivity of the material of the insulating layer 20 to the material of the protective layer 23 can be greater than or equal to 2.5. For example, the material of the insulating layer 20 can be silicon nitride (SiN), and the material of the protective layer 23 can be aluminum oxide (Al2O3), but is not limited to these.

[0061] Next, as Figure 12 As shown, a dielectric layer 32 can be deposited over the entire substrate 12 to cover the dielectric layer 30 and the protective layer 22. Next, the size of the bottom electrode layer 16 is defined, and a portion of the dielectric layer 32, protective layers 22 and 23, bottom electrode layer 16, and dielectric layer 14 can be removed using one or more semiconductor fabrication processes such as photolithography and etching. Then, a dielectric layer 34 is deposited over the entire substrate 12 to cover the dielectric layer 32 and the substrate 12.

[0062] Next, a first contact structure 42 can be formed to electrically connect the bottom electrode layer 16, and a second contact structure 44 can be formed to electrically connect the top electrode layer 28. This process may include the following steps: First, a dielectric layer 36 can be deposited over the entire substrate 12 to cover the dielectric layer 34. Then, a planarization process is used to remove a portion of the dielectric layer 36, giving the dielectric layer 36 a flat top surface 361. Next, an insertion process is performed to form the first contact structure 42 and the second contact structure 44 in the dielectric layer 36. The first contact structure 42 is electrically connected to the bottom electrode layer 16, and the second contact structure 44 is electrically connected to the top electrode layer 28. This completes the fabrication of the semiconductor device 10a. Further details regarding the fabrication of the semiconductor device 10a can be found in the relevant description of the fabrication of the semiconductor device 10.

[0063] Please refer to Figure 12 This is a cross-sectional schematic diagram illustrating a semiconductor element 10a according to another embodiment of the present invention. The main difference between semiconductor element 10a and semiconductor element 10 is that the protective layer 24 is a composite structure composed of protective layers 22 and 23. Specifically, the protective layer 24 sequentially includes a first sublayer (i.e., protective layer 22) and a second sublayer (i.e., protective layer 23) from top to bottom. The first sublayer and the insulating layer 20 are formed in the same step, and the material of the first sublayer is the same as the material of the insulating layer 20. The etch selectivity ratio of the material of the first sublayer to the material of the second sublayer can be greater than or equal to 2.5.

[0064] The first sub-layer (i.e., protective layer 22) has a thickness T3, protective layer 23 has a thickness T5, and protective layer 24 has a thickness T6, where the thickness T6 is equal to the sum of thicknesses T3 and T5. The thickness T6 of protective layer 24 is different from the thickness T41 of insulating layer 20. According to one embodiment of the present invention, the ratio of the thickness T41 of insulating layer 20 to the thickness T6 of protective layer 24 may be greater than or equal to 4.

[0065] In this embodiment, the top surface 241 of the protective layer 24 (which is also the top surface 221 of the protective layer 22) is flush with the first step surface 161, and the thickness T6 of the protective layer 24 is equal to the step difference SD2, but is not limited thereto. In other embodiments, the top surface 241 of the protective layer 24 may be lower than the first step surface 161 (that is, the thickness T6 of the protective layer 24 may be less than the step difference SD2). In this embodiment, the length of the insulating layer 20 in the horizontal direction D1 (unspecified) is greater than the length of the first step surface 161 in the horizontal direction D1 (unspecified), and the side surface 203 of the insulating layer 20 and the connecting surface 163 have a spacing distance HD in the horizontal direction D1 (see...). Figure 11The protective layer 24 overlaps the insulating layer 20 in the vertical direction D2, but is not limited thereto. In other embodiments, the side surface 203 of the insulating layer 20 may be flush with the connection surface 163, that is, the spacing distance HD is equal to 0. Other details regarding the semiconductor element 10a can be found in the relevant description of the semiconductor element 10, and will not be repeated here.

[0066] Please refer to Figure 14 This is a cross-sectional schematic diagram of a semiconductor element 10b according to another embodiment of the present invention. The main difference between semiconductor element 10b and semiconductor element 10 is that the top surface 221 of the protective layer 22 can be lower than the first step surface 161, that is, the thickness T3 of the protective layer 22 is less than the step difference SD2. Furthermore, the length of the insulating layer 20 in the horizontal direction D1 (unspecified) can be equal to the length of the first step surface 161 in the horizontal direction D1 (unspecified). In this case, the side surface 203 of the insulating layer 20 is flush with the connecting surface 163, and the distance HD between the side surface 203 of the insulating layer 20 and the connecting surface 163 in the horizontal direction D1 (see [reference]). Figure 7 If the value is 0, the protective layer 22 and the insulating layer 20 do not overlap in the vertical direction D2. For example, when defining the top electrode layer 28 (see...). Figure 5 (Related instructions) allow adjustment of the coverage area of ​​the etching mask (not shown) positioned above the top electrode layer 28, and adjustment of etching process parameters to control the etching depth, thereby obtaining... Figure 14 Semiconductor element 10b is described in the text. Further details regarding semiconductor element 10b can be found in the relevant description of semiconductor element 10, and will not be repeated here.

[0067] Please refer to Figure 15 This is a cross-sectional schematic diagram of a semiconductor device 10c according to another embodiment of the present invention. The main difference between semiconductor device 10c and semiconductor device 10a is that protective layer 24 is replaced by protective layer 23. For example, in Figure 8 or Figure 13 In the process, the parameters of the deposition process can be controlled to adjust the thickness T5 of the protective layer 23 so that the top surface 231 of the protective layer 23 is flush with the first step surface 161, that is, the thickness T5 of the protective layer 23 is equal to the step difference SD2. Compared with the protective layer 24 of the semiconductor device 10a, the protective layer 23 of this embodiment contains only a single film layer, and the material of the protective layer 23 is different from that of the insulating layer 20. Other details about the semiconductor device 10c can be found in the relevant description of the semiconductor device 10a, and will not be repeated here.

[0068] Compared to existing technologies, this invention includes a stepped structure in the bottom electrode layer, which provides space for setting a protective layer. On the one hand, this does not affect the capacitance value provided by the MIM structure, and on the other hand, it avoids the etchant used to define the top electrode layer from contacting the bottom electrode layer. This increases the fabrication process window when defining the top electrode layer, which is beneficial for maintaining the performance of semiconductor devices and / or improving the production yield of semiconductor devices.

[0069] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, comprising: a bottom electrode layer comprising a first staircase structure, wherein the first staircase structure comprises a first step and a second step lower than the first step; a protective layer disposed on the second step; an insulating layer disposed on the first step; a top electrode layer disposed on the insulating layer; a first contact structure electrically connected to the bottom electrode layer; and a second contact structure electrically connected to the top electrode layer.

2. The semiconductor device of claim 1, wherein a thickness of the protective layer is different from a thickness of the insulating layer.

3. The semiconductor device of claim 1, wherein a top surface of the protective layer is lower than or flush with the first step.

4. The semiconductor device of claim 1, wherein the protective layer and the insulating layer comprise a same material.

5. The semiconductor device of claim 1, wherein an etch selectivity of a material of the insulating layer to a material of the protective layer is greater than or equal to 2.

5.

6. The semiconductor device of claim 1, wherein the protective layer comprises, in order from top to bottom, a first sub-layer and a second sub-layer, a material of the first sub-layer being the same as a material of the insulating layer.

7. The semiconductor device of claim 6, wherein an etch selectivity of the material of the first sub-layer to a material of the second sub-layer is greater than or equal to 2.

5.

8. The semiconductor device of claim 1, wherein a ratio of a thickness of the insulating layer to a thickness of the protective layer is greater than or equal to 4.

9. The semiconductor device of claim 1, further comprising: a dielectric layer disposed below the bottom electrode layer, wherein the dielectric layer comprises a second staircase structure, the second staircase structure comprising a third step and a fourth step lower than the third step, the first step disposed above the third step, and the second step disposed above the fourth step.

10. The semiconductor device of claim 9, wherein the dielectric layer has different thicknesses.

11. A method of fabricating a semiconductor device, comprising: forming a bottom electrode layer, wherein the bottom electrode layer comprises a first staircase structure, and the first staircase structure comprises a first step and a second step lower than the first step; forming a protective layer on the second step; forming an insulating layer on the first step; forming a top electrode layer on the insulating layer; forming a first contact structure electrically connected to the bottom electrode layer; and forming a second contact structure electrically connected to the top electrode layer.

12. The method of claim 11, wherein a thickness of the protective layer is different from a thickness of the insulating layer.

13. The method of claim 11, wherein a top surface of the protective layer is lower than or flush with the first step.

14. The method of claim 11, wherein the protective layer and the insulating layer comprise a same material.

15. The method of claim 11, wherein an etch selectivity of a material of the insulating layer to a material of the protective layer is greater than or equal to 2.

5.

16. The method of claim 11, wherein the protective layer comprises, in order from top to bottom, a first sub-layer and a second sub-layer, a material of the first sub-layer being the same as a material of the insulating layer. ​ ​ 17. The method of claim 16, wherein an etch selectivity of a material of the first sublayer to a material of the second sublayer is greater than or equal to 2.

5.

18. The method of claim 11, wherein a ratio of a thickness of the insulating layer to a thickness of the protective layer is greater than or equal to 4.

19. The method of claim 11, further comprising: forming a dielectric layer, wherein the dielectric layer comprises a second staircase structure, the second staircase structure comprising a third step surface and a fourth step surface lower than the third step surface; and forming the bottom electrode layer on the dielectric layer, wherein the first step surface is disposed above the third step surface and the second step surface is disposed above the fourth step surface.

20. The method of claim 19, wherein the dielectric layer has different thicknesses.

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