Apparatus and method for voltage drop detection in die architectures

Abstract

A die package includes voltage logic (120) to provide a voltage to a voltage rail, clock logic (104) to generate a clock signal, and adaptive clock distribution logic (102) to receive the clock signal (105) and the voltage (121). The adaptive clock distribution logic (102) may increment the event count (103) when the clock signal is above a threshold frequency, or when the voltage is below a threshold voltage level. The die package also includes a processor (106) that may monitor the event count during operation and determine a state of the adaptive clock allocation logic (102) based on the event count (103). In some examples, the processor (106) may test the adaptive clock distribution logic (102) by causing the clock signal (105) to operate above a threshold frequency or causing the voltage logic to provide a voltage below a threshold voltage level. The processor (106) may then read the event count (103) to determine a state.

Description

BACKGROUND TECHNICAL FIELD

[0002] The present disclosure relates generally to die architectures, and more specifically to detecting voltage droop in a die architecture.

[0003] Related Art

[0004] In various applications, die architectures, such as system-on-a-chip (SoC) architectures, experience voltage droop events. For example, a processor can receive an operating voltage from a voltage rail. If the workload of the processor changes sufficiently large within a window of time, the processor can suddenly begin to draw more or less current from the voltage rail, causing a voltage droop on the voltage rail. When a voltage droop occurs, components receiving power from the voltage rail can experience a drop in voltage level. As a result, circuitry can fail or begin to experience uncertain behavior. Some droop mitigation efforts include operating the voltage rail at a higher voltage level in an attempt to prevent the voltage from dropping below a minimum level when a voltage droop event occurs. However, these mechanisms increase the power consumption of the components and can also increase the cost of the components required to run at the higher voltage level. SUMMARY

[0005] According to an aspect, a die package includes an adaptive clock distribution logic component and a processor electrically coupled to the adaptive clock distribution logic component. The adaptive clock distribution logic component is configured to detect an activation event and increment an event count within a register based on detecting the activation event. Further, the processor is configured to access the register and read the event count within the register. The processor is also configured to compare the event count to a threshold count value. The processor is further configured to send a signal to at least one component electrically coupled to the die package based on the comparison.

[0006] According to another aspect, a method by a processor includes accessing a register of an adaptive clock distribution logic component configured to increment an event count within the register based on detecting an activation event and reading the event count within the register. The method also includes comparing the event count to a threshold count value. Further, the method includes sending a signal to at least one device based on the comparison.

[0007] According to yet another aspect, a non-transitory machine-readable storage medium includes instructions that, when executed by at least one processor, cause the at least one processor to perform operations. The operations include accessing a register of an adaptive clock distribution logic component configured to increment an event count within the register based on detecting an activation event and reading the event count within the register. The operations also include comparing the event count to a threshold count value. Further, the operations include sending a signal to at least one device based on the comparison.

[0008] According to another aspect, an apparatus includes a memory storing instructions and at least one processor communicatively coupled to the memory. The at least one processor is configured to execute the instructions to access a register of an adaptive clock distribution logic component configured to increment an event count within the register based on detecting an activation event and read the event count within the register. The at least one processor is also configured to execute the instructions to compare the event count to a threshold count value. Further, the at least one processor is configured to execute the instructions to send a signal to at least one device based on the comparison. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram of an integrated circuit according to some implementations; Figure 2A and Figure 2B is a block diagram illustrating a portion of an integrated circuit according to some implementations; Figure 3A and Figure 3B is a block diagram illustrating a portion of an integrated circuit according to some implementations; Figure 4A and Figure 4B is a block diagram illustrating a portion of an integrated circuit according to some implementations; Figure 5A , Figure 5B and Figure 5C is a block diagram illustrating a portion of an integrated circuit according to some implementations; Figure 6A and Figure 6B is a block diagram illustrating a portion of an integrated circuit according to some implementations; Figure 7 is a flowchart of an example process for testing an adaptive clock distribution logic component according to some implementations; and Figure 8 is a flowchart of an example process for monitoring an adaptive clock distribution logic component according to some implementations. DETAILED DESCRIPTION

[0010] While features, methods, apparatus, and systems described herein can be embodied in a variety of forms, some exemplary and non-limiting embodiments are shown in the drawings and described below. Some of the components described in the disclosure are optional and some implementations can include additional components, different components, or fewer components than those components explicitly described in the disclosure.

[0011] Embodiments described herein relate to logic components within a die architecture that detect voltage drop events and testing of logic components that detect voltage drop events. The logic components can include adaptive clock distribution (ACD) functionality that reduces a rate of an operating clock signal based on a detected operating condition.

[0012] For example, a system on chip (SoC) can include various components (e.g., processors, memory devices, logic blocks, etc.) that receive a supply voltage from a voltage rail. The SoC can also include a clock logic component that generates and provides an output clock signal to the various components. For example, the clock logic component can include a phase-locked loop (PLL)-based clock generator that receives an input clock signal at a first frequency and frequency divides the input clock signal to generate an output clock signal at a second frequency. In some examples, the PLL receives an input clock and frequency multiplies the input clock signal to generate the output clock signal (e.g., frequency multiplication). The SoC can also include an ACD logic component that can detect one or more activation events. For example, at least in some cases, the ACD logic component can detect when the supply voltage from the voltage rail drops below a voltage threshold (e.g., 1.2 volts, 3.3 volts, 5 volts, etc.). When the ACD logic component detects that the supply voltage drops below the voltage threshold, the ACD logic component reduces an operating frequency of the output clock signal provided to the various components. For example, the ACD logic component can receive a clock signal at a first frequency (e.g., from the clock logic component). When the supply voltage remains at or above the voltage threshold, the ACD logic component provides the clock signal at the first frequency to the various components (e.g., the ACD logic component operates as a “pass-through” of the clock signal). However, if the supply voltage drops below the voltage threshold, the ACD logic component can activate and provide the clock signal to the various components at a second frequency. The second frequency can be less than the first frequency.

[0013] For example, the ACD logic can divide (or in some examples multiply) a clock signal received from the clock logic at a first frequency by two, four, eight, or any suitable factor to reduce the clock signal from the first frequency to a second frequency. The second frequency can be half, a quarter, or an eighth of the first frequency, etc. The reduction in frequency of the clock signal can reduce the amount of current drawn from the voltage rail by various components, which can mitigate the effects of the voltage droop on the various components. When the supply voltage increases to at least the voltage threshold, the ACD logic can deactivate and the clock signal resumes operating (i.e., running) at the first frequency (e.g., the ACD logic stops dividing or multiplying the clock signal). In some cases, the ACD logic can be configured to deactivate after the supply voltage remains at or above the voltage threshold for at least a predetermined time interval (e.g., 100 nanoseconds, 2 milliseconds, etc.).

[0014] In some examples, the ACD logic can detect an activation event when the clock signal from the clock logic operates at a frequency outside of the clock frequency range, such as above the upper clock frequency threshold. When the ACD logic detects that the clock signal operates above the clock frequency threshold, the ACD logic activates the operating frequency of the clock signal and reduces it from the first frequency to the second frequency, as described herein. The reduction in frequency of the clock signal by the ACD logic can prevent various components from operating at a higher clock frequency, which can be detrimental to the components and / or cause the components to draw additional current from the voltage rail. When the clock signal reduces back to at least the clock frequency threshold, the ACD logic deactivates and the clock signal provided to the various components resumes operating at the first frequency (e.g., the original frequency). In some cases, the ACD logic can be configured to deactivate after the clock signal from the clock logic has remained at or below the clock frequency threshold for at least a predetermined time interval.

[0015] In some cases, and by performing one or more of the example processes described herein, the ACD logic can mitigate the effects of a voltage droop event on components while allowing at least some systems to continue operating regardless of the voltage droop event. Further, the ACD logic can enable the voltage rail to provide a supply voltage to various components of the SOC at a lower minimum voltage.

[0016] However, using ACD logic components alone can be insufficient for various reasons. For example, in safety-critical systems, such as in automotive safety-critical applications (e.g., collision avoidance, autonomous driving, mapping and navigation, etc.), the operational frequency cannot be reduced for a relatively long and / or unknown period of time. Further, some safety-critical applications monitor a clock signal, and if the clock signal remains below a threshold frequency level for more than a threshold amount of time, fail or at least generate an error. In some cases, the ACD logic component itself can experience a hardware failure and inadvertently activate, resulting in an undesired and / or prolonged period of reduced clock signal frequency. In such cases, components such as processors can experience unexpected or undesirable behavior. In other examples, the ACD logic component can detect a voltage drop event and, in response, reduce the frequency of the clock signal, but can fail to restore the original frequency of the clock signal due to one or more errors.

[0017] To address one or more of these potential issues, in some examples, an integrated circuit performs operations that monitor the operation of an ACD logic component of a SoC, and based on the monitoring, the integrated circuit can limit or even disable the ACD logic component. For example, the integrated circuit can include a processor electrically coupled to a voltage logic component and an ACD logic component. As described herein, the ACD logic component can include one or more registers that provide a corresponding event count, which can indicate a number of times the ACD logic component was activated within a time interval. As described herein, for example, the event count can indicate a number of voltage event counts and / or clock event counts. The processor can occasionally (e.g., periodically) access one or more of the registers of the ACD logic component and read the corresponding event counts.

[0018] For each of the event counts (e.g., voltage event counts, clock event counts), the processor of the integrated circuit can determine whether the ACD logic component is operating correctly based on comparing the one or more event counts to a corresponding event count threshold. The event count threshold can correspond to an expected event count and / or an event count range. For example, if the event count falls within its corresponding event count range, the processor can generate a status indicating that the ACD logic component passed the corresponding test and thus the ACD logic component is operating correctly. Alternatively, if the event count fails to fall within its corresponding event count range, the processor can generate a status indicating that the corresponding test failed and the ACD logic component is not operating correctly.

[0019] Another reason ACD activation can occur outside of the expected range is that the set of workloads running on the safety logic component causes workload transitions to occur frequently, causing ACD activation to occur frequently, which in turn causes the ACD to slow down the clock frequency of the safety logic component. In this case, although the ACD can be operating correctly, this can cause the safety logic component to fail to complete safety functions, generating a FUSA WARNING or FUSA ERROR, where the processor can take necessary actions in response to the FUSA WARNING or FUSA ERROR to avoid a safety system failure. The FUSA WARNING signal can indicate that ACD events are occurring as frequently as preconfigured in the counter threshold and have reached a warning level, indicating that performance can be impacted because of the slowing down of the clock frequency to manage voltage droop events. On the other hand, the FUSA ERROR signal can indicate that the frequency or duration of ACD events is much higher than preconfigured in the counter threshold. Thus, performance can be severely impacted due to the slowing down of the clock frequency.

[0020] In some cases, the processor can generate a state based on which of a plurality of event count ranges the read event count falls into. For example, if the event count falls within a first range (e.g., 0 to X1), the processor can generate a first state (e.g., indicating a correctly functioning ACD logic component). Additionally, if the event count falls within a second range (e.g., X1+1 to X2), the processor can generate a second state (e.g., a warning state), and if the event count falls within a third range (e.g., above X2), the processor can generate a third state (e.g., an error state).

[0021] In some examples, an integrated circuit performs an operation that tests the operation of an ACD logic component of a SoC, and based on the test, the integrated circuit can limit or even disable the ACD logic component. The ACD logic component tests described herein can be performed prior to shipment of the integrated circuit (e.g., a die package containing the SoC), at every power up of the integrated circuit, and / or occasionally throughout the lifetime of the integrated circuit (e.g., every hour, once a day, once a week, etc.). For example, the integrated circuit can include a processor electrically coupled to a voltage logic component and an ACD logic component. As described herein, the ACD logic component can include one or more registers that provide a corresponding event count, which can indicate a number of times the ACD logic component was activated within a time interval. In some examples, the event count can also indicate a duration of ACD activation during the time interval. The voltage logic component can be, for example, a power management IC (PMIC), or any other suitable logic component that can provide a supply voltage. Further, the voltage logic component can be configured to provide a supply voltage to various electrical components of the SoC, such as the processor and the ACD logic component of the integrated circuit.

[0022] In some cases, the integrated circuit can perform a voltage test to test the operation of the ACD logic component. For example, a processor of the integrated circuit can send a signal to the voltage logic component, which can cause the voltage logic component to lower the supply voltage below a threshold voltage level. The threshold voltage level can be the voltage level at which the ACD logic component should activate to reduce the clock signal. Further, the supply voltage can be held below the threshold voltage level for a time interval (e.g., 4 milliseconds, 10 milliseconds, 1 second, etc.). At the end of the time interval, the same or an additional processor reads one or more voltage test event counts (e.g., total event count, total duration count) from the ACD logic component registers and stores the voltage event counts within a memory device.

[0023] In addition or alternative to the voltage test, the integrated circuit can perform a clock test to test the operation of the ACD logic component. For example, a processor of the integrated circuit can send a signal to the clock logic component, which can cause the clock logic component to adjust the frequency of the clock signal above a threshold frequency level. The threshold frequency level can be the frequency level at which the ACD logic component should activate and reduce the clock signal frequency. Further, the clock frequency level can be held above the threshold frequency level for a time interval (e.g., 4 milliseconds, 10 milliseconds, 1 second, etc.). At the end of the time interval, the same or an additional processor reads one or more clock test event counts from the ACD logic component registers and stores the clock test event counts within a memory device.

[0024] For each of the event counts (e.g., voltage event counts, clock event counts), the integrated processor can determine whether the ACD logic component is operating correctly based on a comparison of the one or more event counts to a corresponding event count threshold. The event count threshold can correspond to an expected event count and / or an event count range. For example, if the event count falls within its corresponding event count range, the processor can generate a status indicating that the ACD logic component passed the corresponding test and, thus, the ACD logic component is operating correctly. Alternatively, if the event count fails to fall within its corresponding event count range, the processor can generate a status indicating that the corresponding test failed and the ACD logic component is not operating correctly.

[0025] In some cases, the processor can generate a state based on which of a plurality of event count ranges the read event count falls into. For example, if the event count falls within a first range (e.g., 0 to X1), the processor can generate a first state (e.g., an ACD logic component indicating correct operation). Additionally, if the event count falls within a second range (e.g., X1+1 to X2), the processor can generate a second state (e.g., a warning state), and if the event count falls within a third range (e.g., above X2), the processor can generate a third state (e.g., an error state).

[0026] In some cases, the processor generates a state indicating that the ACD logic component is operating correctly only if the ACD logic component passes all of the tests performed. If the ACD logic component fails any of the tests performed, the processor can generate a state indicating that the ACD logic component is not operating correctly. Further, in some examples, the processor sends a second signal based on the state. For example, if the state indicates that the ACD logic component is not operating correctly, the processor can issue an error or warning interrupt to other logic components (e.g., FUSA_ERROR or FUSA_WARNING) that handle errors, such as another processor (e.g., a microcontroller unit (MCU), an internal safety processor within the SoC). In some cases, the ACD logic component can be disabled based on the error, and additionally or alternatively, certain SoC-level or system-level functionality (e.g., collision avoidance features, autonomous driving features, mapping and navigation features, etc.) can be limited or disabled based on the error.

[0027] Among other advantages, the integrated circuit can test operation of the ACD logic component within the SoC, and based on the test, the integrated circuit can determine whether the ACD logic component is operating correctly. Further, and based on the determination, the integrated circuit can selectively enable or selectively disable functionality of various components of the SoC, such as functionality within a safety-critical system. These advantages will be appreciated by those of ordinary skill in the art, and others will be recognized as well.

[0028] Figure 1This is a block diagram of an integrated circuit package 100 including a system-on-a-chip (SoC) 101 electrically coupled to voltage logic unit 120 and one or more external processors 116. The one or more external processors 116 may also be electrically coupled to a memory device 180. Voltage logic unit 120 can be supplied with one or more power supply voltages via one or more voltage rails 121. Although one voltage logic unit 120 is illustrated for simplicity, the integrated circuit package 100 may include additional voltage logic units 120 that supply voltages to various portions of the integrated circuit package 100. For example, external processors 116 and SoC 101 may receive voltages from individual voltage logic units 120 on corresponding voltage rails 121. Furthermore, voltage logic unit 120 allows for programming of the power supply voltages. For example, voltage logic unit 120 may be a PMIC. Additionally, each external processor 116 may be, for example, a graphics processing unit (GPU), a central processing unit (CPU), a microcontroller, or any other suitable processing device.

[0029] Furthermore, as illustrated, SoC 101 may include clock logic unit 104, ACD logic unit 102, counter logic unit 103, and one or more processors 106. SoC 101 may also include additional logic units, such as a first security logic unit 110, a second security logic unit 112, and a third security logic unit 114. Clock logic unit 104 is electrically coupled to ACD logic unit 102 and may provide an input clock signal 105 to ACD logic unit 102. For example, clock logic unit 104 may include one or more PLL circuits, clock generation circuits, and clock divider circuits to provide the input clock signal 105. The input clock signal 105 may operate at a programmed first frequency. For example, clock logic unit 104 may include one or more registers that, when written to, control the frequency of the input clock signal 105. ACD logic unit 102 is also electrically coupled to counter logic unit 103 and each of the first security logic unit 110, the second security logic unit 112, and the third security logic unit 114. ACD logic unit 102 can receive input clock signal 105 from clock logic unit and provide output clock signal 115 to, for example, first security logic unit 110, second security logic unit 112 and third security logic unit 114.

[0030] As described herein, when ACD logic unit 102 is not activated, ACD logic unit 102 can provide an output clock signal 115 at the same frequency as the input clock signal 105. For example, ACD logic unit 102 can allow the input clock signal 105 to "pass" while in a deactivated state. However, ACD logic unit 102 can be activated when it detects that the supply voltage from voltage rail 121 is out of range. For example, ACD logic unit 102 can be activated when the supply voltage drops below a voltage threshold (e.g., during a workload transition event). Additionally or alternatively, ACD logic unit 102 can be activated when the frequency of the input clock signal 105 is outside the corresponding range. For example, ACD logic unit 102 can be activated when the input clock signal 105 operates at a frequency higher than a clock frequency threshold. When ACD logic unit 102 is activated, ACD logic unit 102 generates an output clock signal 115 at a frequency lower than the frequency of the input clock signal 105. For example, as described herein, ACD logic unit 102 can divide the input clock signal 105 by a factor (e.g., which can be programmed in a register) to generate an output clock signal 115. When the input clock signal 105 is divided by 2, the frequency of the output clock signal 115 can be, for example, half the frequency of the input clock signal 105.

[0031] When ACD logic unit 102 is activated, it can generate an ACD event signal 131 that is provided to counter logic unit 103. For example, when no event is detected, ACD logic unit 102 can provide the ACD event signal 131 at a first voltage level (e.g., 0 volts). However, when an event is detected (e.g., an out-of-range supply voltage, an out-of-range input clock signal 105), ACD logic unit 102 can provide the ACD event signal 131 at a second voltage level (e.g., 3.3 volts). ACD logic unit 102 can maintain the ACD event signal 131 at the second voltage level until it determines that the event no longer exists. In some cases, ACD logic unit 102 provides the ACD event signal 131 as a pulse when an event is detected, or any other suitable mechanism can be used to indicate the event.

[0032] Counter logic unit 103 can detect the voltage level of ACD event signal 131 and increment one or more counters when ACD event signal 131 indicates the presence of an event. For example, counter logic unit 103 may include event count counter 103A, which increments when ACD event signal 131 indicates a new event, such as in some examples when ACD event signal 131 transitions from a first voltage level to a second voltage level (e.g., based on edge detection or level detection). Thus, for example, assuming an event count starting at zero, event count counter 103A increments to one when ACD event signal 131 transitions from the first voltage level to the second voltage level. Even after ACD event signal 131 transitions back to the first voltage level, event count counter 103A remains at one. If ACD event signal 131 transitions from the first voltage level to the second voltage level again, counter logic unit 103 increments event count counter 103A again to a value of two.

[0033] Additionally or alternatively, the counter logic unit 103 may include an event duration counter 103B that periodically increments when the ACD event signal 131 indicates an event. For example, when the ACD event signal 131 is at a second voltage level indicating an event, the event duration counter 103B may increment for each time interval, where the time interval is a predetermined value (e.g., 1 nanosecond, 1 microsecond, 1 millisecond, etc.). Thus, for example, again assuming an event count starting from zero, when the ACD event signal 131 transitions from a first voltage level to a second voltage level, the event duration counter 103B increments to one, and then increments again for each time interval as long as the ACD event signal 131 continues to indicate the same event (e.g., as long as the ACD event signal 131 remains at the second voltage level). Once the ACD event signal 131 indicates that the event no longer exists (e.g., when the ACD event signal 131 transitions from the second voltage level to the first voltage level), the event duration counter 103B stops incrementing. Thus, the event duration counter 103B characterizes the duration of activation of one or more ACD logic units 102. In some examples, when the ACD event signal 131 indicates that the event no longer exists, the counter logic unit 103 stores the value in a memory component (e.g., a first-in-first-out (FIFO) memory component) and resets the event duration counter 103B (e.g., resets it to zero).

[0034] Each of the first security logic unit 110, the second security logic unit 112, and the third security logic unit 114 that receives the output clock signal 115 from the ACD logic unit 102 may include any logic unit to be protected (e.g., by receiving a reduced frequency of the input clock signal 105). For example, any of the first security logic unit 110, the second security logic unit 112, and the third security logic unit 114 may include logic unit for one or more safety-critical features (such as safety-critical features in an automotive system), or any other suitable logic unit to be protected. Furthermore, each of the first security logic unit 110, the second security logic unit 112, and the third security logic unit 114 may include one or more electrical components, such as a processing core (e.g., CPU, GPU, AI processing engine), gates, memory components, or any other electrical components.

[0035] Processor 106 may include one or more processing cores and may be, for example, a GPU, CPU, or microcontroller. Although integrated circuit package 100 exemplifies processor 106 and external processor 116, in some examples, processor 106 may perform at least some of the operations described herein with respect to external processor 116. Similarly, in at least some examples, external processor 116 may perform at least some of the operations described herein with respect to processor 106.

[0036] Return to reference Figure 1 Processor 106 can communicate with clock logic unit 104 via communication bus 107. For example, processor 106 can perform a write operation via communication bus 107 to write to one or more configuration storage locations (e.g., registers) of clock logic unit 104 to establish the frequency of input clock signal 105. Processor 106 can also communicate with voltage logic unit 120 via communication bus 123. As an example, processor 106 can perform a write operation via communication bus 123 to write to one or more configuration storage locations of voltage logic unit 120, which are established on the power supply voltage provided on each of one or more voltage rails 121.

[0037] Furthermore, processor 106 can communicate with ACD logic unit 102 via communication bus 125. For example, processor 106 can perform write operations via communication bus 125 to write to one or more configuration memory locations of ACD logic unit 102, which establish the frequency of output clock signal 115 when ACD logic unit 102 is activated. For example, registers of ACD logic unit 102 can define factors for dividing input clock signal 105 to generate output clock signal 115 when ACD logic unit 102 is activated. Processor 106 can read values ​​from non-volatile memory locations and write those values ​​to registers. In some examples, as part of the SoC 101 initialization process (e.g., during startup), processor 106 writes configuration memory locations to clock logic unit 104, voltage logic unit 120, and ACD logic unit 102.

[0038] Processor 106 can also read the counters of counter logic unit 103. For example, processor 106 can perform a read operation via communication bus 117 to read one or more of the event count counter 103A and event duration counter 103B of counter logic unit 103. Similarly, external processor 116 can read the counters of counter logic unit 103. For example, external processor 116 can perform a read operation via communication bus 119 to read one or more of the event count counter 103A and event duration counter 103B of counter logic unit 103. In some examples, external processor 116 can send a request to processor 106 to receive the value read from one or more of the event count counter 103A and event duration counter 103B.

[0039] To determine whether or will operate as expected, the integrated circuit package 100 can test the ACD logic unit 102. In some examples, to test the ACD logic unit 102, a voltage test is performed where the supply voltage provided by the voltage logic unit 120 on one or more voltage rails 121 is intentionally reduced to detect activation of the ACD logic unit 102. For example, the processor 106 can write to one or more configuration memory locations of the voltage logic unit 120 to reduce the supply voltage provided on the voltage rails 121 from a nominal voltage level (e.g., a level within the expected operating voltage range) to below a threshold voltage level. The threshold voltage level can be the voltage level at which the ACD logic unit 102 is expected to activate to generate an output clock signal 115 with a reduced frequency. The supply voltage can be maintained below the threshold voltage level for a time interval. This time interval can be greater than (e.g., a multiple thereof) the amount of time the ACD logic unit 102 is expected to wait before reducing the output clock signal 115 after detecting a low supply voltage. During this time interval, if ACD logic unit 102 operates correctly, it should cause ACD event signal 131 received by counter logic unit 103 to indicate an event. In response, counter logic unit 103 updates one or more counters in its counters. For example, counter logic unit 103 may increment event count counter 103A, and may periodically increment event duration counter 103B, as described herein, as long as ACD event signal 131 continues to indicate an event. At the end of the time interval, processor 106 may write to one or more configuration storage locations of voltage logic unit 120 to increase the power supply voltage supplied on voltage rail 121 back to the nominal voltage level.

[0040] Furthermore, processor 106 can read one or more counters in the counter logic unit 103 via communication bus 117. For example, processor 106 can read event count counter 103A to obtain the event count value for the voltage test. The processor can also read event duration counter 103B to obtain the event duration value for the voltage test. In some cases, processor 106 can send event values ​​(such as event count value and event duration value) to external processor 116 via communication bus 141. Alternatively, in some examples, processor 106 can send a signal to external processor 116 via communication bus 141. The signal instructs external processor 116 that the counters within counter logic unit 103 are ready to be read. In response, external processor 116 reads event count counter 103A via communication bus 119 to obtain the event count value. External processor 116 can also read event duration counter 103B via communication bus 119 to obtain the event duration value. External processor 116 can then store the event count value and event duration value in a memory device. For example, external processor 116 can store the event count value and the event duration value as event count value 180A and event duration value 180B respectively in memory device 180. Memory device 180 can be, for example, a FIFO memory component of integrated circuit package 100 or any other suitable memory device.

[0041] As a supplement to or alternative to voltage testing, clock testing can be performed. For example, processor 106 can write to one or more configuration memory locations of clock logic unit 104 to cause clock logic unit 104 to generate an input clock signal 105 above a threshold frequency level. The threshold frequency level can be the frequency level at which ACD logic unit 102 is expected to activate to generate an output clock signal 115 with a reduced frequency. The input clock signal 105 can be maintained above the threshold frequency level for a time interval, as described herein. During this time interval, ACD logic unit 102 should generate an ACD event signal 131 to indicate an event if it operates correctly. Based on the received ACD event signal 131, counter logic unit 103 updates one or more counters in its counters. At the end of the time interval, processor 106 can write to one or more configuration memory locations of clock logic unit 104 to cause clock logic unit 104 to generate the input clock signal 105 at the nominal operating frequency.

[0042] As described herein, processor 106 can read event count counter 103A to obtain an event count value for clock testing. Processor 106 reads event duration counter 103B to obtain an event duration value for clock testing. In some cases, processor 106 can send event values ​​(such as event count value and event duration value) to external processor 116 via communication bus 141. Alternatively, in some examples, processor 106 can send a signal to external processor 116 via communication bus 141. The signal instructs external processor 116 that the counter within counter logic unit 103 is ready to be read. In response, external processor 116 reads event count counter 103A via communication bus 119 to obtain an event count value and event duration value for clock testing. External processor 116 can then store the event count value and event duration value as event count value 180A and event duration value 180B, respectively, in memory device 180.

[0043] In some examples, and based on the event count value 180A and / or event duration value 180B stored in memory device 180, external processor 116 can determine whether ACD logic unit 102 operates as expected (e.g., with expected or allowed tolerance levels). For example, external processor 116 can determine whether one or more event values, including the event count value and the event duration value, are within a corresponding range. For example, for each event value, external processor 116 can determine whether the event value is greater than a minimum value and less than a maximum value. For example, the minimum and maximum values ​​for each corresponding range can be stored as thresholds 180C in memory device 180. Alternatively, in some examples, processor 106, instead of external processor 116, can determine whether ACD logic unit 102 operates as expected. For example, the event count value 180A and / or event duration value 180B can be stored in the internal memory of SoC 101 (such as registers located within counter logic unit 103). The processor 106 can read the event count value 180A and / or the event duration value 180B, and can determine whether one or more event values, including the event count value and the event duration value, are within the corresponding range.

[0044] Furthermore, the external processor 116 can generate a test status value 180D for a corresponding test based on whether the event value is within the corresponding range. For example, if the event value of a specific test (e.g., voltage test, clock test) is within the corresponding range, the external processor 116 can generate a first test status value 180D for that specific test (e.g., 0, indicating no error). However, if the event value of a specific test is not within the corresponding range, the external processor 116 can generate a second test status value 180D (e.g., 1, indicating an error). The external processor 116 can store the test status value 180D in the memory device 180.

[0045] In some examples, external processor 116 may generate a test status value 180D for a test based on the degree of error. For example, for a given test, external processor 116 may determine how far an event value is from its corresponding range. For example, assuming the event value is higher than its corresponding maximum range value, external processor 116 may perform an operation to subtract the maximum range value from the event value to determine the event offset. External processor 116 may generate the test status value 180D for a test based on the event offset. For example, if the event offset falls within a first range (e.g., within 20% of the maximum range value), external processor 116 may generate a first test status value 180D indicating a "warning," and if the event offset falls within a second range (e.g., greater than 20% of the maximum range value), external processor 116 may generate a second test status value 180D indicating an "error." External processor 116 may store the test status value 180D in memory device 180.

[0046] Furthermore, based on test status values ​​180D, external processor 116 can generate an ACD status signal 129. ACD status signal 129 can indicate the status of ACD logic unit 102. For example, if any of the test status values ​​180D indicates an error, external processor 116 can generate ACD status signal 129 to indicate that ACD logic unit 102 is not operating correctly. In some examples, ACD status signal 129 also indicates the degree of error. For example, if any test status value 180D indicates "error," external processor 116 generates ACD status signal 129 to indicate that ACD logic unit 102 is "error." Otherwise, if no test status value 180D indicates "error," external processor 116 generates ACD status signal 129 to indicate that ACD logic unit 102 is "warning." A "warning" can indicate that although the performance of ACD logic unit 102 has degraded to a pre-configured warning level, the performance has not yet degraded to the "error" level. For example, ACD status signal 129 can be received by other integrated circuit packages.

[0047] In some cases, external processor 116 may send additional signals to processor 106 via communication bus 141, instructing processor 106 that ACD logic unit 102 should be disabled. For example, external processor 116 may send additional signals to processor 106 if it determines that ACD logic unit 102 is not operating correctly. In some examples, external processor 116 sends additional signals to processor 106 only when it determines that ACD logic unit 102 is “in error,” rather than when it determines that ACD logic unit 102 is “warning.” In response to receiving an additional signal, processor 106 may write to one or more configuration memory locations of ACD logic unit 102 to disable ACD functionality (i.e., prevent ACD logic unit 102 from activating). For example, processor 106 may write to one or more configuration registers of voltage logic unit 120 to increase the minimum voltage (Vmin) supplied to voltage rail 121 monitored by ACD logic unit 102.

[0048] In at least some embodiments, external processor 116 and / or processor 106 determine whether ACD logic unit 102 is operating correctly (e.g., when ACD logic unit 102 is used during safety-critical operation). For example, ACD logic unit 102 may monitor one or more power supply voltages and / or the frequency of input clock signal 105 as described herein, and may generate an output clock signal 115 with a reduced frequency when the power supply voltage is outside a corresponding power supply voltage range. In some examples, ACD logic unit 102 may monitor input clock signal 105, and may generate an output clock signal 115 with a reduced frequency when the frequency of input clock signal 105 is outside a corresponding clock frequency range. Furthermore, as described herein, external processor 116 may perform read operations via communication bus 119 to read event count values ​​from event count counter 103A, and / or read event duration values ​​from event duration counter 103B. External processor 116 may compare the event count values ​​to corresponding ranges. Each corresponding range may be defined by a threshold 180C stored in memory device 180. Similarly, the external processor 116 can compare the event duration value with a corresponding range. If the event count value and / or the event duration value are outside their corresponding range, the external processor 116 can generate an ACD status signal 129 as described herein.

[0049] In some examples, external processor 116 (or in some examples, processor 106) determines a threshold based on characterizing the activation of ACD logic unit 102 during the startup calibration process. For example, at startup, SoC 101 may cause first security logic unit 110, second security logic unit 112, and third security logic unit 114 to perform corresponding operations, such as performing corresponding security-critical applications. These operations may be performed for a predetermined amount of time. At the end of the startup calibration process, external processor 116 may determine the number of ACD logic unit 102 activations, including event count values ​​from event count counter 103A and / or event duration values ​​from event duration counter 103B, as described herein. External processor 116 may determine the threshold based on the event count values ​​and / or event duration values. For example, external processor 116 may determine the minimum value of the range as zero (e.g., no event) and the maximum value of the range as a percentage of the corresponding event value (e.g., 110%). External processor 116 may store the minimum and maximum values ​​within a threshold 180C of memory device 180.

[0050] In some examples, and based on event count values ​​and / or event duration values, external processor 116 can determine the minimum voltage (V) that voltage logic unit 120 should provide to each of one or more voltage rails 121. MIN For example, external processor 116 may determine an event range into which an event count value or event duration value (or, for example, the sum of both) falls. Each of the event ranges may be associated with a minimum voltage. Based on the determined event range, external processor 116 determines the corresponding minimum voltage. External processor 116 may also generate a message including a value characterizing the minimum voltage and may send this message to processor 106. In response to receiving the message, processor 106 writes the value characterizing the minimum voltage to a configuration storage location of voltage logic unit 120, which is established based on the power supply voltage provided on each of one or more voltage rails 121. In some examples, external processor 116 may write this value to the configuration storage location of voltage logic unit 120.

[0051] Figure 2A and Figure 2B Examples Figure 1 An exemplary portion of the integrated circuit package 100. For example, Figure 2A An exemplary clock test of ACD logic unit 102 is illustrated, and Figure 2B An exemplary voltage test of ACD logic unit 102 is illustrated. Voltage tests and clock tests can be performed simultaneously, serially, or sequentially.

[0052] like Figure 2AAs illustrated, to perform a clock test, processor 106 may send clock adjustment data 201 to clock logic unit 104. Clock adjustment data 201 may cause clock logic unit 104 to generate input clock signal 105 at a specific frequency. For example, clock adjustment data 201 may include one or more values ​​from one or more configuration storage locations of clock logic unit 104 that establish the frequency of input clock signal 105. Furthermore, the established frequency may be higher than a clock frequency threshold expected to activate ACD logic unit 102.

[0053] Based on the received input clock signal 105, ACD logic unit 102 generates an output clock signal 115. If ACD logic unit 102 operates correctly and is activated, it generates the output clock signal 115 at a frequency less than that of the input clock signal 105. Otherwise, if ACD logic unit 102 does not operate correctly and fails to activate, it may transmit the input clock signal 105 as the output clock signal 115, or it may provide the output clock signal 115 at an incorrect frequency.

[0054] Furthermore, if ACD logic unit 102 is indeed activated, it generates an ACD event signal 131, which is received by counter logic unit 103. As described herein, counter logic unit 103 may increment one or more counters based on the ACD event signal 131. In this example, when ACD event signal 131 indicates an event (i.e., ACD logic unit 102 is activated), counter logic unit 103 increments the clock frequency of event counter 202 (e.g., event count counter 103A).

[0055] refer to Figure 2B To perform a voltage test, processor 106 may send voltage adjustment data 221 to voltage logic unit 120. Voltage adjustment data 221 may cause voltage logic unit 120 to provide (e.g., via voltage rail 121) a power supply voltage 223 that is lower than the voltage level at which ACD logic unit 102 should be activated. For example, voltage adjustment data 221 may include one or more values ​​from one or more configuration storage locations of voltage logic unit 120 that establish the voltage level of power supply voltage 223. Furthermore, the established voltage level of power supply voltage 223 may be lower than the minimum voltage level at which ACD logic unit 102 is expected to activate (e.g., ACD logic unit 102 is expected to activate at or below the voltage level).

[0056] Based on the received power supply voltage 223, ACD logic unit 102 generates an output clock signal 115. If ACD logic unit 102 operates correctly and is activated because it detects that the power supply voltage 223 is below a minimum voltage level, then ACD logic unit 102 generates the output clock signal 115 at a frequency less than that of the input clock signal 105. Otherwise, if ACD logic unit 102 does not operate correctly and fails to activate, then ACD logic unit 102 transmits the input clock signal 105 as the output clock signal 115.

[0057] Furthermore, if ACD logic unit 102 is indeed activated, it generates an ACD event signal 131, which is received by counter logic unit 103. In this example, when ACD event signal 131 indicates an event (i.e., ACD logic unit 102 is activated), counter logic unit 103 increments the voltage event counter 224 (e.g., event count counter 103A).

[0058] Figure 3A and Figure 3B Examples Figure 1 An exemplary portion of the integrated circuit package 100. (Refer to...) Figure 3A The counter logic unit 103 includes an activation counter 302 that increments in response to any ACD activation indicated by an ACD event signal 131. For example, during a voltage test, the ACD logic unit 102 may generate the ACD event signal 131 to indicate an event in response to detecting a drop in the supply voltage (e.g., the supply voltage provided on voltage rail 121) below a corresponding voltage threshold. Similarly, the ACD logic unit 102 may generate the ACD event signal 131 to indicate an event during a clock test in response to detecting an increase in the frequency of an input clock signal (e.g., input clock signal 105) above a corresponding clock frequency threshold. To determine the activation event count, an external processor 116 may read the activation counter 302 to obtain activation count data 303. In some examples, the processor 106 reads the activation counter 302 to obtain activation count data 303, and the activation counter 302 requests and receives the activation count data 303 from the processor 106. The activation count data 303 identifies the activation count (i.e., the number of times the ACD logic unit 102 has been activated within a time interval). In some examples, when read, the activation counter 302 is reset to its initial value (e.g., reset to zero).

[0059] In some examples, and during testing of ACD logic unit 102 (e.g., performing voltage and clock tests), external processor 116 may periodically read activation counter 302 to obtain activation count data 303. For example, external processor 116 may read activation counter 302 at the end of each voltage or clock test. External processor 116 may also compare the activation count identified by activation count data 303 with a corresponding range (e.g., as defined by threshold 180C in memory device 180). If the activation count is not within the corresponding range, external processor 116 may generate ACD status signal 129 as described herein. For example, if ten voltage tests are to be performed (e.g., the supply voltage is reduced and returned to the nominal voltage level ten times), the activation count may be expected to be ten. For example, the corresponding range could then be eight to twelve. If the activation count read at the end of the ten tests is not within the range of eight to twelve, external processor 116 may generate ACD status signal 129 to indicate an error in ACD logic unit 102.

[0060] In at least some of the embodiments described herein, the external processor 116 may determine whether the ACD logic unit 102 is operating correctly during operation (e.g., when the ACD logic unit 102 is used during safety-critical operation). For example, when the ACD logic unit 102 is monitoring the power supply voltage and / or the input clock signal frequency to determine whether to reduce the frequency of the output signal clock as described herein, the external processor 116 may periodically (e.g., periodically) read the activation counter 302 to obtain activation count data 303. In some cases, the external processor may periodically read the activation counter 302 at any rate from every 10 milliseconds to every 35 milliseconds (inclusive). For example, the external processor 116 may read the activation counter 302 every 10 milliseconds. For each read of the activation counter 302, the external processor 116 may compare the activation count identified by the activation count data 303 with a corresponding range (e.g., as defined by a threshold 180C in the memory device 180) and may generate an ACD status signal 129 based on this comparison. For example, the corresponding range may include a minimum value (e.g., zero) and a maximum value (e.g., greater than zero). If the activation count is not greater than or equal to the minimum value and not less than or equal to the maximum value, the external processor 116 may generate an ACD status signal 129 to indicate an error as described herein.

[0061] exist Figure 3BIn addition to the activation counter 302, the counter logic unit 103 also includes a timer 304. The timer 304 can be programmed by the processor 106. For example, the processor 106 can perform a write operation to write timer data 305 to the timer 304. The timer data 305 can characterize a time amount (e.g., 10 milliseconds to 35 milliseconds). When programmed, the timer 304 can delay the programmed time amount, and when the programmed time amount expires, a timer expiration signal can be generated. In response to detecting the timer expiration signal, the counter logic unit 103 reads the activation counter 302 to obtain the activation count. Furthermore, the counter logic unit 103 can compare the activation count identified by the activation count data 303 with a corresponding range (e.g., the processor 106 can program it into an additional storage location of the counter logic unit 103), and can generate an ACD status signal 129 based on this comparison. For example, when the activation count is outside the corresponding range, the counter logic unit 103 can generate the ACD status signal 129. For example, when the activation count data 303 is equal to or higher than the first threshold but lower than the second threshold, the ACD status signal 129 can indicate FUSA_WARNING, and when the activation count data 303 is equal to or higher than the second threshold, the ACD status signal can indicate FUSA_ERROR.

[0062] Figure 4A and Figure 4B Examples Figure 1 An exemplary portion of the integrated circuit package 100. (Refer to...) Figure 4A The counter logic unit 103 includes one or more duration counters 402 that periodically increment (e.g., every nanosecond, every microsecond, every 10 microseconds, etc.) when the ACD event signal 131 indicates an event. For example, as described herein, the ACD logic unit 102 may generate the ACD event signal 131 to indicate an event when it detects that the supply voltage is below a corresponding voltage threshold, or when it detects that the frequency of an input clock signal is above a corresponding frequency threshold. In one example, the duration counter 402 is configured to measure the duration count of a single active event. For example, the duration counter 402 may include a counter and a FIFO. Upon receiving the ACD event signal 131 indicating an event, the duration counter 402 begins to increment periodically from an initial value (e.g., zero) until the ACD event signal 131 indicates no event. When the ACD event signal 131 indicates no event, the value in the duration counter 402 is stored in the FIFO. The duration counter 402 is then reset and increments from its initial value (e.g., zero) in response to an additional event such as that indicated by the ACD event signal 131. When the duration counter 402 is read, the value within the FIFO is provided.

[0063] In another example, duration counter 402 is configured to measure the duration count of multiple active events. For example, duration counter 402 may periodically increment until ACD event signal 131 indicates no event. Once ACD event signal 131 indicates an additional event, duration counter 402 continues to periodically increment (e.g., without resetting). Duration counter 402 may be reset upon reading (e.g., by an external processor 116).

[0064] To determine the duration event count, external processor 116 may read duration counter 402 to obtain duration count data 403. Duration count data 403 characterizes the amount of time during which ACD logic unit 102 is activated (e.g., during one activation event or during multiple activation events). In some examples, when read, duration counter 402 is reset to its initial value (e.g., reset to zero).

[0065] In some examples, and during testing of ACD logic unit 102 (e.g., performing voltage and clock tests), external processor 116 may periodically read duration counter 402 to obtain duration count data 403. For example, external processor 116 may read duration counter 402 at the end of each voltage or clock test. External processor 116 may also compare the duration count identified by duration count data 403 with a corresponding range (e.g., as defined by threshold 180C in memory device 180). If the duration count is not within the corresponding range, external processor 116 may generate ACD status signal 129 to indicate an ACD logic unit 102 event as described herein.

[0066] In at least some of the embodiments described herein, ACD logic unit 102 may be monitored during operation (e.g., when ACD logic unit 102 is used during safety-critical operation). For example, when ACD logic unit 102 is monitoring the power supply voltage and / or input clock signal frequency to determine whether to reduce the frequency of the output signal clock as described herein, external processor 116 may periodically (e.g., periodically) read duration counter 402 to obtain duration count data 403. In some cases, external processor 116 may periodically read duration counter 402 at any rate from every 10 milliseconds to every 35 milliseconds (inclusive). For example, external processor 116 may read duration counter 402 every 10 milliseconds. For each read of duration counter 402, external processor 116 may compare the duration count identified by duration count data 403 with a corresponding range (e.g., as defined by threshold 180C in memory device 180) and may generate ACD status signal 129 based on this comparison. For example, the corresponding range may include a minimum value and a maximum value. If the duration count is not greater than or equal to the minimum value and not less than or equal to the maximum value, the external processor 116 may generate an ACD status signal 129 to indicate an error as described herein.

[0067] exist Figure 4B In addition to the duration counter 402, the counter logic unit 103 also includes a timer 404. The timer 404 can be programmed by the processor 106. For example, the processor 106 can perform a write operation to write timer data 405 to the timer 404. The timer data 405 can characterize a time amount (e.g., 10 milliseconds to 35 milliseconds). When programmed, the timer 404 can delay the programmed time amount, and when the programmed time amount expires, a timer expiration signal can be generated. In response to detecting the timer expiration signal, the counter logic unit 103 can read the duration counter 402 to obtain a duration count. Furthermore, the counter logic unit 103 can compare the duration count identified by the duration count data 403 with a corresponding range (e.g., the processor 106 can program it into an additional storage location of the counter logic unit 103), and can generate an ACD status signal 129 based on this comparison. For example, the counter logic unit 103 can generate the ACD status signal 129 when the duration count is outside its corresponding range.

[0068] Figure 5A , Figure 5B and Figure 5C Examples Figure 1 An exemplary portion of the integrated circuit package 100. In these examples, the output clock signal 115 from the ACD logic unit 102 is monitored to detect errors. For example, refer to...Figure 5A The ACD logic unit 102 receives an input clock signal 105 from the clock logic unit 104, and when the ACD logic unit 102 is activated, generates an output clock signal 115 at a frequency lower than that of the input clock signal 105. As described herein, for example, the ACD logic unit 102 may divide the input clock signal 105 by a factor to generate the output clock signal 115. In this example, the counter logic unit 103 receives the output clock signal 115, which is also provided to the first security logic unit 110, the second security logic unit 112, and the third security logic unit 114. The counter logic unit 103 detects when the output clock signal 115 operates at a lower frequency and, in response, periodically increments a decreasing clock counter 502. For example, when the output clock signal 115 is detected to be operating at a lower frequency, the counter logic unit 103 may increment the decreasing clock counter 502 every microsecond.

[0069] Furthermore, the counter logic unit 103 can compare the value within the reduced clock counter 502 with a reduced clock threshold (e.g., defined by a threshold 180C stored in memory device 180 and programmed into the counter logic unit 103 by processor 106), and can generate an ACD status signal 129 when the value exceeds the reduced clock threshold. In some examples, the counter logic unit 103 generates the ACD status signal 129 to indicate a "warning" to the ACD logic unit 102 when the value is equal to or higher than a first reduced clock threshold but lower than a second reduced clock threshold, and generates the ACD status signal 129 to indicate an "error" to the ACD logic unit 102 when the value is equal to or higher than the second reduced clock threshold.

[0070] like Figure 5BAs illustrated, in some cases, the counter logic unit 103 includes two clock counters, wherein a first clock counter 511 increments based on an input clock signal 105, and a second clock counter 513 increments based on an output clock signal 115. The clock logic unit 103 may also include a timer 515 that defines a time interval. When the timer expires, the clock logic unit 103 can read the first clock counter 511 to obtain the input clock count and can read the second clock counter 513 to obtain the output clock count. The clock logic unit 103 can determine the difference between the input clock count and the output clock count and can compare this difference with one or more clock count thresholds, which can be programmed into a clock count threshold register 517. The counter logic unit 103 can generate an ACD status signal 129 based on this comparison. For example, when the difference is equal to or higher than the first clock count threshold but lower than the second clock count threshold, the counter logic unit 103 can generate an ACD status signal 129 to indicate "warning" to the ACD logic unit 102, and when the difference is equal to or higher than the second clock count threshold, it can generate an ACD status signal 129 to indicate "error" to the ACD logic unit 102.

[0071] about Figure 5C And as regarding Figure 5A As described, ACD logic unit 102 receives input clock signal 105 from clock logic unit 104, and when ACD logic unit 102 is activated, generates output clock signal 115 at a frequency lower than that of input clock signal 105. However, in this example, processor 106 receives output clock signal 115 and determines the duration for which output clock signal 115 remains at the lower frequency. For example, processor 106 may receive output clock signal 115 on an input / output (I / O) pin.

[0072] Additionally, processor 106 can sample the output clock signal 115 to determine whether the frequency of the output clock signal 115 is at the nominal level or at a reduced level. As an example, assume the output clock signal 115 operates at the nominal frequency. Processor 106 can periodically sample the output clock signal 115 (e.g., at twice the nominal frequency) to determine that the output clock signal 115 operates at the nominal frequency. Furthermore, assume the ACD logic unit 102 is activated (e.g., in response to a detected power supply voltage drop event, during a voltage test, etc.) and the frequency of the output clock signal 115 is reduced, such as to half the nominal frequency.

[0073] Processor 106, which continues to periodically sample the output clock signal 115, can determine that the frequency of the output clock signal 115 has decreased. In response to this determination, processor 106 can begin maintaining data in a storage location (e.g., an internal memory device) characterizing how long the output clock signal 115 has decreased. For example, whenever processor 106 samples the output clock signal 115 and determines that the frequency of the output clock signal 115 remains decreasing, processor 106 can increment a duration count in a register. Processor 106 can continue updating the duration count in the register until processor 106 determines that the output clock signal 115 is operating at the nominal frequency.

[0074] When processor 106 determines that output clock signal 115 operates at a reduced frequency until processor 106 determines that the frequency of output clock signal 115 returns to the nominal level, processor 106 may compare a duration count with a reduced clock threshold (e.g., as defined by threshold 180C stored in memory device 180 and programmed into counter logic unit 103 by processor 106), and may generate an ACD status signal 129 when the duration count exceeds the reduced clock threshold. In some examples, processor 106 generates ACD status signal 129 to indicate a "warning" to ACD logic unit 102 when the duration count is equal to or higher than a first reduced clock threshold but lower than a second reduced clock threshold, and generates ACD status signal 129 to indicate an "error" to ACD logic unit 102 when the value is equal to or higher than the second reduced clock threshold.

[0075] refer to Figure 6A The processor 106 can perform operations to determine the voltage level that the voltage logic unit 120 should provide to the voltage rail 121 (e.g., at startup). For example, the processor 106 can write a first value 601 to the V of the voltage logic unit 120. MINRegister 602 (e.g., via communication bus 123) enables voltage logic unit 120 to supply a first voltage to voltage rail 121. Furthermore, first safety logic unit 110, second safety logic unit 112, and third safety logic unit 114 can perform corresponding operations. For example, first safety logic unit 110, second safety logic unit 112, and third safety logic unit 114 perform corresponding safety-critical applications. These operations can be performed for a predetermined amount of time. At the end of the predetermined amount of time, processor 106 can obtain count data 605 from counter logic unit 103. Count data 605 may include one or more event count values ​​from event count counter 103A and / or event duration values ​​from event duration counter 103B, as described herein. Processor 106 can then compare count data 605 (e.g., one or more event count values ​​and / or event duration values) with corresponding thresholds. For example, processor 106 can obtain decreasing threshold data 607 characterizing the threshold from memory device 603. Furthermore, processor 106 can determine whether each value included in count data 605 exceeds its corresponding threshold. If one or more event count values ​​and / or event duration values ​​do not exceed the corresponding threshold, the operation to determine the voltage level is complete.

[0076] However, if one or more event count values ​​and / or event duration values ​​exceed their corresponding thresholds, the processor 106 can write the second value 601 into the V of the voltage logic unit 120. MIN Register 602 is used to enable voltage logic unit 120 to provide a second voltage to voltage rail 121. The second voltage may be greater than the first voltage. First safety logic unit 110, second safety logic unit 112, and third safety logic unit 114 can then re-execute the corresponding operation for a predetermined amount of time, wherein processor 106 retrieves the event count value and / or event duration value from event count counter 103A and event duration counter 103B at the end of the predetermined amount of time. Processor 106 again compares one or more event count values ​​and / or event duration values ​​with corresponding thresholds to determine whether a further increase in the power supply voltage is needed. The above operation is repeated until a voltage level is determined. In some examples, the operation is complete once the voltage level reaches the threshold level.

[0077] refer to Figure 6BIn some examples, a test procedure is performed during startup (e.g., power-on) to verify the functionality and / or calibration of ACD logic unit 102. For example, at startup, processor 106 may obtain data (e.g., calibration data) characterizing target frequency 623 and target voltage 625 from memory device 603. Processor 106 may write target voltage 625 to voltage logic unit 120 (e.g., via communication bus 123) to cause voltage logic unit 120 to provide the target voltage on voltage rail 121. The processor may also write target frequency 623 to clock logic unit 104 (e.g., via communication bus 107) to cause clock logic unit 104 to generate input clock signal 105 at the target frequency.

[0078] In some examples, processor 106 may use circuitry within ACD logic unit 102 to trigger ACD circuit calibration. The automatic calibration circuitry generates a code indicating the calibration value. Furthermore, processor 106 may obtain ACD calibration value 627 from memory device 603. Processor 106 can then compare the generated new calibration value with a previous calibration value stored in memory 603. If the difference between the obtained new calibration value and the previous calibration value stored in memory 603 is within a pre-configured calibration range, the test process is considered successful. This means that the ACD calibration value is valid for the correct operation of ACD logic unit 102. Otherwise, if the difference between the new calibration value and the previous calibration value is not within the pre-configured calibration range, the test process is considered to have failed. Therefore, processor 106 may generate ACD test data 629 indicating a calibration test process failure. In some examples, as described herein, processor 106 may write to one or more configuration registers of voltage logic unit 120 to increase the minimum voltage supplied to voltage rail 121 as a way to obtain a new calibration value within a desired range (e.g., within a pre-configured calibration margin threshold), and the test procedure may be performed again. In some examples, when the startup test fails, processor 106 may disable ACD logic unit 102, and as possible mitigation, one or more configuration registers of voltage logic unit 120 may be written to increase the minimum voltage supplied to voltage rail 121 to prevent voltage drop events. In some examples, the test procedure described above for the startup test of ACD logic unit 102 calibration is performed for all valid operating voltage and operating frequency combinations of target safety logic units 110, 112, and 114.

[0079] As an additional or alternative test, in some examples, the first security logic unit 110, the second security logic unit 112, and the third security logic unit 114 may perform corresponding operations for a predetermined amount of time. For example, the first security logic unit 110, the second security logic unit 112, and the third security logic unit 114 may include one or more processors that execute instructions stored in an internal memory device. For example, these instructions may characterize a test application. At the end of the predetermined amount of time, the processor 106 obtains count data 605 from the counter logic unit 103, including an event count value from the event count counter 103A and / or an event duration value from the event duration counter 103B. Furthermore, the processor 106 may obtain an ACD calibration value 627 from the memory device 603 and may compare the count data 605 with the ACD calibration value 627 to determine whether the ACD logic unit 102 is operating correctly. For example, the processor 106 may determine the difference between each of the event count values ​​and / or event duration values ​​and its corresponding ACD calibration value 627. If each of the differences is less than a first predetermined amount (e.g., two), processor 106 generates ACD test data 629 indicating that the ACD test has passed (e.g., ACD logic unit 102 is operating correctly). However, if one or more differences are equal to or greater than the first predetermined amount and less than the second predetermined amount, processor 106 writes to voltage logic unit 120 as described herein to raise the power supply voltage level. For example, processor 106 may write to a register of voltage logic unit 120 to cause voltage logic unit 120 to raise the power supply voltage level by 0.3 volts. Processor 106 may generate ACD test data 629 to indicate that the power supply voltage has risen to allow ACD logic unit 102 to operate. If one or more differences are equal to or greater than the second predetermined amount, processor 106 generates ACD test data 629 indicating that the ACD test has failed (e.g., ACD logic unit 102 is not operating correctly). In some examples, processor 106 may perform an operation to disable ACD logic unit 102 activation when one or more differences are equal to or greater than the second predetermined amount.

[0080] Processor 106 may send ACD test data 629 to external processor 116 (e.g., via communication bus 119). In response to receiving ACD test data 629, external processor 116 may generate ACD status signal 129. For example, if ACD test data 629 indicates that ACD logic unit 102 is not operating correctly, external processor 116 may generate ACD status signal 129 to indicate that ACD logic unit 102 is not operating correctly, as described herein.

[0081] Figure 7This is a flowchart of an exemplary process 700 for testing adaptive clock distribution logic components according to some exemplary embodiments. For example, one or more die packages (such as integrated circuit package 100) may perform one or more operations of the exemplary process 700.

[0082] refer to Figure 7 At block 702, a first signal is sent to adjust the operating conditions of the adaptive clock allocation logic unit from a first state to a second state. For example, and as described herein, processor 106 may write to one or more memory locations of clock logic unit 104 to cause clock logic unit 104 to increase the frequency of the input clock signal 105 received by ACD logic unit 102 from the nominal frequency to an increase equal to or higher than the frequency at which ACD logic unit 102 is expected to activate. Additionally or alternatively, processor 106 may write to one or more memory locations of voltage logic unit 120 to cause voltage logic unit 120 to decrease the supply voltage received by ACD logic unit 102 on voltage rail 121. The supply voltage decreases from the nominal voltage level to a decreased voltage level lower than the voltage level at which ACD logic unit 102 is expected to activate. At block 704, the adaptive clock allocation logic unit is allowed to operate for a predetermined amount of time. For example, during a predetermined time period, the first safety logic unit 110, the second safety logic unit 112, and the third safety logic unit 114 can perform corresponding operations to draw current from the voltage rail 121.

[0083] Proceeding to block 706, a second signal is sent to adjust the operating conditions of the adaptive clock allocation logic unit from a second state to a first state. For example, processor 106 may write to one or more memory locations of clock logic unit 104 to cause clock logic unit 104 to reduce the frequency of input clock signal 105 back to the nominal frequency. Additionally or alternatively, processor 106 may write to one or more memory locations of voltage logic unit 120 to cause voltage logic unit 120 to increase the supply voltage back to the nominal voltage level. At block 708, an event count is read from the counter register of the adaptive clock allocation logic unit. For example, processor 106 may read one or more of the event count counter 103A and event duration counter 103B of counter logic unit 103 to determine the event count.

[0084] Furthermore, at block 710, the state of the adaptive clock allocation logic unit is determined based on event counts. For example, processor 106 may compare one or more values ​​read from event count counter 103A and / or event duration counter 103B with corresponding thresholds to determine whether ACD logic unit 102 is operating correctly. Based on this state, a third signal is sent at block 712. For example, processor 106 may send an ACD status signal 129 based on determining whether ACD logic unit 102 is operating correctly.

[0085] Figure 8 This is a flowchart of an exemplary process 800 for monitoring adaptive clock distribution logic components according to some exemplary embodiments. For example, one or more die packages (such as integrated circuit package 100) may perform one or more operations of the exemplary process 800.

[0086] refer to Figure 8 At block 802, instructions characterizing the workload are executed for a predetermined amount of time. For example, and as described herein, one or more of the first security logic unit 110, the second security logic unit 112, and the third security logic unit 114 may include a processor that executes instructions for a predetermined amount of time. The workload may be, for example, a test workload running at startup, or a workload running during normal operation. At block 804, an event count is read from the counter register of the adaptive clock allocation logic unit. For example, processor 106 may read the event count from one or more of the event count counter 103A and the event duration counter 103B of the counter logic unit 103.

[0087] Additionally, at block 806, a threshold event count is read from a memory device. For example, processor 106 may read one or more thresholds 180C characterizing the threshold event count from memory device 180. Based on the event count and the threshold event count, at block 808, the ACD state of the adaptive clock allocation logic unit is determined based on the event count and the threshold count. For example, as described herein, processor 106 may compare the event count with the threshold count and may determine the ACD state (e.g., test state value 180D) based on that comparison. In some examples, if the event count is equal to or greater than the threshold count, processor 106 may generate an ACD state to indicate that ACD logic unit 102 is not operating correctly. Otherwise, if the event count is less than the threshold count, processor 106 may generate an ACD state to indicate that ACD logic unit 102 is operating correctly. In some examples, after reading the event count from the count register, processor 106 clears the count register (e.g., processor 106 writes zero to the count register).

[0088] At block 810, processor 106 determines whether to report the ACD status. For example, if the ACD status indicates that ACD logic unit 102 is not operating correctly, processor 106 may determine to report the ACD status. If the ACD status indicates that ACD logic unit 102 is operating correctly, processor 106 may determine not to report the ACD status. If no ACD status is reported, the method returns to block 802 to continue monitoring ACD logic unit 102. However, if an ACD status report is to be made, the method proceeds to block 812. In some examples, processor 106 determines to report the ACD status after the ACD logic unit has been determined to be operating incorrectly multiple times. For example, processor 106 may determine to report the ACD status after the event count exceeds a threshold count three times within a predetermined time interval. At block 812, a signal indicating the ACD status is sent. For example, processor 106 may send an ACD status signal 129 to another device. In response, the other device may display a warning message indicating that ACD logic unit 102 is not operating correctly, or may perform an operation to disable ACD logic unit 102. In some examples, processor 106 sends a signal to ACD logic unit 102 to disable future ACD activation.

[0089] Specific implementation examples are further described in the following numbered clauses: 1. A die package, the die package comprising: An adaptive clock allocation logic unit, wherein the adaptive clock allocation logic unit is configured to: Detect activation events; and Based on the detection of the activation event, increment the event count in the register; and The processor, electrically coupled to the adaptive clock allocation logic unit, is configured to: Access the register and read the event count within the register; Compare the event count with the threshold count value; and Based on the comparison, a signal is sent to at least one component electrically coupled to the die package.

[0090] 2. The die package according to Clause 1, wherein the processor is configured to send the signal to the at least one component when the event count exceeds the threshold count value.

[0091] 3. The die package as described in Clause 2, wherein the processor is configured to disable the adaptive clock allocation logic when the event count exceeds the threshold count value.

[0092] 4. The die package according to any one of Clauses 1 to 3, wherein the event count represents the number of adaptive clock distribution logic components activated within a time period.

[0093] 5. The die package according to any one of Clauses 1 to 4, wherein the event count characterizes the duration of activation of the adaptive clock allocation logic unit.

[0094] 6. A die package according to any one of clauses 1 to 5, the die package including a clock logic component configured to provide a clock signal to the adaptive clock allocation logic component, wherein the adaptive clock allocation logic component is configured to detect the activation event when the frequency of the clock signal is greater than a threshold frequency.

[0095] 7. The die package according to Clause 6, wherein the adaptive clock allocation logic is configured to detect the activation event when the frequency of the clock signal is greater than the threshold frequency for a minimum duration.

[0096] 8. A die package according to any one of clauses 1 to 7, the die package including a voltage logic component configured to provide a voltage to the adaptive clock distribution logic component, wherein the adaptive clock distribution logic component is configured to detect the activation event when the voltage is less than a threshold voltage level.

[0097] 9. The die package according to Clause 8, wherein the adaptive clock allocation logic is configured to detect the activation event when the voltage is less than the threshold voltage level for a minimum duration.

[0098] 10. A die package according to any one of clauses 1 to 9, wherein the processor is configured to: The workload was completed within the predetermined timeframe; and After the predetermined time interval, the register of the adaptive clock allocation logic unit is accessed and read.

[0099] 11. A method performed by a processor, the method comprising: Access the register of the adaptive clock allocation logic unit, which is configured to increment the event count in the register based on the detection of an activation event, and read the event count in the register; Compare the event count with the threshold count value; and Based on the comparison, a signal is sent to at least one device.

[0100] 12. The method according to Clause 11, the method further comprising sending the signal to the device when the event count exceeds the threshold count value.

[0101] 13. The method according to Clause 12, the method further comprising disabling the adaptive clock allocation logic when the event count exceeds the threshold count value.

[0102] 14. The method according to any one of clauses 11 to 13, wherein the event count represents the number of adaptive clock allocation logic components activated within a time period.

[0103] 15. The method according to any one of clauses 11 to 14, wherein the event count characterizes the duration of activation of the adaptive clock allocation logic unit.

[0104] 16. The method according to any one of clauses 11 to 15, the method further comprising setting the frequency of a clock signal to be greater than a threshold frequency, causing the adaptive clock allocation logic component to detect the activation event.

[0105] 17. The method according to any one of clauses 11 to 16, the method further comprising setting a voltage level less than a threshold voltage level to cause the adaptive clock allocation logic unit to detect the activation event.

[0106] 18. The method according to any one of clauses 11 to 17, wherein the method further comprises: The workload was completed within the predetermined timeframe; and After the predetermined time interval, the register of the adaptive clock allocation logic unit is accessed and read.

[0107] 19. A non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium comprising instructions that, when executed by at least one processor, cause the at least one processor to: Access the register of the adaptive clock allocation logic unit, which is configured to increment the event count in the register based on the detection of an activation event, and read the event count in the register; Compare the event count with the threshold count value; and Based on the comparison, a signal is sent to at least one device.

[0108] 20. The non-transitory machine-readable storage medium according to Clause 19, wherein the instructions, when executed by the at least one processor, cause the at least one processor to send the signal to at least one component when the event count exceeds the threshold count value.

[0109] 21. The non-transitory machine-readable storage medium according to Clause 20, wherein the instructions, when executed by the at least one processor, cause the at least one processor to disable the adaptive clock allocation logic unit when the event count exceeds the threshold count value.

[0110] 22. The non-transitory machine-readable storage medium according to any one of Clauses 19 to 21, wherein the event count represents the number of adaptive clock allocation logic units activated within a time period.

[0111] 23. The non-transitory machine-readable storage medium according to any one of Clauses 19 to 22, wherein the event count characterizes the duration of activation of the adaptive clock allocation logic unit.

[0112] 24. A non-transitory machine-readable storage medium according to any one of clauses 19 to 23, wherein the instructions, when executed by the at least one processor, cause the at least one processor to set the frequency of a clock signal to be greater than a threshold frequency, thereby causing the adaptive clock allocation logic unit to detect the activation event.

[0113] 25. A non-transitory machine-readable storage medium according to any one of clauses 19 to 24, wherein the instructions, when executed by the at least one processor, cause the at least one processor to set a voltage level less than a threshold voltage level, thereby causing the adaptive clock allocation logic unit to detect the activation event.

[0114] 26. A non-transitory machine-readable storage medium according to any one of clauses 19 to 25, wherein the instructions, when executed by the at least one processor, cause the at least one processor to: The workload was completed within the predetermined timeframe; and After the predetermined time interval, the register of the adaptive clock allocation logic unit is accessed and read.

[0115] 27. An apparatus comprising: Memory, which stores instructions; and At least one processor, communicatively coupled to the memory and configured to execute the instructions to: Access the register of the adaptive clock allocation logic unit, which is configured to increment the event count in the register based on the detection of an activation event, and read the event count in the register; Compare the event count with the threshold count value; and Based on the comparison, a signal is sent to at least one device.

[0116] 28. The apparatus according to Clause 27, wherein the processor is configured to send the signal to the at least one component when the event count exceeds the threshold count value.

[0117] 29. The apparatus according to Clause 28, wherein the processor is configured to disable the adaptive clock allocation logic when the event count exceeds the threshold count value.

[0118] 30. The apparatus according to any one of clauses 27 to 29, wherein the event count represents the number of adaptive clock allocation logic components activated within a time period.

[0119] 31. The apparatus according to any one of clauses 27 to 30, wherein the event count characterizes the duration of activation of the adaptive clock allocation logic component.

[0120] 32. The apparatus according to any one of clauses 27 to 31, the apparatus comprising a clock logic component configured to provide a clock signal to the adaptive clock allocation logic component, wherein the adaptive clock allocation logic component is configured to detect the activation event when the frequency of the clock signal is greater than a threshold frequency.

[0121] 33. The apparatus according to clause 32, wherein the adaptive clock allocation logic component is configured to detect the activation event when the frequency of the clock signal is greater than the threshold frequency for a minimum duration.

[0122] 34. The apparatus according to any one of clauses 27 to 33, the apparatus comprising a voltage logic unit configured to provide a voltage to the adaptive clock allocation logic unit, wherein the adaptive clock allocation logic unit is configured to detect the activation event when the voltage is less than a threshold voltage level.

[0123] 35. The apparatus according to clause 34, wherein the adaptive clock allocation logic is configured to detect the activation event when the voltage is less than the threshold voltage level for a minimum duration.

[0124] 36. The apparatus according to any one of clauses 27 to 35, wherein the processor is configured to: The workload was completed within the predetermined timeframe; and After the predetermined time interval, the register of the adaptive clock allocation logic unit is accessed and read.

[0125] 37. A die package, the die package comprising: A clock logic component, configured to generate a clock signal; An adaptive clock allocation logic unit, electrically coupled to the clock logic unit and configured to: Receive the clock signal from the clock logic component; and When the frequency of the clock signal exceeds a threshold frequency level, the event count in the register is incremented; and The processor, electrically coupled to the clock logic unit and the adaptive clock allocation logic unit, is configured to: Send a first signal to the clock logic component, the first signal causing the clock signal to operate above the threshold frequency level; Access the register and read the event count within the register; The state of the adaptive clock allocation logic unit is determined based on the event count; and A second signal indicating the state of the adaptive clock allocation logic component is sent to at least one component electrically coupled to the die package.

[0126] 38. A method performed by a processor, the method comprising: A first signal is sent to the clock logic unit of the die, the first signal causing the clock signal output by the clock logic unit to operate above a threshold frequency level, the threshold frequency level causing the adaptive clock allocation logic unit of the die to increment the event count in the register; Access and read the event count in the register of the adaptive clock allocation logic unit of the die; The state of the adaptive clock allocation logic unit is determined based on the event count; and A second signal indicating the state of the adaptive clock allocation logic component is sent to at least one component electrically coupled to the die.

[0127] 39. A non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium comprising instructions that, when executed by at least one processor, cause the at least one processor to: A first signal is sent to the clock logic unit of the die, the first signal causing the clock signal output by the clock logic unit to operate above a threshold frequency level, the threshold frequency level causing the adaptive clock allocation logic unit of the die to increment the event count in the register; Access the register and read the event count within the register of the adaptive clock allocation logic unit of the die; The state of the adaptive clock allocation logic unit is determined based on the event count; and A second signal indicating the state of the adaptive clock allocation logic component is sent to at least one component electrically coupled to the die.

[0128] 40. A die package, the die package comprising: A voltage logic unit configured to supply voltage to a voltage rail; An adaptive clock allocation logic unit, electrically coupled to the voltage rail and configured to increment an event count in a register when the voltage fails to exceed a voltage threshold; and The processor, electrically coupled to the voltage logic unit and the adaptive clock allocation logic unit, is configured to: Send a first signal to the voltage logic component, the first signal causing the voltage to be adjusted below the voltage threshold; Access the register and read the event count within the register; The state of the adaptive clock allocation logic unit is determined based on the event count; and A second signal indicating the state of the adaptive clock allocation logic component is sent to at least one component electrically coupled to the die package.

[0129] 41. A method performed by a processor, the method comprising: A first signal is sent to the voltage logic unit of the die, the first signal causing the voltage output by the voltage logic unit to be adjusted below a voltage threshold, thereby causing the adaptive clock allocation logic unit of the die to increment the event count in the register; Access the register and read the event count within the register of the adaptive clock allocation logic unit of the die; The state of the adaptive clock allocation logic unit is determined based on the event count; and A second signal indicating the state of the adaptive clock allocation logic component is sent to at least one component electrically coupled to the die.

[0130] 42. A non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium comprising instructions that, when executed by at least one processor, cause the at least one processor to: A first signal is sent to the voltage logic unit of the die, the first signal causing the voltage output by the voltage logic unit to be adjusted below a voltage threshold, thereby causing the adaptive clock allocation logic unit of the die to increment the event count in the register; Access the register and read the event count within the register of the adaptive clock allocation logic unit of the die; The state of the adaptive clock allocation logic unit is determined based on the event count; and A second signal indicating the state of the adaptive clock allocation logic component is sent to at least one component electrically coupled to the die.

[0131] Although the method described above refers to the illustrated flowchart, many other ways can be used to perform the actions associated with this method. For example, the order of some operations can be changed, and some implementations can omit one or more of the described operations and / or include additional operations.

[0132] Furthermore, the methods and systems described herein can be embodied, at least in part, in the form of computer-implemented processes and apparatus for performing those processes. The disclosed methods can also be embodied, at least in part, in the form of a tangible, non-transitory machine-readable storage medium encoded with computer program code, which, when executed, causes a machine to manufacture at least one integrated circuit performing one or more of the operations described herein. For example, the method can be embodied in hardware, executable instructions (e.g., software) executed by a processor, or a combination of both. The medium may include, for example, RAM, ROM, CD-ROM, DVD-ROM, BD-ROM, hard disk drive, flash memory, or any other non-transitory machine-readable storage medium. When the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for causing a machine to manufacture an integrated circuit. The method can also be embodied, at least in part, in the form of a computer, with the computer program code loaded into or executed in the computer, making the computer a dedicated computer for causing a machine to manufacture an integrated circuit. For example, when implemented on a general-purpose processor, computer program code segments configure the processor to create specific logic circuits. The method can also alternatively be embodied, at least in part, in an application-specific integrated circuit (ASIC) or any other integrated circuit for performing the method.

[0133] Furthermore, terms such as "circuit" and "logic" may individually or in combination include analog circuits, digital circuits, hardwired circuits, programmable circuits, processing circuits, hardware logic circuits, state machine circuits, and any other suitable type of physical hardware component. Additionally, the embodiments described herein can be employed in a wide variety of devices, such as networking devices, telecommunications devices, smartphones, gaming devices, enterprise devices, storage devices (e.g., cloud storage devices), automotive systems (e.g., collision avoidance systems, object detection systems, navigation systems, etc.), and computing devices (e.g., cloud computing devices), as well as other types of devices.

[0134] The subject matter has been described with reference to exemplary embodiments. Because these are merely examples, the claimed invention is not limited to these embodiments. Changes and modifications may be made without departing from the spirit of the claimed subject matter. The claims are intended to cover such changes and modifications.

Claims

1. A die package comprising: adaptive clock distribution logic configured to: detect an activation event; and increment an event count within a register based on detecting the activation event; and a processor electrically coupled to the adaptive clock distribution logic and configured to: access the register and read the event count within the register; compare the event count to a threshold count value; and based on the comparison, send a signal to at least one component electrically coupled to the die package.

2. The die package of claim 1, wherein the processor is configured to send the signal to the at least one component when the event count exceeds the threshold count value.

3. The die package of claim 2, wherein the processor is configured to disable the adaptive clock distribution logic when the event count exceeds the threshold count value.

4. The die package of claim 1, wherein the event count characterizes a number of adaptive clock distribution logic activations within a time period.

5. The die package of claim 1, wherein the event count characterizes a duration of adaptive clock distribution logic activation.

6. The die package of claim 1, comprising a clock logic configured to provide a clock signal to the adaptive clock distribution logic, wherein the adaptive clock distribution logic is configured to detect the activation event when a frequency of the clock signal is greater than a threshold frequency.

7. The die package of claim 6, wherein the adaptive clock distribution logic is configured to detect the activation event when the frequency of the clock signal is greater than the threshold frequency for a minimum duration.

8. The die package of claim 1, comprising a voltage logic configured to provide a voltage to the adaptive clock distribution logic, wherein the adaptive clock distribution logic is configured to detect the activation event when the voltage is less than a threshold voltage level.

9. The die package of claim 8, wherein the adaptive clock distribution logic is configured to detect the activation event when the voltage is less than the threshold voltage level for a minimum duration.

10. The die package of claim 1, wherein the processor is configured to: execute a workload for a predetermined amount of time; after the predetermined amount of time, access and read the register of the adaptive clock distribution logic.

11. A method by a processor, the method comprising: accessing a register of adaptive clock distribution logic configured to increment an event count within the register based on detecting an activation event, and reading the event count within the register; comparing the event count to a threshold count value; and based on the comparison, sending a signal to at least one device.

12. The method of claim 11, further comprising sending the signal to the device when the event count exceeds the threshold count value.

13. The method of claim 12, further comprising disabling the adaptive clock distribution logic when the event count exceeds the threshold count value.

14. The method of claim 11, wherein the event count characterizes a number of adaptive clock distribution logic activations within a time period.

15. The method of claim 11, wherein the event count characterizes a duration of adaptive clock distribution logic activation.

16. The method of claim 11, further comprising setting a frequency of a clock signal to be greater than a threshold frequency, thereby causing the adaptive clock distribution logic to detect the activation event.

17. The method of claim 11, further comprising setting a voltage level to be less than a threshold voltage level, thereby causing the adaptive clock distribution logic to detect the activation event.

18. The method of claim 11, further comprising: executing a workload for a predetermined amount of time; after the predetermined amount of time, accessing and reading the register of the adaptive clock distribution logic.

19. A non-transitory machine-readable storage medium comprising instructions that, when executed by at least one processor, cause the at least one processor to: access a register of an adaptive clock distribution logic configured to increment an event count within the register based on detecting an activation event, and read the event count within the register; compare the event count to a threshold count value; and based on the comparison, send a signal to at least one device.

20. An apparatus comprising: a memory storing instructions; and at least one processor communicatively coupled to the memory and configured to execute the instructions to: access a register of an adaptive clock distribution logic configured to increment an event count within the register based on detecting an activation event, and read the event count within the register; compare the event count to a threshold count value; and based on the comparison, send a signal to at least one device. ​

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