Laminated ceramic electronic component

Abstract

The invention provides a laminated ceramic electronic component capable of coping with a larger current. A multilayer ceramic electronic component (100) according to the present invention is provided with a multilayer ceramic capacitor and a bonding electrode (40). The first main surface (12a) and the second main surface (12b) face each other in the stacking direction, the first surface (12c) and the second surface (12d) face each other in a first direction orthogonal to the stacking direction, and the third surface (12e) and the fourth surface (12f) face each other in a second direction orthogonal to the stacking direction and the first direction; and at least four or more external electrodes (30) disposed on any one of the first surface (12c), the second surface (12d), the third surface (12e), and the fourth surface (12f), and a bonding electrode (40) disposed on any one of the first main surface (12a) or the second main surface (12b) and electrically bonding at least two or more external electrodes having the same potential among the external electrodes (30) to each other. The multilayer ceramic capacitor is characterized in that when the DC resistance of the multilayer ceramic capacitor (10) is set to be Rdc1 and the DC resistance of the bonding electrode (40) is set to be Rdc3, Rdc1 < = Rdc3.

Description

TECHNICAL FIELD

[0001] The present application relates to a laminated ceramic electronic component. BACKGROUND

[0002] For example, as a decoupling capacitor used for stabilizing a power supply voltage supplied to an integrated circuit component (IC) operating at high speed, a noise countermeasure component for a power supply line supplied to an integrated circuit component (IC), a through-type 3-terminal capacitor is known. The through-type 3-terminal capacitor generally has a laminate having a first main surface and a second main surface facing each other, a first side surface and a second side surface facing each other, and a first end surface and a second end surface facing each other. Inside the laminate, a plurality of first internal electrode layers and second internal electrode layers are alternately arranged in a laminating direction. Further, both ends of the first internal electrode layers are led out to the first end surface and the second end surface, and both ends of the second internal electrode layers are led out to the first side surface and the second side surface. In addition, the first internal electrode layers are connected to a first external electrode and a second external electrode, and the second internal electrode layers are connected to a third external electrode and a fourth external electrode.

[0003] In the case where the general through-type 3-terminal capacitor is used as a noise filter, a direct current flows through the signal internal electrode (first internal electrode layer). However, if the capacitance is made low, the number of pieces of the signal internal electrode (first internal electrode layer) becomes small, and the direct current resistance becomes large, and thus there is a problem that heat generated from the capacitor becomes large.

[0004] Therefore, as a configuration of a through-type 3-terminal capacitor capable of suppressing an increase in electrostatic capacity and an increase in direct current resistance, a configuration like that of Patent Literature 1 is provided. By making the number of pieces of the signal internal electrode (first internal electrode layer) large, and making the signal internal electrodes (first internal electrode layers) face each other, both the electrostatic capacity and the direct current resistance can be suppressed.

[0005] PRIOR ART DOCUMENTS

[0006] PATENT LITERATURE

[0007] Patent Literature 1: Japanese Patent Application Laid-Open No. 9-55335 SUMMARY

[0008] PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] However, the configuration like that of Patent Literature 1 has the following problem. That is, in a given size limit, there is a limit to increasing the number of pieces of the signal internal electrode (first internal electrode layer), and it is difficult to cope with a larger current.

[0010] Therefore, a main object of the present application is to provide a laminated ceramic electronic component capable of coping with a larger current.

[0011] Technical solutions for solving the problem

[0012] The laminated ceramic electronic component of the present invention is a laminated ceramic electronic component comprising: a laminate having a first main surface and a second main surface opposite to each other in the lamination direction, a first surface and a second surface opposite to each other in a first direction orthogonal to the lamination direction, and a third surface and a fourth surface opposite to each other in a second direction orthogonal to the lamination direction and the first direction; and at least four or more external electrodes disposed on any one of the first surface, the second surface, the third surface and the fourth surface, wherein a bonding electrode is disposed on any one of the first main surface or the second main surface to electrically bond at least two or more external electrodes of the same potential to each other, wherein when the DC resistance of the laminated ceramic capacitor is set to Rdc1 and the DC resistance of the bonding electrode is set to Rdc3, Rdc1≤Rdc3.

[0013] According to the multilayer ceramic electronic component of the present invention, a bonding electrode is disposed on either the first main surface or the second main surface to electrically bond at least two or more external electrodes of the same potential to each other. When the DC resistance of the multilayer ceramic capacitor is set to Rdc1 and the DC resistance of the bonding electrode is set to Rdc3, Rdc1≤Rdc3, so the combined resistance of the multilayer ceramic capacitor and the bonding electrode becomes less than the resistance of a single multilayer ceramic capacitor. Therefore, a multilayer ceramic electronic component capable of handling larger currents can be provided.

[0014] Invention Effects

[0015] According to the present invention, a stacked ceramic electronic component capable of handling larger currents is provided.

[0016] The above-described objects, other objects, features, and advantages of the present invention will become clearer from the following detailed description of specific embodiments with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a perspective view showing the appearance of the stacked ceramic electronic component according to the first embodiment of the present invention.

[0018] Figure 2 This is a front view of the laminated ceramic electronic component according to the first embodiment of the present invention.

[0019] Figure 3 This is a top view of the laminated ceramic electronic component according to the first embodiment of the present invention.

[0020] Figure 4 yes Figure 1 A cross-sectional view at line IV-IV.

[0021] Figure 5 yes Figure 1 A cross-sectional view at line VV.

[0022] Figure 6 yes Figure 4 A cross-sectional view at line VI-VI.

[0023] Figure 7 yes Figure 4 A cross-sectional view at line VII-VII.

[0024] Figure 8 This is a perspective view of a laminated ceramic electronic component according to a variation of the first embodiment of the present invention.

[0025] Figure 9 This is a cross-sectional view in the stacking direction showing the mounting structure of the stacked ceramic electronic component according to the first embodiment of the present invention.

[0026] Figure 10 This is a cross-sectional view in a second direction showing the mounting structure of the laminated ceramic electronic component according to the first embodiment of the present invention.

[0027] Figure 11 This is a cross-sectional view showing a first modified example of a multilayer ceramic capacitor according to the first embodiment of the present invention, and is related to... Figure 4 The diagram corresponding to the sectional view.

[0028] Figure 12 This is a cross-sectional view showing a first modified example of a multilayer ceramic capacitor according to the first embodiment of the present invention, and is related to... Figure 5 The diagram corresponding to the sectional view.

[0029] Figure 13 yes Figure 11 A cross-sectional view at line XIII-XIII.

[0030] Figure 14 yes Figure 11 A cross-sectional view at line XIV-XIV.

[0031] Figure 15 This is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and is related to... Figure 4 The diagram corresponding to the sectional view.

[0032] Figure 16 This is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and is related to... Figure 5 The diagram corresponding to the sectional view.

[0033] Figure 17This is a perspective view showing the appearance of the stacked ceramic electronic component according to the second embodiment of the present invention.

[0034] Figure 18 This is a front view of the laminated ceramic electronic component according to the second embodiment of the present invention.

[0035] Figure 19 This is a side view of the laminated ceramic electronic component according to the second embodiment of the present invention.

[0036] Figure 20 This is a top view of the stacked ceramic electronic component according to the second embodiment of the present invention.

[0037] Figure 21 yes Figure 17 A sectional view at line XXI-XXI.

[0038] Figure 22 yes Figure 17 A sectional view at line XXII-XXII.

[0039] Figure 23 yes Figure 17 A sectional view at line XXI-XXI.

[0040] Figure 24 yes Figure 17 A cross-sectional view at line XXIV-XXIV.

[0041] Figure 25 yes Figure 17 A cross-sectional view at line XXV-XXV.

[0042] Figure 26 yes Figure 17 The exploded three-dimensional view of the stacked body shown. Detailed Implementation

[0043] A. First Implementation

[0044] 1. Laminated ceramic electronic components

[0045] The laminated ceramic electronic component 100 according to an embodiment of the present invention will be described.

[0046] Figure 1 This is a perspective view showing the appearance of the stacked ceramic electronic component according to the first embodiment of the present invention. Figure 2 This is a front view of the laminated ceramic electronic component according to the first embodiment of the present invention. Figure 3 This is a top view of the laminated ceramic electronic component according to the first embodiment of the present invention. Figure 4 yes Figure 1 A cross-sectional view at line IV-IV. Figure 5 yes Figure 1A cross-sectional view at line VV. Figure 6 yes Figure 4 A cross-sectional view at line VI-VI. Figure 7 yes Figure 4 A cross-sectional view at line VII-VII.

[0047] like Figures 1 to 3 As shown, the multilayer ceramic electronic component 100 according to the embodiments of the present invention includes a multilayer ceramic capacitor 10 and a bonding electrode 40.

[0048] (a) Multilayer ceramic capacitor

[0049] The multilayer ceramic capacitor 10 of the present invention will be described.

[0050] The multilayer ceramic capacitor 10 has a multilayer body 12 and multiple external electrodes 30.

[0051] The laminate 12 has a first principal surface 12a and a second principal surface 12b opposite each other in the lamination direction x, a first surface 12c and a second surface 12d opposite each other in a first direction y orthogonal to the lamination direction x, and a third surface 12e and a fourth surface 12f opposite each other in a second direction z orthogonal to both the lamination direction x and the first direction y. The direction in which the first principal surface 12a and the second principal surface 12b of the laminate 12 connect to each other is the lamination direction x.

[0052] The laminate 12 has a cuboid shape. Furthermore, the laminate 12 preferably has rounded corners and edges. A corner is the intersection of three adjacent faces of the laminate 12, and an edge is the intersection of two adjacent faces of the laminate 12. Additionally, some or all of the first main face 12a and the second main face 12b, the first face 12c and the second face 12d, and the third face 12e and the fourth face 12f may have irregularities or protrusions.

[0053] The laminate 12 has a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 have an inner dielectric layer 14a and an outer dielectric layer 14b. In addition, the internal electrodes 16 have a first internal electrode 16a and a second internal electrode 16b.

[0054] Furthermore, the laminate 12 has an inner layer 18, a first outer layer 20a located on the side of the first main surface 12a, and a second outer layer 20b located on the side of the second main surface 12b.

[0055] The first outer layer 20a is located on the first main surface 12a side of the laminate 12 and is an assembly of multiple outer dielectric layers 14b located between the first main surface 12a and the inner electrode 16 closest to the first main surface 12a.

[0056] The second outer layer 20b is located on the second main surface 12b side of the laminate 12, and is an assembly of multiple outer dielectric layers 14b located between the second main surface 12b and the inner electrode 16 closest to the second main surface 12b.

[0057] Furthermore, the area sandwiched between the first outer layer 20a and the second outer layer 20b is the inner layer 18.

[0058] The inner layer 18 has a first internal electrode 16a with one end exposed on the first surface 12c and the other end exposed on the second surface 12d, a second internal electrode 16b with one end exposed on the third surface 12e and the other end exposed on the fourth surface 12f, and an inner dielectric layer 14a.

[0059] The dielectric layer 14 can be formed from a dielectric material, for example. As a dielectric material, a dielectric ceramic containing main components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3 can be used. Alternatively, materials with secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components can also be used. Furthermore, the inner dielectric layer 14a and the outer dielectric layer 14b can be made of the same dielectric material, or they can be made of different dielectric materials to define the functions in the inner layer 18 and the outer layers 20a and 20b. Additionally, at least one of Si, Mg, Ba, and Mn can be added as an additive. The additive is present between the ceramic particles.

[0060] Regarding the inner dielectric layer 14a, for example, if it contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can prevent insulation breakdown that may occur between the first inner electrode 16a and the second inner electrode 16b. Furthermore, it is not limited to this; the inner dielectric layer 14a can also contain SrTiO3 or the like as a main component. In contrast, to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable to form it from a material with a high dielectric constant, such as BaTiO3.

[0061] The dielectric layer 14 can have multiple grains containing perovskite-type compounds with BaTiO3 as the basic structure.

[0062] When the dielectric layer 14 is thin, the capacitance of the capacitor is larger, so the grain diameter is preferably less than 1 μm.

[0063] The number of stacked dielectric layers 14 is not particularly limited, but it is preferable to have 5 or more and 1000 or less, including the first outer layer 20a and the second outer layer 20b. Furthermore, the thickness of the dielectric layer 14 is preferably, for example, 0.3 μm or more and 6.0 μm or less.

[0064] (Internal electrodes)

[0065] The internal electrode 16 has a first internal electrode 16a and a second internal electrode 16b. The first internal electrode 16a and the second internal electrode 16b are alternately stacked with an inner dielectric layer 14a in between.

[0066] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a is opposite to the first main surface 12a and the second main surface 12b, and has a first opposing electrode portion 22a opposite to the second internal electrode 16b, a first lead-out electrode portion 24a connected to the first opposing electrode portion 22a and led out to the first surface 12c, and a second lead-out electrode portion 24b led out to the second surface 12d.

[0067] The shape of the first opposing electrode portion 22a of the first internal electrode 16a is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion may be rounded in plan view, or the corner portion may be formed obliquely (conical) in plan view. Alternatively, it may be conical in plan view with an oblique orientation.

[0068] The shapes of the first lead-out electrode portion 24a and the second lead-out electrode portion 24b of the first internal electrode 16a are not particularly limited, but are preferably rectangular in plan view. However, the corner portions may be rounded in plan view, or the corner portions may be formed obliquely (conical) in plan view. Alternatively, they may be conical in plan view with an oblique orientation.

[0069] The second internal electrode 16b is disposed on the surface of an inner dielectric layer 14a that is different from the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b has a second opposing electrode portion 22b opposite to the first internal electrode 16a, a third lead-out electrode portion 24c connected to the second opposing electrode portion 22b and led out to the third surface 12e, and a fourth lead-out electrode portion 24d led out to the fourth surface 12f.

[0070] The shape of the second opposing electrode portion 22b of the second internal electrode 16b is not particularly limited, but it is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed obliquely (conical) in plan view. Alternatively, it may be conical in plan view with an oblique orientation.

[0071] The shapes of the third lead-out electrode portion 24c and the fourth lead-out electrode portion 24d of the second internal electrode 16b are not particularly limited, but are preferably rectangular in plan view. However, the corner portions may be rounded in plan view, or the corner portions may be formed obliquely (conical) in plan view. Alternatively, they may be conical in plan view with an oblique orientation.

[0072] Additionally, the laminate 12 has a side portion (W gap) 26a between the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b in the second direction z and the third surface 12e, and a side portion (W gap) 26b between the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b in the second direction z and the fourth surface 12f.

[0073] Furthermore, the laminate 12 has an end (L gap) 27a between the first counter electrode portion 22a of the first internal electrode 16a and the second counter electrode portion 22b of the second internal electrode 16b in the first direction y and the first surface 12c, and an end (L gap) 27b between the first counter electrode portion 22a of the first internal electrode 16a and the second counter electrode portion 22b of the second internal electrode 16b in the first direction y and the second surface 12d.

[0074] The first internal electrode 16a and the second internal electrode 16b can be made of suitable conductive materials, such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys or Ag-Pd alloys, but are not limited thereto. Furthermore, the first internal electrode 16a and the second internal electrode 16b can be made of the same conductive material or different conductive materials.

[0075] Furthermore, by including Sn in the first internal electrode 16a and the second internal electrode 16b, the potential barrier height at the interface between the internal electrode 16 and the dielectric layer 14 can be increased, alleviating the electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14, thereby improving the reliability under high-temperature loads. In this case, even if Sn is only included in either the first internal electrode 16a or the second internal electrode 16b, the effect can be fully realized.

[0076] Furthermore, it is preferable that the total number of the first internal electrode 16a and the second internal electrode 16b is 2 or more and 1000 or less. Additionally, the thickness of the first internal electrode 16a and the second internal electrode 16b is not particularly limited, but is preferably, for example, 0.3 μm or more and 6.0 μm or less.

[0077] (External electrode)

[0078] The external electrode 30 has a plurality of external electrodes 30 connected to the first internal electrode 16a and the second internal electrode 16b. The external electrode 30 has a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0079] The first external electrode 30a is disposed on the first surface 12c and connected to the first internal electrode 16a. In addition, the first external electrode 30a may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the third surface 12e, and a portion of the fourth surface 12f.

[0080] The second external electrode 30b is disposed on the second surface 12d and connected to the first internal electrode 16a. In addition, the second external electrode 30b may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the third surface 12e, and a portion of the fourth surface 12f.

[0081] The third external electrode 30c is disposed on the third surface 12e and connected to the second internal electrode 16b. Alternatively, the third external electrode 30c may also be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0082] The fourth external electrode 30d is disposed on the fourth surface 12f and connected to the second internal electrode 16b. Alternatively, the fourth external electrode 30d may also be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0083] Furthermore, although not shown, the first external electrode 30a to the fourth external electrode 30d are disposed on either the first main surface 12a or the second main surface 12b, but they may not be formed on either main surface. In this case, the dimension of the multilayer ceramic capacitor 10 in the stacking direction x can be reduced, and the multilayer ceramic capacitor 10 can be made thinner.

[0084] Within the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b are opposed to each other across the inner dielectric layer 14a, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first external electrode 30a and the second external electrode 30b connected to the first internal electrode 16a and the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode 16b, exhibiting the characteristics of a capacitor.

[0085] The first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d preferably each have a base electrode layer 32 and a plating layer. The plating layer preferably has a lower plating layer 34 and an upper plating layer 36.

[0086] In other words, the first external electrode 30a preferably has a first base electrode layer 32a, a first lower plating layer 34a, and a first upper plating layer 36a. The second external electrode 30b preferably has a second base electrode layer 32b, a second lower plating layer 34b, and a second upper plating layer 36b. The third external electrode 30c preferably has a third base electrode layer 32c, a third lower plating layer 34c, and a third upper plating layer 36c. The fourth external electrode 30d preferably has a fourth base electrode layer 32d, a fourth lower plating layer 34d, and a fourth upper plating layer 36d.

[0087] The substrate electrode layer 32 includes at least one selected from the sintered layer, the conductive resin layer, the thin film layer, etc.

[0088] First, the case where the base electrode layer 32 is formed by a sintered layer will be described. The sintered layer comprises a metallic component and a glass component. The glass component comprises at least one selected from B, Si, Ba, Mg, Al, Li, etc. Furthermore, the metallic component of the sintered layer comprises, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. Moreover, the sintered layer may also consist of multiple layers.

[0089] Furthermore, when the base electrode layer 32 is formed by sintering, it may also be a structure containing the same type of components and metals as the dielectric layer 14. In this case, assuming that the dielectric layer 14 contains a CaZrO system, the same type of components are Ca and Zr.

[0090] The sintered layer is formed by applying a conductive paste containing glass and metal components to the laminate 12 and then sintering it. The sintered layer can be formed by simultaneously sintering a laminated sheet having internal electrodes 16 and a dielectric layer 14 and applying conductive paste to the laminated sheet; or it can be formed by sintering a laminated sheet having internal electrodes 16 and a dielectric layer 14 to obtain the laminate 12, then applying conductive paste and sintering it. Furthermore, when simultaneously sintering the laminated sheet having internal electrodes 16 and a dielectric layer 14 and applying conductive paste to the laminated sheet, it is preferable to add a dielectric component instead of a glass component, or both, to form the sintered layer.

[0091] The thickness (center thickness of the end face) of the first sintered layer and the second sintered layer located at the center of the stacking direction x connecting the first main surface 12a and the second main surface 12b, and the thickness (center thickness of the end face) of the first sintered layer and the second sintered layer connecting the first surface 12c and the second surface 12d in the first direction y (center thickness of the end face) is preferably, for example, 5 μm or more and 55 μm or less.

[0092] Furthermore, when a base electrode layer (sintered layer) is also provided on a portion of the first main surface 12a or a portion of the second main surface 12b, the thickness of the first sintered layer and the second sintered layer on the first main surface 12a or the second main surface 12b at the center in the first direction y connecting the first surface 12c and the second surface 12d, and the thickness of the first sintered layer and the second sintered layer in the stacking direction x connecting the first main surface 12a and the second main surface 12b, is preferably, for example, 1 μm or more and 30 μm or less.

[0093] Next, the case where the base electrode layer 32 is formed by a conductive resin layer will be described. The conductive resin layer may be disposed on the sintered layer as a cover layer, or it may be disposed directly on the laminate 12 without a sintered layer. Furthermore, the conductive resin layer may completely cover the sintered layer, or it may cover a portion of the sintered layer. Moreover, there may be multiple conductive resin layers.

[0094] The conductive resin layer comprises a thermosetting resin and a metal. Because it contains a thermosetting resin, the conductive resin layer is more flexible than, for example, a sintered layer composed of a coated film or a conductive paste. Therefore, even when subjected to physical impacts, such as thermal cycling impacts, on the multilayer ceramic capacitor 10, the conductive resin layer functions as a buffer layer, preventing cracks from forming in the multilayer ceramic capacitor 10.

[0095] The metal included in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or alloys thereof. Furthermore, metal powder coated with Ag can also be used. When using metal powder coated with Ag, Cu, Ni, Sn, Bi, or alloys thereof are preferred. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; Ag is a noble metal, therefore it does not oxidize and has high weather resistance. Furthermore, it is possible to reduce the cost of the base metal while maintaining the aforementioned properties of Ag.

[0096] Furthermore, the metal included in the conductive resin layer can also be a metal that has undergone anti-oxidation treatment on Cu or Ni. Additionally, the metal included in the conductive resin layer can also be metal powder coated with Sn, Ni, or Cu. When using metal powder coated with Sn, Ni, or Cu, Ag, Cu, Ni, Sn, Bi, or alloys thereof are preferably used as the metal powder.

[0097] The metal contained in the conductive resin layer primarily bears the responsibility for the conductive resin layer's electrical conductivity. Specifically, conductive fillers are in contact with each other, thereby forming electrical pathways within the conductive resin layer.

[0098] Regarding the metal contained in the conductive resin layer, spherical or flat metals can be used, but it is preferable to use a mixture of spherical and flat metal powders.

[0099] For example, various known thermosetting resins such as epoxy resin, phenolic resin, polyurethane resin, silicone resin, and polyimide resin can be used as the conductive resin layer. Among them, epoxy resin, with its excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0100] Furthermore, it is preferable to include a curing agent together with the thermosetting resin in the conductive resin layer. When using epoxy resin as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, reactive ester, and amide-imide compounds can be used as the curing agent for the epoxy resin.

[0101] The thickest part of the conductive resin layer is preferably 5 μm or more and 50 μm or less.

[0102] Next, the case where the base electrode layer 32 is formed from a thin film layer will be described. The thin film layer can also be formed on the surface of the laminate 12. When the thin film layer is used as the base electrode layer 32, it is formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer with a thickness of 1 μm or less on which metal particles are deposited.

[0103] Furthermore, the base electrode layer 32 may also be formed by a plating layer. In this case, the plating layer preferably comprises at least one metal selected from Cu, Ni, Sn, Pd, Au, Ag, Bi, or Zn, or an alloy containing such metal. The plating layer preferably does not contain glass, and the metal content per unit area of ​​the plating layer is preferably 99% by volume or more.

[0104] (Lower plating layer)

[0105] The lower plating layer 34 includes a first lower plating layer 34a configured to cover the first base electrode layer 32a, a second lower plating layer 34b configured to cover the second base electrode layer 32b, a third lower plating layer 34c configured to cover the third base electrode layer 32c, and a fourth lower plating layer 34d configured to cover the fourth base electrode layer 32d.

[0106] As the lower plating layer 34, for example, it includes at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0107] Furthermore, the lower plating layer 34 is preferably a Ni plating layer. When the lower plating layer 34 is a Ni plating layer, it is possible to prevent the base electrode layer 32 from being eroded by the solder when mounting the multilayer ceramic capacitor 10.

[0108] Furthermore, the thickness of the lower plating layer 34 is preferably 1 μm or more and 8 μm or less.

[0109] (Upper plating layer)

[0110] The upper plating layer 36 includes a first upper plating layer 36a configured to cover the first lower plating layer 34a, a second upper plating layer 36b configured to cover the second lower plating layer 34b, a third upper plating layer 36c configured to cover the third lower plating layer 34c, and a fourth upper plating layer 36d configured to cover the fourth lower plating layer 34d.

[0111] As the upper plating layer 36, for example, it includes at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0112] Furthermore, the upper plating layer 36 is preferably a Sn plating layer. When the upper plating layer 36 is a Sn plating layer, the wettability of the solder when mounting the multilayer ceramic capacitor 10 can be improved, making mounting easier.

[0113] Furthermore, the thickness of the upper plating layer 36 is preferably 1 μm or more and 8 μm or less.

[0114] Furthermore, although the plating layer has a two-layer structure of lower plating layer 34 and upper plating layer 36, it is not limited to this and can also be a three-layer structure. In the case of a three-layer plating layer structure, it is preferable that from the side of the laminate 12, there is a Sn plating layer, a Ni plating layer, and a Sn plating layer.

[0115] The dimension in the first direction y of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrode 30, is designated as dimension L. Dimension L is preferably 0.51 mm or more and 3.2 mm or less. The dimension in the second direction z of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrode 30, is designated as dimension W. Dimension W is preferably 0.21 mm or more and 2.5 mm or less. The dimension in the lamination direction x of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrode 30, is designated as dimension T. Dimension T is preferably 0.05 mm or more and 2.5 mm or less.

[0116] Next, the bonding electrode 40 will be described.

[0117] On either the first main surface 12a or the second main surface 12b of the laminate 12, a bonding electrode 40 is disposed to electrically bond at least two or more external electrodes of the same potential in the external electrodes 30 to each other.

[0118] In the multilayer ceramic electronic component 100 of the first embodiment, the bonding electrode 40 electrically bonds the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10 on the first main surface 12a of the multilayer body 12.

[0119] The bonding electrode 40 includes a bonding base electrode 42, a bonding lower plating layer 44 covering the bonding base electrode 42, and a bonding upper plating layer 46 covering the bonding lower plating layer 44. Alternatively, the bonding electrode 40 may be composed solely of the bonding base electrode 42. In this case, the bonding base electrode 42 may be formed, for example, by a sputtering electrode.

[0120] Preferably, when the DC resistance of the multilayer ceramic capacitor 10 is set to Rdc1 and the DC resistance of the bonding electrode 40 is set to Rdc3, Rdc1 ≤ Rdc3.

[0121] When Rdc1 > Rdc3, the current containing the noise component becomes less likely to flow through the capacitor due to the voltage division effect, thus reducing the noise removal effect.

[0122] Rdc3 is preferably more than 1.0 times and less than 5.0 times Rdc1. Basically, if the combined resistance is reduced, the current becomes easier to flow. However, when Rdc3 is greater than 5.0 times Rdc1, the effect of making the current flow easier decreases.

[0123] The thickness t1 of the bonding electrode 40 in the stacking direction x is preferably thinner than the thickness t2 of the outer electrode 30 disposed on the same plane as the bonding electrode 40 in the stacking direction x.

[0124] Regarding the bonding electrode 40, the thicker the thickness in the stacking direction x, the smaller Rdc3 can be. However, if it becomes larger than the dimension in the stacking direction x of the external electrode 30 disposed on the main surface, the overall dimension in the stacking direction x of the multilayer ceramic capacitor 10 will become larger. Therefore, by making the thickness in the stacking direction x of the bonding electrode 40 thinner than the thickness in the stacking direction x of the external electrode 30 disposed on the same plane as the bonding electrode 40, Rdc3 can be increased, and a large current can flow through the multilayer ceramic capacitor 10 without making the dimension in the stacking direction x of the multilayer ceramic capacitor 10 too large.

[0125] The method for measuring the Rdc of the bonding electrode 40 and the multilayer ceramic capacitor 10 is as follows.

[0126] That is, firstly, the external electrodes 30 of the multilayer ceramic capacitor 10 connected to the bonding electrode 40 are removed from the surface of the multilayer 12 by means of, for example, laser, grinding, or solvent treatment. At this time, it is sufficient to remove any one of the external electrodes 30 connected to the bonding electrode 40 from the surface of the multilayer 12. Then, the bonding electrode 40 and the multilayer ceramic capacitor 10 are measured separately using the four-terminal method.

[0127] The main component of the bonding electrode 40 is preferably a metal such as Cu, NiCr, or NiCu, but it is not limited to this.

[0128] The porosity of the bonding substrate electrode 42 of the bonding electrode 40 is preferably greater than the porosity of the base electrode layer 32 of the outer electrode 30. By making the porosity of the bonding substrate electrode 42 greater than the porosity of the base electrode layer 32, Rdc3 can be increased. Regarding the porosity, when the bonding lower plating layer 44 and the bonding upper plating layer 46 are configured, it is defined by observing the porosity and the area outside the porosity when viewed in the stacking direction x of the bonding substrate electrode 42 and the base electrode layer 32 after the bonding lower plating layer 44 and the bonding upper plating layer 46 have been removed.

[0129] Assuming that the bending strength is lower when the T dimension is less than 100 μm, for example less than 50 μm, the bending strength of the multilayer ceramic capacitor 10 can be improved by disposing the bonding electrode 40 on any surface of the first main surface 12a or the second main surface 12b of the multilayer 12.

[0130] in addition, Figure 1 The bonding electrode 40 shown is rectangular, but not limited to this. The length of the central region in the width direction in the first direction y can be less than or greater than the length of the end in the width direction. Alternatively, it can be a conical shape in the second direction z, where the dimension tapers from one end to the other or from the other end to one end. It can also be formed into a stepped tapering shape.

[0131] according to Figure 1 The multilayer ceramic capacitor 10 shown has a bonding electrode 40 disposed on its first main surface 12a, which electrically bonds the first external electrode 30a and the second external electrode 30b. When the DC resistance of the multilayer ceramic capacitor is set to Rdc1 and the DC resistance of the bonding electrode 40 is set to Rdc3, Rdc1 ≤ Rdc3. Therefore, the combined resistance of the multilayer ceramic capacitor 10 and the bonding electrode 40 becomes smaller than the resistance of a single multilayer ceramic capacitor 10, thus enabling the multilayer ceramic capacitor 10 to handle larger currents.

[0132] Variations of the first embodiment

[0133] Next, an example of a multilayer ceramic electronic component 100A according to a first variation of the first embodiment of the present invention will be described. Figure 8 This is a perspective view of a laminated ceramic electronic component according to a variation of the first embodiment of the present invention. However, regarding... Figures 1 to 7 For identical or equivalent structures, use the same reference numerals and omit detailed descriptions.

[0134] like Figure 8 As shown, the modified example involves a multilayer ceramic electronic component 100A, which includes a multilayer ceramic capacitor 10 and a bonding electrode 40A.

[0135] In the first embodiment, in the multilayer ceramic electronic component 100A, the bonding electrode 40A electrically bonds the third external electrode 30c and the fourth external electrode 30d of the multilayer ceramic capacitor 10 on the first main surface 12a of the multilayer body 12.

[0136] Preferably, when the DC resistance of the multilayer ceramic capacitor 10 is set to Rdc1 and the DC resistance of the junction electrode 40A is set to Rdc3, Rdc1 ≤ Rdc3.

[0137] 2. Mounting structure of laminated ceramic electronic components

[0138] Next, the mounting structure 300 of the stacked ceramic electronic component 100 according to an embodiment of the present invention will be described.

[0139] Figure 9 This is a cross-sectional view in the stacking direction showing the mounting structure of the stacked ceramic electronic component according to the first embodiment of the present invention. Figure 10 This is a cross-sectional view in a second direction showing the mounting structure of the laminated ceramic electronic component according to the first embodiment of the present invention.

[0140] like Figure 9 as well as Figure 10 As shown, the mounting structure 300 of the multilayer ceramic electronic component according to this embodiment includes the multilayer ceramic electronic component 100 according to this embodiment and the mounting substrate 60. The mounting substrate 60 includes a substrate core material 62 and connecting conductors (conductor connection pads) 64.

[0141] The core material 62 of the substrate can be, for example, a substrate made of a material in which epoxy resin or polyimide resin is impregnated into a substrate mixed with glass cloth and glass nonwoven fabric, or a ceramic substrate manufactured by sintering a sheet mixed with ceramic and glass. Furthermore, the core material 62 of the substrate can be a single-layer substrate or a substrate composed of multiple layers stacked together. The thickness of the core material 62 of the substrate is not particularly limited, but is preferably, for example, 200 μm or more and 800 μm or less.

[0142] One main surface of the core material 62 of the substrate constitutes a substrate-side mounting surface 62a, on which a conductor connection pad 64 is disposed and which serves as the mounting surface of the laminated ceramic electronic component 100.

[0143] The conductor connection disk 64 includes a first conductor connection disk 64a, a second conductor connection disk 64b, a third conductor connection disk 64c, and a fourth conductor connection disk 64d.

[0144] The first conductor connection pad 64a is a portion electrically and mechanically connected to the first external electrode 30a of the multilayer ceramic capacitor 10 via the bonding material 66. The second conductor connection pad 64b is a portion electrically and mechanically connected to the second external electrode 30b of the multilayer ceramic capacitor 10 via the bonding material 66. The third conductor connection pad 64c is a portion electrically and mechanically connected to the third external electrode 30c of the multilayer ceramic capacitor 10 via the bonding material 66. The fourth conductor connection pad 64d is a portion electrically and mechanically connected to the fourth external electrode 30d of the multilayer ceramic capacitor 10 via the bonding material 66.

[0145] Alternatively, the conductor connection disk 64 can be disposed on the main surface opposite to the substrate-side mounting surface 62a of the core material 62 of the substrate.

[0146] The material of the conductor pad 64 is not particularly limited, but metals such as Cu, Au, Pd, and Pt can be used. Furthermore, the thickness of the conductor pad 64, i.e., its dimension in the stacking direction x, is not particularly limited, but it is preferably set to 20 μm or more and 200 μm or less. The bonding material 66 can be, for example, a high-heat-resistant epoxy adhesive or solder.

[0147] Furthermore, in the above description, the mounting substrate 60 corresponds to the mounting substrate of the present invention. The core material 62 of the substrate corresponds to the core material of the substrate of the present invention. The mounting surface 62a of the substrate side corresponds to the mounting surface of the present invention. The plurality of conductor connecting pads 64 correspond to the plurality of connecting conductors of the present invention. However, regarding the connecting conductors of the present invention, apart from the so-called connecting pads, any conductor that is disposed between the multilayer ceramic capacitor 10 and the mounting substrate 60 and can electrically connect the two is not limited to other uses, functions, shapes, names, etc.

[0148] Furthermore, in the mounting configuration 300 of the laminated ceramic electronic components, the first external electrode 30a and the second external electrode 30b are connected to the anode. This shortens the current distance, preventing an increase in insulation resistance while ensuring moisture resistance reliability.

[0149] about Figure 9 as well as Figure 10The mounting configuration 300 of the illustrated multilayer ceramic electronic component (MLC) preferably mounts the MLC 100 such that the bonding electrode 40 of the MLC 100 is positioned in the opposite direction to the mounting substrate 60. That is, preferably, the bonding electrode 40 of the MLC 100 is positioned on the first main surface side (non-mounting surface side) of the multilayer ceramic capacitor 10, and the multilayer ceramic capacitor 10 of the MLC 100 is mounted on the mounting substrate 60 side. By mounting in this way, the distance between the multilayer ceramic capacitor 10 and the mounting substrate 60 is not increased, thus making it easier to obtain a low ESL effect. Furthermore, mounting can be performed without affecting the mounting of the MLC 100 to the mounting substrate.

[0150] 3. Manufacturing method of multilayer ceramic capacitors

[0151] The manufacturing method of the multilayer ceramic capacitor 10 of the present invention will be described below.

[0152] (a) Manufacturing method of multilayer ceramic capacitors

[0153] First, prepare the conductive paste for the dielectric sheet and internal electrodes. The conductive paste for the dielectric sheet and internal electrodes contains an adhesive and a solvent. Known adhesives and solvents can be used.

[0154] Next, conductive paste for the internal electrodes is printed on the dielectric sheet in a given pattern, for example, by inkjet printing, screen printing, or gravure printing. Thus, a dielectric sheet with a pattern of the first internal electrode and a dielectric sheet with a pattern of the second internal electrode are prepared. Then, the sheet with the first internal electrode printed and the sheet with the second internal electrode printed are laminated together, thereby forming the inner layer 18.

[0155] Next, a given number of dielectric sheets without printed internal electrode patterns are stacked, thereby forming the first outer layer 20a on the first main surface 12a side. Then, the portion prepared above to become the inner layer 18 is stacked, and a given number of dielectric sheets without printed internal electrode patterns are stacked on top of the inner layer 18, thereby forming the second outer layer 20b on the second main surface 12b side. Thus, a laminated sheet is manufactured.

[0156] Next, the laminated sheets are pressed in the stacking direction by means of isostatic pressing to produce a laminated block.

[0157] Next, the stacked blocks are cut to a given size to produce stacked pieces. At this point, the corners and edges of the stacked pieces can also be rounded using methods such as tumble grinding.

[0158] Next, the stacked sheets are fired to produce the stack 12. Regarding the firing temperature, although it depends on the materials of the ceramic and the internal electrodes, it is preferably above 900°C and below 1400°C.

[0159] Next, a bonding electrode 40 is formed on the surface of the first main surface 12a of the laminate 12. The bonding electrode 40 is formed by extruding conductive paste from a slit and applying it, or by screen printing to form the bonding substrate electrode 42.

[0160] Then, a first base electrode layer 32a of the first external electrode 30a and a second base electrode layer 32b of the second external electrode 30b are formed on the first surface 12c and the second surface 12d of the laminate 12 in which the bonding electrode 40 is formed. Furthermore, a third base electrode layer 32c of the third external electrode 30c and a fourth base electrode layer 32d of the fourth external electrode 30d are formed on the third surface 12e and the fourth surface 12f of the laminate 12 obtained by firing.

[0161] In the case of forming a sintered layer as a base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a sintering process is performed to form the base electrode layer 32.

[0162] More specifically, firstly, a third base electrode layer 32c of the third external electrode 30c and a fourth base electrode layer 32d of the fourth external electrode 30d are formed on the third surface 12e and the fourth surface 12f of the laminate 12 obtained by firing.

[0163] Various methods can be used to form the third base electrode layer 32c and the fourth base electrode layer 32d. For example, a method of extruding conductive paste from a slit and applying it can be used. In this method, by increasing the amount of conductive paste extruded, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed not only on the third surface 12e and the fourth surface 12f, but also on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0164] Furthermore, it can also be formed using a roller transfer method. In the case of roller transfer, not only are the third base electrode layer 32c and the fourth base electrode layer 32d formed on the third surface 12e and the fourth surface 12f, but the third base electrode layer 32c and the fourth base electrode layer 32d are also formed on a portion of the first main surface 12a and a portion of the second main surface 12b. By increasing the pressing pressure during roller transfer, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0165] Next, a first base electrode layer 32a of the first external electrode 30a and a second base electrode layer 32b of the second external electrode 30b are formed on the first surface 12c and the second surface 12d of the laminate obtained by firing.

[0166] Here, various methods can be used to form the first base electrode layer 32a and the second base electrode layer 32b. For example, by using methods such as impregnation, it is possible not only to form them on the first surface 12c and the second surface 12d, but also to form them as a part extending to the first main surface 12a, a part of the second main surface 12b, a part of the third surface 12e, and a part of the fourth surface 12f.

[0167] In this embodiment, the first base electrode layer 32a, the second base electrode layer 32b, the third base electrode layer 32c, and the fourth base electrode layer 32d may also be fired simultaneously.

[0168] When a conductive resin layer is formed as the base electrode layer 32, the conductive resin layer can be formed by the following method. Alternatively, the conductive resin layer can be formed on the surface of the sintered layer, or it can be formed directly on the laminate as a monomer without forming a sintered layer.

[0169] As a method for forming a conductive resin layer, a conductive resin paste comprising a thermosetting resin and a metal is applied to a sintered layer or a laminate, and then heat-treated at a temperature of 250°C or higher and 550°C or lower to thermocure the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably suppressed to below 100 ppm.

[0170] As a method for applying conductive resin paste, similar to the method for forming the base electrode layer 32 from the sintered layer, for example, a process of extruding conductive paste from a slit and applying it, or a roller transfer method can be used to form it.

[0171] Then, a lower plating layer 34 is formed on the substrate electrode layer 32 and the surface of the laminate 12, and an upper plating layer 36 is formed to cover the lower plating layer 34. Simultaneously, a bonding lower plating layer 44 is formed on the surface of the bonding substrate electrode 42, and a bonding upper plating layer 46 is formed to cover the bonding lower plating layer 44. More specifically, a Ni plating layer is formed on the substrate electrode layer 32 as the lower plating layer 34. Then, a Sn plating layer is formed on the surface of the lower plating layer 34 as the upper plating layer 36. Similarly, a Ni plating layer is formed on the bonding substrate electrode 42 as the bonding lower plating layer 44, and a Sn plating layer is formed on the surface of the bonding lower plating layer 44 as the bonding upper plating layer 46. During the plating process, either electrolytic plating or electroless plating can be used. However, regarding electroless plating, in order to increase the plating deposition rate, pretreatment using catalysts or the like is required, which has the disadvantage of complicating the process. Therefore, electroplating is usually the preferred method.

[0172] Like the above, it is capable of manufacturing Figure 1 The described laminated ceramic electronic component 100.

[0173] Alternatively, a fired laminate 12 may be manufactured, and after the external electrode 30 is formed on the laminate 12, a bonding electrode 40 may be formed.

[0174] That is, after forming the external electrode 30 to obtain the multilayer ceramic capacitor 10, the bonding electrode 40 is formed on the surface of the first main surface 12a in the multilayer body 12 of the multilayer ceramic capacitor 10 by screen printing and sputtering.

[0175] Therefore, it is possible to manufacture Figure 1 The described laminated ceramic electronic component 100.

[0176] 4. Modifications to the multilayer ceramic capacitor according to the first embodiment

[0177] Hereinafter, various modifications (first modification and second modification) of the multilayer ceramic capacitor in the multilayer ceramic electronic component according to the first embodiment will be described. Furthermore, for these modifications, the same reference numerals are used for components corresponding to those in the above-described embodiment, and detailed descriptions thereof are omitted.

[0178] (1) First variation

[0179] The first variation of this embodiment relates to a multilayer ceramic capacitor 10A, which differs from the multilayer ceramic capacitor 10 of this embodiment only in the structure of the laminate 12A. Therefore, the same reference numerals are used for the parts that are the same as those in the multilayer ceramic capacitor 10, and their descriptions are omitted.

[0180] Figure 11 This is a cross-sectional view showing a first modified example of a multilayer ceramic capacitor according to the first embodiment of the present invention, and is related to... Figure 4 The diagram corresponding to the sectional view. Figure 12 This is a cross-sectional view showing a first modified example of a multilayer ceramic capacitor according to the first embodiment of the present invention, and is related to... Figure 5 The diagram corresponding to the sectional view. Figure 13 yes Figure 11 A cross-sectional view at line XIII-XIII. Figure 14 yes Figure 11 A cross-sectional view at line XIV-XIV.

[0181] The multilayer ceramic capacitor 10A has a multilayer body 12A and an external electrode 30.

[0182] The laminate 12A includes a first main surface 12a and a second main surface 12b opposite each other in the lamination direction x, a first surface 12c and a second surface 12d opposite each other in the first direction y orthogonal to the lamination direction x, and a third surface 12e and a fourth surface 12f opposite each other in the second direction z orthogonal to the lamination direction x and the first direction y.

[0183] The laminate 12A has a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. In addition, the internal electrodes 16 have a first internal electrode 16a and a second internal electrode 16b.

[0184] A first dummy electrode 25a is disposed at the ends (L gaps) 27a and 27b of the laminate 12A so as to be exposed on the first surface 12c, and a second dummy electrode 25b is disposed so as to be exposed on the second surface 12d.

[0185] Preferably, the first dummy electrode 25a and the second dummy electrode 25b are disposed on the same plane as the second internal electrode 16b, and have the same thickness as the second internal electrode 16b.

[0186] If the coverage of the first dummy electrode 25a and the second dummy electrode 25b is reduced, the current path can be shortened.

[0187] The first dummy electrode 25a and the second dummy electrode 25b can also be disposed on the first outer layer portion 20a and the second outer layer portion 20b. In this case, it is preferable to dispose of them on portions corresponding to the locations where the ends (L gaps) 27a, 27b of the laminate 12 are moved parallel to each other in the lamination direction x. By disposing them in this way, it becomes easier to form a plating layer without disposing of a base electrode layer 32.

[0188] Furthermore, when the first dummy electrode 25a and the second dummy electrode 25b are disposed on the same plane as the second internal electrode 16b, when printing the second internal electrode 16b, the first dummy electrode 25a and the second dummy electrode 25b are printed together with the second internal electrode 16b, thereby enabling the first dummy electrode 25a and the second dummy electrode 25b to be disposed on the same plane as the second internal electrode 16b.

[0189] Alternatively, a third dummy electrode 25c may be disposed on the side (W gap) 26a, 26b of the laminate 12A so that it is exposed on the third surface 12e, and a fourth dummy electrode 25d may be disposed so that it is exposed on the fourth surface 12f.

[0190] Preferably, the third dummy electrode 25c and the fourth dummy electrode 25d are disposed on the same plane as the first internal electrode 16a and have the same thickness as the first internal electrode 16a.

[0191] If the coverage of the third dummy electrode 25c and the fourth dummy electrode 25d is reduced, the current path can be shortened.

[0192] The third dummy electrode 25c and the fourth dummy electrode 25d can also be disposed on the first outer layer portion 20a and the second outer layer portion 20b. In this case, it is preferable to dispose of them on portions corresponding to the locations where the sides (W gaps) 26a and 26b of the laminate 12A are moved parallel to each other in the lamination direction x. By disposing them in this way, it becomes easier to form a plating layer without disposing of the base electrode layer 32.

[0193] Furthermore, when the third dummy electrode 25c and the fourth dummy electrode 25d are disposed on the same plane as the first internal electrode 16a, when printing the first internal electrode 16a, the third dummy electrode 25c and the fourth dummy electrode 25d are printed together with the second internal electrode 16b, thereby enabling the third dummy electrode 25c and the fourth dummy electrode 25d to be disposed on the same plane as the first internal electrode 16a.

[0194] Figures 11 to 14 The stacked ceramic capacitor 10A shown has a first dummy electrode 25a, a second dummy electrode 25b, a third dummy electrode 25c, and a fourth dummy electrode 25d disposed on the sides (W gaps) 26a and 26b of the stack 12A and the ends (L gaps) 27a and 27b of the stack 12A, thus preventing deformation during pressing.

[0195] in addition, Figures 11 to 14Although the stacked ceramic capacitor 10A shown has a first dummy electrode 25a, a second dummy electrode 25b, a third dummy electrode 25c and a fourth dummy electrode 25d arranged on the sides (W gaps) 26a and 26b of the stacked body 12A and at the ends (L gaps) 27a and 27b of the stacked body 12A, it is not limited to this.

[0196] That is, the first dummy electrode 25a and the second dummy electrode 25b can be disposed at the ends (L gaps) 27a and 27b of the laminate 12A, and the third dummy electrode 25c and the fourth dummy electrode 25d can be not disposed at the sides (W gaps) 26a and 26b of the laminate 12A.

[0197] On the other hand, the third dummy electrode 25c and the fourth dummy electrode 25d may be disposed on the sides (W gaps) 26a and 26b of the laminate 12A, and the first dummy electrode 25a and the second dummy electrode 25b may not be disposed on the ends (L gaps) 27a and 27b of the laminate 12A.

[0198] (2) Second variation

[0199] The second variation of this embodiment involves a multilayer ceramic capacitor 10B, which differs from the multilayer ceramic capacitor 10 of this embodiment only in the structure of the laminate 12B. Therefore, the same reference numerals are used for the parts that are the same as those in the multilayer ceramic capacitor 10, and their descriptions are omitted.

[0200] Figure 15 This is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and is related to... Figure 4 The diagram corresponding to the sectional view. Figure 16 This is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and is related to... Figure 5 The diagram corresponding to the sectional view.

[0201] The laminate 12B includes a first principal surface 12a and a second principal surface 12b opposite each other in the lamination direction x, a first surface 12c and a second surface 12d opposite each other in the first direction y orthogonal to the lamination direction x, and a third surface 12e and a fourth surface 12f opposite each other in the second direction z orthogonal to the lamination direction x and the first direction y.

[0202] The laminate 12B has a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. In addition, the internal electrodes 16 have a first internal electrode 16a and a second internal electrode 16b.

[0203] The laminate 12B has an inner layer 18 and a first outer layer 20a and a second outer layer 20b configured to hold the inner layer 18 in the lamination direction x.

[0204] The inner dielectric layer 14a of the inner layer portion 18 may also be configured to be sandwiched between the first internal electrode 16a and the first internal electrode 16a. In this case, the first internal electrode 16a and the first internal electrode 16a are continuously disposed with the inner dielectric layer 14a of the inner layer portion 18 in between.

[0205] Furthermore, the inner dielectric layer 14a of the inner layer 18 may also be configured to be sandwiched between the second internal electrode 16b and the second internal electrode 16b. In this case, the second internal electrode 16b and the second internal electrode 16b are continuously disposed with respect to the dielectric layer 14a of the inner layer 18. The inner dielectric layer 14a of the inner layer 18 may, for example, contain dielectric ceramic particles having a perovskite structure and being primarily composed of perovskite-type compounds containing Ba and Ti. Additionally, at least one of Si, Mg, Ba, and Mn may be added as an additive material to these primary components. The additive material exists between the ceramic particles.

[0206] The inner layer 18 of the laminate 12B has a capacitor forming portion 28 in which a first internal electrode 16a and a second internal electrode 16b are opposed to each other across a dielectric layer 14 to form an electrostatic capacitor, and an internal electrode stacking portion 29 which is a region in which two or more first internal electrodes 16a are continuously stacked. The laminated ceramic capacitor 10B exhibits capacitor characteristics through this capacitor forming portion 28.

[0207] Furthermore, the internal electrode stack 29 is configured to be separated into multiple internal electrode stacks 29 from the second internal electrode 16b. As a result, the assembly of the first internal electrode 16a is dispersed, thereby improving heat dissipation and suppressing temperature rise.

[0208] like Figure 15 as well as Figure 16 As shown, in the multilayer ceramic capacitor 10B, the internal electrode stack 29 is separated by two second internal electrodes 16b, and the internal electrode stack 29 is divided into a first internal electrode stack 29a, a second internal electrode stack 29b, and a third internal electrode stack 29c.

[0209] Furthermore, the second internal electrode 16b, configured to separate the internal electrode stack 29, which is a region where two or more first internal electrodes 16a are continuously stacked, can also be arranged in an odd number. This allows for the stacking of more first internal electrodes 16a, resulting in a reduction in DC resistance.

[0210] Furthermore, the second internal electrode 16b, which is configured to separate the internal electrode stack 29, which is a region where two or more first internal electrodes 16a are continuously stacked, can also be configured to have two or more continuously stacked electrodes. Thus, even if the number of second internal electrodes 16b is reduced, the connection between the second internal electrode 16b and the external electrode 30 can be made more sufficient.

[0211] The second internal electrode 16b can also be disposed between the first internal electrode stack 29 (i.e., between the first internal electrode stack 29a and the first main surface 12a) located on the first main surface 12a side of the laminate 12B, and between the third internal electrode stack 29c (i.e., between the third internal electrode stack 29c and the second main surface 12b) located on the second main surface 12b side of the laminate 12B. This allows capacitor forming portions 28 to be formed near the first outer layer 20a and the second outer layer 20b, thus obtaining a portion of the electrostatic capacitance, shortening the current path to the mounting substrate, and achieving a low ESL effect.

[0212] Furthermore, the second internal electrode 16b may not be disposed between the first internal electrode stack 29a and the first main surface 12a in the region where two or more first internal electrodes 16a are continuously stacked on the first main surface 12a side of the laminate 12B, nor between the third internal electrode stack 29c and the second main surface 12b in the region where two or more first internal electrodes 16a are continuously stacked on the second main surface 12b side of the laminate 12B. As a result, the distance from the surface of the laminate 12B to the capacitor forming portion 28 that forms the electrostatic capacitor is increased, and even if cracks occur on the surface of the laminate 12B due to external loads, the insulation resistance is less likely to deteriorate.

[0213] The thickness of the inner dielectric layer 14a adjacent to the second inner electrode 16b is preferably greater than the thickness of the inner dielectric layer 14a sandwiched between the first inner electrodes 16a. This allows for the stacking of more first inner electrodes 16a, resulting in a greater reduction in DC resistance.

[0214] Furthermore, it is preferable that the thickness of the second internal electrode 16b is greater than the thickness of the first internal electrode 16a. This ensures that even with further reduction in capacitance, the connection between the third lead-out electrode portion 24c of the second internal electrode 16b and the third external electrode 30c disposed on the first surface 12c can be maintained, as can the connection between the fourth lead-out electrode portion 24d of the second internal electrode 16b and the fourth external electrode 30d disposed on the second surface 12d.

[0215] B. Second Implementation Method

[0216] 1. Laminated ceramic electronic components

[0217] Next, an example of a stacked ceramic electronic component 500 according to the second embodiment of the present invention will be described.

[0218] Figure 17 This is a perspective view showing the appearance of the stacked ceramic electronic component according to the second embodiment of the present invention. Figure 18 This is a front view of the laminated ceramic electronic component according to the second embodiment of the present invention. Figure 19 This is a side view of the laminated ceramic electronic component according to the second embodiment of the present invention. Figure 20 This is a top view of the stacked ceramic electronic component according to the second embodiment of the present invention. Figure 21 yes Figure 17 A sectional view at line XXI-XXI. Figure 22 yes Figure 17 A sectional view at line XXII-XXII. Figure 23 yes Figure 17 A sectional view at line XXI-XXI. Figure 24 yes Figure 17 A cross-sectional view at line XXIV-XXIV. Figure 25 yes Figure 17 A cross-sectional view at line XXV-XXV. Figure 26 yes Figure 17 The exploded three-dimensional view of the stacked body shown.

[0219] The multilayer ceramic electronic component 500 includes a multilayer ceramic capacitor 510 and a bonding electrode 540.

[0220] The multilayer ceramic capacitor 510 has a multilayer body 512 and multiple external electrodes 530.

[0221] The laminate 512 has a first main surface 512a and a second main surface 512b opposite each other in the lamination direction x, a first surface 512c and a second surface 512d opposite each other in a first direction y orthogonal to the lamination direction x, and a third surface 512e and a fourth surface 512f opposite each other in a second direction z orthogonal to both the lamination direction x and the first direction y. The direction in which the first main surface 512a and the second main surface 512b of the laminate 512 are connected to each other is the lamination direction x.

[0222] Furthermore, the laminate 512 preferably has rounded corners and edges. A corner is the intersection of three adjacent faces of the laminate 512, and an edge is the intersection of two adjacent faces of the laminate 512. Additionally, some or all of the first main face 512a and the second main face 512b, the first face 512c and the second face 512d, and the third face 512e and the fourth face 512f may have irregularities or protrusions.

[0223] The laminate 512 includes a plurality of dielectric layers 514 and a plurality of internal electrodes 516. The dielectric layers 514 include an inner dielectric layer 514a and an outer dielectric layer 514b. In addition, the internal electrodes 516 have a first internal electrode 516a and a second internal electrode 516b.

[0224] Furthermore, the laminate 512 has an inner layer 518, a first outer layer 520a located on the side of the first main surface 512a, and a second outer layer 520b located on the side of the second main surface 512b.

[0225] The first outer layer 520a is located on the first main surface 512a side of the laminate 512, and is an assembly of multiple outer dielectric layers 514b located between the first main surface 512a and the inner electrode 516 closest to the first main surface 512a.

[0226] The second outer layer 520b is located on the second main surface 512b side of the laminate 512, and is an assembly of multiple outer dielectric layers 514b located between the second main surface 512b and the inner electrode 516 closest to the second main surface 512b.

[0227] Furthermore, the area sandwiched between the first outer layer 520a and the second outer layer 520b is the inner layer 518.

[0228] The inner layer 518 has a first internal electrode 516a with one end exposed on the first surface 512c and the third surface 512e and the other end exposed on the second surface 512d and the fourth surface 512f, a second internal electrode 516b with one end exposed on the first surface 512c and the third surface 512e and the other end exposed on the second surface 512d and the third surface 512e, and an inner dielectric layer 514a.

[0229] The dielectric layer 514 can be formed from a dielectric material, for example. As a dielectric material, for example, a dielectric ceramic containing main components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. Alternatively, materials with secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds added to these main components can also be used. Furthermore, the inner dielectric layer 514a and the outer dielectric layer 514b can be made of the same dielectric material or different dielectric materials.

[0230] Regarding the inner dielectric layer 514a, for example, if it contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can prevent insulation breakdown that may occur between the first inner electrode 516a and the second inner electrode 516b. Furthermore, it is not limited to this; the inner dielectric layer 514a may also contain SrTiO3 or the like as a main component. In contrast, to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable to form it from a material with a high dielectric constant, such as BaTiO3.

[0231] The dielectric layer 514 can have multiple grains containing perovskite-type compounds with BaTiO3 as the basic structure.

[0232] When the dielectric layer 514 is thin, the capacitance of the capacitor is larger, so the grain diameter is preferably less than 1 μm.

[0233] The number of stacked dielectric layers 514 is not particularly limited, but it is preferable to have 5 or more and 1000 or less, including the first outer layer portion 520a and the second outer layer portion 520b. Furthermore, the thickness of the dielectric layer 514 is preferably, for example, 0.3 μm or more and 6.0 μm or less.

[0234] (Internal electrodes)

[0235] The internal electrode 516 has a plurality of first internal electrodes 516a and a plurality of second internal electrodes 516b. The first internal electrodes 516a and the second internal electrodes 516b are stacked alternately with a dielectric layer 514 between them.

[0236] The first internal electrode 516a is disposed on the surface of the inner dielectric layer 514a. The first internal electrode 516a is opposite to the first main surface 512a and the second main surface 512b, and has a first opposing electrode portion 522a opposite to the second internal electrode 516b, and is stacked in the direction connecting the first main surface 512a and the second main surface 512b.

[0237] The first internal electrode 516a is led out to the first surface 512c and the third surface 512e of the laminate 512 via the first lead-out electrode portion 524a, and to the second surface 512d and the fourth surface 512f of the laminate 512 via the second lead-out electrode portion 524b. Furthermore, the width of the first lead-out electrode portion 524a leading to the first surface 512c can be approximately equal to the width leading to the third surface 512e, and the width of the second lead-out electrode portion 524b leading to the second surface 512d can be approximately equal to the width leading to the fourth surface 512f.

[0238] Furthermore, the first internal electrode 516a is continuously led out to the first surface 512c and the third surface 512e of the laminate 512 via the first lead-out electrode portion 524a, and continuously led out to the second surface 512d and the fourth surface 512f of the laminate 512 via the second lead-out electrode portion 524b. However, it is not limited to this and may be led out discontinuously. In addition, the first internal electrode 516a may also be configured to be exposed only on any one of the first surface 512c to the fourth surface 512f.

[0239] The second internal electrode 516b is disposed on the surface of an inner dielectric layer 514a that is different from the inner dielectric layer 514a on which the first internal electrode 516a is disposed. The second internal electrode 516b is opposite to the first main surface 512a and the second main surface 512b, and has a second opposing electrode portion 522b opposite to the first internal electrode 516a, and is stacked in the direction connecting the first main surface 512a and the second main surface 512b.

[0240] The second internal electrode 516b is led out to the first surface 512c and the fourth surface 512f of the laminate 512 via the third lead-out electrode portion 524c, and to the second surface 512d and the third surface 512e of the laminate 512 via the fourth lead-out electrode portion 524d. Furthermore, the width of the third lead-out electrode portion 524c leading to the first surface 512c can be approximately equal to the width leading to the fourth surface 512f, and the width of the fourth lead-out electrode portion 524d leading to the second surface 512d can be approximately equal to the width leading to the third surface 512e.

[0241] Furthermore, the second internal electrode 516b is continuously led out to the first surface 512c and the fourth surface 512f of the laminate 512 via the third lead-out electrode portion 524c, and continuously led out to the second surface 512d and the third surface 512e of the laminate 512 via the fourth lead-out electrode portion 524d. However, it is not limited to this and may be led out discontinuously. In addition, the second internal electrode 516b may also be configured to be exposed only on any one of the first surface 512c to the fourth surface 512f.

[0242] Furthermore, preferably, when the stacked ceramic capacitor 510 is viewed from the stacking direction, the straight line connecting the first lead-out electrode portion 524a and the second lead-out electrode portion 524b of the first internal electrode 516a intersects the straight line connecting the third lead-out electrode portion 524c and the fourth lead-out electrode portion 524d of the second internal electrode 516b.

[0243] In addition, such as Figure 23 As shown, the laminate 512 includes a side portion (W gap) 526a of the laminate 512 located between one end of the second opposing electrode portion 522b of the second inner electrode 516b and the first surface 512c in the first direction y, and a side portion (W gap) 526b of the laminate 512 located between the other end of the first opposing electrode portion 522a of the first inner electrode 516a and the second surface 512d in the first direction y.

[0244] Furthermore, such as Figure 24 As shown, the laminate 512 includes an end portion (L gap) 527a of the laminate 512 located between one end of the second opposing electrode portion 522b of the second inner electrode 516b and the third surface 512e in the second direction z, and a side portion (L gap) 527b of the laminate 512 located between the other end of the first opposing electrode portion 522a of the first inner electrode 516a and the fourth surface 512f in the second direction z.

[0245] The first internal electrode 516a and the second internal electrode 516b can be made of suitable conductive materials, such as metals like Ni, Cu, Ag, Pd, and Au, alloys containing at least one of these metals like Ni-Cu alloys and Ag-Pd alloys, but are not limited to this. Furthermore, the first internal electrode 516a and the second internal electrode 516b can be made of the same conductive material or different conductive materials.

[0246] Furthermore, by including Sn in the first internal electrode 516a and the second internal electrode 516b, the potential barrier height at the interface between the internal electrode 516 and the dielectric layer 514 can be increased, alleviating the electric field concentration at the interface between the internal electrode 516 and the dielectric layer 514, thereby improving the reliability under high-temperature loads. In this case, even if Sn is only included in either the first internal electrode 516a or the second internal electrode 516b, the effect can be fully realized.

[0247] Furthermore, it is preferable that the total number of the first internal electrode 516a and the second internal electrode 516b is 2 or more and 1000 or less. Additionally, the thickness of the first internal electrode 516a and the second internal electrode 516b is not particularly limited, but is preferably, for example, 0.3 μm or more and 6.0 μm or less.

[0248] In this embodiment, the first opposing electrode portion 522a of the first internal electrode 516a and the second opposing electrode portion 522b of the second internal electrode 516b are opposed to each other through an inner dielectric layer 514a, thereby forming a capacitor and exhibiting the characteristics of a capacitor.

[0249] (External electrode)

[0250] The external electrode 530 has a plurality of external electrodes 530 connected to the first internal electrode 516a and the second internal electrode 516b. The external electrode 530 has a first external electrode 530a, a second external electrode 530b, a third external electrode 530c, and a fourth external electrode 530d.

[0251] The first external electrode 530a is configured to cover the first lead-out electrode portion 524a in the first surface 512c and the third surface 512e, and is configured to cover a portion of the first main surface 512a and the second main surface 512b. The first external electrode 530a is electrically connected to the first lead-out electrode portion 524a of the first internal electrode 516a.

[0252] The second external electrode 530b is configured to cover the second lead-out electrode portion 524b in the second surface 512d and the fourth surface 512f, and is configured to cover a portion of the first main surface 512a and the second main surface 512b. The second external electrode 530b is electrically connected to the second lead-out electrode portion 524b of the first internal electrode 516a.

[0253] The third external electrode 530c is configured to cover the third lead-out electrode portion 524c in the first surface 512c and the fourth surface 512f, and is configured to cover a portion of the first main surface 512a and the second main surface 512b. The third external electrode 530c is electrically connected to the third lead-out electrode portion 524c of the second internal electrode 516b.

[0254] The fourth external electrode 530d is configured to cover the fourth lead-out electrode portion 524d in the second surface 512d and the third surface 512e, and is configured to cover a portion of the first main surface 512a and the second main surface 512b. The fourth external electrode 530d is electrically connected to the fourth lead-out electrode portion 524d of the second internal electrode 516b.

[0255] Furthermore, although not shown, the first external electrode 530a to the fourth external electrode 530d are disposed on either the first main surface 512a or the second main surface 512b, but they may not be formed on either main surface. In this case, the dimension of the multilayer ceramic capacitor 510 in the stacking direction x can be reduced, and the multilayer ceramic capacitor 510 can be made thinner.

[0256] Within the laminate 512, the first opposing electrode portion 522a of the first internal electrode 516a and the second opposing electrode portion 522b of the second internal electrode 516b are opposed to each other across a dielectric layer 514, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first external electrode 530a and the second external electrode 530b connected to the first internal electrode 516a and the third external electrode 530c and the fourth external electrode 530d connected to the second internal electrode 516b, exhibiting the characteristics of a capacitor.

[0257] The external electrode 530 preferably has a base electrode layer 532 and a plating layer formed to cover the base electrode layer 532. The plating layer includes a lower plating layer 534 and an upper plating layer 536 covering the lower plating layer 534.

[0258] The substrate electrode layer 532 has a first substrate electrode layer 532a, a second substrate electrode layer 532b, a third substrate electrode layer 532c, and a fourth substrate electrode layer 532d. These first substrate electrode layers 532a, second substrate electrode layers 532b, third substrate electrode layers 532c, and fourth substrate electrode layers 532d are formed from thin film layers containing multiple thin film electrodes to further improve performance.

[0259] The first base electrode layer 532a is formed to cover a portion of the first main surface 512a and the second main surface 512b, and a portion of the first surface 512c and the third surface 512e.

[0260] The second base electrode layer 532b is formed to cover a portion of the first main surface 512a and the second main surface 512b, and a portion of the second surface 512d and the fourth surface 512f.

[0261] The third base electrode layer 532c is formed to cover a portion of the first main surface 512a and the second main surface 512b, and a portion of the first surface 512c and the fourth surface 512f.

[0262] The fourth base electrode layer 532d is formed to cover a portion of the first main surface 512a and the second main surface 512b, and a portion of the second surface 512d and the third surface 512e.

[0263] First, the case where the base electrode layer 532 is formed by a sintered layer will be described. The sintered layer comprises a metallic component and a glass component. The glass component comprises at least one selected from B, Si, Ba, Mg, Al, Li, etc. Furthermore, the metallic component of the sintered layer comprises, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. Moreover, the sintered layer may also consist of multiple layers.

[0264] Furthermore, when the base electrode layer 532 is formed by sintering, it may also be a structure containing the same type of components and metals as the dielectric layer 514. In this case, assuming that the dielectric layer 514 contains a CaZrO system, the same type of components are Ca and Zr.

[0265] The sintered layer is formed by applying a conductive paste containing glass and metal components to the laminate 512 and then sintering it. The sintered layer can be formed by simultaneously sintering a laminated sheet having an internal electrode 516 and a dielectric layer 514 and applying a conductive paste to the laminated sheet; or it can be formed by sintering a laminated sheet having an internal electrode 516 and a dielectric layer 514 to obtain the laminate 512, then applying a conductive paste and sintering it. Furthermore, when simultaneously sintering the laminated sheet having an internal electrode 516 and a dielectric layer 514 and applying a conductive paste to the laminated sheet, it is preferable to add a dielectric component instead of a glass component, or to add both, to form the sintered layer.

[0266] (Lower plating layer)

[0267] The lower plating layer 534 includes a first lower plating layer 534a configured to cover the first base electrode layer 532a, a second lower plating layer 534b configured to cover the second base electrode layer 532b, a third lower plating layer 534c configured to cover the third base electrode layer 532c, and a fourth lower plating layer 534d configured to cover the fourth base electrode layer 532d.

[0268] As the underlying plating layer 534, for example, it includes at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0269] Furthermore, the lower plating layer 534 is preferably a Ni plating layer. When the lower plating layer 534 is a Ni plating layer, it can prevent the base electrode layer 532 from being eroded by the solder when mounting the multilayer ceramic capacitor 510.

[0270] Furthermore, the thickness of the lower plating layer 534 is preferably 1 μm or more and 8 μm or less.

[0271] (Upper plating layer)

[0272] The upper plating layer 536 includes a first upper plating layer 536a configured to cover the first lower plating layer 534a, a second upper plating layer 536b configured to cover the second lower plating layer 534b, a third upper plating layer 536c configured to cover the third lower plating layer 534c, and a fourth upper plating layer 536d configured to cover the fourth lower plating layer 534d.

[0273] As an upper plating layer 536, for example, it includes at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0274] Furthermore, the upper plating layer 536 is preferably a Sn plating layer. When the upper plating layer 536 is a Sn plating layer, the wettability of the solder when mounting the multilayer ceramic capacitor 10 can be improved, making mounting easier.

[0275] Furthermore, the thickness of the upper plating layer 536 is preferably 1 μm or more and 8 μm or less.

[0276] The dimension in the first direction y of the multilayer ceramic capacitor 510, including the laminate 512 and the external electrode 530, is designated as dimension L. Dimension L is preferably 0.1 mm or more and 6.0 mm or less. The dimension in the second direction z of the multilayer ceramic capacitor 510, including the laminate 512 and the external electrode 530, is designated as dimension W. Dimension W is preferably 0.1 mm or more and 6.0 mm or less. The dimension in the stacking direction x of the multilayer ceramic capacitor 510, including the laminate 512 and the external electrode 530, is designated as dimension T. Dimension T is preferably 0.03 mm or more and 1.8 mm or less.

[0277] The dimensions of the multilayer ceramic capacitor 510 are preferably set to 7 / 10 ≤ L / W ≤ 10 / 7. In this way, the multilayer 512 becomes approximately square, thus increasing the degree of freedom in installation.

[0278] In the second embodiment, in the multilayer ceramic electronic component 500, the bonding electrode 540 electrically bonds the first external electrode 530a and the second external electrode 530b of the multilayer ceramic capacitor 510 on the first main surface 512a of the laminate 512. Alternatively, the bonding electrode 540 may not electrically bond the first external electrode 530a and the second external electrode 530b of the multilayer ceramic capacitor 510, but instead electrically bond the third external electrode 530c and the fourth external electrode 530d.

[0279] The bonding electrode 540 includes a bonding base electrode 542, a bonding lower plating layer 544 covering the bonding base electrode 542, and a bonding upper plating layer 546 covering the bonding lower plating layer 544. Alternatively, the bonding electrode 540 may be composed solely of the bonding base electrode 542.

[0280] Preferably, when the DC resistance of the multilayer ceramic capacitor 510 is set to Rdc1 and the DC resistance of the bonding electrode 540 is set to Rdc3, Rdc1 ≤ Rdc3.

[0281] Furthermore, as described above, the embodiments of the present invention are disclosed through the above description, but the present invention is not limited thereto.

[0282] That is, various changes can be made to the above-described embodiments regarding mechanism, shape, material, quantity, position or configuration without departing from the technical concept and scope of the present invention, and these are included in the present invention.

[0283] <1>

[0284] A multilayer ceramic electronic component comprising a multilayer ceramic capacitor and bonding electrodes.

[0285] The multilayer ceramic capacitor comprises:

[0286] A laminated body having a first main surface and a second main surface opposite to each other in the lamination direction, a first surface and a second surface opposite to each other in the first direction orthogonal to the lamination direction, and a third surface and a fourth surface opposite to each other in the second direction orthogonal to the lamination direction and the first direction; and

[0287] At least four external electrodes are disposed on any one of the first, second, third, and fourth surfaces.

[0288] The bonding electrode is disposed on either the first main surface or the second main surface, and electrically bonds at least two of the external electrodes with the same potential to each other.

[0289] When the DC resistance of the multilayer ceramic capacitor is set to Rdc1 and the DC resistance of the bonding electrode is set to Rdc3, Rdc1≤Rdc3.

[0290] <2>

[0291] According to the laminated ceramic electronic component described in <1>, wherein...

[0292] The Rdc3 is more than 1.0 times and less than 5.0 times the Rdc1.

[0293] <3>

[0294] According to the laminated ceramic electronic component described in <1> or <2>, wherein,

[0295] The thickness of the bonding electrode in the stacking direction is thinner than the thickness of the outer electrode disposed on the same plane as the bonding electrode in the stacking direction.

[0296] <4>

[0297] The laminated ceramic electronic component according to any one of <1> to <3>, wherein...

[0298] The external electrode has a base electrode and a plating layer.

[0299] The bonding electrode comprises a bonding substrate electrode and a bonding plating layer.

[0300] The porosity of the bonding substrate electrode is higher than that of the substrate electrode disposed on the same plane as the bonding substrate electrode, and the plating layer and the bonding plating layer are plating layers of the same type.

[0301] <5>

[0302] The laminated ceramic electronic component according to any one of <1> to <3>, wherein...

[0303] The external electrode has a base electrode and a plating layer.

[0304] The bonding electrode is a sputtering electrode.

[0305] The porosity of the bonding electrode is lower than that of the substrate electrode disposed on the same plane as the bonding electrode.

[0306] Explanation of reference numerals in the attached figures

[0307] 100, 100A, 500: Laminated ceramic electronic components;

[0308] 10, 10A, 10B, 510: Multilayer ceramic capacitors;

[0309] 12, 512: Layered bodies;

[0310] 12a, 512a: Page 1;

[0311] 12b, 512b: Page 2;

[0312] 12c, 512c: Page 3;

[0313] 12d, 512d: Page 4;

[0314] 12e, 512e: Page 5;

[0315] 12f, 512f: Page 6;

[0316] 14, 514: Dielectric layer;

[0317] 14a, 514a: Inner dielectric layer;

[0318] 14b, 514b: outer dielectric layer;

[0319] 16, 516: Internal electrodes;

[0320] 16a, 516a: First internal electrode;

[0321] 16b, 516b: Second internal electrode;

[0322] 18, 518: Inner layer;

[0323] 20a, 520a: First outer layer;

[0324] 20b, 520b: Second outer layer;

[0325] 22a, 522a: First opposing electrode section;

[0326] 22b, 522b: Second opposing electrode section;

[0327] 24a, 524a: First lead-out electrode section;

[0328] 24b, 524b: Second lead-out electrode section;

[0329] 24c, 524c: Third lead-out electrode section;

[0330] 24d, 524d: 4th lead-out electrode section;

[0331] 26a, 26b, 526a, 526b: Sides of the laminate (W gaps);

[0332] 27a, 27b, 527a, 527b: Ends of the laminate (L gap);

[0333] 30, 530: External electrodes;

[0334] 30a, 530a: First external electrode;

[0335] 30b, 530b: Second external electrode;

[0336] 30c, 530c: Third external electrode;

[0337] 30d, 530d: Fourth external electrode;

[0338] 32, 532: Substrate electrode layer;

[0339] 32a, 532a: First base electrode layer;

[0340] 32b, 532b: Second base electrode layer;

[0341] 32c, 532c: Third base electrode layer;

[0342] 32d, 532d: Fourth base electrode layer;

[0343] 34, 534: Lower plating layer;

[0344] 34a, 534a: First lower plating layer;

[0345] 34b, 534b: Second lower plating layer;

[0346] 34c, 534c: Third lower plating layer;

[0347] 34d, 534d: The fourth lower plating layer;

[0348] 36, 536: Upper plating layer;

[0349] 36a, 536a: First upper plating layer;

[0350] 36b, 536b: Second upper plating layer;

[0351] 36c, 536c: Third upper plating layer;

[0352] 36d, 536d: The fourth upper plating layer;

[0353] 40, 540: Bonding electrodes;

[0354] 42, 542: Substrate bonding electrode;

[0355] 44, 544: Bonding the lower plating layer;

[0356] 46, 546: Join the upper plating layer;

[0357] 25a: First dummy electrode;

[0358] 25b: Second dummy electrode;

[0359] 25c: Third dummy electrode;

[0360] 25d: Fourth dummy electrode;

[0361] 28: Capacitor forming section;

[0362] 29: Internal electrode stack;

[0363] 29a: First internal electrode stack;

[0364] 29b: Second internal electrode stack;

[0365] 29c: Third internal electrode stack;

[0366] x: Stacking direction;

[0367] y: 1st direction;

[0368] z: Second direction;

[0369] L: The dimension of the multilayer ceramic capacitor in the first direction;

[0370] W: The dimension of the multilayer ceramic capacitor in the second direction;

[0371] T: Dimensions in the stacking direction of the multilayer ceramic capacitor.

Claims

1. A multilayer ceramic electronic component comprising a multilayer ceramic capacitor and a bonding electrode, the multilayer ceramic capacitor comprising: a multilayer body having a first main surface and a second main surface opposite to each other in a stacking direction, a first surface and a second surface opposite to each other in a first direction orthogonal to the stacking direction, and a third surface and a fourth surface opposite to each other in a second direction orthogonal to the stacking direction and the first direction; and at least four or more external electrodes disposed on any of the first surface, the second surface, the third surface, and the fourth surface, the bonding electrode being disposed on any of the first main surface or the second main surface and electrically bonding to each other at least two or more external electrodes of the same potential among the external electrodes, wherein when a direct current resistance of the multilayer ceramic capacitor is Rdc1 and a direct current resistance of the bonding electrode is Rdc3, Rdc1 ≤ Rdc3.

2. The multilayer ceramic electronic component according to claim 1, wherein the Rdc3 is 1.0 times or more and 5.0 times or less of the Rdc1.

3. The multilayer ceramic electronic component according to claim 1 or claim 2, wherein a thickness of the bonding electrode in the stacking direction is thinner than a thickness of an external electrode disposed on the same plane as the bonding electrode in the stacking direction.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the external electrode comprises a base electrode and a plating layer, the bonding electrode comprises a bonding base electrode and a bonding plating layer, a porosity of the bonding base electrode is higher than a porosity of the base electrode disposed on the same plane as the bonding base electrode, and the plating layer and the bonding plating layer are the same kind of plating layer.

5. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the external electrode comprises a base electrode and a plating layer, the bonding electrode is a sputtering electrode, a porosity of the bonding electrode is lower than a porosity of the base electrode disposed on the same plane as the bonding electrode.

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