Memory device and forming method thereof

Abstract

A memory device includes: a stack structure including a plurality of gate lines and a select gate line; a first channel structure extending in a first direction through the plurality of gate lines; a dielectric layer disposed on the first channel structure and the select gate line and extending in a second direction perpendicular to the first direction; and a conductive layer disposed in the dielectric layer, and the conductive layer is in contact with the selection gate line.

Description

Technical Field

[0001] This disclosure relates to memory devices, and more specifically, to improved structures of memory devices and methods for forming memory devices. Background Technology

[0002] Planar memory cells can be miniaturized to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is approaching its upper limit.

[0003] 3D memory architecture can overcome the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0004] According to one aspect of this disclosure, a memory device is disclosed. The memory device includes: a stacked structure including a plurality of gate lines and a select gate line; a first channel structure extending through the plurality of gate lines along a first direction; a dielectric layer disposed on the first channel structure and the select gate line and extending along a second direction perpendicular to the first direction; and a conductive layer disposed in the dielectric layer, wherein the conductive layer is in contact with the select gate line.

[0005] In some embodiments, the top portion of the first channel structure is filled with a dielectric layer.

[0006] In some implementations, in a side view of the memory device, the first bottom surface of the dielectric layer is lower than the second bottom surface of the selected gate line.

[0007] In some embodiments, the first channel structure includes a barrier layer, a storage layer, a tunneling layer, a semiconductor channel layer, and a capping layer stacked along a second direction, and in a side view of the memory device, the first top surface of the semiconductor channel layer is lower than the second bottom surface of the selected gate line.

[0008] In some implementations, the dielectric layer covers at least one first channel structure.

[0009] In some implementations, the memory device also includes an isolation structure that divides the select gate line into multiple segments.

[0010] In some implementations, the isolation structure extends along a first direction and a third direction perpendicular to the first and second directions.

[0011] In some implementations, the isolation structure is disposed in the dielectric layer.

[0012] In some implementations, the isolation structure is disposed between the first channel structure and the adjacent channel structure.

[0013] In some embodiments, the first channel structure or adjacent channel structure includes a barrier layer, a storage layer, a tunneling layer, a semiconductor channel layer, and a capping layer stacked along a second direction, and a portion of the storage layer of the first channel structure or adjacent channel structure is covered by an isolation structure.

[0014] In some implementations, in a side view of the memory device, the second top surface of the portion of the memory layer covered by the isolation structure is below the select gate line.

[0015] In some implementations, the first thickness of the selected gate line is greater than the second thickness of each of the plurality of gate lines.

[0016] In some implementations, the gate line is selected to be formed of a semiconductor material.

[0017] In some embodiments, the memory device includes a core region and a pickup region. Multiple first channel structures, a dielectric layer, and a conductive layer are disposed in the pickup region, and multiple second channel structures are disposed in the core region.

[0018] In some embodiments, a first arrangement of a plurality of first channel structures in the pickup region of a plan view of a memory device is the same as a second arrangement of a plurality of second channel structures in the core region of a plan view of a memory device.

[0019] According to another aspect of this disclosure, a memory device is disclosed. The memory device includes a stacked structure and a channel structure, the stacked structure including a plurality of gate lines and a select gate line, and the channel structure extending through the plurality of gate lines along a first direction. The channel structure includes a semiconductor channel and a memory film disposed on the semiconductor channel, and in a side view of the memory device, a first top surface of the semiconductor channel is lower than a second top surface of the select gate line.

[0020] In some embodiments, the memory film includes a tunneling layer over a semiconductor channel, a memory layer over the tunneling layer, and a barrier layer over the memory layer, and in a side view of the memory device, a first top surface of the semiconductor channel is lower than a third top surface of the memory film.

[0021] In some implementations, in a side view of the memory device, the first top surface of the semiconductor channel is lower than the bottom surface of the selected gate line.

[0022] In some embodiments, the memory device further includes a dielectric layer and a conductive layer, the dielectric layer being disposed on the channel structure and the select gate line and extending along a second direction perpendicular to the first direction, the conductive layer being disposed in the dielectric layer and contacting the select gate line.

[0023] In some implementations, the first thickness of the dielectric layer is greater than the second thickness of the selected gate line.

[0024] In some implementations, the top portion of the channel structure includes a dielectric layer surrounded by a memory film.

[0025] According to another aspect of this disclosure, a method for forming a memory device is disclosed. The method includes: forming a stacked structure and a select gate line on the stacked structure; forming a channel structure extending along a first direction in the stacked structure; dividing the select gate line into multiple segments; removing a top portion of the channel structure; forming a first dielectric layer on the top portion of the channel structure; and forming a conductive layer in the first dielectric layer that contacts the select gate line.

[0026] In some embodiments, forming a channel structure extending in a first direction in a stacked structure includes: forming a channel hole extending in the first direction in the stacked structure; forming a memory film in the channel hole; and forming a semiconductor channel in the channel hole over the memory film.

[0027] In some implementations, dividing the select gate line into multiple segments includes: forming a trench that divides the select gate line into multiple segments; and forming a second dielectric layer in the trench to isolate the multiple segments.

[0028] In some implementations, removing the top portion of the channel structure includes removing a portion of the semiconductor channel and the second dielectric layer.

[0029] In some implementations, the semiconductor channel includes a first polysilicon layer, and the selected gate line includes a second polysilicon layer, and the first polysilicon layer and the second polysilicon layer have different etch rates in the removal operation.

[0030] In some implementations, during the removal operation, the first etch rate of the first polysilicon layer is greater than the second etch rate of the second polysilicon layer.

[0031] In some embodiments, forming a first dielectric layer on the top portion of the channel structure includes forming a first dielectric layer covering the semiconductor channel and the selected gate line. Attached Figure Description

[0032] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the present disclosure and enable those skilled in the art to implement and use it.

[0033] Figure 1 A plan view of an exemplary memory device according to some embodiments of the present disclosure is shown.

[0034] Figure 2A-2B A cross-section of an exemplary memory device according to some embodiments of the present disclosure is shown.

[0035] Figure 3-13 Cross sections of exemplary memory devices at different stages of the manufacturing process according to some embodiments of the present disclosure are shown.

[0036] Figure 14 A flowchart of an exemplary method for forming a memory device according to some embodiments of the present disclosure is shown.

[0037] Figure 15 A block diagram of an exemplary system having a memory device according to some embodiments of the present disclosure is shown.

[0038] Figure 16A A view of an exemplary memory card having a memory device according to some embodiments of the present disclosure is shown.

[0039] Figure 16B A view of an exemplary solid-state drive (SSD) having a memory device according to some embodiments of the present disclosure is shown.

[0040] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0041] While specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified in ways not specifically shown in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0042] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can also be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, again at least partly depending on the context.

[0043] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with intermediate features or layers, and that “above” or “on top of” means not only “above” or “on top of” but also includes “above” or “on top of” without intermediate features or layers (i.e., directly on).

[0044] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element(s). In addition to the orientations shown in the accompanying drawings, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially related descriptive terms used herein may be interpreted accordingly.

[0045] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias (vias) are formed) and one or more dielectric layers. Dielectric

[0046] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0047] As used herein, the term "3D memory device" refers to a semiconductor device having strings of vertically oriented memory cell transistors (referred to herein as "memory strings," such as NAND memory strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically / perpendicularly" means perpendicular to the lateral surface of the substrate.

[0048] In some 3D memory devices (e.g., 3D NAND memory devices), a stack of gate electrodes can be arranged on a substrate, with multiple semiconductor channels passing through and intersecting the word lines into the implanted substrate. The bottom / lower gate electrode or electrode serves as the source select gate line, sometimes referred to as the bottom select gate (BSG). The top / upper gate electrode or electrode serves as the drain select gate (DSG) line, sometimes referred to as the top select gate (TSG). The gate electrode between the top / upper select gate electrode and the bottom / lower gate electrode serves as the word line (WL). The intersection of the word line and the semiconductor channel forms the memory cell.

[0049] With the continued demand for higher storage capacity, 3D NAND memory devices with multi-layer stacked structures have been proposed. Compared to existing 3D NAND memory devices, 3D NAND memory devices with multi-layer stacked structures typically have more layers (or conductor / dielectric layer pairs or steps) along the vertical direction. As the total thickness of the dielectric layers, including silicon oxide and / or silicon nitride, increases, the etching operation becomes more difficult. Simultaneously, the TSG polysilicon layer needs to connect multiple sets of pick-ups, and these pick-ups need to be placed next to the effective channel to reduce resistance and bring out the TSG. This further increases the difficulty of the channel etching process.

[0050] To address the aforementioned issues, this disclosure introduces an improved structure for the memory device and a method for forming the memory device, wherein the channel structure in the pickup region and the core region is identical to reduce etching difficulty. Furthermore, this disclosure also achieves the TSG pickup design by performing photolithography, etching, and deposition operations after channel formation.

[0051] Figure 1 A plan view of a memory device 100 according to some embodiments of the present disclosure is shown. Figure 2A-2B A memory device 100 according to some embodiments of the present disclosure is shown. Figure 1 The cross section of line AA' in the diagram. For example... Figure 1 As shown, the memory device includes a core region 102 and a pickup region 104. A plurality of first channel structures 108 are formed in the pickup region 104, and a plurality of second channel structures 106 are formed in the core region 102. In some embodiments, the arrangement of the plurality of first channel structures 108 in the pickup region 104 in the plan view of the memory device 100 is the same as the arrangement of the plurality of second channel structures 106 in the core region 102 in the plan view of the memory device. In other words, the channel structures in both the core region 102 and the pickup region 104 can be designed to be identical to reduce etching difficulty. Furthermore, the manufacturing process of the channel structures in both the core region 102 and the pickup region 104 can be simplified.

[0052] like Figure 2A As shown, the memory device 100 includes a stacked structure formed by multiple gate lines 206 and select gate lines 202 (e.g., one or more top select gates (TSGs) and one or more bottom select gates (BSGs) 204). In some embodiments, depending on the gate replacement operation being performed, the gate lines 206 may include conductive layers or dielectric layers. In some embodiments, prior to the gate replacement operation, the stacked structure may include staggered dielectric layers. For example, the stacked structure may include staggered silicon nitride and silicon oxide layers. In some embodiments, after the gate replacement operation, the stacked structure may include staggered conductive and dielectric layers extending in the X direction. In some embodiments, the conductive layer may be a word line, and the dielectric layer 208 may be a silicon oxide layer. In some embodiments, the conductive layer may be a gate structure comprising a gate conductive layer and a gate dielectric layer formed between the gate conductive layer and the dielectric layer 208. In some embodiments, the gate dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric layer comprises silicon oxide as a gate oxide. The gate conductive layer may comprise any suitable conductive material, such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides. In some embodiments, the gate conductive layer may comprise doped polysilicon in the form of gate polysilicon.

[0053] like Figure 2AAs shown, a first channel structure 108 extends along the Z direction through multiple gate lines 206. A select gate line 202 is formed above the stacked structure. A dielectric layer 210 extends along the X direction and is formed on the first channel structure 108 and the select gate line 202. A conductive layer 110 (e.g., a pickup structure) is formed in the dielectric layer 210, and the conductive layer 110 contacts the select gate line 202. In other words, the conductive layer 110 is formed in the dielectric layer 210 and contacts the select gate line 202 to achieve TSG pickup functionality.

[0054] In some embodiments, the isolation structure 112 (e.g., a TSG notch structure) may be formed in the dielectric layer 210 to divide the select gate line 202 into multiple segments. In some embodiments, the isolation structure 112 extends along the Z and Y directions to divide the select gate line 202 into multiple segments. In some embodiments, the dielectric layer 210 and the isolation structure 112 may be formed of the same material, such as silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the boundary between the dielectric layer 210 and the isolation structure 112 may not be obvious in a cross-sectional view, such as... Figure 2A As shown.

[0055] like Figure 2A As shown, the first channel structure 108 includes a barrier layer 220, a storage layer 222, a tunneling layer 224, a semiconductor channel layer 226, and a capping layer 228 stacked along the X direction. In some embodiments, the first channel structure 108 includes a barrier layer 220, a storage layer 222, a tunneling layer 224, a semiconductor channel layer 226, and a capping layer 228 stacked along the radial direction of the channel structure 108. In some embodiments, the barrier layer 220, the storage layer 222, and the tunneling layer 224 are also referred to as storage films. In some embodiments, the semiconductor channel layer 226 and the capping layer 228 are also referred to as semiconductor channels. In some embodiments, the barrier layer 220 may include silicon oxide, silicon oxynitride, a high-dielectric material, or any combination thereof. In some embodiments, the storage layer 222 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer 224 may include silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the storage film may be a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO).

[0056] like Figure 2A As shown, the top portion of the first channel structure 108 is filled with a dielectric layer 210. Specifically, the memory film, including the barrier layer 220, the storage layer 222, and the tunneling layer 224, is higher than the semiconductor channel, which includes the semiconductor channel layer 226 and the capping layer 228, and the space formed between the memory film and the semiconductor channel is filled with the dielectric layer 210. In other words, the top portion of the channel structure 108 includes a dielectric layer 210 surrounded by the memory film.

[0057] In some embodiments, in a side view of the memory device 100, the first bottom surface of the dielectric layer 210 is lower than the second bottom surface of the select gate line 202. In some embodiments, in a side view of the memory device 100, the first top surface of the semiconductor channel, including the semiconductor channel layer 226 and the capping layer 228, is lower than the second bottom surface of the select gate line 202.

[0058] In some embodiments, the dielectric layer 210 covers at least one first channel structure 108. In some embodiments, an isolation structure 112 is disposed between the first channel structure 108 and an adjacent channel structure 109. In some embodiments, such as Figure 2A As shown, a portion of the storage layer 222 of the first channel structure 108 or the adjacent channel structure 109 is covered by the isolation structure 112. In some embodiments, such as Figure 2B As shown, the isolation structure 112 may cut only one channel structure, for example, adjacent channel structure 109, and a portion of the barrier layer 220, storage layer 222, and tunneling layer 224 of the adjacent channel structure 109 is covered by the isolation structure 112. In some embodiments, the isolation structure 112 may also cover the semiconductor channel layer 226. In some embodiments, in a side view of the memory device 100, the second top surface of the portion of the storage layer 222 covered by the isolation structure 112 is lower than the select gate line 202. In some embodiments, the first thickness of the select gate line 202 is greater than the second thickness of each of the plurality of gate lines 206. In some embodiments, the select gate line 202 is formed of a semiconductor material. In some embodiments, the thickness of the dielectric layer 210 is greater than the thickness of the select gate line 202.

[0059] It should be noted that in some embodiments, after the channel structure is formed, the memory device 100 can be flipped and the substrate can be removed to expose the channel structure. Then, the barrier layer 220, the storage layer 222, and the tunneling layer 224 can be removed to expose the semiconductor channel layer 226. A semiconductor layer (e.g., a polysilicon layer) can be formed on the exposed semiconductor channel layer 226 as a common source.

[0060] Figure 3-13 Cross sections of a memory device 100 at different stages of the manufacturing process according to some embodiments of the present disclosure are shown. Figure 14 A flowchart of an exemplary method 1400 for forming a memory device 100 according to some embodiments of the present disclosure is shown. For the purpose of better describing the present disclosure, it will be described together with other methods. Figure 3-13 The cross-section of the memory device 100 in the middle and Figure 14Method 1400. It should be understood that the operations shown in Method 1400 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 3-13 and Figure 14 The different orders shown are executed sequentially.

[0061] like Figure 3 and Figure 14 As shown in operation 1402, a stacked structure is formed. The stacked structure includes staggered gate lines 206 and a dielectric layer 208 extending in the X direction on the substrate. In some embodiments, a BSG 204 may be formed between the stacked structure and the substrate. It should be noted here that in some embodiments, the stacked structure may include staggered dielectric layers, such as staggered silicon oxide and silicon nitride layers, and a word line replacement operation may be performed later to replace the silicon nitride layer with a conductive layer.

[0062] In some embodiments, gate line 206 may be a word line, and dielectric layer 208 may be a silicon oxide layer. In some embodiments, gate line 206 may be a dielectric layer, such as a silicon nitride layer, and dielectric layer 208 may be a silicon oxide layer. In some embodiments, when gate line 206 is a dielectric layer (e.g., a silicon nitride layer), the silicon nitride layer may be replaced by a conductive layer after a replacement operation is performed in a subsequent process. In some embodiments, gate line 206 may be a gate structure including a gate dielectric layer and a gate conductive layer on the gate dielectric layer. In some embodiments, the gate dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric layer includes silicon oxide in the form of a gate oxide. The gate conductive layer may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate conductive layer may include doped polysilicon in the form of gate polysilicon. Select gate line 202 is formed on the stacked structure.

[0063] In some implementations, BSG 204, select gate line 202, and the stacked structure are formed together. The bottom / lower gate electrode or electrode serves as the source select gate (SSG) line, which is also referred to as the bottom select gate (BSG) in some cases. The top / upper gate electrode or electrode serves as the drain select gate (DSG) line, which is also referred to as the top select gate (TSG) in some cases.

[0064] like Figure 4-5 and Figure 14 As shown in operation 1404, a channel structure 108 extending along the Z direction in the stacked structure is formed. Figure 4As shown, channel holes 107 extending along the Z direction in the stacked structure are formed. Then, as... Figure 5 As shown, a memory film including a barrier layer 220, a memory layer 222, and a tunneling layer 224 is formed in the channel via. Then, a semiconductor channel including a semiconductor channel layer 226 and a capping layer 228 is formed on top of the memory film in the channel via.

[0065] like Figure 6 and Figure 14 As shown in operation 1406, the select gate line 202 is divided into multiple segments by trench structure 111. In some embodiments, a sacrificial layer 203 is formed on the select gate line 202, and trench structure 111 is formed extending along the Z and Y directions into the sacrificial layer 203, the select gate line 202, and a portion of the channel structure 108. In some embodiments, the trench structure 111 is located at the location of the isolation structure 112 (e.g., a TSG notch structure) formed later.

[0066] In some implementations, trenches are formed extending along the Z and Y directions into a portion of the sacrificial layer 203, the select gate line 202, and the channel structure 108 to divide the select gate line 202 into multiple segments. A trench structure 111, such as a dielectric layer, is then formed in the trenches to isolate the multiple segments.

[0067] like Figure 7-11 and Figure 14 As shown in operation 1408, the top portion of the channel structure 108 is removed. Figure 7 As shown, a mask layer 205, such as a photoresist layer, is formed on the sacrificial layer 203 to define the TSG pickup area. In some embodiments, openings in the mask layer 205 define... Figure 1 The pickup area 104 is shown. In some embodiments, the pickup area 104 covers multiple channel structures, including a first channel structure 108 and an adjacent channel structure 109.

[0068] Then, as Figure 8 As shown, a first removal operation, such as a dry etching process or a wet etching process, is performed to remove a portion of the sacrificial layer 203. In some embodiments, the sacrificial layer 203 may include silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the first removal operation may stop above the channel plugs of the channel structures 108 and 109.

[0069] like Figure 9 As shown, a second removal operation, such as a dry etching process or a wet etching process, is performed to remove a portion of the dielectric layer above the select gate line 202. In some embodiments, the second removal operation may remove the channel plugs of the channel structures 108 and 109 and stop above the select gate line 202.

[0070] Then, as Figure 10 As shown, a third removal operation, such as a dry etching process or a wet etching process, is performed to remove a portion of the trench structure 111 and the capping layer 228. In some embodiments, the trench structure 111 and the capping layer 228 are formed of the same dielectric material and can be removed in the same removal operation.

[0071] like Figure 11 As shown, a fourth removal operation, such as a dry etching process or a wet etching process, is performed to remove a portion of the semiconductor channel layer 226. In some embodiments, the semiconductor channel layer 226 is formed of polysilicon, and the select gate line 202 is also formed of polysilicon. However, the select gate line 202 and the semiconductor channel layer 226 can have different etching rates in the same etching process, and therefore the fourth removal operation can remove only the semiconductor channel layer 226 without damaging or slightly damaging the select gate line 202. In some embodiments, the select gate line 202 and the semiconductor channel layer 226 can include polysilicon layers with different doping types, different doping materials, and / or different doping concentrations, such that the select gate line 202 and the semiconductor channel layer 226 can have different etching rates in the same etching process. In some embodiments, in the fourth removal operation, the etching rate of the polysilicon layer of the semiconductor channel layer 226 is greater than the etching rate of the polysilicon layer of the select gate line 202 in this removal operation.

[0072] like Figure 12 and Figure 14 As shown in operation 1410, a dielectric layer 210 is formed on the top portions of channel structures 108 and 109. In some embodiments, the dielectric layer 210 covers the semiconductor channels (including channel structures 108 and 109) and the select gate line 202. In some embodiments, in a side view of the memory device 100, the bottom surface of the dielectric layer 210 is lower than the bottom surface of the select gate line 202. In some embodiments, in a side view of the memory device 100, the top surface of the semiconductor channel, including semiconductor channel layer 226 and capping layer 228, is lower than the bottom surface of the select gate line 202.

[0073] like Figure 13 and Figure 14 As shown in operation 1412, a conductive layer 110 is formed in the dielectric layer 210 to contact the select gate line 202. The conductive layer 110 can be connected to a pickup circuit to implement a TSG pickup design.

[0074] By using the structure and method of forming the memory device, the channel structure in the pickup region and the core region can be designed to be identical to reduce etching difficulty. Furthermore, this disclosure also achieves the TSG pickup design by performing photolithography, etching, and deposition operations after channel formation.

[0075] Figure 15 A block diagram of a system 1500 having a memory device according to some aspects of this disclosure is shown. System 1500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 15 As shown, system 1500 may include a host 1508 and a memory system 1502 having one or more memory devices 1504 and a memory controller 1506. The host 1508 may be a processor (e.g., a central processing unit (CPU)) of an electronic device, or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 1508 may be configured to send data to or receive data from memory device 1504.

[0076] According to some embodiments, the memory controller 1506 is coupled to the memory device 1504 and the host 1508, and is configured to control the memory device 1504. In some embodiments, the memory device 1504 may be... Figure 1-13The memory device 100 is included. A memory controller 1506 can manage data stored in the memory device 1504 and communicate with a host 1508. In some embodiments, the memory controller 1506 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 1506 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage and enterprise storage arrays for mobile devices (e.g., smartphones, tablets, laptops, etc.). The memory controller 1506 can be configured to control the operation of the memory device 1504, such as read, erase, and program operations. In some embodiments, the memory controller 1506 is configured to control the memory cell array via first and second peripheral circuitry. The memory controller 1506 can also be configured to manage various functions relating to data stored or to be stored in the memory device 1504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1506 is also configured to process error correction codes (ECC) for data read from or written to the memory device 1504. The memory controller 1506 may also perform any other suitable function, such as formatting the memory device 1504. The memory controller 1506 can communicate with external devices (e.g., host 1508) according to specific communication protocols. For example, the memory controller 1506 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0077] The memory controller 1506 and one or more memory devices 1504 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 1502 can be implemented and packaged into different types of end electronic products. Figure 16AIn one example shown, the memory controller 1506 and a single memory device 1504 can be integrated into a memory card 1602. The memory card 1602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1602 may also include a connection between the memory card 1602 and a host computer (e.g., Figure 15 The memory card connector 1604 is coupled to the host 1508. In such a... Figure 16B In another example shown, the memory controller 1506 and multiple memory devices 1504 can be integrated into the SSD 1606. The SSD 1606 may also include interfaces for connecting the SSD 1606 to a host computer (e.g., ...). Figure 15 The SSD connector 1608 is coupled to the host 1508. In some embodiments, the storage capacity and / or operating speed of the SSD 1606 is greater than the storage capacity and / or operating speed of the memory card 1602.

[0078] The foregoing description of specific implementations can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalent variations of the disclosed implementations.

[0079] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A memory device, comprising: a stack structure including a plurality of gate lines and a select gate line; a first channel structure extending through the plurality of gate lines along a first direction; a dielectric layer disposed on the first channel structure and the select gate line and extending along a second direction perpendicular to the first direction; and a conductive layer disposed in the dielectric layer and in contact with the select gate line. A top portion of the first channel structure is filled with the dielectric layer.

2. The memory device of claim 1, wherein, In a side view of the memory device, a first bottom surface of the dielectric layer is lower than a second bottom surface of the select gate line.

3. The memory device of claim 1, wherein, The first channel structure includes a blocking layer, a storage layer, a tunneling layer, a semiconductor channel layer, and a capping layer stacked along the second direction, and in a side view of the memory device, a first top surface of the semiconductor channel layer is lower than the second bottom surface of the select gate line.

4. The memory device of claim 3, wherein, The dielectric layer covers at least one first channel structure.

5. The memory device of claim 1, wherein, 6. The memory device of claim 1, further comprising: an isolation structure separating the select gate line into a plurality of segments. The isolation structure extends along the first direction and a third direction perpendicular to the first direction and the second direction.

7. The memory device of claim 6, wherein, The isolation structure is disposed in the dielectric layer.

8. The memory device of claim 6, wherein, The isolation structure is disposed between the first channel structure and an adjacent channel structure.

9. The memory device of claim 6, wherein, The first channel structure or the adjacent channel structure includes a blocking layer, a storage layer, a tunneling layer, a semiconductor channel layer, and a capping layer stacked along the second direction, and a portion of the storage layer of the first channel structure or the adjacent channel structure is covered by the isolation structure.

10. The memory device of claim 9, wherein, In a side view of the memory device, a second top surface of the portion of the storage layer covered by the isolation structure is lower than the select gate line.

11. The memory device of claim 10, wherein, A first thickness of the select gate line is greater than a second thickness of each of the plurality of gate lines.

12. The memory device of claim 1, wherein, The select gate line is formed of a semiconductor material.

13. The memory device of claim 1, wherein, A memory device includes a core area and a pickup area, wherein:

14. The memory device of claim 1, wherein, a plurality of first channel structures, the dielectric layer, and the conductive layer are disposed in the pickup area; and a plurality of second channel structures are disposed in the core area. A first arrangement of the plurality of first channel structures in the pickup area in a plan view of the memory device is the same as a second arrangement of the plurality of second channel structures in the core area in the plan view of the memory device.

15. The memory device of claim 14, wherein, 16. A memory device, comprising: a stack structure including a plurality of gate lines and a select gate line; and a channel structure extending through the plurality of gate lines along a first direction, wherein the channel structure includes a semiconductor channel and a storage film disposed on the semiconductor channel, and in a side view of the memory device, a first top surface of the semiconductor channel is lower than a second top surface of the select gate line. ​ ​ 17. The memory device of claim 16, wherein, The storage film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer, and in a side view of the memory device, the first top surface of the semiconductor channel is lower than a third top surface of the storage film.

18. The memory device of claim 16, wherein, In a side view of the memory device, the first top surface of the semiconductor channel is lower than a bottom surface of the select gate line.

19. The memory device of claim 16, further comprising: a dielectric layer disposed on the channel structure and the select gate line and extending along a second direction perpendicular to the first direction; and a conductive layer disposed in the dielectric layer and the conductive layer is in contact with the select gate line.

20. The memory device of claim 19, wherein, A first thickness of the dielectric layer is greater than a second thickness of the select gate line.

21. The memory device of claim 19, wherein, A top portion of the channel structure includes the dielectric layer surrounded by the storage film.

22. A method of forming a memory device, comprising: forming a stack structure and a select gate line on the stack structure; forming a channel structure extending in a first direction in the stack structure; dividing the select gate line into a plurality of segments; removing a top portion of the channel structure; forming a first dielectric layer on the top portion of the channel structure; and forming a conductive layer in the first dielectric layer in contact with the select gate line.

23. The method of claim 22, wherein, Forming the channel structure extending in the first direction in the stack structure includes: forming a channel hole extending in the first direction in the stack structure; forming a storage film in the channel hole; and forming a semiconductor channel in the channel hole over the storage film.

24. The method of claim 23, wherein, Dividing the select gate line into the plurality of segments includes: forming a trench dividing the select gate line into the plurality of segments; and forming a second dielectric layer in the trench to isolate the plurality of segments.

25. The method of claim 24, wherein, Removing the top portion of the channel structure includes: removing a portion of the semiconductor channel and the second dielectric layer.

26. The method of claim 25, wherein, The semiconductor channel includes a first polysilicon layer and the select gate line includes a second polysilicon layer, and the first polysilicon layer and the second polysilicon layer have different etch rates in a removal operation.

27. The method of claim 26, wherein, In the removal operation, a first etch rate of the first polysilicon layer is greater than a second etch rate of the second polysilicon layer.

28. The method of claim 25, wherein, Forming the first dielectric layer on the top portion of the channel structure includes: forming the first dielectric layer covering the semiconductor channel and the select gate line.

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