Reading device, system and method

Abstract

The invention relates to a reading device, system and method for industrial automation for reading a signal generator wherein the reading device comprises: a computer unit comprising a first serial interface and a second serial interface, the first serial interface has a first data output, a first data input, and a preferred clock output, and the second serial interface has a second data output, a second data input, and a clock input, the clock input being connected to the first data output, and the clock input being connected to the second data output. The computer unit is designed to output, at the first data output, a clock signal for providing a clock for both the signal generator to be read and the second serial interface, and to output, at the second data output, a clock signal for providing a clock for both the signal generator to be read and the second serial interface. And receiving a signal generator data signal from the signal generator via the first data input and / or the second data input.

Description

Technical Field

[0001] This invention relates to a reading device for industrial automation, used to read a signal generator. The reading device includes a computer unit comprising a first serial interface and a second serial interface. The first serial interface has a first data output terminal, a first data input terminal, and preferably a clock output terminal. The second serial interface has a second data output terminal, a second data input terminal, and a clock input terminal. Background Technology

[0002] The signal generator includes, for example, a position encoder and is specifically designed to provide position information via a signal generator-data signal. The reading device is specifically designed to receive the signal generator-data signal and read position information from it. Summary of the Invention

[0003] The purpose of this invention is to achieve flexible reading of signal generators in an efficient manner.

[0004] This objective is achieved by the reading device according to claim 1. The clock input of the second serial interface of the reading device is connected to the first data output, and the computer unit is designed to output a clock signal at the first data output to provide a clock for the signal generator to be read and the second serial interface, and to receive a signal generator-data signal from the signal generator via the first data input and / or the second data input. The clock input is connected to the first data output, particularly via (especially extending to the outside of the computer unit) lines, such as printed wires and / or cables.

[0005] In the above scheme, the first data output (specifically, replacing the clock output) is used to generate a clock signal. Normally, a data output is used to output a data signal, not a clock signal. By using the data output to output a clock signal, new possibilities for generating clock signals are opened—specifically, it is possible to generate a clock signal at a frequency many times lower than the internal clock of the first serial interface (or the interface-clock signal obtainable from the clock output). Since the clock signal is used to provide a clock for both the signal generator to be read and the second serial interface, it is possible to make the second serial interface operate at the same clock as the clock at which the signal generator outputs its signal generator-data signal. This allows the signal generator-data signal to be received through the second serial interface in a simple manner. Furthermore, the signal generator-data signal can be received (particularly additionally or alternatively) through the first serial interface. If the first serial interface operates at a higher clock frequency compared to the second serial interface, the signal generator-data signal can be oversampled in this case to detect, for example, time values ​​(explained in more detail below) with sufficiently high accuracy, particularly the recovery time.

[0006] The signal generator is specifically designed for communication according to the ENDAT 2.1 or ENDAT 2.2 protocol. Traditionally, such signal generators are read from an FPGA or a microcontroller with special peripherals. The above approach makes it particularly possible to read such signal generators using a standard microcontroller. Specifically, no additional timer units and / or interrupts are required during data communication (i.e., during reading). Therefore, the above approach can be implemented, for example, in the microcontroller's firmware.

[0007] Advantageous improvements are the subject of the dependent claims. Preferably, the computer unit is a microcontroller. In particular, the computer unit is designed as a standard microcontroller. By using a microcontroller as the computer unit, the reading device can be implemented efficiently.

[0008] Preferably, the first serial interface is a first SPI interface, and / or the second serial interface is a second SPI interface. Microcontrollers typically have at least two (idle) SPI interfaces. For example, the first serial interface operates as an SPI master, and the second serial interface operates as an SPI slave. By interconnecting the first data output terminal (specifically the SPI-MOSI- terminal) of the first SPI interface with the clock input terminal (specifically the SPI-CLK-IN- terminal) of the second SPI interface, the above-described scheme for reading the signal generator can be implemented efficiently using two SPI interfaces.

[0009] Preferably, the computer unit is designed to output a read device-data signal to the signal generator via a second data output terminal. The read device-data signal is particularly used to transmit requests for current location information, and / or configuration commands, and / or control commands. Since the second serial interface operates using the same clock signal as the signal generator, the output of the read device-data signal can be easily implemented, allowing the signal generator to receive the read device-data signal. For example, one data bit can be transmitted per clock cycle of the clock signal.

[0010] Preferably, the reading device is designed to operate the first serial interface at a higher clock frequency than the second serial interface to read the signal generator. In this way, the second serial interface can operate at the same clock frequency as the signal generator—thus enabling more efficient communication with the signal generator—while the first serial interface operates at a higher clock frequency, thus allowing for, for example, more detailed data analysis of the received signal generator-data signal.

[0011] Preferably, the computer unit is designed to receive a signal generator-data signal using a first data input terminal, so as to detect (especially measure) a time value related to the operation of the signal generator based on the signal generator-data signal. This time value specifically refers to the time difference between the end of a clock provided by a clock signal and the resulting level change in the signal generator-data signal. For example, this time value is the so-called recovery time. Preferably, the reading device is designed to provide diagnostic information about the signal generator based on this time value. For example, the reading device checks whether safety-related operational requirements are met based on the time value and provides corresponding diagnostic information indicating the result of this check.

[0012] The present invention also relates to a system including a reading device and a signal generator. The signal generator preferably includes a position encoder designed to provide a signal generator-data signal.

[0013] Preferably, the system further includes a signal converter connected between the reading device and the signal generator, allowing the clock signal, signal generator-data signal, and / or reading device-data signal to pass through the signal converter. The signal converter is preferably designed to perform level conversion on the clock signal, signal generator-data signal, and / or reading device-data signal, and / or signal transmission type conversion between single-ended and differential signal transmission types. Preferably, the signal converter includes at least one RS485 interface through which level conversion and / or signal transmission type conversion are performed.

[0014] The signal converter device preferably has at least one switching input terminal, a signal converter-input terminal, a signal converter-output terminal, and a bidirectional signal converter-port. The bidirectional signal converter-port is connected to the bidirectional signal generator-data port of the signal generator and can be switched between an input mode (for receiving signal generator-data signals from the signal generator-data port) and an output mode (for outputting readout-data signals to the signal generator-data port) via the switching input terminal. In input mode, the logic level generated at the bidirectional signal converter-port is provided at the signal converter-output terminal. In output mode, the logic level generated at the signal converter-input terminal is provided at the bidirectional signal converter-port.

[0015] The signal converter input is suitably set to a fixed voltage level, the switching input is connected to the second data output of the reading device, and the signal converter output is connected to the second data input of the reading device. The fixed voltage level is specifically a logic high level. Therefore, preferably, the reading device-data signal to be transmitted to the signal generator is fed into the switching input, and in particular, not fed into the signal converter input (which is typically configured for this purpose). In this way, switching between input and output modes can be achieved through the reading device-data signal itself, thus eliminating the need for an additional switching signal for this purpose.

[0016] Specifically, the signal converter port is connected to the signal generator-data port via a first data line for non-inverting signal transmission and a second data line for inverting signal transmission. The system suitably includes a pull-up resistor connected to the second data line and a pull-down resistor connected to the first data line. In response to a logic high level on the read device-data signal, the signal converter device switches to output mode, thereby providing a logic high level at the bidirectional signal converter port based on a fixed voltage level generated at the signal converter-input terminal. In response to a logic low level on the read device-data signal, the signal converter device switches to input mode, and the bidirectional signal converter port is pulled to a logic low level due to the pull-up and pull-down resistors. The logic low level at the switching input terminal can be used both to send a logic low level to the signal generator and to receive the signal generator-data signal. Therefore, bidirectional communication can be achieved efficiently. In particular, bidirectional communication with precise bit switching between transmitted and received data bits can be achieved.

[0017] According to an alternative design, the computer unit has a third serial interface with a third data output terminal, a switch input terminal connected to the third data output terminal, a signal converter input terminal connected to the second data output terminal, and a signal converter output terminal connected to the second data input terminal and / or the first data input terminal. Preferably, a third SPI interface is used as the third serial interface. Through the third serial interface, the bidirectional signal converter port can switch between input and output modes. Therefore, the passive transmission of low levels can be eliminated.

[0018] The present invention also relates to a method for operating a reading device or system, comprising the steps of: outputting a clock signal for providing a clock for both a signal generator to be read and a second serial interface; and receiving a signal generator-data signal from the signal generator through a first data input terminal and / or a second data input terminal. Attached Figure Description

[0019] Other exemplary details and exemplary implementations will now be explained with reference to the accompanying drawings.

[0020] Figure 1 A schematic diagram of a system according to a first embodiment is shown, the system having a reading device, a signal generator, and a signal converter.

[0021] Figure 2 The time curves of the clock signal, signal generator-data signal, and internal clock are shown.

[0022] Figure 3 A schematic diagram of a system according to a second embodiment is shown, the system having a reading device, a signal generator, and a signal converter according to the second embodiment. Detailed Implementation

[0023] Figure 1 A schematic diagram of system 1 according to a first embodiment is shown, the system including a reading device 2, a signal generator 3, and an optional signal converter 4. System 1 represents an exemplary application environment of the reading device 2. The reading device 2 may also be provided separately.

[0024] The reading device 2 is used to read the signal generator 3. The reading device 2 and / or the signal generator 3 are suitably designed for industrial automation.

[0025] The reading device 2 includes a computer unit 5, which may be designed as a microcontroller, for example. Specifically, the computer unit 5 is not designed as an FPGA. Exemplarily, the computer unit 5 is the reading device 2. The computer unit 5 suitably includes a computer unit housing 16, which is specifically the outer casing of the computer unit 5.

[0026] Computer unit 5 includes a first serial interface 6 and a second serial interface 7. The first serial interface 6 is specifically designed as a first SPI interface. The second serial interface 7 is specifically designed as a second SPI interface. SPI stands for "Serial Peripheral Interface".

[0027] The first serial interface 6 has a first data output terminal 8 and a first data input terminal 9. Preferably, the first serial interface also has a clock output terminal 10. The first data output terminal 8 is specifically an SPI-MOSI terminal. SPI-MOSI stands for "Serial Peripheral Interface Master Output Slave Input". The first data input terminal 9 is specifically an SPI-MISO terminal. SPI-MISO stands for "Serial Peripheral Interface Master Input Slave Output".

[0028] The second serial interface 7 has a second data output terminal 12, a second data input terminal 13, and a clock input terminal 11. The second data output terminal 12 is in particular an SPI-MISO terminal. The second data input terminal 13 is in particular an SPI-MOSI terminal.

[0029] Computer unit 5 preferably includes a processor unit 14 and a storage unit 15, the processor unit having at least one processing core. Processor unit 14 is particularly designed to process data received via serial interfaces 6, 7 and / or provide (especially generate) data to be transmitted via serial interfaces 6, 7. Storage unit 15 preferably includes volatile memory (e.g., working memory) and / or non-volatile memory. According to alternative designs, storage unit 15 or a portion of storage unit 15 (e.g., non-volatile memory) may be located externally to computer unit 5.

[0030] Signal generator 3 is designed to output a signal generator-data signal. Signal generator 3 is preferably a sensor mechanism, particularly a sensor mechanism for detecting position (e.g., linear or rotary position). Signal generator 3 preferably includes a sensor unit 17, particularly a position encoder, designed to provide the signal generator-data signal. The signal generator-data signal contains, for example, position information indicating the position detected using signal generator 3. For example, signal generator 3 is used to detect the position of a drive (particularly a servo drive). For example, signal generator 3 detects the position of the drive element of the drive (particularly a rotor or carriage). Signal generator 3 preferably has a safety certification of SIL3 or lower.

[0031] The signal generator 3 preferably includes a signal generator-clock input terminal 18 and a (particularly bidirectional) signal generator-data port 19, which are preferably not designed as SPI interfaces. The signal generator-clock input terminal 18 includes, for example, a non-inverting clock-line terminal 20 and an inverting clock-line terminal 21. The signal generator-data port 19 includes, for example, a non-inverting data-line terminal 22 and an inverting data-line terminal 23.

[0032] Signal generator 3 is suitable for communication according to a synchronous serial protocol, particularly via signal generator-data port 19. For example, signal generator 3 is designed to communicate according to the ENDAT 2.1 or ENDAT 2.2 protocol (especially including diagnostic functions for the safety position sensor), particularly via signal generator-data port 19. Furthermore, signal generator 3 can be designed to communicate according to the SPI or BISS-C protocol, particularly via signal generator-data port 19.

[0033] The signal generator-clock input 18 is adapted to receive a clock signal provided by the reading device 2. The signal generator 3 is adapted to output a signal generator-data signal at the signal generator-data port 19 specifically based on the clock signal received at the signal generator-clock input 18, and / or to receive a reading device-data signal specifically based on the clock signal; preferably, the output timing of the signal generator-data signal and / or the reception timing of the reading device-data signal are set by the received clock signal. The signal generator 3 is exemplary designed to receive the clock signal and / or the reading device-data signal as differential signals, and / or output the signal generator-data signal as a differential signal. The term "differential signal" refers to a signal transmitted via differential signal transmission. Differential signal transmission can also be called symmetrical signal transmission.

[0034] The signal generator 3 also includes a signal generator-processor unit 24, which is preferably designed to receive a clock signal through the signal generator-clock input terminal 18, and / or generate a signal generator-data signal to be output through the signal generator-data port 19, and / or receive a reading device-data signal through the signal generator-data port 19.

[0035] For example, system 1 includes a signal converter 4, specifically connected between the readout device 2 and the signal generator 3, such that clock signals, signal generator-data signals, and / or readout device-data signals pass through the signal converter 4. The signal converter 4 is preferably designed to perform level conversion on the clock signals, signal generator-data signals, and / or readout device-data signals, and / or to perform signal transmission type conversion between single-ended signal transmission and differential signal transmission.

[0036] The signal converter device 4 preferably includes at least one RS485 interface through which level conversion and / or signal transmission type conversion are performed.

[0037] The signal converter device 4 preferably includes a first signal converter unit 25 and a second signal converter unit 26. The first signal converter unit 25 is connected between the first serial interface 6 and the signal generator clock input terminal 18. The second signal converter unit 26 is connected between the second serial interface 6 and the signal generator data port 19. Signal converter units 25 and 26 are preferably designed as RS485 interfaces.

[0038] The first signal converter-unit 25 includes a first switching input terminal 27, a first signal converter-input terminal 28, an (optional) first signal converter-output terminal 29, and a (particularly bidirectional) first signal converter-port 30. The first signal converter-port 30 preferably includes a first non-inverting line terminal 31 and a first inverting line terminal 32.

[0039] The second signal converter unit 26 includes a second switching input terminal 33, a second signal converter input terminal 34, a second signal converter output terminal 35, and (particularly bidirectional) a second signal converter port 36. The second signal converter port 36 preferably includes a second non-inverting line terminal 37 and a second inverting line terminal 38.

[0040] Each signal converter unit 25, 26 can be switched between a corresponding input mode and a corresponding output mode, specifically via corresponding switching inputs 27, 33. In output mode, the signal generated at the corresponding signal converter input 28 is converted into a signal that can be tapped at the corresponding signal converter ports 30, 36. In input mode, the signal generated at the corresponding signal converter ports 30, 36 is converted into a signal that can be tapped at the corresponding signal converter outputs 29, 35.

[0041] In response to a logic high level at the corresponding switching input 27 or 33, the corresponding signal converter-unit is in output mode. In response to a logic low level at the corresponding switching input 27 or 33, the corresponding signal converter-unit will be in input mode.

[0042] Each signal converter unit 25, 26 is designed to perform corresponding level conversion and corresponding signal transmission type conversion between single-ended and differential signal transmission. The term "signal transmission type conversion" refers to the conversion of signal transmission types, specifically, the conversion between single-ended and differential signal transmission. The term "single-ended signal transmission" refers to non-differential signal transmission. During level conversion, the corresponding voltage levels of high and / or low levels are specifically converted between two values.

[0043] The interconnection of the components of System 1 will be described below.

[0044] Clock input 11 is connected to first data output 8, for example, via first clock line 39. Signal generator-clock input 18 is connected to first data output 8, for example, via signal converter device 4. Specifically, first signal converter-data input 28 is connected to first data output 8, for example, via second clock line 40. First clock line 39 branches off from second clock line 40. Signal generator-clock input 18 is connected to first signal converter-port 30. For example, non-inverting clock line terminal 20 is connected to first non-inverting line terminal 31 via first line 41, while inverting clock line terminal 21 is connected to inverting line terminal 32 via second line 42. First switching input 27 is set to a fixed voltage level, particularly a logic high level. First signal converter-output 29 is preferably left unoccupied.

[0045] The signal generator-data port 19 is connected to the first data input terminal 9, the second data input terminal 13, and preferably the second data output terminal 12, specifically via the signal converter device 4. The first data input terminal 9 is specifically connected to the second signal converter-output terminal 35 via the first signal generator-data signal line 43. The second data input terminal 13 is specifically connected to the second signal converter-output terminal 35 via the second signal generator-data signal line 44. For example, the first signal generator-data signal line 43 branches off from the second signal generator-data signal line 44. The second switching input terminal 33 is connected to the second data output terminal 12, for example, via the readout device-data signal line 45. The second signal converter-input terminal 34 is set to a fixed voltage level, particularly a logic high level.

[0046] The second signal converter - port 36 is connected to the signal generator - data port 19, specifically via the first data line 46 and the second data line 47. The first data line 46 is used for non-inverting signal transmission, and the second data line 47 is used for inverting signal transmission.

[0047] System 1 also includes a pull-up resistor 48 connected to the second data line 47 and a pull-down resistor 49 connected to the first data line 46.

[0048] The listed lines 39, 40, 41, 42, 43, 44, 45, 46, and 47 are implemented, in particular, on the outside of the computer unit 5, the signal generator 3, and / or the signal converter device 4, for example, by printed wires and / or cables.

[0049] According to the alternative design, the signal converter device 4 is absent; specifically, in this case, the computer unit 5 is directly connected to the signal generator 3. For example, in this case, the computer unit 5 and the signal generator 3 communicate in the same manner (e.g., non-differential) and / or using the same logic levels.

[0050] The operation of System 1 will be discussed in more detail below.

[0051] Computer unit 5 outputs a clock signal at the first data output terminal 8 to provide a clock signal for both the signal generator 3 to be read and the second serial interface 7. For example, the clock signal is transmitted to the signal generator 3 via the first signal converter-unit 25, specifically the signal generator-clock input terminal 18. Furthermore, clock signal 50 is output (specifically directly) from the first data output terminal 8 to the first clock input terminal 11. Clock signal 50 alternates between logic high and logic low levels, both of which are suitably provided by computer unit 5 for the same (specifically constant) duration.

[0052] Computer unit 5 is suitably designed to provide an internal clock 52 that is different from the clock signal. Suitably, computer unit 5 operates the first serial interface 6 according to the internal clock. For example, the internal clock determines the maximum time resolution at which computer unit 5 can output clock signal 50 through first data output terminal 8 and / or receive signal generator-data signal through first data input terminal 9, and / or determines the time point at which computer unit 5 reads new signal value of signal generator-data signal at first data input terminal 9 and / or outputs new signal value of clock signal at first data output terminal 8. In particular, the frequency of the internal clock is higher than that of the clock signal. For example, the frequency of the internal clock is an integer multiple of the clock signal frequency (in particular, at least two or three times the clock signal frequency). For example, the internal clock can be obtained at clock output terminal 10. The signal providing the internal clock is also called the interface-clock signal.

[0053] Suitablely, computer unit 5 operates the second serial interface 7 based on a clock signal received through clock input terminal 11. For example, the clock signal determines the maximum time resolution at which computer unit 5 can output a read device-data signal through second data output terminal 12 and / or receive a signal generator-data signal through second data input terminal 13, and / or determines the time point at which computer unit 5 reads a new signal value from the signal generator-data signal at second data input terminal 13 and / or outputs a new signal value from the read device-data signal at second data output terminal 12. For example, computer unit 5 reads exactly one data bit from the signal generator-data signal through second data input terminal 13 in each clock cycle of the clock signal. For example, computer unit 5 outputs exactly one data bit from the read device-data signal through second data output terminal 12 in each clock cycle of the clock signal.

[0054] Signal generator 3 communicates via signal generator-data port 19 according to the clock signal 50, which is transmitted in particular via signal converter device 4 and received at signal generator-clock input terminal 18. For example, the clock signal determines the maximum time resolution at which signal generator 3 can read in and / or output a signal generator-data signal via signal generator-data port 19, and / or determines the time point at which signal generator 3 outputs a new signal value of the signal generator-data signal via signal generator-data port 19 and / or reads a new signal value of the signal generator-data signal via signal generator-data port 19. For example, signal generator 3 reads exactly one data bit of the signal generator-data signal via signal generator-data port 19 in each clock cycle of the clock signal. For example, signal generator 3 outputs exactly one data bit of the signal generator-data signal via signal generator-data port 19 in each clock cycle of the clock signal.

[0055] Computer unit 5 is designed to receive signal generator-data signals from signal generator 3 via a first data input terminal 9 and / or a second data input terminal 13. The data transmitted via the signal generator-data signals is specifically transmitted in telegraphic form.

[0056] The reading device 2 is preferably designed to operate the first serial interface 6 at a higher clock frequency than the second serial interface 7 to read the signal generator 3. As described above, the first serial interface 6 operates according to the interface clock signal, while the second serial interface operates using the clock signal 50 output at the first data output terminal 8.

[0057] Computer unit 5 is suitably designed to output a read device-data signal to signal generator 3 via a second data output terminal 12. The data transmitted via the read device-data signal is specifically transmitted in telegraphic form. Through the read device-data signal, computer unit 5 sends, for example, requests (e.g., requests for current location information) and / or configuration and / or control commands to signal generator 3.

[0058] Figure 2 The diagram shows the time curves for clock signal 50, signal generator-data signal 51, and internal clock 52. Time is plotted on the horizontal axis, and logic levels are plotted on the vertical axis. (Refer to the following...) Figure 2 Explain the detection of time values.

[0059] Preferably, the computer unit 5 is designed to receive the signal generator-data signal 51 using the first data input terminal 9, so as to detect a time value related to the operation of the signal generator 3 based on the signal generator-data signal 51. For example, the time value is the time difference 53 between the end 54 of the clock provided by the clock signal 50 and the resulting level change 55 of the signal generator-data signal 51. The provided clock is terminated in particular by the computer unit 5 setting the clock signal 50 to a constant logic level (here, for example, a logic high level) permanently (or at least for multiple clock cycles); alternatively, it can also be set to a low level to terminate the clock. During the level change 55, the signal generator-data signal 51 changes its logic level (e.g., from a logic high level to a logic low level) and then maintains the changed logic level (e.g., a low level), particularly permanently or temporarily, for example, until the clock signal 50 resumes or until a predetermined time period has elapsed.

[0060] Signal generator 3 suitably has its own internal clock and, in particular, can continue to operate even in the absence of a clock signal 50, especially providing certain functions. For example, signal generator 3 is designed to change the logic level of signal generator-data signal 51 in response to the termination of the clock signal 50, especially after a predetermined time period (e.g., a predetermined number of clock cycles of the internal clock of signal generator 3) has elapsed (especially by signal generator 3).

[0061] Preferably, the reading device 2 is designed to provide diagnostic information about the signal generator 3 based on a time value. This time value is particularly the recovery time, for example, an indicator of the normal operation of the signal generator 3. For example, the computer unit 5 performs (particularly repetitive) acquisition and checking of the time value, particularly within the safety-related operating range of the signal generator 3. For example, the computer unit 5 repeatedly (particularly periodically) terminates the timing of the clock signal 50 to repeatedly (particularly periodically) acquire and check the time value (particularly until the signal generator 3 performs a level change 55 on the signal generator-data signal 51). For example, the computer unit 5 checks the time value by comparing it with a predetermined threshold. Suitably, the computer unit 5 generates diagnostic information based on the comparison result. The diagnostic information specifically indicates whether the time value is within the allowable range or whether there is an unacceptable time value deviation. The diagnostic information can suitably indicate whether the signal generator 3 is operating safely.

[0062] Computer unit 5 appropriately restores the clock signal after the clock signal ends 54 (especially after a predetermined time has elapsed after the end 54).

[0063] Preferably, the time values ​​are measured after the request from computer unit 5, i.e., especially after computer unit 5 has issued a request. The telegram ending with the response of signal generator 3 (i.e., signal generator 3 issues a response) is suitably converted into a telegram containing the request from computer unit 5 using a continuous clock, so that the time values ​​can be suitably measured in each cycle.

[0064] Suitablely, the time value can be determined by computer unit 5 by reading and analyzing signal generator-data signal 51 and counting signal-clock (from the end 54 of the clock provided by clock signal 50 to the level change 55 of signal generator-data signal 51) of internal clock 52.

[0065] The following describes how data can be transmitted bidirectionally between the reading device 2 and the signal generator 3 via the second signal converter-unit 26.

[0066] First, let's introduce the transmission of data signals from the reading device 2 to the signal generator 3.

[0067] The reading device 2 outputs a reading device-data signal to the second switching input terminal 33. A logic high level generated on the second switching input terminal 33 of the reading device-data signal causes the second signal converter-unit 26 to be in output mode; that is, the second signal converter-unit 26 outputs the logic level generated on the second signal converter-input terminal 34, i.e., a logic high level, at the second signal converter-port 36. A logic low level generated on the switching input terminal 33 of the reading device-data signal causes the second signal converter-unit 26 to be in input mode; that is, the second signal converter-unit 26 outputs the logic level generated at the second signal converter-port 36 at the second signal converter-output terminal. Suitably, in input mode, the second signal converter-port 36 is in a high-impedance state. Preferably, the signal generator 3 does not transmit data during the transmission of the reading device-data signal, but instead switches to receiving data through its signal generator-data port 19, so that the signal generator-data port 19 is also suitably in a high-impedance state. In this state, the logic level at signal generator-data port 19 is determined by pull-up resistor 48 and pull-down resistor 49, thereby generating a logic low level at signal generator-data port 19. Therefore, both logic high and logic low levels can be transmitted from read device 2 to signal generator 3.

[0068] Next, we will discuss the transmission of the data signal from the signal generator 3 to the reading device 2.

[0069] To perform this transmission, the reading device 2 outputs a logic low level at the second data output terminal 12 to put the second signal converter-unit 26 into input mode. In this input mode, the second signal converter-unit 26 outputs the logic level generated at the second signal converter-port 36 at the second signal converter-output terminal 35. In this state, the logic level provided at the signal converter data port 19 (of the signal converter data signal to be transmitted) determines the logic level output at the signal converter-output terminal 35 (and received by the first data input terminal 9 and / or the second data input terminal 13).

[0070] Preferably, the first serial interface 6 generates a bit-precision clock signal (specifically clock signal 50) and appropriately evaluates the input data (specifically the signal generator-data signal) through oversampling. The internal clock of the first serial interface 6 is preferably an integer multiple of the clock available at the clock output terminal 10. The second serial interface 7 (via clock signal 50) is synchronized with the first serial interface 6 and generates the output data-reading device-data signal.

[0071] The transmitted data (reader-data signal) is sent via the enable pin (second switching input 33) of the RS485 transceiver (signal converter 4), eliminating the need for a dedicated switching signal between transmission and reception. Data lines (specifically lines 46 and 47) are terminated with pull-up and pull-down resistors. Only dominant data (logic 1) is transmitted; recessive states (logic 0) are generated through termination. Reception is automatic if no dominant state is transmitted.

[0072] Data (signal generator-data signal) is received via both the first interface 6 and the second interface 7 through data inputs 9 and 13. The second interface 7 receives the signal generator-data signal synchronously with clock signal 50 (one data bit per clock cycle). This enables convenient processing of user data in the microcontroller firmware. The first interface 6 receives the signal generator-data signal at a high integer multiple of the internal SPI clock, based on the interface clock signal. This enables subsequent data analysis, for example, for evaluating recovery time.

[0073] Suitablely, for the purpose of assessing the recovery time (especially for safety requirements), the first interface 6 can be further clocked internally, i.e., continuing to use the interface clock signal while terminating the clock signal 50, and only outputting a series of high levels to the signal generator 3 through the first data output terminal 8. In this way, the recovery time can be sampled at a clock frequency through the first interface 6.

[0074] Figure 3 System 1 according to a second embodiment is shown. Except for the differences explained below, the second embodiment is suitably designed like the first embodiment, and therefore the above explanation also applies to the second embodiment.

[0075] The computer unit 5 of the second embodiment suitably includes a third serial interface 56. It should be noted that the computer unit 5 of the first embodiment is not limited to having only two serial interfaces, but may (equally) have one or more other serial interfaces.

[0076] The third serial interface 56 is specifically designed as a third SPI interface. The third serial interface 56 has a third data output terminal 57, a third data input terminal 58, and a clock input terminal 59. The third data output terminal 57 is specifically an SPI-MISO terminal. The third data input terminal 58 is specifically an SPI-MOSI terminal.

[0077] The third data output terminal 57 is connected to the second switching input terminal 33 via the switch line 60.

[0078] The second data output terminal 12 is connected to the second signal converter input terminal 34 via the reading device-data signal line 61.

[0079] For example, no pull-up or pull-down resistors are connected to data lines 46 and 47.

[0080] Computer unit 5 is designed to selectively set the second signal converter port 36 to input mode or output mode via the third data output terminal 57. In output mode, it outputs reading device-data signal using the second data output terminal 12. In input mode, it receives signal generator-data signal using the first data input terminal 9 and / or the second data input terminal 13.

Claims

1. A reading device (2) for industrial automation, used to read a signal generator (3), wherein, The reading device (2) includes a computer unit (5), which includes a first serial interface (6) and a second serial interface (7). The first serial interface (6) has a first data output terminal (8), a first data input terminal (9), and a preferred clock output terminal (10). The second serial interface (7) has a second data output terminal (12), a second data input terminal (13), and a clock input terminal (11). The clock input terminal (11) is connected to the first data output terminal (8). The computer unit (5) is designed to output a clock signal at the first data output terminal (8) to provide a clock for both the signal generator (3) to be read and the second serial interface (7), and to receive a signal generator-data signal from the signal generator (3) through the first data input terminal (9) and / or the second data input terminal (13).

2. The reading device (2) according to claim 1, wherein, The computer unit (5) is a microcontroller.

3. The reading device (2) according to the preceding claim, wherein, The first serial interface (6) is a first SPI interface, and / or the second serial interface (7) is a second SPI interface.

4. The reading device (2) according to the preceding claim, wherein, The computer unit (5) is designed to output a reading device-data signal to the signal generator (3) via the second data output terminal (12).

5. The reading device (2) according to the preceding claim, wherein, The reading device (2) is designed to operate the first serial interface (6) at a higher clock frequency than the second serial interface (7) to read the signal generator (3).

6. The reading device (2) according to the preceding claim, wherein, The computer unit (5) is designed to receive the signal generator-data signal (51) using the first data input terminal (9) in order to detect, in particular measure, time values ​​related to the operation of the signal generator (3) based on the signal generator-data signal (51).

7. The reading device (2) according to claim 6, wherein, The time value is the time difference (53) between the end (54) of the clock provided by the clock signal (50) and the resulting level change (55) of the signal generator-data signal (51).

8. The reading device (2) according to claim 7, wherein, The reading device (2) is designed to provide diagnostic information about the signal generator (3) based on the time value.

9. A system (1) comprising a reading device (2) according to any one of the preceding claims and a signal generator (3).

10. The system (1) according to claim 9, wherein, The signal generator (3) includes a position encoder designed to provide the signal generator-data signal.

11. The system (1) according to claim 9 or claim 10, further comprising a signal converter device connected between the reading device (2) and the signal generator (3), such that the clock signal, the signal generator-data signal, and / or the reading device-data signal pass through the signal converter device, wherein, The signal converter device is designed to perform level conversion on the clock signal, the signal generator-data signal, and / or the readout device-data signal, and / or to perform signal transmission type conversion between single-ended signal transmission and differential signal transmission.

12. The system (1) according to claim 11, wherein, The signal converter device (4) includes at least one RS485 interface through which the level conversion and / or the signal transmission-conversion are performed.

13. The system (1) according to claim 11 or 12, wherein, The signal converter device (4) includes at least one switching input terminal (33), a signal converter input terminal (34), a signal converter output terminal (35), and a bidirectional signal converter port (36), wherein the bidirectional signal converter port (36) is connected to the bidirectional signal generator data port (19) of the signal generator (3), and can be switched between an input mode for receiving the signal generator data signal from the signal generator data port (19) and an output mode for outputting the reading device data signal to the signal generator data port (19) via the switching input terminal (33), wherein the signal converter input terminal (34) is set to a fixed voltage level, the switching input terminal (33) is connected to the second data output terminal (12) of the reading device, and the signal converter output terminal (35) is connected to the second data input terminal (13) and / or the first data input terminal (9) of the reading device (2).

14. The system (1) according to claim 13, wherein, The signal converter port (36) is connected to the signal generator data port (19) via a first data line (46) for non-inverting signal transmission and a second data line (47) for inverting signal transmission, and wherein the system (1) further includes a pull-up resistor (48) connected to the second data line (47) and a pull-down resistor (49) connected to the first data line (46).

15. The system (1) according to claim 11 or 12, wherein, The signal converter device (4) includes at least one switching input terminal (33), a signal converter-input terminal (34), a signal converter-output terminal (35), and a bidirectional signal converter-port (36), wherein the bidirectional signal converter-port (36) is connected to the bidirectional signal generator-data port (19) of the signal generator (3), and the switching input terminal (33) is capable of switching between an input mode for receiving the signal generator-data signal from the signal generator-data port (19) and an output mode for outputting the reading device-data signal to the signal generator-data port (19); and wherein the computer unit (5) has a third serial interface (56) with a third data output terminal (57), the switching input terminal (33) is connected to the third data output terminal (57), the signal converter-input terminal (34) is connected to the second data output terminal (12), and the signal converter-output terminal (35) is connected to the second data input terminal (13) and / or the first data input terminal (9).

16. A method for operating a reading device (2) according to any one of claims 1 to 8 or a system (1) according to any one of claims 9 to 15, comprising the following steps: The output is a clock signal used to provide a clock for both the signal generator (3) to be read and the second serial interface (7); And receive signal generator-data signals from the signal generator (3) through the first data input terminal (9) and / or the second data input terminal (13).

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