FPGA triple modular redundancy method and device based on data area and electronic equipment

Abstract

The invention discloses an FPGA triple modular redundancy method and device based on a data area and electronic equipment, and relates to the technical field of digital system fault tolerance, and the method comprises the steps: abstracting a circuit netlist into a directed graph; specifying a reinforcement object; for each reinforcement object, starting from the reinforcement object, carrying out retrograde search traversal in the reverse direction of signal transmission, and combining data paths formed by found nodes and cross nodes into a data area of the reinforcement object; merging the data areas with the cross nodes; and performing triple modular redundancy on the basis of the merged data area. On the basis of the circuit netlist, the circuit netlist is abstracted into a digraph form, and triple modular redundancy design is performed in a targeted manner by searching for data paths, dividing data areas and finding out parts which have great influence on the sequential logic circuit, so that the overhead can be saved, and the security reinforcement effect can be improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a method, apparatus, and electronic device for FPGA triple mode redundancy based on data regions. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs) are programmable logic devices characterized by short development cycles, low cost, and high flexibility. They are widely used in electronic system design, aerospace, and other fields. SRAM-based FPGAs, in particular, have become crucial core components in the aerospace industry due to their reconfigurability and cost-effectiveness. However, the presence of numerous high-energy particles in space can affect SRAM-based FPGAs, making them susceptible to single-event transients (SETs) and single-event upsets (SEUs) under space radiation. This can lead to data errors and even system crashes. SEUs and SETs are two transient ionization events in semiconductor devices caused by high-energy particles. These events can cause data to be reversed in the cells, resulting in data errors. FPGAs are particularly sensitive to charged particle radiation, especially with the advent of high-density integrated chips in recent years. Larger circuit capacities and lower operating voltages reduce their reliability in radiation environments.

[0003] Therefore, to ensure the normal operation of FPGAs, single-event upset (SOME) protection technology is receiving increasing attention. Triple Modular Redundancy (TMR) is a basic SOME protection technique. Its solution involves replicating the original circuit three times and adding a voting circuit. This increases the overhead of circuit components to improve data stability and accuracy, effectively providing radiation protection. However, traditional TMR methods have the following shortcomings: (1) The circuit with triple redundancy will generate a large area and power consumption overhead; (2) Applying triple redundancy only to some sensitive devices can save costs, but the hardening effect is not ideal; Therefore, designing an efficient and accurate triple redundancy method can improve the stability and security of circuits while reducing circuit overhead, which is particularly important in today's FPGA design.

[0004] Some existing technologies, such as patent CN202510616791.9 "A method for implementing triple mode redundancy," improve the resistance of the triple-redundant circuit netlist to accumulated errors through circuit netlist partitioning and voter insertion strategies during the triple mode redundancy implementation process. Another example is CN202510524181.6 "A method for optimizing the triple mode redundancy architecture of FPGA circuits," which addresses the problem of overly simplistic strategies in existing commercial triple mode redundancy tools. Its technical solution involves parsing and extracting netlist parsing information from a pre-set circuit netlist; performing circuit tripling and voter insertion based on the netlist parsing information and triple mode redundancy strategy information; and outputting the triple mode redundancy circuit in a user-specified circuit netlist format. None of the aforementioned existing patents involve a triple mode redundancy method based on data regions. Summary of the Invention

[0005] Based on the above problems, the purpose of this invention is to provide a method, device and electronic device for FPGA triple redundancy based on data regions. Based on the circuit netlist, it is abstracted into the form of a directed graph. By finding the data path, dividing the data region, and identifying the parts that have a greater impact on the sequential logic circuit, triple redundancy design is carried out in a targeted manner, saving costs and improving the security hardening effect.

[0006] The term "data region" refers to a circuit region composed of multiple data paths. These data paths typically connect sequential logic devices within the circuit and are critical paths for data transmission. Single-event upsets (SEUs) usually occur in circuit components with data storage capabilities, such as sequential logic devices like flip-flops (DFFs) and distributed RAM. These are often the focus of triple modulo redundancy (TMD) hardening. Single-event transients (SETs), on the other hand, typically occur in combinational logic circuits. Traditional TMD only replicates a portion of sequential logic devices three times, which cannot prevent the impact of SETs on data. If SETs are considered, the entire circuit needs to be replicated three times, resulting in significant overhead.

[0007] The technical solution adopted by this invention to achieve its objective is a triple-modular redundancy method for FPGAs based on data regions, comprising the following steps: S1. Abstract the circuit netlist into a directed graph, where the direction of the graph represents the direction of signal transmission in the circuit; S2. Specify the circuit components that need to be reinforced as the reinforcement targets; S3. Starting from the first reinforced object, perform a reverse search traversal in the opposite direction of signal transmission, marking the found nodes. If a node in another data region is found during the search, mark this node as an intersection node and stop searching the data path before the intersection node. Continue searching for other data paths. If another reinforced object or boundary is found along a certain data path, stop searching that data path, return to the previous node, and continue searching for other data paths until all data paths have been traversed, completing the reverse search of the first reinforced object. The purpose of this step is mainly to find the data paths that can affect the reinforced object. S4. Combine the data paths formed by all nodes and intersection nodes found in step S3 into the data area of ​​the first reinforced object; S5. Following the methods of steps S3 to S4, complete the reverse search traversal of all other reinforced objects and generate the corresponding data areas. S6. Merge data regions with cross nodes; the existence of cross nodes means that the data path and data region where this node is located have an impact on two or more hardened objects. Merging data regions can ensure that multiple hardened objects can be hardened with only one copy, saving costs. S7. Perform triple redundancy based on the merged data area, and insert a voter after the hardened object to vote on the result of triple redundancy.

[0008] Furthermore, the circuit components that need to be reinforced are sequential logic devices.

[0009] Furthermore, the triple redundancy mentioned in step S7 specifically involves: copying the data paths contained within the merged data area three times.

[0010] The present invention also provides an FPGA triple-mode redundancy device based on data regions, comprising: The directed graph generation module is used to abstract the circuit netlist into a directed graph, where the direction of the graph is the direction of circuit signal transmission. The reinforcement object specification module is used to specify the circuit components that need to be reinforced as reinforcement objects; The node search module is used to perform a reverse search traversal of all reinforced objects in the opposite direction of signal transmission, and mark the found nodes. If a node in another data area is found during the search of each reinforced object, this node is marked as an intersection node, and the search of the data path before the intersection node is stopped, and the search of other data paths continues. If another reinforced object or boundary is found along a certain data path, the search of that data path is stopped, and the previous node is returned to continue searching for other data paths until all data paths have been traversed. The data region generation module is used to combine the data paths formed by all nodes and intersection nodes belonging to each reinforced object into the data region of the corresponding reinforced object. The data region merging module is used to merge data regions that have overlapping nodes; The triple redundancy module is used to perform triple redundancy based on the merged data area, and a voter is inserted after the hardened object to vote on the result of the triple redundancy.

[0011] Furthermore, the hardening object designation module can designate any object as a hardening object. If not specified, all sequential logic devices are designated as hardening objects by default.

[0012] Furthermore, the three-mode redundancy module performs three-mode redundancy by copying the data paths contained within the merged data area three times.

[0013] The present invention also provides a data region-based FPGA triple mode redundancy electronic device, including a processor and a memory communicatively connected to the processor, wherein the memory stores instructions that, when executed by the processor, implement the above-described data region-based FPGA triple mode redundancy method.

[0014] The beneficial effects of this invention are as follows: It allows you to specify any circuit component as the hardening target and use it as the starting point for dividing the data area, providing greater flexibility; Using a triple redundancy method based on data regions can greatly improve data stability and enhance security hardening. By dividing the data into regions, data stability can be improved while avoiding triple redundancy for other minor circuit components, thus reducing circuit overhead. Attached Figure Description

[0015] Figure 1 This is the overall flowchart of the FPGA triple-modular redundancy method based on the data region in Embodiment 1 of the present invention; Figure 2 This is a directed graph of the original circuit topology in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the data area of ​​DFF1 in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the data area of ​​DFF2 in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the data area of ​​DFF3 in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the data areas of DFF1 and DFF2 merged according to Embodiment 1 of the present invention; Figure 7This is a directed graph of the circuit topology after implementing triple modular redundancy in Embodiment 1 of the present invention; Figure 8 This is a block diagram of the FPGA triple-modular redundancy device based on the data region in Embodiment 2 of the present invention; Figure 9 This is a block diagram of the FPGA triple-modal redundancy electronic device structure based on the data region in Embodiment 3 of the present invention. Detailed Implementation

[0016] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] Example 1 Figures 1-7 This invention illustrates a specific implementation of the FPGA triple-modular redundancy method based on data regions, comprising the following steps: S1. Abstract the circuit netlist into a directed graph, where the direction of the graph represents the direction of signal transmission in the circuit; S2. Specify the sequential logic devices that need to be hardened as the hardening targets; S3. Starting from the first reinforced object, perform a reverse search traversal in the opposite direction of signal transmission, marking the found nodes. If a node in another data area is found during the search, mark this node as an intersection node and stop searching the data path before the intersection node, continuing to search other data paths. If another reinforced object or boundary is found along a certain data path, stop searching that data path, return to the previous node and continue searching other data paths until all data paths have been traversed, completing the reverse search of the first reinforced object. S4. Combine the data paths formed by all nodes and intersection nodes found in step S3 into the data area of ​​the first reinforced object; S5. Following the methods of steps S3 to S4, complete the reverse search traversal of all other reinforced objects and generate the corresponding data areas. S6. Merge data regions with intersection nodes; S7. Perform triple redundancy based on the merged data area, which means copying the data paths contained in the merged data area three times, and inserting a voter after the hardened object to vote on the result of triple redundancy.

[0018] The following is a detailed explanation using a real circuit as an example: Abstracting the circuit topology as follows: Figure 2The directed graph shown uses sequential flip-flops as the hardening objects for triple modular redundancy. To distinguish the hardened objects from ordinary nodes, sequential flip-flops DFF1, DFF2, and DFF3 are represented by circuit diagrams, while other logic nodes are represented by circles.

[0019] First, using DFF1 as the target for hardening, begin searching the data region. For example... Figure 3 As shown, node E is found first, and the traversal continues until nodes F and D are found. Since F has no preceding node, the traversal of this path ends. From node D, node C is found, and the traversal ends. Finally, the data area of ​​DFF1 is C / D / E / F.

[0020] Then, using DFF2 as the hardening object, begin searching for the data region. For example... Figure 4 As shown, nodes I, H, G, and F are found in sequence. It is then discovered that node F has already been searched and has become a node in the DFF1 data region, therefore it is marked as an intersection node. The final data region of DFF2 is G / H / I / F.

[0021] Then, using DFF3 as the hardening target, begin searching for the data region. For example... Figure 5 As shown, nodes L and J are found sequentially. When continuing forward from J, DFF1 is found to be a reinforced object, so the search for this data path stops. Since there are no other data paths for DFF3 in this embodiment, the traversal ends. Finally, the data area of ​​DFF3 is L / J.

[0022] After the three data regions are constructed, there is a cross node F that connects the data regions DFF1 and DFF2. Therefore, the data regions DFF1 and DFF2 are merged into a single entity, as follows: Figure 6 As shown.

[0023] Finally, triple mode redundancy is performed based on the merged data region. This step only requires three-fold replication of the paths contained within the data region. In the DFF1 / DFF2 data region, node C has two data paths leading to nodes D and A. The path from C to D is within the data region, while the path from C to A is not. Therefore, the replicated circuit does not need to consider the path from C to A, and nodes A, B, and K do not participate in the triple mode redundancy process. Finally, the circuit after triple mode redundancy is connected, and a voter is inserted after the hardened object to vote on the result of triple mode redundancy. The directed graph of the circuit topology after triple mode redundancy is shown below. Figure 7 As shown.

[0024] Example 2 Figure 8 This invention illustrates a specific embodiment of the FPGA triple-mode redundancy device based on the data region, comprising: The directed graph generation module is used to abstract the circuit netlist into a directed graph, where the direction of the graph is the direction of circuit signal transmission. The Hardening Object Specifying module is used to specify the circuit components that need to be hardened as hardening objects. This module can specify any object as a hardening object. If not specified, all sequential logic devices are used as hardening objects by default.

[0025] The node search module is used to perform a reverse search traversal of all reinforced objects in the opposite direction of signal transmission, and mark the found nodes. If a node in another data area is found during the search of each reinforced object, this node is marked as an intersection node, and the search of the data path before the intersection node is stopped, and the search of other data paths continues. If another reinforced object or boundary is found along a certain data path, the search of that data path is stopped, and the previous node is returned to continue searching for other data paths until all data paths have been traversed. The data region generation module is used to combine the data paths formed by all nodes and intersection nodes belonging to each reinforced object into the data region of the corresponding reinforced object. The data region merging module is used to merge data regions that have overlapping nodes; The triple redundancy module is used to perform triple redundancy based on the merged data area, which means that the data paths contained in the merged data area are copied three times, and a voter is inserted after the hardened object to vote on the result of the triple redundancy.

[0026] Example 3 Figure 9 This invention illustrates a specific embodiment of an FPGA triple-mode redundancy electronic device based on a data region according to the present invention: it includes a processor and a memory communicatively connected to the processor. The memory stores instructions that, when executed by the processor, implement the FPGA triple-mode redundancy method based on a data region as described in Embodiment 1 above. In this embodiment, the electronic device also includes input devices such as a mouse and keyboard, and output devices such as a display.

Claims

1. A method for triple modular redundancy in FPGAs based on data regions, characterized in that, Includes the following steps: S1. Abstract the circuit netlist into a directed graph, where the direction of the graph represents the direction of signal transmission in the circuit; S2. Specify the circuit components that need to be reinforced as the reinforcement targets; S3. Starting from the first reinforced object, perform a reverse search traversal in the opposite direction of signal transmission, marking the found nodes. If a node in another data area is found during the search, mark this node as an intersection node and stop searching the data path before the intersection node, continuing to search other data paths. If another reinforced object or boundary is found along a certain data path, stop searching that data path, return to the previous node and continue searching other data paths until all data paths have been traversed, completing the reverse search of the first reinforced object. S4. Combine the data paths formed by all nodes and intersection nodes found in step S3 into the data area of ​​the first reinforced object; S5. Following the methods of steps S3 to S4, complete the reverse search traversal of all other reinforced objects and generate the corresponding data areas. S6. Merge data regions with intersection nodes; S7. Perform triple redundancy based on the merged data area, and insert a voter after the hardened object to vote on the result of triple redundancy.

2. The FPGA triple modular redundancy method based on data region according to claim 1, characterized in that: The circuit components that need to be reinforced are sequential logic devices.

3. The FPGA triple-modular redundancy method based on data region according to claim 1, characterized in that, The triple redundancy mentioned in step S7 specifically involves copying the data paths contained within the merged data area three times.

4. A FPGA triple-modular redundancy device based on data regions, characterized in that, include: The directed graph generation module is used to abstract the circuit netlist into a directed graph, where the direction of the graph is the direction of circuit signal transmission. The reinforcement object specification module is used to specify the circuit components that need to be reinforced as reinforcement objects; The node search module is used to perform a reverse search traversal of all reinforced objects in the opposite direction of signal transmission, and mark the found nodes. If a node in another data area is found during the search of each reinforced object, this node is marked as an intersection node, and the search of the data path before the intersection node is stopped, and the search of other data paths continues. If another reinforced object or boundary is found along a certain data path, the search of that data path is stopped, and the previous node is returned to continue searching for other data paths until all data paths have been traversed. The data region generation module is used to combine the data paths formed by all nodes and intersection nodes belonging to each reinforced object into the data region of the corresponding reinforced object. The data region merging module is used to merge data regions that have overlapping nodes; The triple redundancy module is used to perform triple redundancy based on the merged data area, and a voter is inserted after the hardened object to vote on the result of the triple redundancy.

5. The FPGA triple-modular redundancy device based on data region according to claim 4, characterized in that: The module for specifying the hardening object can designate any object as the hardening object. If not specified, all sequential logic devices are designated as hardening objects by default.

6. The FPGA triple-modular redundancy device based on data region according to claim 4, characterized in that, The three-mode redundancy module performs three-mode redundancy by copying the data paths contained in the merged data area three times.

7. A FPGA-based triple-modular redundancy electronic device, characterized in that: The method includes a processor and a memory communicatively connected to the processor, the memory storing instructions which, when executed by the processor, implement the method as described in any one of claims 1 to 3.

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