Parallel scanning display method and display device
By dividing image data into bit planes and loading them in parallel onto the pixel array, and utilizing the main control chip module for collaborative operation, the problem of uneven display quality under low clock conditions is solved, achieving a high-efficiency, low-power, multi-functional display effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-04
- Publication Date
- 2026-03-13
AI Technical Summary
Existing technologies struggle to achieve high-quality displays under low clock conditions, and existing parallel scanning solutions face challenges in clock and logic integration during chip implementation, failing to effectively support diverse image inputs, soft-light displays, and grayscale compensation, resulting in inconsistent display quality.
By dividing a frame of image data into multiple bit planes and loading them in parallel to the first and second pixel arrays of the display unit, and utilizing the coordinated operation of modules in the main control chip, including segmentation, memory control, transport, and scanning control modules, parallel transmission and loading of multiple lines of data can be achieved, reducing the pixel scanning clock frequency.
It significantly reduces power consumption, improves display quality and reliability, solves the problem of display imbalance, extends product life, and supports multi-functional high-quality displays.
Smart Images
Figure CN121661958A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this application relate to the field of display technology, and more specifically, to a display method and display device for parallel scanning. Background Technology
[0002] In existing technologies, a key challenge for display drivers lies in how to reduce the scanning clock frequency while maintaining or improving display quality, thereby further reducing power consumption, extending product lifespan, and improving reliability and stability. While existing parallel scanning schemes and improved algorithms can improve efficiency through multi-row parallel scanning and avoid simultaneous illumination of pixels in the same row to reduce noise, they are still limited by the difficulties in integrating clock speeds and complex logic during actual driver chip implementation, and therefore cannot fully meet application requirements.
[0003] Furthermore, existing parallel scanning algorithms still suffer from insufficient support for advanced display functions under low clock conditions. For example, they struggle to effectively support diverse image input methods and do not easily implement configurable soft-light display, scan bit depth effects, and stepless dimming. Common video issues such as dead pixels and uneven brightness in real-world applications also lack effective grayscale compensation mechanisms, making it impossible to adjust brightness in excessively bright or dark areas to achieve a balanced display effect. Therefore, it is evident that current technologies, under low clock conditions, cannot simultaneously achieve both chip-level feasibility and high-quality, multi-functional displays. Summary of the Invention
[0004] In view of this, this application provides a parallel scanning display method and display device, which simultaneously loads multiple rows of data from the first row buffer and the second row buffer into the first pixel array and the second pixel array of the display unit, respectively. This can effectively and significantly reduce the clock frequency required for pixel scanning, thereby reducing overall power consumption and achieving high grayscale.
[0005] One aspect of this application provides a parallel scanning display method, the display method comprising: Divide a frame of image data into multiple bit planes; The multiple bit planes are respectively stored in multiple block caches of at least one frame cache, wherein each block cache is used to store multiple rows of data of each bit plane; The multiple rows of data from the various block caches are transmitted in parallel to the first row cache and the second row cache; and The first row selection line and the second row selection line are controlled respectively to load multiple rows of data cached in the first row into the first pixel array of the display unit, and at the same time, multiple rows of data cached in the second row are loaded into the second pixel array of the display unit in parallel.
[0006] Optionally, the display method is applied to a parallel scanning display device, the display device comprising a main control chip and the display unit, the main control chip comprising a segmentation module, a memory control module, a memory module, a transport module, a sequencing module, and a scanning control module, wherein: The frame image data is divided into multiple bit planes by the segmentation module; The memory control module is configured to store the plurality of bit planes into a plurality of block caches of at least one frame cache of the memory module; The memory module has at least one frame cache and multiple block caches configured to store the multiple bit planes; The multiple transport blocks of the transport module are configured to transmit multiple rows of data cached by the multiple blocks in parallel to the first row selection line and the second row selection line of the sequencing module; and The scanning control module is configured to control the first row selection line and the second row selection line of the sequencing module.
[0007] Optionally, the first group of multiple transport blocks in the transport module is configured to transmit multiple rows of data from the first group of block caches in parallel to the first row selection line of the sequencing module, and the second group of multiple transport blocks in the transport module is configured to transmit multiple rows of data from the second group of block caches in parallel to the second row selection line of the sequencing module.
[0008] Optionally, the memory control module includes a memory management block, the memory module includes multiple frame buffers, and the memory management block is configured to operate the reading and writing of the multiple frame buffers.
[0009] Optionally, the memory module includes multiple time-slice sequence memories, the multiple time-slice sequence memories are configured to store time-slice sequences, and the scan control module is configured to issue a request to the transport module to transport or stop transporting the multiple bit planes based on the time-slice sequences of the multiple time-slice sequence memories.
[0010] Optionally, the transport module includes a switch matrix configured to control the operation of the frame image data before and after flipping. Before the frame image data is flipped, the switch matrix sends a request to the memory control module to sequentially read multiple block caches of the at least one frame cache; and After the frame image data is flipped, the switch matrix sends a request to the memory control module to read multiple block caches of the at least one frame cache in reverse order.
[0011] Optionally, the multiple bit planes of the frame image data are evenly divided into a first part and a second part. The multiple bit planes divided into the first part are stored in the first group of the multiple block caches of the at least one frame cache, and the multiple bit planes divided into the second part are stored in the second group of the multiple block caches of the at least one frame cache.
[0012] Optionally, the main control chip further includes a field synchronization signal module, which is configured to operate based on the source of the frame image data. The frame image data is generated by the main control chip, and the field synchronization signal module generates a field synchronization signal to drive the scanning control module; and The frame image data is input from outside the main control chip, and the field synchronization signal module receives a field synchronization signal from outside the main control chip to drive the scanning control module.
[0013] Optionally, the first row cache and the second row cache each contain multiple sets of row caches, and the scan control module is configured to operate as follows: When one of the row caches in at least one pair of row caches is full, the scan control module switches the storage of the multiple rows of data to the other row cache in the at least one pair of row caches.
[0014] Another aspect of this application provides a parallel scanning display device, the display device comprising: The main control chip includes: The segmentation module is configured to divide a frame of image data into multiple bit planes; The memory control module is coupled to the segmentation module; A memory module is coupled to the memory control module, the memory control module being configured to store the plurality of bit planes into a plurality of block caches of at least one frame cache of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; A transport module, coupled to the memory control module, the transport module comprising multiple transport blocks, wherein the multiple transport blocks correspond to multiple block caches of the at least one frame cache; A sequencing module, coupled to the transport module, includes a first row buffer, a second row buffer, a first row selection line, and a second row selection line. The plurality of transport blocks are configured to transmit the multiple rows of data in the plurality of block buffers in parallel to the first row buffer and the second row buffer. The scanning control module is coupled to the transport module and the sequencing module; and The display unit, coupled to the sequencing module, uses the scanning control module to control the first row selection line and the second row selection line respectively, loading the multiple rows of data cached in the first row into the first pixel array of the display unit, and simultaneously loading the multiple rows of data cached in the second row into the second pixel array of the display unit in parallel.
[0015] Optionally, the memory control module includes a memory management block, the memory module includes multiple frame buffers, and the memory management block is configured to operate the reading and writing of the multiple frame buffers.
[0016] Optionally, the memory module includes multiple time-slice sequence memories, the multiple time-slice sequence memories are configured to store time-slice sequences, and the scan control module is configured to issue a request to the transport module to transport or stop transporting the multiple bit planes based on the time-slice sequences of the multiple time-slice sequence memories.
[0017] Optionally, the transport module includes a switch matrix coupled to the memory control module and the plurality of transport blocks, the switch matrix being configured to control the operation of the frame image data before and after flipping: Before the frame image data is flipped, the switch matrix sends a request to the memory control module to sequentially read multiple block caches of the at least one frame cache; and After the frame image data is flipped, the switch matrix sends a request to the memory control module to read multiple block caches of the at least one frame cache in reverse order.
[0018] Optionally, the multiple bit planes of the frame image data are evenly divided into a first part and a second part. The multiple bit planes divided into the first part are stored in the first group of the multiple block caches of the at least one frame cache, and the multiple bit planes divided into the second part are stored in the second group of the multiple block caches of the at least one frame cache.
[0019] Optionally, the main control chip further includes a field synchronization signal module coupled to the scanning control module, the field synchronization signal module being configured to operate according to the source of the frame image data: The frame image data is generated by the main control chip, and the field synchronization signal module generates a field synchronization signal to drive the scanning control module; and The frame image data is input from outside the main control chip, and the field synchronization signal module receives a field synchronization signal from outside the main control chip to drive the scanning control module.
[0020] Optionally, the first row cache and the second row cache each contain multiple sets of row caches, and the scan control module is configured to operate as follows: When the storage of one of the row caches in at least one set of row caches is full, the scan control module switches the storage of the multiple rows of data to another row cache in the at least one set of row caches. Attached Figure Description
[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this application and are not intended to limit this application, wherein: Figure 1 A schematic diagram of a parallel scanning display device according to an embodiment of this application is shown.
[0022] Figure 2 This diagram illustrates a memory module in a parallel scanning display device according to an embodiment of this application.
[0023] Figure 3 This diagram illustrates a row buffer, row selection line, and display unit in a parallel scanning display device according to an embodiment of this application.
[0024] Figure 4 A flowchart illustrating a parallel scanning display method according to an embodiment of this application is shown. Detailed Implementation
[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.
[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0027] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0028] Firstly, in this application, to achieve precise control of each pixel in the micro LED display device, subsequent embodiments will specifically employ digital quantities (i.e., binary data) as the control method. Specifically, by precisely controlling the illumination duration of each pixel, different grayscale levels are achieved for each pixel in the micro LED display device, thereby realizing a delicate image display effect. For example, the scanning frequency of the micro LED display device is 60Hz, meaning that one scanning cycle is completed every 16.6ms, and the grayscale value range of each pixel in the micro LED display device is... 255 corresponds to 8 bits in binary. Therefore, to precisely control the different grayscale levels of each pixel in a micro LED display, 8 bits are needed for individual control. More specifically, this is achieved by controlling the 8-bit binary number input to each pixel (i.e., ... This allows for fine-tuning of its grayscale levels.
[0029] It should be noted that a bit plane refers to the binary data used for each pixel, and each bit of binary data can be considered as a bit plane. Referring to the previous example, It can be considered as the first bit plane. This can be considered a second bit plane, and so on. When the display device sequentially reads the data from each bit plane, it can generate the image of the current frame. Based on the foregoing, the control data of the micro-LED display device is divided into multiple bit plane data. In some embodiments, the micro-LED display device sequentially reads the data from each bit plane to complete image scanning. Specifically, it will... Divide into 255 equal parts and read... The scan can be completed by analyzing the data of each bit plane.
[0030] like Figure 1 The diagram shown is a schematic representation of a parallel scanning display device according to an embodiment of this application. The display device includes an interface 2, an image signal processing unit (ISP) 3, a main control chip 4, and a display unit 5. The image signal processing unit 3 is coupled between the interface 2 and the main control chip 4, and the main control chip 4 is coupled to the display unit 5.
[0031] The image signal processing unit 3 is configured to be located between the interface 2 for input image data and the main control chip 4 (such as an FPGA chip, including CPU, GPU and MCU) for executing the algorithm. The image signal processing unit 3 is used to preprocess and convert the input image data (or video source data). Its functions include: receiving and processing grayscale video source data from the interface 2, and performing Gamma correction processing on the data to ensure that the output grayscale matches the brightness perception of the human eye, so as to generate a bit plane data stream that meets the display requirements of the subsequent micro LED driving architecture.
[0032] like Figure 1 and Figure 2 As shown, Figure 2 This is a schematic diagram of a memory module in a parallel scanning display device according to an embodiment of this application. The main control chip 4 includes a segmentation module, a memory control module, a memory module, a transport module, a sequencing module, and a scan control module. The memory control module is coupled to the segmentation module, the memory module is coupled to the memory control module, the transport module is coupled to the memory control module, the scan control module is coupled to the transport module and the sequencing module, and the display unit 5 is coupled to the sequencing module.
[0033] The segmentation module is configured to divide a frame of image data into multiple bit planes. The memory control module is configured to store the multiple bit planes into multiple block caches of at least one frame cache of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane. In one embodiment, the segmentation module performs bit plane separation processing on the frame image data, dividing the first-width grayscale data into multiple sets of parallel second-width bit plane streams, and performing serial-to-parallel conversion to generate a third-width bit plane stream. Subsequently, the memory control module stores the data of the bit planes into the multiple block caches according to a preset block storage scheme.
[0034] In one embodiment, the segmentation module can divide the plurality of bit planes of the frame image data into a first part and a second part on an average basis. The plurality of bit planes divided into the first part are respectively stored in a first group (e.g., block cache 0 to block cache 3) of the plurality of block caches of the at least one frame cache, and the plurality of bit planes divided into the second part are respectively stored in a second group (e.g., block cache 4 to block cache 7) of the plurality of block caches of the at least one frame cache.
[0035] In one embodiment, the memory control module includes a memory management block, which contains multiple frame buffers (such as frame buffer 0 and frame buffer 1). The memory management block is configured to operate the reading and writing of the multiple frame buffers. For example, frame buffer 0 and frame buffer 1 are operated alternately by the memory management block (i.e., ping-pong operation). When frame buffer 0 is being read to output the current image data, frame buffer 1 synchronously receives and writes the next frame of image data; in the next loop, the process is reversed, with frame buffer 1 responsible for output and frame buffer 0 responsible for writing. This alternating reading and writing of the two frame buffers avoids read / write conflicts and improves data processing and driving efficiency.
[0036] Furthermore, the memory module includes multiple time-slice sequence memories (such as time-slice sequence memory 0 and time-slice sequence memory 1), which are configured to store time-slice sequences. The scan control module is configured to issue a request to the transport module to transport or stop transporting the multiple bit planes based on the time-slice sequences of the multiple time-slice sequence memories. The time-slice sequence memory 0 and the time-slice sequence memory 1 perform ping-pong operations corresponding to the frame buffer 0 and the frame buffer 1 to avoid time-slice sequence read / write conflicts.
[0037] The transport module includes multiple transport blocks, wherein the multiple transport blocks correspond to multiple block caches of the at least one frame buffer. For example, when frame buffer 0 is read to output current image data, transport blocks 0 to 7 correspond to block caches 0 to 7 in frame buffer 0; or when frame buffer 1 is read to output current image data, transport blocks 0 to 7 correspond to block caches 0' to 7' in frame buffer 1.
[0038] In one embodiment, the transport module includes a switch matrix coupled to the memory control module and the plurality of transport blocks. The switch matrix is configured to control the operation of the frame image data before and after flipping (e.g., flipping the frame image data vertically): before flipping the frame image data, the switch matrix sends a request to the memory control module to read the plurality of block caches of the at least one frame cache in a forward manner (e.g., reading block cache 0 to block cache 7 in sequence); and after flipping the frame image data, the switch matrix sends a request to the memory control module to read the plurality of block caches of the at least one frame cache in a reverse manner (e.g., reading block cache 7 to block cache 0 in sequence). The operation of the switch matrix enables the frame image data to be flipped vertically quickly, effectively improving the efficiency of image flipping.
[0039] like Figure 1 , Figure 2 and Figure 3 As shown, Figure 3This is a schematic diagram of a row buffer, row selection line, and display unit in a parallel scanning display device according to an embodiment of this application. The sequencing module is coupled to the transport module, wherein the sequencing module includes a first row buffer, a second row buffer, a first row selection line, and a second row selection line, and the plurality of transport blocks are configured to transmit the multiple rows of data in the plurality of block buffers in parallel to the first row buffer and the second row buffer.
[0040] Specifically, the first line buffer includes line buffers A0 to A3, and the second line buffer includes line buffers A4 to A7. When frame buffer 0 is read to output the current image data, multiple lines of data from block buffers 0 to 3 are transmitted in parallel to line buffers A0 to A3 via transport blocks 0 to 3, and multiple lines of data from block buffers 4 to 7 are transmitted in parallel to line buffers A4 to A7 via transport blocks 4 to 7. When frame buffer 1 is read to output the current image data, multiple lines of data from block buffers 0' to 3' are transmitted in parallel to line buffers A0 to A3 via transport blocks 0 to 3, and multiple lines of data from block buffers 4' to 7' are transmitted in parallel to line buffers A4 to A7 via transport blocks 4 to 7.
[0041] Furthermore, the first row cache and the second row cache each contain multiple sets of row caches. The first sequence of the first row cache (top portion) corresponds to row caches A0-A3 (the first half of the row) and B0-B3 (the second half of the row), and the second sequence of the second row cache (bottom portion) corresponds to row caches A4-A7 (the first half of the row) and B4-B7 (the second half of the row). When loading the first row of the first pixel array (top portion), row cache A0 loads the first half of the first row, and row cache B0 loads the second half of the first row, with the loading time interval between row cache A0 and row cache B0 being at least one clock cycle. Simultaneously, when loading the first row of the second pixel array (bottom portion), row cache A4 loads the first half of the first row, and row cache B4 loads the second half of the first row, with the loading time interval between row cache A4 and row cache B4 being at least one clock cycle, and the loading time interval between row cache B0 and row cache A4 being at least one clock cycle, and so on. By staggering and interleaving the loading of multiple line caches, data corruption caused by simultaneous reading and writing can be avoided, resulting in more even power consumption, a more stable screen, and less noise. This improves read speed, stability, and energy efficiency without increasing hardware bandwidth.
[0042] Finally, the scanning control module controls the first row selection line and the second row selection line respectively to load the multiple rows of data cached in the first row into the first pixel array of the display unit 5, and simultaneously loads the multiple rows of data cached in the second row into the second pixel array of the display unit 5. For example, the scanning control module controls the first row selection line to activate the row to be loaded in the first pixel array corresponding to the first row cache; and simultaneously controls the second row selection line to activate the row to be loaded in the second pixel array corresponding to the second row cache.
[0043] In addition, the scanning control module is also configured to transmit EM signals to the first pixel array and the second pixel array of the display unit 5 to adjust the brightness of the first pixel array and the second pixel array.
[0044] In one embodiment, the main control chip 4 further includes a field synchronization signal module coupled to the scanning control module, the field synchronization signal module being configured to operate according to the source of the frame image data: The frame image data is generated by the main control chip 4. The field synchronization signal module generates a field synchronization signal (i.e., actively generated signal) through a counter to drive the scanning control module. The frame image data is externally input from the main control chip 4. The field synchronization signal module receives a field synchronization signal (i.e., passively received signal) from the outside of the main control chip 4 to drive the scanning control module. By setting the field synchronization signal module, the user can drive the scanning control module externally or internally, which can improve the applicability of the scanning control module in different environments.
[0045] Based on the above structure, the frame image data corrected by the image signal processing unit 3 is then segmented into bit planes by the segmentation module. The segmented multi-line data is then stored and retrieved in the memory module under the control of the memory control module. Next, the transport module, according to the control and scheduling of the scanning control module, transmits the retrieved data in parallel to the first and second line buffers of the sequencing module. Simultaneously, the multi-line data in the first line buffer is loaded into the first pixel array of the display unit, and the multi-line data in the second line buffer is loaded into the second pixel array of the display unit. Through the coordinated operation of the modules, the frame image data can be correctly loaded into the first and second pixel arrays to drive the display unit 5.
[0046] Existing parallel scanning algorithms have insufficient support for advanced display functions under low clock conditions. This application simultaneously loads multiple rows of data from the first and second row buffers into the first and second pixel arrays of the display unit, respectively. This accelerates the pixel scanning speed of the scanning control module, shortens the time for transmitting multiple bit planes of the frame image data, and significantly reduces the clock frequency required for pixel scanning. This reduces overall power consumption and achieves high grayscale, thereby overcoming dead pixels and uneven local brightness to achieve a balanced display effect. The reduction in clock frequency and power consumption makes the driving of the display unit 5 more stable and reliable, and improves the product's lifespan and display quality.
[0047] like Figure 4 The diagram shown is a flowchart of a parallel scanning display method according to an embodiment of this application, applied to... Figures 1 to 3 The display device includes an interface 2, an image signal processing unit 3, a main control chip 4, and a display unit 5. The image signal processing unit 3 is coupled between the interface 2 and the main control chip 4, and the main control chip 4 is coupled to the display unit 5. Furthermore, the main control chip 4 includes a segmentation module, a memory control module, a memory module, a transport module, a sequencing module, and a scan control module. The memory control module is coupled to the segmentation module, the memory module is coupled to the memory control module, the transport module is coupled to the memory control module, the scan control module is coupled to the transport module and the sequencing module, and the display unit 5 is coupled to the sequencing module. The display method includes the following steps S101, S102, S103, and S104: Step S101: The segmentation module of the main control chip 4 divides a frame of image data into multiple bit planes. Specifically, the segmentation module performs bit plane separation processing on the frame of image data, dividing the first-width grayscale data into multiple sets of parallel second-width bit plane streams, and performing serial-to-parallel conversion to generate a third-width bit plane stream.
[0048] Step S102: The memory control module stores the multiple bit planes into multiple block caches of at least one frame cache of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane. Specifically, the memory control module is configured to store the data of the bit plane into the multiple block caches according to a preset block storage scheme.
[0049] In one embodiment, the segmentation module can divide the plurality of bit planes of the frame image data into a first part and a second part on an average basis. The plurality of bit planes divided into the first part are stored in the first group (e.g., block cache 0 to block cache 3) of the plurality of block caches of the at least one frame cache, and the plurality of bit planes divided into the second part are stored in the second group (e.g., block cache 4 to block cache 7) of the plurality of block caches of the at least one frame cache, thereby improving the storage speed of the plurality of bit planes.
[0050] In one embodiment, the memory control module includes a memory management block, which contains multiple frame buffers (such as frame buffer 0 and frame buffer 1). The memory management block is configured to operate the reading and writing of the multiple frame buffers. For example, frame buffer 0 and frame buffer 1 are operated alternately by the memory management block (i.e., ping-pong operation). When frame buffer 0 is being read to output the current image data, frame buffer 1 synchronously receives and writes the next frame of image data; in the next cycle, the process is reversed, with frame buffer 1 responsible for output and frame buffer 0 responsible for writing.
[0051] Step S103: The multiple rows of data in the multiple block caches are transmitted in parallel to the first row cache and the second row cache of the sequencing module via multiple transport blocks of the transport module. Specifically, the multiple transport blocks correspond to the multiple block caches of the at least one frame cache, wherein transport blocks 0 to 7 correspond to block caches 0 to 7 in frame cache 0, that is, the multiple rows of data in block caches 0 to 7 are transmitted in parallel to line caches A0 to A3 of the first row cache and line caches A4 to A7 of the second row cache via transport blocks 0 to 7; or transport blocks 0 to 7 correspond to block caches 0' to 7' in frame cache 1, that is, the multiple rows of data in block caches 0' to 7' are transmitted in parallel to line caches A0 to A3 of the first row cache and line caches A4 to A7 of the second row cache via transport blocks 0 to 7.
[0052] Step S104: Using the scanning control module, control the first row selection line and the second row selection line of the sequencing module respectively, load the multi-row data cached in the first row into the first pixel array of the display unit 5, and simultaneously load the multi-row data cached in the second row into the second pixel array of the display unit 5 in parallel.
[0053] Specifically, the scanning control module controls the first row selection line to activate the row to be loaded in the first pixel array corresponding to the first row cache; at the same time, it controls the second row selection line (e.g., row selection line 4 to row selection line 7) to activate the row to be loaded in the second pixel array corresponding to the second row cache.
[0054] Compared with related technologies, this application simultaneously loads multiple rows of data from the first and second row caches into the first and second pixel arrays of the display unit, respectively. This accelerates the pixel scanning speed of the scanning control module, shortens the time for transmitting multiple bit planes of the frame image data, and significantly reduces the clock frequency required for pixel scanning. This reduces overall power consumption and achieves high grayscale, thereby overcoming problems such as dead pixels and uneven local brightness to achieve a balanced display effect. The reduction in clock frequency and power consumption makes the driving of the display unit 5 more stable and reliable, and improves the product's lifespan and display quality.
[0055] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.
[0056] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.
Claims
1. A parallel scanning display method, characterized in that, The display method includes: Divide a frame of image data into multiple bit planes; The multiple bit planes are respectively stored in multiple block caches of at least one frame cache, wherein each block cache is used to store multiple rows of data of each bit plane; The multiple rows of data from the multiple block caches are transmitted in parallel to the first row cache and the second row cache; and The first row selection line and the second row selection line are controlled respectively to load multiple rows of data cached in the first row into the first pixel array of the display unit, and at the same time, multiple rows of data cached in the second row are loaded into the second pixel array of the display unit in parallel.
2. The parallel scanning display method according to claim 1, characterized in that, The display method is applied to a parallel scanning display device, which includes a main control chip and the display unit. The main control chip includes a segmentation module, a memory control module, a memory module, a transport module, a sequencing module, and a scanning control module, wherein: The frame image data is divided into multiple bit planes by the segmentation module; The memory control module is configured to store the plurality of bit planes into a plurality of block caches of at least one frame cache of the memory module; The memory module has at least one frame cache and multiple block caches configured to store the multiple bit planes; The multiple transport blocks of the transport module are configured to transmit multiple rows of data cached by the multiple blocks in parallel to the first row selection line and the second row selection line of the sequencing module; and The scanning control module is configured to control the first row selection line and the second row selection line of the sequencing module.
3. The parallel scanning display method according to claim 2, characterized in that, The first group of multiple transport blocks in the transport module is configured to transmit multiple rows of data from the first group in the multiple block caches in parallel to the first row selection line of the sequencing module, and the second group of multiple transport blocks in the transport module is configured to transmit multiple rows of data from the second group in the multiple block caches in parallel to the second row selection line of the sequencing module.
4. The parallel scanning display method according to claim 2, characterized in that, The memory control module includes a memory management block, and the memory module includes multiple frame buffers. The memory management block is configured to perform alternating reading and writing of the multiple frame buffers.
5. The parallel scanning display method according to claim 4, characterized in that, The memory module includes multiple time-slice sequence memories, which are configured to store time-slice sequences. The scan control module is configured to issue a request to the transport module to transport or stop transporting the multiple bit planes based on the time-slice sequences of the multiple time-slice sequence memories, and the multiple time-slice sequence memories perform alternating operations corresponding to the multiple frame buffers.
6. The parallel scanning display method according to claim 2, characterized in that, The transport module includes a switch matrix, which is configured to control the operation of the frame image data before and after flipping. Before the frame image data is flipped, the switch matrix sends a request to the memory control module to sequentially read multiple block caches of the at least one frame cache; and After the frame image data is flipped, the switch matrix sends a request to the memory control module to read multiple block caches of the at least one frame cache in reverse order.
7. The parallel scanning display method according to claim 2, characterized in that, The multiple bit planes of the frame image data are equally divided into a first part and a second part. The multiple bit planes divided into the first part are stored in the first group of the multiple block caches of the at least one frame cache, and the multiple bit planes divided into the second part are stored in the second group of the multiple block caches of the at least one frame cache.
8. The parallel scanning display method according to claim 2, characterized in that, The main control chip also includes a field synchronization signal module, which is configured to operate based on the source of the frame image data. The frame image data is generated by the main control chip, and the field synchronization signal module generates a field synchronization signal to drive the scanning control module; and The frame image data is input from outside the main control chip, and the field synchronization signal module receives a field synchronization signal from outside the main control chip to drive the scanning control module.
9. The parallel scanning display method according to claim 2, characterized in that, The first row cache and the second row cache each contain multiple sets of row caches, and the scan control module is configured to operate as follows: When one of the row caches in at least one pair of row caches is full, the scan control module switches the storage of the multiple rows of data to the other row cache in the at least one pair of row caches.
10. A parallel scanning display device, characterized in that, The display device includes: a memory module, a transport module, and a scanning control module, wherein the transport module is coupled to the memory module and the scanning control module, wherein: The memory module's frame buffer has multiple block caches configured to store multiple bit planes; The multiple transport blocks of the transport module are configured to transmit multiple rows of data cached by the multiple blocks in parallel to the first row selection line and the second row selection line; The scanning control module is configured to control the first row selection line and the second row selection line respectively, load multiple rows of data cached in the first row into the first pixel array of the display unit, and simultaneously load multiple rows of data cached in the second row into the second pixel array of the display unit.
11. A parallel scanning display device, characterized in that, The display device includes: The main control chip includes: The segmentation module is configured to divide a frame of image data into multiple bit planes; The memory control module is coupled to the segmentation module; A memory module is coupled to the memory control module, the memory control module being configured to store the plurality of bit planes into a plurality of block caches of at least one frame cache of the memory module, wherein each block cache is used to store multiple rows of data in each bit plane; A transport module, coupled to the memory control module, the transport module comprising multiple transport blocks, wherein the multiple transport blocks correspond to multiple block caches of the at least one frame cache; A sequencing module, coupled to the transport module, includes a first row buffer, a second row buffer, a first row selection line, and a second row selection line. The plurality of transport blocks are configured to transmit the multiple rows of data in the plurality of block buffers in parallel to the first row buffer and the second row buffer. A scanning control module is coupled to the transport module and the sequencing module; and The display unit, coupled to the sequencing module, uses the scanning control module to control the first row selection line and the second row selection line respectively, loading the multiple rows of data cached in the first row into the first pixel array of the display unit, and simultaneously loading the multiple rows of data cached in the second row into the second pixel array of the display unit in parallel.
12. The parallel scanning display device according to claim 11, characterized in that, The memory control module includes a memory management block, and the memory module includes multiple frame buffers. The memory management block is configured to perform alternating reading and writing of the multiple frame buffers.
13. The parallel scanning display device according to claim 12, characterized in that, The memory module includes multiple time-slice sequence memories, which are configured to store time-slice sequences. The scan control module is configured to issue a request to the transport module to transport or stop transporting the multiple bit planes based on the time-slice sequences of the multiple time-slice sequence memories, and the multiple time-slice sequence memories perform alternating operations corresponding to the multiple frame buffers.
14. The parallel scanning display device according to claim 11, characterized in that, The transport module includes a switch matrix coupled to the memory control module and the plurality of transport blocks. The switch matrix is configured to control the operation of the frame image data before and after flipping. Before the frame image data is flipped, the switch matrix sends a request to the memory control module to sequentially read multiple block caches of the at least one frame cache; and After the frame image data is flipped, the switch matrix sends a request to the memory control module to read multiple block caches of the at least one frame cache in reverse order.
15. The parallel scanning display device according to claim 11, characterized in that, The multiple bit planes of the frame image data are equally divided into a first part and a second part. The multiple bit planes divided into the first part are stored in the first group of the multiple block caches of the at least one frame cache, and the multiple bit planes divided into the second part are stored in the second group of the multiple block caches of the at least one frame cache.
16. The parallel scanning display device according to claim 11, characterized in that, The main control chip also includes a field synchronization signal module coupled to the scanning control module, the field synchronization signal module being configured to operate based on the source of the frame image data: The frame image data is generated by the main control chip, and the field synchronization signal module generates a field synchronization signal to drive the scanning control module; and The frame image data is input from outside the main control chip, and the field synchronization signal module receives a field synchronization signal from outside the main control chip to drive the scanning control module.
17. The parallel scanning display device according to claim 11, characterized in that, The first row cache and the second row cache each contain multiple sets of row caches, and the scan control module is configured to operate as follows: When one of the row caches in at least one pair of row caches is full, the scan control module switches the storage of the multiple rows of data to the other row cache in the at least one pair of row caches.