Data driver and display device including same

Abstract

A data driver according to an embodiment and a display device including the same are disclosed. The data driver includes: an output circuit configured to output an image data voltage in analog form; a selection circuit configured to connect one of an output terminal of the output circuit and a conductive line to which a black data voltage is applied to a data line; and a control circuit configured to control the selection circuit such that the image data voltage and the black data voltage are alternately output at predetermined time intervals.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0124520, filed on September 12, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to data drives and display devices including such data drives. Background Technology

[0004] Various flat panel display devices, such as liquid crystal displays and electroluminescent displays, are known. Electroluminescent displays can display input images by emitting light themselves without backlight, using light-emitting elements disposed on each pixel. Based on the material of the light-emitting layer, the light-emitting elements of electroluminescent displays can be classified into organic light-emitting elements and inorganic light-emitting elements.

[0005] Recently, display devices using light-emitting diodes (LEDs) (inorganic light-emitting elements) as the light-emitting elements of pixels have attracted attention as next-generation display devices. Because LEDs are made of inorganic materials, they do not require a separate encapsulation layer to protect organic materials from moisture, and they are more reliable and have a longer lifespan than organic light-emitting diodes (OLEDs). In addition, LEDs have fast illumination speed, excellent luminous efficiency, and shock resistance. Summary of the Invention

[0006] Because multiple LEDs arranged in an LED display device have the characteristic of high luminous efficiency under high driving current, it is necessary to drive the LEDs with a high current and high duty cycle for a short period of time.

[0007] In a method for implementing duty cycle driving, the driving speed or driving frequency is increased to sequentially apply image data voltages and then sequentially apply black data voltages during a frame period.

[0008] However, this driving method has limitations in reducing the duty cycle of the light-emitting element.

[0009] This disclosure is intended to address all of the aforementioned needs and issues.

[0010] This disclosure provides a data driver capable of reducing the duty cycle of a light-emitting element and a display device including the data driver.

[0011] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0012] A data driver according to an embodiment of the present disclosure may include: an output circuit configured to output an image data voltage in analog form; a selection circuit configured to connect one of the output terminal of the output circuit and a wire to which a black data voltage is applied to a data line; and a control circuit configured to control the selection circuit to alternately output the image data voltage and the black data voltage at predetermined time intervals.

[0013] A display device according to an embodiment of the present disclosure may include: a pixel array having arranged a plurality of data lines, a plurality of gate lines, and a plurality of pixels; a data driver configured to output a data voltage to the plurality of data lines; and a gate driver configured to output a gate signal to the plurality of gate lines; wherein the data driver includes: an output circuit configured to output an image data voltage in analog form; a selection circuit configured to connect one of the output terminal of the output circuit and a wire to which a black data voltage is applied; and a control circuit configured to control the selection circuit to alternately output the image data voltage and the black data voltage at predetermined time intervals.

[0014] This disclosure reduces the duty cycle of the light-emitting element by alternately outputting image data voltage and black data voltage to the data line at predetermined time intervals.

[0015] This disclosure can reduce the duty cycle of the light-emitting element, thereby reducing power consumption and minimizing the peak current.

[0016] This disclosure enables low-power operation due to its ability to reduce power consumption.

[0017] The effects of this application are not limited to those described above, and those skilled in the art will clearly understand from the following description and appended claims other effects not mentioned. Attached Figure Description

[0018] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0019] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0020] Figure 2 This is a diagram illustrating a pixel circuit according to an embodiment of the present disclosure;

[0021] Figure 3This is a diagram illustrating the unit pixel structure according to an embodiment of the present disclosure;

[0022] Figure 4 This is a diagram illustrating the configuration of a data driver according to an embodiment of the present disclosure;

[0023] Figures 5A to 5C , Figures 6 to 8 as well as Figure 9A and Figure 9B This is a diagram used to explain the data voltage output principle according to the first embodiment of the present disclosure;

[0024] Figure 10 and Figure 11 This is a diagram used to explain the data voltage output principle according to the second embodiment of the present disclosure;

[0025] Figure 12 and Figure 13 This is a diagram used to explain the data voltage output principle according to the third embodiment of this disclosure. Detailed Implementation

[0026] The advantages and features of this application, as well as methods of implementing them, will become apparent from the preferred embodiments described in detail with reference to the accompanying drawings. However, this application is not limited to the embodiments described below and can be implemented in different forms. The embodiments are provided only to fully disclose this disclosure and to fully convey the scope of this disclosure to those skilled in the art. This application is defined by the disclosed claims.

[0027] Since the shapes, dimensions, scales, angles, quantities, etc., disclosed in the drawings used to describe embodiments of this disclosure are merely exemplary, this disclosure is not limited to the items shown. Throughout the specification, the same reference numerals denote the same parts. Furthermore, in describing this disclosure, detailed descriptions of relevant known technologies will be omitted where it is determined that such detailed descriptions might unnecessarily obscure the gist of this disclosure.

[0028] When using terms such as "comprising," "having," or "consisting of" in this specification, other parts may be added unless "only" is used. Unless otherwise expressly stated, the singular form of a component includes the plural form.

[0029] When explaining components, it should be understood that the tolerance range is included, even if there is no separate explicit description.

[0030] When describing positional relationships, such as when describing the positional relationship between two parts as "on top of", "in the upper part", "in the lower part", "next to", etc., one or more other parts may also be located between the two parts unless "immediately adjacent" or "directly" is used.

[0031] Although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the "first component" mentioned below can also be a "second component" within the technical spirit of this disclosure.

[0032] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0033] The following embodiments may be combined or integrated with each other in part or in whole, and may be connected and operated in various technical ways. The embodiments may be performed independently of each other or in relation to each other.

[0034] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] In the display device disclosed herein, the pixel circuit and gate driving circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon (LTPS) TFTs including low-temperature polycrystalline silicon, etc.

[0036] The gate signal oscillates between the gate on-state voltage and the gate off-state voltage. The gate on-state voltage is set to a voltage higher than the transistor's threshold voltage, and the gate off-state voltage is set to a voltage lower than the transistor's threshold voltage.

[0037] A transistor turns on in response to a gate on-voltage and turns off in response to a gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be a high gate voltage, and the gate off-voltage can be a low gate voltage. In the case of a p-channel transistor, the gate on-voltage can be a low gate voltage, and the gate off-voltage can be a high gate voltage.

[0038] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0039] refer to Figure 1 The display device according to embodiments of the present disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels of the display panel 100. Additionally, the display device includes a power supply 150.

[0040] The display panel 100 may be, but is not limited to, a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be a heterogeneous panel, at least a portion of which is curved or elliptical.

[0041] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels. These power lines may be commonly connected to pixel circuitry to provide the voltage required to drive the pixels 101.

[0042] Each pixel 101 can be divided into red, green, and blue sub-pixels for color implementation. Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic light-emitting diode (LED). Each pixel circuitry is connected to data lines, gate lines, and power lines. In the following description, a pixel may be interpreted as a sub-pixel.

[0043] Pixels can be arranged as true-color pixels and pentile pixels. A pentile pixel can achieve a higher resolution than a true-color pixel by driving two sub-pixels of different colors as a single pixel (pixel 101) and using a pre-defined pixel rendering algorithm. The pixel rendering algorithm can compensate for insufficient color representation in each pixel by utilizing the colors of light emitted from neighboring pixels.

[0044] The display area AA comprises multiple pixel rows L1 to Ln. Each of the pixel rows L1 to Ln comprises a row of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. Those pixels arranged in a pixel row share a gate line 103. Subpixels arranged along the data line direction in the column direction Y share the same data line 102.

[0045] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and real objects in the background are visible. The display panel 100 can be made of a flexible display panel.

[0046] Power supply 150 receives an input voltage applied from host system 300 and outputs the voltage required to drive pixels 101 of display panel 100 and display panel driving circuitry. For this purpose, power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 150 can output a constant voltage (or DC voltage) via the DC-DC converter, such as gate on-state voltage, gate off-state voltage, pixel drive voltage, cathode voltage, reference voltage, and IC drive voltage of display panel driving circuitry. Gate on-state voltage and gate off-state voltage can be provided to level shifter 140 and gate driver 120. Voltages such as pixel drive voltage, cathode voltage, and reference voltage can be provided to pixel 101 via a power line commonly connected to pixel 101.

[0047] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image into the pixels 101 of the display panel 100. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0048] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. The touch sensor driver is not included. Figure 1 As shown in the diagram, the data driver 110 and the touch sensor driver can be integrated into a single source driver IC.

[0049] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 can receive a gamma reference voltage and generate a gamma compensation voltage for each grayscale using a voltage divider circuit. The gamma compensation voltage for each grayscale is provided to a digital-to-analog converter (hereinafter referred to as "DAC") located in each channel of the data driver 110.

[0050] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting a first mode and a second mode. The DAC converts the pixel data into a gamma-compensated voltage and outputs a data voltage for the pixel data.

[0051] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wiring of the display area AA. The gate driver 120 may be disposed in at least one of the left non-display area NA and the right non-display area NA outside the display area AA in the display panel 100, or at least a portion of the gate driver 120 may be disposed within the display area AA.

[0052] Under the control of the timing controller 130, the gate driver 120 sequentially outputs gate signal pulses to the gate line 103. The gate driver 120 can sequentially provide the gate signal to the gate line 103 by shifting the gate signal pulses using a shift register. When multiple gate signals are applied to individual pixels, the gate driver 120 may include multiple shift registers. The gate signals may include scan signals and emission signals (or EM signals) input to the pixel circuit through multiple gate lines.

[0053] The timing controller 130 receives digital video data of the input image and timing signals synchronized with the data from the host system 300. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of one horizontal period (1H).

[0054] The timing controller 130 can control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 300. The timing controller 130 can synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0055] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 140. The level shifter 140 can convert the voltage of the gate timing control signal received from the timing controller 130 into the swing width between the gate on voltage and the gate off voltage, and provide it to the gate driver 120.

[0056] The host system 300 may include a motherboard from one of a television system, set-top box, navigation system, personal computer (PC), vehicle system, mobile terminal, and wearable terminal. The host system 300 can scale the image signal from the video source according to the resolution of the display panel 100 and can transmit it to the timing controller 130 along with a timing signal.

[0057] Figure 2 This is a diagram illustrating a pixel circuit according to an embodiment of the present disclosure.

[0058] refer to Figure 2The pixel circuit according to an embodiment of the present disclosure includes a light-emitting element LD, a driving element DT that supplies current to the light-emitting element LD, a plurality of switching elements T1 and T2 that switch a current path connected to the driving element DT, and a capacitor Cst. The driving element DT and the switching elements T1 and T2 may be implemented as p-channel transistors, but are not limited thereto.

[0059] A light-emitting element (LD) may include an anode, a cathode, and a light-emitting layer. The cathode of the LD may be connected to a first power line PL1 to which a pixel driving voltage EVDD is applied. The anode of the LD may be connected to a driving element DT. The LD may be, but is not limited to, light-emitting elements such as OLEDs, mini-LEDs, or micro-LEDs. In the case of mini-LEDs or micro-LEDs, the LD may have a vertical structure, wherein electrodes are arranged on the upper and lower parts of the semiconductor chip in which the LD is integrated, but is not limited to this. The semiconductor chip in which the LD is integrated may be implemented in a lateral structure or a flip-chip structure.

[0060] The driving element DT can be turned on by the voltage of the first node n1 to drive the light-emitting element LD. The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to the second power line PL2 to which the pixel base voltage EVSS is applied.

[0061] The first switching element T1 provides a data voltage Vdata to the gate electrode of the driving element DT in response to the scan signal SCAN. The first switching element T1 includes a gate electrode to which the scan signal SCAN is applied, a first electrode connected to a data line DL to which the data voltage is applied, and a second electrode connected to a first node n1.

[0062] The second switching element T2 applies a reference voltage Vref to the second node n2 in response to the scan signal SCAN. The second switching element T2 includes a gate electrode to which the scan signal SCAN is applied, a first electrode connected to the second node n2, and a second electrode connected to the reference voltage line RL to which the reference voltage Vref is applied. Alternatively, the second switching element T2 can be implemented as a dual transistor comprising two transistors connected in series, but is not limited thereto.

[0063] Capacitor Cst is connected between a first node n1 and a second node n2. Capacitor Cst includes a first electrode connected to the first node n1 and a second electrode connected to the second node n2.

[0064] The pixel circuits described in this article are merely examples and are not necessarily limited to this.

[0065] Figure 3This is a diagram illustrating a unit pixel structure according to an embodiment of the present disclosure.

[0066] refer to Figure 3 Pixel 101 may include two sub-pixels for each color. Each pixel 101 includes two sub-pixels S1 and S4, which are adjacent in a second direction (Y direction) parallel to the data line 102 and have pixel data of the first color written on them; two sub-pixels S2 and S5, which are adjacent in the second direction (Y direction) and have pixel data of the second color written on them; and two sub-pixels S3 and S6, which are adjacent in the second direction (Y direction) and have pixel data of the third color written on them. The first color may be red, the second color may be green, and the third color may be blue, but is not limited thereto. For example, sub-pixels S1 and S4 may be red sub-pixels SP_R with a data voltage of red data applied to them. Sub-pixels S2 and S5 may be green sub-pixels SP_G with a data voltage of green data applied to them. Sub-pixels S3 (3-1) and S6 (3-2) can be blue sub-pixels SP_B that have been subjected to a data voltage of blue data.

[0067] Sub-pixels S1, S2, and S3 can be interpreted as main sub-pixels. Sub-pixels S4, S5, and S6 can be interpreted as redundant or auxiliary sub-pixels.

[0068] In this case, data lines connected to sub-pixels of the same color can be shared. For example, sub-pixels S1 and S4 can be connected to a single data line 1021, sub-pixels S2 and S5 can be connected to a single data line 1022, and sub-pixels S3 and S6 can be connected to a single data line 1023.

[0069] Furthermore, the gate lines connected to the sub-pixels of each pixel row can be shared. For example, sub-pixels S1-1 and S4-1, S2-1 and S5-2, and S3-1 and S6-3 can share the gate line 1031 to which the scan signal SCAN is applied.

[0070] Figure 4 This is a diagram illustrating the configuration of a data driver according to an embodiment of the present disclosure. Figures 5A to 5C , Figures 6 to 8 as well as Figure 9A and Figure 9B This is a diagram used to explain the data voltage output principle according to the first embodiment of this disclosure.

[0071] refer to Figure 4 The data driver according to embodiments of the present disclosure may include a control circuit 110a, an output circuit 110b, a selection circuit 110c, and a memory 110d.

[0072] The control circuit 110a can receive pixel data and data timing control signals from the timing controller, transmit the pixel data to the output circuit 110b based on the received data timing control signals, and control the selection circuit 110c to control the image data voltage or black data voltage to be output to the corresponding data line DL via the output channels OUT(1), OUT(2), ..., OUT(N-1) and OUT(N).

[0073] For example, in duty cycle driven mode, control circuit 110a can control selection circuit 110c to alternately output image data voltage or black data voltage.

[0074] In the case of non-duty cycle drive, control circuit 110a can copy pixel data corresponding to the image data voltage output to the data line and store the pixel data in memory 110d. It can also use the stored pixel data to output the same image data voltage to output circuit 110b so that the black data voltage is replaced with the image data voltage when the black data voltage is output.

[0075] The output circuit 110b may include a shift register SR, a latch LAT, a digital-to-analog converter DAC, and an amplifier AMP.

[0076] The shift register SR can shift the clock input from the timing controller to generate a sampling clock, and can output the generated sampling clock sequentially to the latch LAT.

[0077] The latch (LAT) can sample and store the pixel data of the input image according to the timing of the sequentially input sampling clock, and can simultaneously output the stored pixel data.

[0078] A digital-to-analog converter (DAC) can use the gamma compensation voltage for each grayscale level to convert pixel data output from a latch (LAT) into analog image data voltage.

[0079] The amplifier (AMP) can amplify the voltage level of analog image data voltage and output the amplified image data voltage to the corresponding data line through the output terminal.

[0080] Selection circuit 110c may include multiple first switches SW1 and multiple second switches SW2. The multiple first switches SW1 can output image data voltage from output circuit 110b to the data line corresponding to the output channel. The multiple second switches SW2 can output black data voltage to the corresponding data line of each output channel.

[0081] In this case, black data voltage can be supplied from the power supply, but it is not limited to this.

[0082] Each of the multiple first switches SW1 is connected between the output of the amplifier AMP in the output circuit 110b and the data line, and when turned on by the control circuit 110a, the image data voltage can be output to the data line. During this period, the corresponding second switch SW2 is turned off.

[0083] Each of the multiple second switches SW2 is connected between the wire to which the black data voltage is applied and the data line, and the black data voltage can be output to the data line when turned on by the control circuit 110a. During this period, the corresponding first switch SW1 is turned off.

[0084] In embodiments based on this disclosure, such as Figures 5A to 5C As shown, the image data voltages D1...D6 and the black data voltage B are alternately output to the data lines via the selection circuit 110c at different timings at predetermined time intervals. Here, the predetermined time interval for alternately outputting the image data voltage and the black data voltage to the data lines can be n × horizontal period H (n is a non-negative integer). Furthermore, the time interval between different timings of applying the image data voltage and the black data voltage to the same pixel row represents the emission time of the light-emitting element.

[0085] The following describes the benefits of the duty cycle driving method according to embodiments of this disclosure compared to a comparative example.

[0086] like Figure 6 As shown, the duty cycle driving method of the comparative example applies image data voltages D1...D6 sequentially through all scan lines during one frame period, and then applies black data voltages sequentially.

[0087] In the case of the duty cycle driven method in the comparative example, such as Figure 7 As shown, since the black data voltage is applied after the image data voltage is applied to all scan lines, the duty cycle can be adjusted from 25% to 75%, but the duty cycle cannot be adjusted below 25%.

[0088] like Figure 8As shown, the duty cycle driving method according to the first embodiment of this disclosure alternately applies image data voltages D1...D6 and black data voltages B to each data line at predetermined time intervals.

[0089] Image data voltages D1...D6 are applied synchronously with the first output of the scan signal output through each scan line, and black data voltage B is applied synchronously with the second output of the scan signal after the emission time. Furthermore, after the last scan signal for applying the image data voltages is output, multiple black data voltages corresponding to the length of the emission time can be applied sequentially.

[0090] For example, image data voltage D1 is applied synchronously with the first output timing of the first scan signal SCAN [1], and black data voltage B is applied synchronously with the second output timing of the first scan signal SCAN [1]. Image data voltage D2 is applied synchronously with the first output timing of the second scan signal SCAN [2], and black data voltage B is applied synchronously with the second output timing of the second scan signal SCAN [2]. In terms of timing, the second output timing of one scan signal can be between the first output timings of two other adjacent scan signals. For example, as Figure 8 As shown, the second output timing of the first scan signal SCAN[1] can be between the first output timing of the third scan signal SCAN[3] and the first output timing of the fourth scan signal SCAN[4]. In this way, the image data voltages D1...D6 and the black data voltage B can be applied alternately at predetermined time intervals.

[0091] Therefore, in embodiments according to this disclosure, since the image data voltage and the black data voltage can be applied separately in time and alternately until the last scan signal for applying the image data voltage is output, the black data voltage can be applied freely.

[0092] In this case, the first output timing of adjacent scan signals, such as the first output timing of the nth scan signal and the first output timing of the (n+1)th scan signal, are separated by a time interval that is one horizontal period (1H) larger than a predetermined time interval (n × horizontal period H). For example, as Figure 8 As shown, the first output timing of adjacent scan signals is separated by a time interval of one horizontal period (1H), but is not limited thereto.

[0093] When the duty cycle driving method according to the first embodiment of this disclosure is applied, such as Figure 9A and 9B As shown, the duty cycle can be adjusted from a minimum of 1% to a maximum of 50%, thus allowing the duty cycle to be adjusted to a minimum of 25% lower than the duty cycle driven method implemented in the comparative example.

[0094] For example, such as Figure 9A As shown, if the vertical resolution is 510×4=2160H and the light emission time of the light-emitting element is 20H, then the minimum duty cycle can be 20 / 2160×100≒ 1%.

[0095] As another example, such as Figure 9B As shown, if the vertical resolution is 510×4=2160H and the light emission time of the light-emitting element is 1080H, then the maximum duty cycle can be 1080 / 2160×100≒50%.

[0096] When the driving method according to the first embodiment of this disclosure is applied, the duty cycle can be adjusted according to the light emission time of the light-emitting element. For example, as the light emission time of the light-emitting element decreases, the duty cycle decreases; conversely, as the light emission time increases, the duty cycle increases.

[0097] Furthermore, in embodiments according to this disclosure, the duty cycle can be set differently based on the luminous efficiency of the light-emitting element of each color.

[0098] Figure 10 and Figure 11 This is a diagram used to explain the data voltage output principle according to the second embodiment of the present disclosure.

[0099] refer to Figure 10 and Figure 11 The light-emitting element of the red pixel, which has the greatest change in luminous efficiency, can be duty cycle driven, while the light-emitting elements of the remaining green and blue pixels can be non-duty cycle driven.

[0100] The reason is that for light-emitting elements with small changes in luminous efficiency, driving them with a lower duty cycle has almost no effect on reducing power consumption, but increases peak current.

[0101] For example, in the case of red pixels, image data voltages R1...R6 are applied at the first output timing of the scan signal output to each scan line, and black data voltage B is applied at the second output timing after the emission time.

[0102] In the case of green pixels, image data voltages G1...G6 are applied at the first output timing of the scan signal output to each scan line, and the same image data voltages G1...G4 are applied at the second output timing after the emission time. In this case, other voltages, such as black data voltage B, may be applied during the emission time corresponding to the time interval between the first and second output timings of the first scan signal SCAN[1].

[0103] In the case of blue pixels, image data voltages B1...B6 are applied at the first output timing of the scan signal output to each scan line, and the same image data voltages B1...B4 are applied at the second output timing after the emission time. In this case, other voltages, such as black data voltage B, may be applied during the emission time corresponding to the time interval between the first and second output timings of the first scan signal SCAN[1].

[0104] The data driver can apply image data voltage at the first output timing of the scan signal output to each scan line of the green and blue pixels, and copy or store the corresponding image data voltage, and then output the stored image data voltage at the second output timing.

[0105] Therefore, the light-emitting elements of the red pixels are driven with a 10% duty cycle, while the light-emitting elements of the green and blue pixels are driven with a 100% duty cycle, meaning they are not duty cycle driven.

[0106] In a second embodiment according to this disclosure, only the light-emitting element of the red pixel with the largest change in luminous efficiency is duty cycle driven, thereby not only reducing power consumption but also minimizing the magnitude of the peak current.

[0107] Figure 12 and Figure 13 This is a diagram used to explain the data voltage output principle according to the third embodiment of this disclosure.

[0108] refer to Figure 12 and Figure 13 The light-emitting elements of red and blue pixels, whose luminous efficiency changes, can be duty cycle driven, while the light-emitting elements of the remaining green pixels can be non-duty cycle driven.

[0109] For example, in the case of red pixels, image data voltages R1...R6 are applied at the first output timing of the scan signal output to each scan line, and black data voltage B is applied at the second output timing after the emission time.

[0110] In the case of green pixels, image data voltages G1...G6 are applied at the first output timing of the scan signal output to each scan line, and the same image data voltages G1...G4 are applied at the second output timing after the emission time. In this case, other voltages, such as black data voltage B, may be applied during the emission time corresponding to the time interval between the first and second output timings of the first scan signal SCAN[1].

[0111] In the case of blue pixels, image data voltages B1...B6 are applied at the first output timing of the scan signal output to each scan line, and black data voltage B is applied at the second output timing after the emission time.

[0112] Therefore, the light-emitting elements of the red and blue pixels are driven with a 10% duty cycle, while the light-emitting elements of the green pixels are driven with a 100% duty cycle, meaning they are not duty cycle driven.

[0113] In a third embodiment according to this disclosure, the light-emitting elements of the red and blue pixels, where only the luminous efficiency changes, are duty cycle driven, thereby not only reducing power consumption but also minimizing the magnitude of the peak current.

[0114] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A data driver, comprising: Output circuit, configured to output image data voltage in analog form; The selection circuit is configured to connect one of the output terminal of the output circuit and a wire to which a black data voltage is applied to the data line; as well as A control circuit configured to control the selection circuit to alternately output the image data voltage and the black data voltage at predetermined time intervals.

2. The data driver according to claim 1, wherein, The control circuit is configured to control the selection circuit such that, during each frame period, the image data voltage is output at a first output of the gate signal at a timed time, and the black data voltage is output at a second output of the gate signal at a timed time.

3. The data driver according to claim 2, wherein, The predetermined time interval is set to n × horizontal period, where n is a natural number.

4. The data driver according to claim 2, wherein, The control circuit is configured to control the selection circuit such that when the image data voltage is output to the red sub-pixel, the red image data voltage is output at the first output timing, and the black data voltage is output at the second output timing.

5. The data driver according to claim 4, wherein, The control circuit is configured to control the selection circuit such that when the sub-pixel to which the image data voltage is to be output is a green sub-pixel, a green image data voltage is output at the first output timing, and an image data voltage with the same green image data voltage is output at the second output timing.

6. The data driver according to claim 5, wherein, The control circuit is configured to control the selection circuit such that when the sub-pixel to which the image data voltage is to be output is a blue sub-pixel, a blue image data voltage is output at the first output timing, and an image data voltage with the same blue image data voltage is output at the second output timing.

7. The data driver according to claim 6, further comprising: A memory that stores pixel data corresponding to the green image data voltage and the blue image data voltage output at the first output timing.

8. The data driver according to claim 1, wherein, The selection circuit includes: A plurality of first switches, the plurality of first switches being connected between the output terminal of the output circuit and the data line; and A plurality of second switches are connected between the wire and the data line.

9. A display device, comprising: A pixel array, wherein multiple data lines, multiple gate lines and multiple pixels are arranged in the pixel array; A data driver configured to output a data voltage to the plurality of data lines; as well as A gate driver configured to output a gate signal to the plurality of gate lines; The data driver includes: Output circuit, configured to output image data voltage in analog form; A selection circuit, configured to connect one of the output terminal of the output circuit and a wire to which a black data voltage is applied, to the data line; and A control circuit configured to control the selection circuit to alternately output the image data voltage and the black data voltage at predetermined time intervals.

10. The display device according to claim 9, wherein, The control circuit is configured to control the selection circuit such that, during each frame period, the image data voltage is output at a first output of the gate signal at a timed time, and the black data voltage is output at a second output of the gate signal at a timed time.

11. The display device according to claim 10, wherein, Each of the plurality of pixels includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The control circuit is configured to control the selection circuit such that when the image data voltage is output to the red sub-pixel, the red image data voltage is output at the first output timing, and the black data voltage is output at the second output timing.

12. The display device according to claim 11, wherein, The control circuit is configured to control the selection circuit such that when the image data voltage is output to the green sub-pixel, a green image data voltage is output at the first output timing, and an image data voltage with the same green image data voltage is output at the second output timing.

13. The display device according to claim 12, wherein, The control circuit is configured to control the selection circuit such that when the image data voltage is output to the blue sub-pixel, a blue image data voltage is output at the first output timing, and an image data voltage with the same blue image data voltage is output at the second output timing.

14. The display device according to claim 13, wherein, The data driver also includes: A memory that stores pixel data corresponding to the green image data voltage and the blue image data voltage output at the first output timing.

15. The display device according to claim 11, wherein, The red sub-pixel, the green sub-pixel, and the blue sub-pixel are all connected to a gate line and are respectively connected to different data lines.

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