Display device

Abstract

A display device according to an embodiment is disclosed. The display device includes: a display panel including a first area in which a plurality of pixels are arranged and a second area; a plurality of gate drivers disposed in the first region and the second region; a first clock line connected to a gate driver disposed in the first region; a second clock line connected to a gate driver disposed in the second region; and a level shifter configured to generate a first clock signal and a second clock signal to be applied to one of the first clock line and the second clock line, respectively, where the first clock signal and the second clock signal have different voltage levels or gate on times.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0125868, filed on September 13, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] Based on the material of the light-emitting layer, electroluminescent display devices are divided into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), which have the advantages of fast response speed and excellent or wide luminous efficiency, brightness and viewing angle.

[0005] In organic light-emitting display devices, organic light-emitting diodes (called "OLEDs") are formed in each of a plurality of pixels. These organic light-emitting display devices not only have fast response and excellent luminous efficiency, brightness and viewing angle, but also excellent contrast and color reproduction rate because they can represent black tones as full black.

[0006] Some display devices (such as liquid crystal display devices or organic light-emitting display devices) include a display panel having multiple pixels (or subpixels), a driver that outputs drive signals for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver. Summary of the Invention

[0007] To achieve a narrow bezel in the display panel, the gate driver that outputs the gate signal is positioned between multiple pixels in the display area of ​​the display panel. However, depending on the shape of the display panel, a delay may occur in the clock signal applied to the gate driver, which results in a delay in the gate signal output to the gate driver, and consequently, brightness variations depending on the area of ​​the display panel.

[0008] This disclosure aims to address all the aforementioned defects and problems.

[0009] This disclosure provides a display device that improves brightness deviation between its regions.

[0010] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0011] A display device according to an embodiment of the present disclosure may include: a display panel including a first region and a second region in which a plurality of pixels are arranged; a plurality of gate drivers disposed in the first region and the second region; a first clock line connected to the gate drivers disposed in the first region; a second clock line connected to the gate drivers disposed in the second region; and a level shifter (or converter) configured to generate a first clock signal and a second clock signal to be applied to one of the first clock line and the second clock line respectively, wherein the first clock signal and the second clock signal have different voltage levels (or voltage levels) or gate on-times.

[0012] A display device according to an embodiment of the present disclosure may include: a display panel including a first region and a second region in which a plurality of pixels are arranged; a plurality of gate drivers disposed in the first region and the second region; and a timing controller configured to generate a first clock signal and a second clock signal to be applied to the gate drivers disposed in the first region and the second region, respectively, wherein the first clock signal and the second clock signal have different gate on-times.

[0013] A display device according to an embodiment of the present disclosure may include: a display panel including a first region and a second region in which a plurality of pixels are arranged; a plurality of gate drivers disposed in the first region and the second region; and a level shifter configured to generate a first clock signal and a second clock signal to be applied to the gate drivers disposed in the first region and the second region, respectively, wherein the first clock signal and the second clock signal have different voltage levels.

[0014] According to this disclosure, by dividing the display area of ​​the display panel based on the shape of the display panel, separating the clock lines that apply clock signals to the gate drivers disposed in the divided areas, and applying clock signals with different voltage levels or gate conduction times through the separated clock lines, brightness deviations between the divided areas can be eliminated.

[0015] According to this disclosure, power consumption can be reduced based on the area of ​​the display device (specifically, the display panel), thereby achieving low-power operation.

[0016] The effects of this disclosure are not limited to those described above, and other effects not mentioned will be readily apparent to those skilled in the art from the following description and the appended claims. Attached Figure Description

[0017] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0018] Figures 1A to 1BThis is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0019] Figure 2 It is a graphic illustrating the shape of a display panel according to an embodiment of the present disclosure;

[0020] Figure 3 It is a diagram. Figure 2 A diagram showing the configuration of the gate driver;

[0021] Figures 4A to 4C It is a diagram used to explain the principle of applying a clock signal based on a comparison example;

[0022] Figures 5A to 5C This is a diagram used to explain the principle of applying a clock signal according to the first embodiment of this disclosure;

[0023] Figures 6A to 6D This is a diagram used to explain the principle of applying a clock signal according to a second embodiment of the present disclosure;

[0024] Figures 7A to 7B This is a diagram used as an example to explain the principle of applying a clock signal to a boundary region; and

[0025] Figures 8A to 8B This is a diagram used as another example to explain the principle of applying a clock signal to a boundary region. Detailed Implementation

[0026] The advantages and features of this disclosure, as well as methods of implementing them, will become apparent from the preferred embodiments described in detail with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below and can be implemented in various forms. The embodiments are provided only to fully disclose this disclosure and to fully convey its scope to those skilled in the art, and this disclosure is defined by the appended claims.

[0027] Since the shapes, dimensions, scales, angles, quantities, etc., disclosed in the drawings used to describe embodiments of this disclosure are merely exemplary, this disclosure is not limited to the items shown. Throughout the disclosure, the same reference numerals indicate the same parts. Furthermore, in describing this disclosure, detailed descriptions of related known technologies will be omitted where it is determined that such detailed descriptions may unnecessarily obscure the gist of this disclosure.

[0028] When using terms such as "comprising," "having," or "consisting of" as used in this disclosure, other parts may be added unless "only" is used. Unless otherwise expressly stated, the singular form of a component includes the plural form.

[0029] When explaining components, it should be understood that the tolerance range is included, even if there is no separate explicit description.

[0030] When describing positional relationships, for example, when the positional relationship between two parts is described as "on," "at the upper part of," "at the lower part of," "near," etc., one or more other parts may be located between the two parts, unless "immediately" or "directly" is used.

[0031] Although terms like "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical spirit of this disclosure, the "first component" mentioned below can also be the "second component."

[0032] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0033] The following embodiments may be combined or integrated with each other in whole or in part, and may be linked and operated in various technical ways. The embodiments may be performed independently or in relation to each other.

[0034] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0035] Figures 1A to 1B This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0036] refer to Figures 1A to 1B The display device according to embodiments of the present disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels of the display panel 100. Additionally, the display device includes a power supply 150.

[0037] Display panel 100 may be, but is not limited to, a panel with a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, display panel 100 may be a heterogeneous (or non-uniform) panel in which at least a portion is curved or elliptical.

[0038] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and multiple pixels 101 arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels 101. These power lines may be commonly connected to pixel circuitry to supply the voltage required to drive the pixels 101.

[0039] Each of the pixels 101 can be divided into (in other words, include) red subpixels, green subpixels, and blue subpixels for color implementation. Each pixel may also include a white subpixel. Each subpixel includes pixel circuitry for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic light-emitting diode (LED). Each pixel circuitry is connected to data lines, gate lines, and power lines. In the following description, a pixel may be interpreted as a subpixel.

[0040] The display area AA comprises multiple pixel rows (or pixel rows) L1 to Ln. Each of the pixel rows L1 to Ln comprises a row (or row) of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. Pixels arranged in a pixel row share the same gate line 103. Pixels (or sub-pixels) arranged along the data line direction in the column direction (Y-axis direction) share the same data line 102. A horizontal period is the time obtained by dividing a frame period by the total number of pixel rows L1 to Ln.

[0041] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device in which an image is displayed on the screen and real objects in the background are visible. The display panel 100 can be made of a flexible display panel (in other words, formed as a flexible display panel).

[0042] Power supply 150 receives an input voltage applied from host system 300 and outputs the voltages required to drive pixels 101 of display panel 100 and display panel driving circuitry. For this purpose, power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 150 can output constant voltages (or DC voltages) such as gate on (or off) voltages, gate off (or off) voltages, pixel drive voltages, cathode voltages, reference voltages, and IC drive voltages for display panel driving circuitry via the DC-DC converter. Gate on and gate off voltages can be supplied to level shifter 140 and gate driver 120. Voltages such as pixel drive voltages, cathode voltages, and reference voltages can be supplied to pixel 101 via power lines commonly connected to pixel 101.

[0043] The power supply 150 may also include a gamma voltage generator. The gamma voltage generator receives a high-potential reference voltage and a low-potential reference voltage, and outputs multiple gamma reference voltages divided at specific intervals on a preset gamma curve (e.g., a 2.2 gamma curve). The gamma reference voltages are supplied to a data driver 110. In the data driver 110, the gamma reference voltages are subdivided into grayscale voltages by a voltage divider circuit. The gamma voltage generator can be implemented as a programmable gamma circuit, which can adjust the voltage of each of the gamma reference voltages according to digital data. A timing controller 130, a host system 300, or a separate external device can update the digital data stored in the registers of the programmable gamma circuit via a communication interface.

[0044] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image into the pixels 101 of the display panel 100. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0045] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. The touch sensor driver is not included. Figure 1A and Figure 1B As shown in the diagram, the data driver 110 and the touch sensor driver can be integrated into a single source driver IC.

[0046] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 can receive a gamma reference voltage and generate a gamma compensation voltage for each grayscale through a voltage divider circuit. The grayscale gamma compensation voltage for each grayscale is supplied to a digital-to-analog converter (hereinafter referred to as "DAC") disposed in each channel of the data driver 110.

[0047] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting a first mode and a second mode. The DAC converts the pixel data into a gamma-compensated voltage and outputs a data voltage for the pixel data.

[0048] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wiring in the display area AA. The gate driver 120 may be disposed in at least one of the left display area and the right non-display area outside the display area AA in the display panel 100, or at least a portion thereof may be disposed within the display area AA.

[0049] Under the control of timing controller 130, gate driver 120 sequentially outputs pulses of the gate signal to gate line 103. Gate driver 120 can sequentially supply gate signals to gate line 103 by shifting the pulses of the gate signal using a shift register. When multiple gate signals are applied to each pixel, gate driver 120 may include multiple shift registers. Gate signals may include scan signals and transmit signals (or EM signals) input to the pixel circuitry through multiple gate lines.

[0050] The gate driver 120 can be positioned in the non-display area as a gate in panel (GIP) or between sub-pixels SP in the display area AA as a gate in active area (GIA). For example, Figure 1B As shown, the circuitry of the gate driver 120 can be located between pixels 101 within the display area AA.

[0051] The timing controller 130 receives digital video data of the input image and timing signals synchronized with the data from the host system 300. The timing signals may include a vertical (or vertical) synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of one horizontal period (1H).

[0052] The timing controller 130 can control the display panel driving circuit based on timing signals received from the host system 300 (e.g., vertical synchronization signal Vsync, horizontal synchronization signal Hsync, and data enable signal DE), by generating a data timing control signal for controlling the operating timing of the data driver 110 and a gate timing control signal for controlling the operating timing of the gate driver 120. The timing controller 130 can synchronize the data driver 110 and the gate driver 120 by controlling the operating timing of the display panel driving circuit.

[0053] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 140. The level shifter 140 can convert the voltage of the gate timing control signal received from the timing controller 130 into the swing width between the gate turn-on voltage and the gate turn-off voltage, and supply it to the gate driver 120.

[0054] The timing controller 130 can analyze the input image for each frame and generate control signals for selectively outputting gate signals based on the analysis results. The generated control signals can be provided to the shift register of the gate driver 120 via the level shifter 140.

[0055] The host system 300 may include a motherboard of one of a television system, set-top box, navigation system, personal computer (PC), vehicle system, mobile terminal, or wearable terminal. The host system 300 can scale the image signal from the video source according to the resolution of the display panel 100 and can send it along with timing signals to the timing controller 130.

[0056] Figure 2 It is a graphic illustrating the shape of a display panel according to an embodiment of the present disclosure, and Figure 3 It is a diagram. Figure 2 A diagram showing the configuration of the gate driver.

[0057] refer to Figure 2 According to embodiments of the present disclosure, the display panel may have an irregular shape, such as a shape with a length (or width) that varies depending on its position, rather than a rectangular shape. The display panel may include a first region A1 and a second region A2, depending on its shape, in which an image is displayed. The first region is in the Y-axis direction (e.g., ...). Figure 1A The region shown can be longer than the second region.

[0058] The gate driver 120 can be formed between pixels along the column direction, but is not limited to this. For example, the gate driver 120 can be formed between pixels along the row direction.

[0059] Gate driver 120 may include a scan driver that outputs a scan signal. The scan driver may output the scan signal based on a clock signal and a low-potential voltage.

[0060] refer to Figure 3 According to embodiments of the present disclosure, the gate driver may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor or pull-up transistor T7, an eighth transistor or pull-down transistor T8, a first capacitor C1, and a second capacitor C2.

[0061] The first transistor T1 is turned on by the previous clock signal CLK(n-1) and is connected to the first node 81 and the second node 82. The first transistor T1 includes a gate electrode to which the previous clock signal CLK(n-1) is applied, a first electrode connected to the first node 81, and a second electrode connected to the second node 82.

[0062] The second transistor T2 is turned on by a voltage from the second control node Qb(n) and connected to the second node 82 by a first power line PL1 to which a high potential voltage VGH is applied. The second transistor T2 includes a gate electrode connected to the second control node Qb(n), a first electrode connected to the second node 82, and a second electrode connected to the first power line PL1.

[0063] The third transistor T3 is turned on by the subsequent clock signal CLK(n+2) and connects the second power line PL2, which is subject to a low potential voltage VGL, to the second control node Qb(n). The third transistor T3 includes a gate electrode to which the subsequent clock signal CLK(n+2) is applied, a first electrode connected to the second power line PL2, and a second electrode connected to the second control node Qb(n).

[0064] The fourth transistor T4 is turned on by the voltage from the first node 81 and connects the second control node Qb(n) to the first power line PL1. The fourth transistor T4 includes a gate electrode connected to the first node 81, a first electrode connected to the second control node Qb(n), and a second electrode connected to the first power line PL1.

[0065] The fifth transistor T5 is turned on by a low potential voltage VGL and connects the second node 82 to the first control node Q(n). The fifth transistor T5 includes a gate electrode connected to the second power line PL2, a first electrode connected to the second node 82, and a second electrode connected to the first control node Q(n).

[0066] The sixth transistor T6 is turned on by the voltage from the second node 82 and connects the second control node Qb(n) to the first power line PL1. The sixth transistor T6 includes a gate electrode connected to the second node 82, a first electrode connected to the second control node Qb(n), and a second electrode connected to the first power line PL1.

[0067] The seventh transistor T7 is turned on by the voltage from the first control node Q(n) and outputs a low-potential voltage VGL to the output node OUT. The seventh transistor T7 includes a gate electrode connected to the first control node Q(n), a first electrode connected to the clock line CL to which the clock signal CLK(n) is applied, and a second electrode connected to the output node OUT.

[0068] The eighth transistor T8 is turned on by the voltage from the second control node Qb(n) and outputs a high-potential voltage VGH to the output node OUT. The eighth transistor T8 includes a gate electrode connected to the second control node Qb(n), a first electrode connected to the output node OUT, and a second electrode connected to the first power line PL1.

[0069] The first capacitor C1 is connected between the gate electrode and the second electrode of the seventh transistor T7. The second capacitor C2 is connected between the gate electrode and the second electrode of the eighth transistor T8.

[0070] Because the gate driver outputs the gate signal based on a clock signal and a low potential voltage, any delay in the clock signal can cause a delay in the gate signal.

[0071] Figures 4A to 4C It is a diagram used to explain the principle of applying a clock signal based on a comparison example.

[0072] refer to Figures 4A to 4C In the comparative example, a clock signal GCLK can be generated using a timing controller 130 and a level shifter 140. In other words, the timing controller 130 can generate a clock signal GCLK0 with a first voltage level VCC and apply the clock signal to the level shifter 140.

[0073] The level shifter 140 can generate a clock signal GCLK with a second voltage level (i.e., gate on voltage VGH1 and gate off voltage VGL1) from a clock signal GCLK0 with a first voltage level, and then apply the clock signal GCLK to all gate drivers of the first region A1 and the second region A2 in the display panel.

[0074] The clock signal GCLK is applied equally to all gate drivers in the first region A1 and the second region A2. Because the length of the wiring through which the clock signal is applied varies depending on the region, the RC delay varies. For example, the RC delay in the first region A1 is greater than the RC delay in the second region A2. Therefore, the delay of the clock signal GCLK occurs depending on the region, which leads to a delay in the gate signal GOUT, resulting in a variation in the gate on-time and causing brightness deviation. Specifically, because the gate on-time of the gate signal GOUT in the first region A1 is shorter than that in the second region A2, the brightness in the first region is relatively lower.

[0075] Therefore, embodiments of this disclosure propose measures to improve clock signal delay deviations.

[0076] In the first embodiment, the clock lines to which the clock signals are applied are separated (or differentiated) according to the region, and clock signals with different voltage levels are applied through the separate clock lines respectively.

[0077] Figures 5A to 5C This is a diagram used to explain the principle of applying a clock signal according to the first embodiment.

[0078] refer to Figures 5A to 5CIn the first embodiment, a timing controller 130 and a level shifter 140 can be used to generate a first clock signal GCLK1 and a second clock signal GCLK2 with different voltage levels depending on the region. Specifically, the timing controller 130 can generate a clock signal GCLK0 with a first voltage level VCC and apply the clock signal to the first level shifter 140a and the second level shifter 140b.

[0079] The first level shifter 140a can generate a first clock signal GCLK1 with a second voltage level (i.e., a second gate on voltage VGH2 and a second gate off voltage VGL2) from a clock signal GCLK0 with a first voltage level, and apply the generated first clock signal GCLK1 to all gate drivers in the first area A1 of the display panel through the first clock line CL1.

[0080] The second level shifter 140b can generate a second clock signal GCLK2 with a second voltage level (i.e., a first gate on voltage VGH1 and a first gate off voltage VGL1) from a clock signal GCLK0 with a first voltage level, and apply the generated second clock signal GCLK2 to all gate drivers in the second area A2 of the display panel through the second clock line CL2.

[0081] Here, the gate on-voltage is set such that the second gate on-voltage VGH2 > the first gate on-voltage VGH1, and the gate off-voltage is set such that the second gate off-voltage VGL2 < the first gate off-voltage VGL1.

[0082] By applying a first clock signal GCLK1 with a second gate on voltage VGH2 and a second gate off voltage VGL2 to the first region A1 and applying a second clock signal GCLK2 with a first gate on voltage VGH1 and a first gate off voltage VGL1 to the second region A2, the gate on-time deviation of the gate signal output from the gate driver in each region (i.e., the first region A1 and the second region A2) can be eliminated.

[0083] In the first embodiment, the gate on-state voltage of the clock signal applied to a region with a relatively high RC delay is increased, and its gate off-state voltage is decreased, but the embodiment is not limited to this. For example, the gate on-state voltage of the clock signal applied to a region with a relatively low RC delay can be decreased, and its gate off-state voltage can be increased.

[0084] The data showing the results of improving the brightness deviation between areas are presented in Table 1 below.

[0085] [Table 1]

[0086]

[0087] As shown in Table 1 above, it can be seen that in the comparison example where the same clock signal is applied to all regions, there are brightness variations between regions, while in this embodiment, the brightness variations between regions are eliminated.

[0088] In the second embodiment, the clock lines to which the clock signal is applied are separated (or differentiated) according to the region, and clock signals with different gate on-times are applied through the separate clock lines respectively.

[0089] Figures 6A to 6D This is a diagram used to explain the principle of applying a clock signal according to the second embodiment.

[0090] refer to Figures 6A to 6C In the second embodiment, a timing controller 130 and a level shifter 140 can be used to generate a first clock signal GCLK1 and a second clock signal GCLK2 with different gate on-times depending on the region. Specifically, the timing controller 130 can generate a first initial clock signal GCLK1′ and a second initial clock signal GCLK2′ with different gate on-times having a first voltage level VCC, and apply them to the level shifter 140.

[0091] Here, the second initial clock signal GCLK2' can be generated with a shorter gate on-time than the first initial clock signal GCLK1'.

[0092] The level shifter 140 generates a first clock signal GCLK1 and a second clock signal GCLK2 with a second voltage level (i.e., gate on voltage VGH1 and gate off voltage VGL1) from a first initial clock signal GCLK1′ and a second initial clock signal GCLK2′ with different gate on times having a first voltage level VCC. The generated first clock signal GCLK1 can be applied to all gate drivers in the first area A1 of the display panel through the first clock line CL1, and the generated second clock signal GCLK2 can be applied to all gate drivers in the second area A2 of the display panel through the second clock line CL2.

[0093] Here, the timing controller generates clock signals with different gate on-times, but is not limited to this. For example, clock signals with different gate on-times can be generated by a level shifter.

[0094] refer to Figure 6D The timing controller 130 can generate a clock signal GCLK0 with a first voltage level VCC and apply the clock signal to the level shifter 140.

[0095] The level shifter 140 can generate a first clock signal GCLK1 and a second clock signal GCLK2 with different gate on-times having a second voltage level (i.e., gate on-voltage VGH1 and gate off-voltage VGL1) from a clock signal GCLK0 having a first voltage level VCC. The generated first clock signal GCLK1 can be applied to all gate drivers in the first area A1 of the display panel through the first clock line CL1, and the generated second clock signal GCLK2 can be applied to all gate drivers in the second area A2 of the display panel through the second clock line CL2.

[0096] By applying a first clock signal GCLK1 with a first gate on-time to the first region A1 and a second clock signal GCLK2 with a second gate on-time to the second region A2, the gate on-time deviation of the gate signal output from the gate driver of each region (i.e., the first region A1 and the second region A2) can be eliminated.

[0097] In the second embodiment, the gate on-time of the clock signal applied to a region with a relatively high RC delay is increased, but the embodiment is not limited to this. For example, the gate on-time of the clock signal applied to a region with a relatively low RC delay can be reduced.

[0098] Furthermore, in embodiments of this disclosure, it is intended to slightly adjust the voltage level or gate on-time of the clock signal in the boundary region where the first region A1 and the second region A2 are adjacent to each other.

[0099] As an example, Figures 7A to 7B It is a diagram used to explain the principle of applying a clock signal to the boundary region.

[0100] refer to Figures 7A to 7B In embodiments of this disclosure, the boundary regions adjacent to each other, such as the first region A1 and the second region A2, can be divided into multiple boundary regions, and clock signals with different voltage levels can be applied to gate drivers disposed in each of the multiple boundary regions.

[0101] For example, the boundary region can be divided into first to sixth boundary regions 1, 2, 3, 4, 5 and 6, and a clock signal with six pairs of voltage levels can be applied to the separate first to sixth boundary regions 1, 2, 3, 4, 5 and 6 respectively through six pairs of clock lines.

[0102] A second clock signal GCLK2 with a voltage level applied to the second region A2 is applied to the first boundary region 1, and a first clock signal GCLK1 with a voltage level applied to the first region A1 is applied to the sixth boundary region 6.

[0103] A clock signal having a voltage level between the voltage level of the second clock signal GCLK2 and the voltage level of the first clock signal GCLK1 is applied to the second to fifth boundary regions 2, 3, 4, and 5. For example, a clock signal having a voltage level between the gate on-state voltage VGH or gate off-state voltage VGL of the second clock signal GCLK2 and the gate on-state voltage VGH or gate off-state voltage VGL of the first clock signal GCLK1 can be applied.

[0104] For example, such as Figure 7B As shown, a clock signal with a gate turn-off voltage VGL of -15.0V is applied to the first boundary region 1. A clock signal with a gate turn-off voltage VGL of -15.1V is applied to the second boundary region 2. A clock signal with a gate turn-off voltage VGL of -15.2V is applied to the third boundary region 3. A clock signal with a gate turn-off voltage VGL of -15.3V is applied to the fourth boundary region 4. A clock signal with a gate turn-off voltage VGL of -15.4V is applied to the fifth boundary region 5. A clock signal with a gate turn-off voltage VGL of -15.5V is applied to the sixth boundary region 6.

[0105] In this embodiment, the voltage levels of the clock signals applied to the first to sixth boundary regions 1, 2, 3, 4, 5 and 6 can be generated to increase or decrease by a constant amplitude.

[0106] In other words, the timing controller 130 generates a clock signal with a first voltage level and applies it to the level shifter 140.

[0107] The level shifter 140 may include six level shifters LS, and each of the six level shifters LS may generate a clock signal having a voltage level based on a pair of different gate on-state voltages VGH and gate off-state voltages VGL from a clock signal having a first voltage level.

[0108] Power supply 150 can supply pairs of different gate on-state voltages VGH and gate off-state voltages VGL to the six level shifters LS included in level shifter 140.

[0109] As another example, Figures 8A to 8B It is a diagram used to explain the principle of applying a clock signal to the boundary region.

[0110] refer to Figure 8A and Figure 8BIn embodiments of this disclosure, the boundary regions of the first region A1 and the second region A2, which are adjacent to each other, can be divided into multiple boundary regions, and clock signals with different gate on-times can be applied to gate drivers disposed in each of the multiple boundary regions. Here, some gate drivers disposed in each boundary region can be configured to apply gate signals to pixels in the first region A1, while some other gate drivers can be configured to apply gate signals to pixels in the second region A2, but the configuration is not necessarily limited to this.

[0111] For example, the boundary region can be divided into first to sixth boundary regions 1, 2, 3, 4, 5 and 6, and a clock signal with six pairs of gate on-times can be applied to the separate first to sixth boundary regions 1, 2, 3, 4, 5 and 6 respectively through six pairs of clock lines.

[0112] A second clock signal GCLK2 having a gate on-time applied to the second region A2 is applied to the first boundary region 1, and a first clock signal GCLK1 having a gate on-time applied to the first region A1 is applied to the sixth boundary region 6.

[0113] A clock signal having a gate on-time between the gate on-time of the second clock signal GCLK2 and the gate on-time of the first clock signal GCLK1 is applied to the second to fifth boundary regions 2, 3, 4 and 5.

[0114] For example, such as Figure 8B As shown, a clock signal with a gate on-time of 5.0 μs is applied to the first boundary region 1. A clock signal with a gate on-time of 5.1 μs is applied to the second boundary region 2. A clock signal with a gate on-time of 5.2 μs is applied to the third boundary region 3. A clock signal with a gate on-time of 5.3 μs is applied to the fourth boundary region 4. A clock signal with a gate on-time of 5.4 μs is applied to the fifth boundary region 5. A clock signal with a gate on-time of 5.5 μs is applied to the sixth boundary region 6.

[0115] In this embodiment, the gate conduction time of the clock signals applied to the first to sixth boundary regions 1, 2, 3, 4, 5 and 6 can be generated to increase or decrease by a constant magnitude.

[0116] In one example, timing controller 130 generates clock signals with different gate on-times having a first voltage level and applies them to level shifter 140. Level shifter 140 can generate clock signals with a second voltage level (i.e., gate on-voltage VGH and gate off-voltage VGL) from the clock signals with different gate on-times provided by timing controller 130.

[0117] In another example, timing controller 130 generates a clock signal with a first voltage level and applies it to level shifter 140. Level shifter 140 can generate a clock signal with a second voltage level (i.e., different gate on-times of gate on-voltage VGH and gate off-voltage VGL) from the clock signal with the first voltage level provided by timing controller 130.

[0118] In this case, the power supply 150 can supply the predetermined gate turn-on voltage VGH and gate turn-off voltage VGL to the level shifter 140 under the control of the timing controller 130.

[0119] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A display device comprising: The display panel includes a first region and a second region in which a plurality of pixels are arranged; Multiple gate drivers are disposed in the first region and the second region; A first clock line connected to a gate driver located in the first region; A second clock line connected to the gate driver located in the second region; as well as A level shifter configured to generate a first clock signal and a second clock signal, respectively applied to one of the first clock line and the second clock line. The first clock signal and the second clock signal have different voltage levels or gate conduction times.

2. The display device according to claim 1, wherein, The first region and the second region are divided according to the shape of the display panel, and Compared to the first region, the second region has a shorter length on which a clock signal is applied.

3. The display device according to claim 1, wherein, The level shifter includes a first level shifter and a second level shifter, and The first level shifter generates a first clock signal having a first gate on voltage and a first gate off voltage, and The second level shifter generates a second clock signal having a second gate on voltage and a second gate off voltage.

4. The display device according to claim 3, wherein, The first gate on-state voltage is higher than the second gate on-state voltage, and The first gate turn-off voltage is lower than the second gate turn-off voltage.

5. The display device according to claim 1, further comprising: A timing controller configured to generate a first clock signal having a first gate on-time and a second clock signal having a second gate on-time. The level shifter is configured as follows: A first clock signal having the first gate on-time is applied to the first clock line, and A second clock signal having the second gate on-time is applied to the second clock line.

6. The display device according to claim 5, wherein, The second gate on-time is set to be shorter than the first gate on-time.

7. The display device according to claim 1, further comprising: A timing controller configured to generate a clock signal with a predetermined voltage level. The level shifter is configured as follows: Generate a first clock signal with a first gate on-time and a second clock signal with a second gate on-time. A first clock signal having the first gate on-time is applied to the first clock line, and A second clock signal having the second gate on-time is applied to the second clock line.

8. The display device according to claim 1, wherein, The display panel includes a plurality of boundary regions adjacent to the boundary between the first region and the second region, and The multiple clock signals applied to the multiple boundary regions are set to have different voltage levels or gate conduction times by a predetermined amplitude.

9. A display device comprising: The display panel includes a first region and a second region in which a plurality of pixels are arranged; Multiple gate drivers are disposed in the first region and the second region; as well as A timing controller configured to generate a first clock signal and a second clock signal to be applied to gate drivers disposed in the first region and the second region, respectively. The first clock signal and the second clock signal have different gate on-times.

10. The display device according to claim 9, wherein, The second clock signal has a shorter gate conduction time than the first clock signal.

11. The display device according to claim 9, wherein, The display panel includes a plurality of boundary regions adjacent to the boundary between the first region and the second region, and The multiple clock signals applied to the multiple boundary regions are set differently between the gate on-time of the first clock signal and the gate on-time of the second clock signal.

12. A display device comprising: The display panel includes a first region and a second region in which a plurality of pixels are arranged; Multiple gate drivers are disposed in the first region and the second region; as well as A level shifter configured to generate a first clock signal and a second clock signal to be applied, respectively, to gate drivers disposed in the first region and the second region. The first clock signal and the second clock signal have different voltage levels.

13. The display device according to claim 12, wherein, The second clock signal has a voltage level that is lower than that of the first clock signal.

14. The display device according to claim 13, further comprising: A power supply configured to supply a gate on-state voltage and a gate off-state voltage to the level shifter. Wherein, the first clock signal has a gate on voltage that is higher than the gate on voltage of the second clock signal, and the first clock signal has a gate off voltage that is lower than the gate off voltage of the second clock signal.

15. The display device according to claim 12, wherein, The display panel includes a plurality of boundary regions adjacent to the boundary between the first region and the second region, and The multiple clock signals applied to the multiple boundary regions are set differently between the voltage levels of the first clock signal and the second clock signal.

Images