Pixel circuit, display module and electronic equipment

Abstract

The invention discloses a pixel circuit, a display module and electronic equipment, and relates to the technical field of electronics. The pixel circuit provided by the invention comprises a light-emitting element, a driving transistor, a first capacitor, a first switching tube, a scanning control module and a light-emitting control module, wherein the light-emitting element is connected with the driving transistor through the light-emitting control module; the scanning control module is connected with the driving transistor; the first capacitor is arranged on a display data signal transmission path between the display data input end and the grid electrode of the driving transistor, and the first end of the first capacitor is connected with the grid electrode of the driving transistor; the second end of the first capacitor is coupled with the display data input end; the first end of the first switch tube is connected with the second end of the first capacitor, and the second end of the first switch tube is connected with a reference voltage end; the first capacitor is used for coupling a display data voltage signal input by the display data input end to the grid electrode of the driving transistor under the condition that the first switching tube is in a conducting state.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a pixel circuit, a display module, and an electronic device. Background Technology

[0002] Currently, light-emitting diodes (LEDs) such as OLEDs (organic light-emitting diodes) are widely used in display modules of smart terminals due to their advantages such as high contrast and wide color gamut. Display modules use pixel circuits to drive each row of LED pixels to emit light and achieve image display.

[0003] In related technologies, when each row of pixels is refreshed, the LEDs need to be turned off to refresh the pixel circuit, and then the LEDs need to be turned on again. During the pixel circuit refresh process, such as when display data is written to the storage capacitor, the display data needs to pass through multiple devices such as the driving transistor and the threshold compensation transistor before it can be written to the storage capacitor connected to the gate of the driving transistor. This results in a slow data writing speed for the pixel circuit, thus affecting the display effect. Summary of the Invention

[0004] This application provides a pixel circuit, a display module, and an electronic device, which solves the problem of slow data writing speed of pixel circuits affecting display effect in related technologies.

[0005] In a first aspect, embodiments of this application propose a pixel circuit, including: a light-emitting element, a driving transistor, a first capacitor, a first switching transistor, a scanning control module, and a light-emitting control module. The light-emitting element is connected to the driving transistor through the light-emitting control module, and the scanning control module is connected to the driving transistor. The first capacitor is disposed in the display data signal transmission path between the display data input terminal and the gate of the driving transistor. The first end of the first capacitor is connected to the gate of the driving transistor; the second end of the first capacitor is coupled to the display data input terminal. The first terminal of the first switching transistor is connected to the second terminal of the first capacitor, the second terminal of the first switching transistor is connected to the reference voltage terminal, and the third terminal of the first switching transistor is connected to the first light-emitting control signal terminal. The first capacitor is used to couple the display data voltage signal input from the display data input terminal to the gate of the driving transistor when the first switch is in the on state.

[0006] Secondly, embodiments of this application propose a display module, including: the pixel circuit as described in the first aspect.

[0007] Thirdly, embodiments of this application provide an electronic device, including: a display module as described in the second aspect.

[0008] In this embodiment, the pixel circuit includes a light-emitting element, a driving transistor, a first capacitor, a first switching transistor, a scanning control module, and a light-emitting control module. The light-emitting element is connected to the driving transistor through the light-emitting control module, and the scanning control module is connected to the driving transistor. The first capacitor is disposed in the display data signal transmission path between the display data input terminal and the gate of the driving transistor. The first end of the first capacitor is connected to the gate of the driving transistor, and the second end of the first capacitor is coupled to the display data input terminal. The first end of the first switching transistor is connected to the second end of the first capacitor, the second end of the first switching transistor is connected to a reference voltage terminal, and the third end of the first switching transistor is connected to a first light-emitting control signal terminal. The first capacitor is used to couple the display data voltage signal input from the display data input terminal to the gate of the driving transistor when the first switching transistor is in the on state. Thus, since the first end of the first capacitor is connected to the gate of the driving transistor and the second end of the first capacitor is coupled to the display data input terminal, the embodiments of this application can utilize the first capacitor to quickly couple the display data voltage signal input from the display data input terminal to the gate of the driving transistor. Compared with related technologies, the display data voltage signal input from the display data input terminal does not need to pass through the driving transistor and the threshold compensation transistor sequentially before being written to the gate of the driving transistor. Instead, it is directly coupled to the gate of the driving transistor through the coupling effect of the first capacitor, which improves the writing speed of the voltage input from the display data input terminal, thereby improving the display effect of the pixel circuit. Attached Figure Description

[0009] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of a pixel circuit provided in related technologies; Figure 2 These are schematic diagrams of pixel circuits provided in some embodiments of this application; Figure 3 These are schematic diagrams of pixel circuits provided in some embodiments of this application; Figure 4A These are schematic diagrams of pixel circuits provided in some embodiments of this application; Figure 4B yes Figure 4A A schematic diagram of the control timing of the provided pixel circuit; Figure 5A These are schematic diagrams of pixel circuits provided in some embodiments of this application; Figure 5B yes Figure 5A A schematic diagram of the control timing of the provided pixel circuit; Figure 6 These are schematic diagrams of display modules provided in some embodiments of this application; Figure 7 These are schematic diagrams of display modules provided in some embodiments of this application; Figure 8 These are schematic diagrams of electronic devices provided in some embodiments of this application.

[0010] Explanation of reference numerals in the attached figures: 100 - Pixel circuit; 110 - Scan control module; 120 - Light emission control module; LED - Light emission element; T1 - Driving transistor; T2 - Second switch; T3 - Third switch; T4 - Fourth switch; T5 - Fifth switch; T6 - First switch; T7 - ​​Sixth switch; C1 - First capacitor; C2 - Second capacitor; A - Gate node of driving transistor M1; N1 - First node; N2 - Second node; N3 - Third node; N4 - Fourth node; VDD - First voltage terminal; V SS - Second voltage terminal; Vref - Reference voltage terminal; S1 - First scan signal terminal; S2 - Second scan signal terminal; S3 - Third scan signal terminal; S4 - Fourth scan signal terminal; Data - Display data input terminal; EM - Light emission control signal terminal; EM1 - Second light emission control signal terminal; EM2 - First light emission control signal terminal; 200 - Display module; 210 - Display driver chip; 220 - Power management chip; 230 - Scan driver circuit; 240 - Light emission driver circuit; 300 - Electronic equipment. Detailed Implementation

[0011] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0012] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0013] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection, an indirect connection through an intermediate medium, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0014] Currently, in display modules of terminal devices such as mobile phones and tablets, the relevant technologies generally adopt such as Figure 1 The 7T1C circuit shown serves as the driving circuit for a single LED pixel. For example... Figure 1 As shown, the pixel circuit may include a single LED-emitting pixel located in the nth row, and a driving circuit for the LED-emitting pixel. (Reference) Figure 1 The light-emitting diode (LED) is the LED light-emitting pixel. This driving circuit includes 7 thin-film transistors (TFTs) and 1 storage capacitor. Cst is the storage capacitor, M1 is the driving transistor, M2 is the switch for the display data signal Data, M3 is the threshold compensation transistor (used for threshold voltage compensation of M1), M4 is the switch for initializing the Cst storage capacitor, M5 is the switch for the positive voltage VDD, M6 is the switch for the negative voltage VSS, and M7 is the switch for resetting the LED anode voltage. M1, M2, M3, M4, M5, M6, and M7 can be PMOS transistors. Point A is the gate node of M1.

[0015] Among them, reference Figure 1 The horizontal scanning signal S1 is used to control the gates of transistors M2 and M3, the horizontal scanning signal S2 is used to control the gate of transistor M4, the horizontal scanning signal S3 is used to control the gate of transistor M7, Data is the display data signal, Vref1 is the initialization voltage of capacitor Cst, Vref2 is the initialization voltage of the anode of LED, VDD is the positive voltage of LED D, VSS is the negative voltage of LED D, and EM is the light emission control signal used to control the gates of transistors M5 and M6.

[0016] Figure 1 The pixel circuit shown operates within one frame in four time periods: During the first time period, the M4 transistor is turned on by the line scanning signal S2, and the voltage at point A is adjusted to the negative voltage value of Vref1 by the initialization voltage Vref1, that is, the storage capacitor Cst is initialized, so as to avoid the residual storage voltage in the storage capacitor Cst from affecting the display of the next frame of data.

[0017] During the second time period, the row scan signal S1 is used to turn on transistors M2 and M3. Turning on transistor M2 allows the display data for the current row to be written, which means setting the voltage at point A to V. Data Voltage. At this time, the voltage at point A was initially set to a negative voltage Vref1 in the previous time period. Transistor M1 remains on, and the on-state of transistor M3 shorts the gate and source of transistor M1. The potential at point A will continue to be charged to V. Data +V TH After the current is cut off, the storage capacitor Cst is in a charging state, and the voltage stored in the storage capacitor Cst can be denoted as V. Data +V TH V TH This is the threshold voltage of transistor M1.

[0018] During the third time period, the M7 transistor is turned on by the line scanning signal S3, and the anode potential of the pixel will be initialized to the Vref2 voltage. This resets (initializes) the parasitic capacitance Clu of the LED, preventing the residual stored voltage in the parasitic capacitance Clu from affecting the display of the next frame of data.

[0019] During the fourth time period, the light-emitting control signal EM is used to turn on transistors M5 and M6. At this time, the storage voltage of the storage capacitor Cst is V. Data +V TH The storage capacitor Cst enters the discharge state, keeping transistor M1 on. At this time, the current of transistor M1 flows through the pixel (i.e., the light-emitting diode LED), making the pixel light up.

[0020] The applicant noted that in the relevant technology, when each row of pixels is refreshed, the pixel illumination needs to be turned off, the pixel circuit refreshed, and the LED illumination turned on again after the pixel circuit is refreshed. During the pixel circuit refresh process, for example, when display data is written to the storage capacitor (i.e., the gate of the driving transistor), the display data needs to pass through multiple devices such as the driving transistor and the threshold compensation transistor before it can be written to the storage capacitor connected to the gate of the driving transistor. This results in a slow data writing speed for the pixel circuit, thus affecting the display effect.

[0021] Especially in scenarios with high pixel refresh rates, the short refresh time results in insufficient data writing time. Within a limited time, it is difficult to write enough data to the gate of the driving transistor, causing the actual voltage applied to the pixel to be lower than expected. This leads to a series of problems such as uneven brightness, color shift, and inaccurate grayscale, thus affecting the display effect.

[0022] Based on this, the pixel circuit provided in this application embodiment provides a first capacitor that is directly connected to the gate of the driving transistor. By utilizing the coupling effect of the first capacitor, the data voltage is quickly transferred to the gate of the driving transistor. Compared with related technologies, the data voltage does not need to pass through the driving transistor and the threshold compensation transistor in sequence before being written to the gate of the driving transistor. Instead, it is directly written to the gate of the driving transistor through the coupling effect of the first capacitor, which improves the writing speed of the data voltage and thus improves the display effect of the pixel circuit.

[0023] The pixel circuit, display module, and electronic device provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0024] like Figure 2 As shown, this application embodiment provides a pixel circuit 100, which may include: The light-emitting element LED, driving transistor T1, first capacitor C1, first switching transistor T6, scanning control module 110 and light-emitting control module 120 are included. The light-emitting element LED is connected to driving transistor T1 through light-emitting control module 120, and scanning control module 110 is connected to driving transistor T1. The first capacitor C1 is disposed in the display data signal transmission path between the display data input terminal Data and the gate of the driving transistor T1. The first end of the first capacitor C1 is connected to the gate of the driving transistor T1, and the second end of the first capacitor C1 is coupled to the display data input terminal Data. The first terminal of the first switch transistor T6 is connected to the second terminal of the first capacitor C1, the second terminal of the first switch transistor T6 is connected to the reference voltage terminal Vref, and the third terminal of the first switch transistor T6 is connected to the first light-emitting control signal terminal EM2. The first capacitor C1 is used to couple the display data voltage signal input at the display data input terminal Data to the gate of the driving transistor T1 when the first switch transistor T6 is in the on state.

[0025] In the embodiments of this application, the light-emitting element LED can be an organic light-emitting diode (OLED) or other types of light-emitting diodes. The light-emitting element can be a millimeter-scale light-emitting diode or a micrometer-scale light-emitting diode. The light-emitting element can be one light-emitting diode or two light-emitting diodes, etc. This application does not limit the type, size and number of light-emitting elements.

[0026] In this embodiment, the scan control module 110 performs additional functions such as threshold compensation of the driving transistor T1, gate reset of the driving transistor T1, and anode reset of the light-emitting element LED. The scan control module 110 may include switching transistors controlled by various scan signals in the pixel circuit 100. For example, such as Figure 3 As shown, the scan control module 110 may include a third switch T3 controlled by a first scan signal and used for threshold compensation of driving transistor T1; a fourth switch T4 controlled by the third scan signal and used for gate reset of driving transistor T1; and a sixth switch T7 controlled by a fourth scan signal and used for anode reset of the light-emitting element LED.

[0027] In this embodiment, the light-emitting control module 120 functions to achieve light-emitting control independent of data writing, allowing the pixel circuit to continue displaying the current frame's image while writing the next frame's data, or to achieve inter-line overlapping refresh, thereby improving the refresh rate and reducing visual flicker. The light-emitting control module 120 may include at least one switching transistor disposed in the power supply circuit of the light-emitting element LED in the pixel circuit 100. For example, such as... Figure 3 As shown, the light-emitting control module 120 may include a fifth switch T5 connected in series between the driving transistor T1 and the light-emitting element LED. Alternatively, in other embodiments, the light-emitting control module 120 may include a positive voltage switch (not shown) connected in series between the power supply VDD and the driving transistor T1.

[0028] In this embodiment of the application, the first end of the first capacitor C1 can be connected to the gate of the driving transistor T1 through the first node N1, where the first node N1 is the node between the first end of the first capacitor C1 and the gate of the driving transistor T1.

[0029] In this embodiment, the second terminal of the first capacitor C1 is coupled to the display data input terminal Data. Coupling can be understood as an indirect connection. For example, the second terminal of the first capacitor C1 can be connected to the display data input terminal Data via the second switch T2.

[0030] In this embodiment, the first capacitor C1 has a coupling effect. The coupling effect means that when the potential at the first terminal of the capacitor suddenly decreases, because the voltage difference across the capacitor cannot change abruptly, the potential at the second terminal of the capacitor will also decrease. In ideal coupling, the magnitude of the decrease in the potential at the second terminal of the capacitor can be equal to the magnitude of the decrease in the potential at the first terminal. Therefore, this embodiment can utilize the coupling effect of the first capacitor C1 to display the voltage V input at the Data input terminal. DataThe capacitor C1 is quickly coupled to the gate of the driving transistor T1. Thus, the first capacitor C1 can be used to transfer the display data voltage signal input at the display data input terminal (Data) to the gate of the driving transistor T1. The display data voltage signal may include a second voltage V. Data .

[0031] For example, a first capacitor C1 has a first terminal and a second terminal. The first terminal of the first capacitor C1 is connected to a first node N1, and the second terminal of the first capacitor C1 is connected to a second node N2. Through the coupling effect of the first capacitor C1, when the potential at the second node N2 changes, the potential at the first node N1 changes accordingly, and the voltage change at the first node N1 can be equal to the voltage change at the second node N2. Based on this, when the potential at the second terminal of the first capacitor C1 is adjusted from a third potential to a first potential, through the coupling effect of the first capacitor C1, the potential at the first terminal of the first capacitor C1 is adjusted from a second potential to a fourth potential. The voltage change at the first node N1 is the difference between the first potential and the third potential, and the voltage change at the second node N2 is the difference between the fourth potential and the second potential. The voltage change at the first node N1 is equal to the voltage change at the second node N2. Furthermore, the fourth potential can be determined by the difference between the first potential and the third potential, and the second potential. The third potential is the second voltage V input by the display data input terminal Data. Data Under certain conditions, the second voltage V input at the Data input terminal will be displayed through the coupling effect of the first capacitor C1. Data The signal is quickly transferred to the gate of the driving transistor T1.

[0032] For example, if the first potential is V1 and the second potential is V DD +V TH The third potential is V Data Therefore, the voltage change at the second node N2, i.e., the difference ΔV1 between the first and third potentials, can be expressed as V1 - V Data The voltage change at the first node N1, i.e., the difference between the second and fourth potentials, ΔV2, can be equal to ΔV1; the fourth potential can be determined as V. DD +V TH +V1-V Data That is, the gate potential of the driving transistor T1 is V. DD +V TH +V1-V Data This will display the second voltage V input at the Data input terminal. Data The signal is quickly transferred to the gate of the driving transistor T1.

[0033] It should be noted that, for reference Figure 1In the related technology, transistors M2 and M3 are turned on during the second time period. Turning on transistor M2 causes the display data of the current row to be written to the storage capacitor Cst, which in turn charges the storage capacitor Cst, setting the voltage at point A of the gate node of the driving transistor M1 to V. Data During the voltage process, when transistor M3 is turned on, it can perform threshold compensation on the gate node A of driving transistor M1, that is, further set the voltage at the gate node A of driving transistor M1 to V. Data +V TH During charging and threshold compensation, the voltage V input at the Data input terminal is displayed. Data The data needs to pass through the source and drain of the switching transistor M2 (for displaying data signals), the source and drain of the driving transistor M1, and the source and drain of the threshold compensation transistor M3 in sequence before it can be written to the gate node A of the driving transistor M1. This results in a slow data writing speed for the pixel circuit, which in turn affects the display effect.

[0034] In the embodiments of this application, such as Figure 2 As shown, since the first terminal of the first capacitor C1 is connected to the gate of the driving transistor T1, and the second terminal of the first capacitor C1 is coupled to the display data input terminal Data, the voltage input at the display data input terminal Data can be quickly transferred to the gate of the driving transistor T1 using the first capacitor C1, thus increasing the voltage V input at the display data input terminal Data. Data The gate node of the driving transistor T1 can be quickly written through the coupling effect of the first capacitor C1, without having to write through the source and drain of the driving transistor T1 and the source and drain of the threshold compensation transistor T3 in sequence, thus improving the writing speed of the voltage input at the display data input terminal.

[0035] According to the pixel circuit provided in the embodiments of this application, the first capacitor C1 can be used to quickly couple the display data voltage signal input at the display data input terminal Data to the gate of the driving transistor T1. Compared with related technologies, the display data voltage signal input at the display data input terminal Data does not need to pass through the driving transistor and the threshold compensation transistor in sequence before being written to the gate of the driving transistor. Instead, it is directly coupled to the gate of the driving transistor T1 through the first capacitor C1, which improves the writing speed of the display data voltage signal input at the display data input terminal Data, thereby improving the display effect of the pixel circuit 100.

[0036] In one specific embodiment, in order to control the first capacitor C1 to quickly transfer the charge of the second node N2 to the first node N1, this embodiment of the application may set a first switch T6 connected to the second node N2 to control the voltage pull-down at the second node N2, such as... Figure 2 or Figure 3As shown, in the pixel circuit 100 provided in this application embodiment, the first terminal of the first switch transistor T6 is connected to the second terminal of the first capacitor C1, the second terminal of the first switch transistor T6 is connected to the reference voltage terminal Vref, and the third terminal of the first switch transistor T6 is connected to the first light emission control signal terminal EM2. The first switch T6 is used to adjust the potential of the second terminal of the first capacitor C1 to the first potential V1 when it is in the on state. The first potential is determined by the reference voltage input at the reference voltage terminal Vref.

[0037] When the first switch T6 is in the on state, the potential of the second terminal of the first capacitor C1 is adjusted to the first potential, which is determined by the reference voltage input at the reference voltage terminal Vref.

[0038] The first switching transistor T6 can be a PMOS transistor or an NMOS transistor. This application does not impose specific restrictions on the channel doping type of the first switching transistor T6.

[0039] The first terminal of the first switch transistor T6 can be either the source or the drain, the second terminal of the first switch transistor T6 can be either the source or the drain, and the third terminal of the first switch transistor T6 can be the gate of the first switch transistor T6.

[0040] For example, such as Figure 4A As shown, the first switch T6 can be a PMOS transistor, with the first terminal of the first switch T6 being the source, the second terminal being the drain, and the third terminal being the gate.

[0041] For example, such as Figure 5A As shown, the first switch T6 can be an NMOS transistor. The first terminal of the first switch T6 is the drain, the second terminal is the source, and the third terminal is the gate.

[0042] It should be noted that the pixel circuit 100 has three operating states: reset state, compensation state, and light-emitting state. The function of the first switching transistor T6 differs in each of these operating states.

[0043] When the pixel circuit 100 is in the reset state, the first switch T6 can be in the conducting state, the potential of the second terminal of the first capacitor C1 is adjusted to the first potential, the potential of the second node N2 is the first potential, and the first potential V1 can be determined by the reference voltage input by the reference voltage terminal Vref, thereby resetting the second terminal of the first capacitor C1, so as to avoid the residual charge in the first capacitor C1 from affecting the display of the next frame data.

[0044] When the pixel circuit 100 is in the compensation state, the first switch T6 can be in the off state, thereby preventing the reference voltage input at the reference voltage terminal Vref from affecting the second terminal of the first capacitor C1 being charged to the third potential V. Data .

[0045] When the pixel circuit 100 is in the light-emitting state, the first switch T6 can be in the conducting state, and the potential at the second terminal of the first capacitor C1 changes from the third potential V. Data Adjusted to the first potential V1, through the coupling effect of the first capacitor C1, the potential of the first terminal of the first capacitor C1, that is, the potential of the first node N1, is lowered from the second potential V. DD +V TH Adjusted to the fourth potential V DD +V TH +V1-V Data Thus, the voltage V input at the Data input terminal can be displayed using the first capacitor C1. Data The process quickly transitions to the gate node (i.e., the first node N1) of the driving transistor T1.

[0046] Thus, in this embodiment of the application, the potential of the second terminal of the first capacitor C1 can be adjusted by using the first switching transistor T6 connected to the second terminal of the first capacitor C1. Therefore, by utilizing the coupling effect of the first capacitor C1, the voltage V input at the display data input terminal Data can be displayed. Data The signal is quickly transferred from the second terminal of the first capacitor C1 to the gate node (i.e., the first node N1) of the driving transistor T1.

[0047] In practical applications, the charging process of the storage capacitor and the threshold compensation process of the driving transistor are performed simultaneously in related technologies. However, in the embodiments of this application, the charging process of the capacitor and the threshold compensation process of the driving transistor can be executed separately. In a specific embodiment, in order to separately control the charging process of the first capacitor C1 and the threshold compensation process of the driving transistor T1, the embodiments of this application can use different scanning signals to control the switching transistor T2 for displaying data signals and the switching transistor T3 for threshold compensation of transistor T1, so as to execute the charging process and the threshold compensation process respectively. Figure 3 As shown, the pixel circuit 100 provided in this application embodiment also includes a second switching transistor T2, and the scanning control module 110 includes a third switching transistor T3; the first terminal of the driving transistor T1 is connected to the first voltage terminal VDD; The first terminal of the third switch transistor T3 is connected to the second terminal of the driving transistor T1, the second terminal of the third switch transistor T3 is connected to the gate of the driving transistor T1, and the third terminal of the third switch transistor T3 is connected to the first scan signal terminal S1. The first terminal of the second switch transistor T2 is connected to the display data input terminal Data, the second terminal of the second switch transistor T2 is connected to the second terminal of the first capacitor C1, and the third terminal of the second switch transistor T2 is connected to the second scan signal terminal S2. The scanning signals input to the first scanning signal terminal S1 and the second scanning signal terminal S2 are different.

[0048] The third switch T3 is used to control the threshold compensation of the drive transistor T1. The second switch T2 is used to control the input of the display data input terminal Data.

[0049] In this application, the second switch T2 and the third switch T3 can be PMOS transistors or NMOS transistors, and the channel doping type of the second switch T2 and the third switch T3 is not specifically limited. The first terminal of the third switch T3 can be either the source or the drain, the second terminal of the third switch T3 can be either the source or the drain, and the third terminal of the third switch T3 can be the gate. Similarly, the first terminal of the second switch T2 can be either the source or the drain, the second terminal of the second switch T2 can be either the source or the drain, and the third terminal of the second switch T2 can be the gate.

[0050] For example, such as Figure 4A As shown, the second switch T2 and the third switch T3 can be PMOS transistors. The first terminal of the third switch T3 is the source, the second terminal is the drain, and the third terminal is the gate. The first terminal of the second switch T2 is the source, the second terminal is the drain, and the third terminal is the gate.

[0051] For example, such as Figure 5A As shown, the second switch T2 and the third switch T3 can be NMOS transistors. The first terminal of the third switch T3 is the drain, the second terminal is the source, and the third terminal is the gate. The first terminal of the second switch T2 is the source, the second terminal is the drain, and the third terminal is the gate.

[0052] It should be noted that the pixel circuit 100 has three operating states: reset state, compensation state, and light emission state. The functions of the second switch T2 and the third switch T3 differ in each of these operating states.

[0053] When the pixel circuit 100 is in a reset state, the third switch T3 is turned on by the first scan signal terminal S1. The third switch T3 can be in a conducting state, thereby resetting the third node N3 connected to the second terminal of the driving transistor, thus preventing residual charge at the third node N3 at the second terminal of the driving transistor from affecting the display of the next frame of data. Conversely, when the pixel circuit 100 is in a reset state, the second switch T2 is turned off by the second scan signal terminal S2, thus preventing voltage V input at the display data input terminal Data from being affected. Data This affects the voltage reset at the second node N2 at the second end of the first capacitor C1.

[0054] When the pixel circuit 100 is in the compensation state, the third switch T3 is turned on by controlling the first scan signal terminal S1. The third switch T3 can be in the conducting state, thereby performing threshold compensation on the driving transistor T1 under the drive of the first voltage terminal VDD, so that the gate potential of the driving transistor T1 is adjusted to the second potential V. DD +V TH This is equivalent to pre-compensating the gate potential of the driving transistor T1 before writing data to its gate. When the pixel circuit 100 is in the compensation state, the second switch T2 is turned on via the second scan signal terminal S2. The second switch T2 can be in the on state, and the first capacitor C1 is in the charging state, causing the potential of the second node N2 at the second end of the first capacitor C1 to be adjusted to the third potential V. Data .

[0055] When the pixel circuit 100 is in the light-emitting state, the third switch T3 is controlled to be off by the first scan signal terminal S1, and the second switch T2 is controlled to be off by the second scan signal terminal S2.

[0056] Thus, in this embodiment of the application, the second switch T2 and the third switch T3 can be controlled by different scanning signal terminals, and the second switch T2 and the third switch T3 can be controlled by different scanning signals to perform the capacitor charging process and the threshold compensation process of the driving transistor T1, respectively.

[0057] In one specific embodiment, in order to stabilize the gate potential of the driving transistor T1, such as Figure 3 As shown, the pixel circuit 100 also includes a second capacitor C2. The first end of the second capacitor C2 is connected to the gate of the driving transistor T1, and the second end of the second capacitor C2 is connected to the first voltage terminal VDD. The second switch T2 and the third switch T3 are used to charge the first capacitor C1 and the second capacitor C2 when in the on state, adjust the gate potential of the driving transistor T1 to the second potential, and adjust the potential of the second terminal of the first capacitor C1 to the third potential.

[0058] With the second switch T2 and the third switch T3 in the ON state, the first capacitor C1 and the second capacitor C2 are in the charging state, and the gate potential of the driving transistor T1 is adjusted to the second potential V. DD +V TH The potential at the second terminal of the first capacitor C1 is adjusted to the third potential V. Data ; Wherein, the first voltage terminal VDD is the positive voltage terminal, and the second potential V DD +V TH The first voltage V input from the first voltage terminal VDD DD and the threshold voltage V of the driving transistor T1 TH The sum is determined; the third potential is determined by the second voltage V input at the display data input terminal Data. Data Sure.

[0059] Thus, when the pixel circuit 100 is in the compensation state, the third switch T3 is turned on by controlling the first scan signal terminal S1. The third switch T3 can be in the on state, the second capacitor C2 is in the charging state, and the gate potential of the driving transistor T1 is adjusted to the second potential V. DD +V TH This achieves threshold compensation of the gate potential of the driving transistor T1, and the second capacitor C2 can be used to stabilize the gate potential of the driving transistor T1; and, by controlling the second switch T2 to turn on through the second scan signal terminal S2, the second switch T2 can be in the on state, the first capacitor C1 is in the charging state, and the potential of the second terminal of the first capacitor C1 is adjusted to the third potential V. Data This allows the display data signal to be written into the first capacitor C1.

[0060] In one specific embodiment, in order to control the power supply circuit of the light-emitting element LED, the embodiments of this application may use a fifth switching transistor T5 to control the power supply circuit of the light-emitting element LED, such as... Figure 3 As shown, in the pixel circuit 100, the light emission control module 120 may include a fifth switch transistor T5; the first terminal of the driving transistor T1 is connected to the first voltage terminal VDD, the second terminal of the driving transistor T1 is connected to the first terminal of the fifth switch transistor T5, the second terminal of the fifth switch transistor T5 is connected to the first terminal of the light emission element LED, the third terminal of the fifth switch transistor T5 is connected to the second light emission control signal terminal EM1, and the second terminal of the light emission element LED is connected to the second voltage terminal VSS.

[0061] In this embodiment, the fifth switch T5 can be understood as a negative voltage switch disposed between the light-emitting element LED and the driving transistor T1. In other embodiments, the light-emitting control module 120 may also include a positive voltage switch (not shown in the figure) disposed between the first terminal of the driving transistor T1 and the first voltage terminal VDD. This application does not limit the specific structure of the light-emitting control module 120.

[0062] The driving transistor T1 can be a PMOS transistor or an NMOS transistor, and this application does not impose specific restrictions on the channel doping type of the driving transistor T1. The first terminal of the driving transistor T1 can be either the source or the drain, the second terminal can be either the source or the drain, and the third terminal can be the gate of the driving transistor T1. For example, as... Figure 4A and Figure 5A As shown, the driving transistor T1 can be a PMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate. Alternatively, in other embodiments, the driving transistor T1 can also be an NMOS transistor (not shown), with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate.

[0063] The fifth switch T5 can be a PMOS transistor or an NMOS transistor, and this application does not impose specific restrictions on the channel doping type of the fifth switch T5. The first terminal of the fifth switch T5 can be either the source or the drain, the second terminal can be either the source or the drain, and the third terminal can be the gate of the fifth switch T5. For example, as... Figure 4A and Figure 5A As shown, the fifth switch T5 can be a PMOS transistor, with its first terminal being the source, its second terminal being the drain, and its third terminal being the gate. Alternatively, in other embodiments, the fifth switch T5 can also be an NMOS transistor (not shown), with its first terminal being the drain, its second terminal being the source, and its third terminal being the gate.

[0064] It should be noted that the pixel circuit 100 has three working states: reset state, compensation state, and light emission state.

[0065] When the pixel circuit 100 is in the reset state, the fifth switch T5 is controlled to be off by the second light emission control signal terminal EM1, and the first switch T6 is controlled to be off by the first light emission control signal terminal EM2.

[0066] When the pixel circuit 100 is in the compensation state, the fifth switch T5 is controlled to be off by the second light emission control signal terminal EM1, and the fifth switch T5 can be in the off state. The first switch T6 is controlled to be off by the first light emission control signal terminal EM2, and the first switch T6 can be in the off state.

[0067] When the pixel circuit 100 is in the light-emitting state, the first switch T6 is turned on by the first light-emitting control signal terminal EM2, and the first switch T6 can be in the on state. The fifth switch T5 is turned on by the second light-emitting control signal terminal EM1, and the fifth switch T5 can be in the on state.

[0068] For example, when the pixel circuit 100 is in the light-emitting state, and both the first switch T6 and the fifth switch T5 are in the conducting state, the potential at the second terminal of the first capacitor C1 changes from the third potential V. Data Adjusted to the first potential V1, the gate potential of the driving transistor T1 is changed from the second potential V. DD +V TH When the voltage is adjusted to the fourth potential, the driving transistor T1 is turned on, and the light-emitting element LED is in the light-emitting state. The fourth potential is derived from the second potential V. DD +V TH and the first potential V1 and the third potential V Data The difference ΔV1 is determined. For example, if the difference ΔV1 between the first potential and the third potential is equal to the difference ΔV2 between the fourth potential and the second potential, the fourth potential can be determined as V. DD +V TH +V1-V Data .

[0069] For example, the first switch T6 and the fifth switch T5 are used, in the on state, to change the potential of the second terminal of the first capacitor C1 from the third potential V. Data Adjust to the first potential V1, so that the gate potential of the driving transistor T1 changes from the second potential V. DD +V TH Adjusted to the fourth potential V DD +V TH +V1-V Data The transistor T1 is turned on to drive the LED to emit light.

[0070] The fourth potential is determined by the second potential, and the difference between the first potential and the third potential.

[0071] It should be noted that when the first switch T6 is in the on state, the potential at the second terminal of the first capacitor C1 changes from the third potential V. DataAdjusted to the first potential V1, through the coupling effect of the first capacitor C1, the potential of the first terminal of the first capacitor C1, that is, the potential of the first node N1, is lowered from the second potential V. DD +V TH Adjusted to the fourth potential V DD +V TH +V1-V Data That is, the gate potential of the driving transistor T1 changes from the second potential V. DD +V TH Adjusted to the fourth potential, thus utilizing the first capacitor C1 to display the voltage V input at the Data input terminal. Data The circuit quickly switches to the gate node (i.e., the first node N1) of the driving transistor T1. At this point, with the gate potential of the driving transistor T1 at the fourth potential, the driving transistor T1 can be turned on. Furthermore, with both the driving transistor T1 and the fifth switch T5 in the on state, the LED light-emitting element is driven to emit light by the first voltage terminal VDD.

[0072] In this way, the data writing process of the gate potential of the driving transistor T1 and the illumination state of the light-emitting element LED can be performed synchronously. When the pixel circuit 100 is in the illumination state, the first switching transistor T6 is turned on by controlling the first light-emitting control signal terminal EM2, which will display the voltage V input at the display data input terminal Data. Data The signal is quickly transferred to the gate node of the driving transistor T1. At the same time, the second light-emitting control signal terminal EM1 controls the fifth switch T5 to turn on, so that the light-emitting element LED emits light.

[0073] It should be noted that since the first switch T6 and the fifth switch T5 can operate synchronously in all three operating states of the pixel circuit, when the channel doping types of the first switch T6 and the fifth switch T5 are the same, the first light emission control signal terminal EM2 and the second light emission control signal terminal EM1 can be the same control terminal, further simplifying the control loop of the first switch T6 and the fifth switch T5; however, when the channel doping types of the first switch T6 and the fifth switch T5 are different, the first light emission control signal terminal EM2 and the second light emission control signal terminal EM1 can be different control terminals, and the input levels of the first light emission control signal terminal EM2 and the second light emission control signal terminal EM1 are opposite.

[0074] For example, such as Figure 4AAs shown, both the first switch T6 and the fifth switch T5 are PMOS transistors. The first switch T6 and the fifth switch T5 have the same channel doping type. When the first switch T6 and the fifth switch T5 have the same channel doping type, the first light emission control signal terminal EM2 and the second light emission control signal terminal EM1 can be the same control terminal EM. In other words, when the first switch T6 and the fifth switch T5 have the same channel doping type, the same light emission control signal terminal EM can be used to control the first switch T6 and the fifth switch T5.

[0075] And such Figure 5A As shown, the first switch T6 is an NMOS transistor, and the fifth switch T5 is a PMOS transistor. The first switch T6 and the fifth switch T5 have different channel doping types. When the channel doping types of the first switch T6 and the fifth switch T5 are different, the first light-emitting control signal terminal EM2 and the second light-emitting control signal terminal EM1 can be different control terminals. In other words, when the channel doping types of the first switch T6 and the fifth switch T5 are different, the first light-emitting control signal terminal EM2 and the second light-emitting control signal terminal EM1 can be used to control the first switch T6 and the fifth switch T5 respectively, and the input levels of the first light-emitting control signal terminal EM2 and the second light-emitting control signal terminal EM1 are opposite.

[0076] Thus, when the channel doping types of the first switch T6 and the fifth switch T5 are the same, the embodiments of this application can use the same light emission control signal terminal EM to control the first switch T6 and the fifth switch T5, further simplifying the control loop of the first switch T6 and the fifth switch T5; while when the channel doping types of the first switch T6 and the fifth switch T5 are different, the embodiments of this application can use two light emission control signal terminals EM1 and EM2 with opposite input levels to control the first switch T6 and the fifth switch T5 respectively, ensuring that the first switch T6 and the fifth switch T5 work synchronously.

[0077] In one specific embodiment, in order to reset the light-emitting element LED, such as Figure 3 As shown, the scanning control module 110 also includes a sixth switch transistor T7; the first terminal of the sixth switch transistor T7 is connected to the first terminal of the light-emitting element LED, the second terminal of the sixth switch transistor T7 is connected to the reference voltage terminal Vref, and the third terminal of the sixth switch transistor T7 is connected to the fourth scanning signal terminal S4. The sixth switch T7 is used to adjust the potential of the first terminal of the light-emitting element LED to the first potential V1 when it is in the on state.

[0078] When the sixth switch T7 is in the on state, the potential of the first terminal of the light-emitting element LED is adjusted to the first potential, which is determined by the reference voltage V1 input by the reference voltage terminal Vref.

[0079] It should be noted that the pixel circuit 100 has three working states: reset state, compensation state, and light emission state.

[0080] When the pixel circuit 100 is in a reset state, the sixth switch T7 is turned on by controlling the fourth scan signal terminal S4, so that the sixth switch T7 can be in a conducting state, thereby resetting the potential of the first terminal of the light-emitting element LED; when the pixel circuit 100 is in a reset state, the third switch T3 is turned on by controlling the first scan signal terminal S1, thereby resetting the potential of the second terminal of the driving transistor T1.

[0081] When the pixel circuit 100 is in the compensation state, the sixth switch T7 can be turned on or off via the fourth scan signal terminal S4, without restricting the sixth switch T7 to be in the on or off state. When the pixel circuit 100 is in the compensation state, the third switch T3 can be turned on via the first scan signal terminal S1 to achieve threshold compensation of the gate voltage of the driving transistor T1.

[0082] When the pixel circuit 100 is in the light-emitting state, the sixth switch T7 can be controlled to be off by the fourth scan signal terminal S4, thus preventing the reference voltage from affecting the light-emitting element LED through the sixth switch T7. When the pixel circuit 100 is in the light-emitting state, the third switch T3 can be controlled to be off by the first scan signal terminal S1, thus preventing the third switch T3 from conducting.

[0083] It should be noted that if the sixth switch T7 is turned on when the pixel circuit 100 is in the compensation state, the third switch T3 and the sixth switch T7 can maintain synchronous operation in all three working states of the pixel circuit. In order to further simplify the control loop of the pixel circuit 100, when the channel doping types of the third switch T3 and the sixth switch T7 are the same, the first scan signal terminal S1 and the fourth scan signal terminal S4 are the same control terminal; when the channel doping types of the third switch T3 and the sixth switch T7 are different, the input levels of the first scan signal terminal S1 and the fourth scan signal terminal S4 are opposite.

[0084] For example, such as Figure 4AAs shown, both the third switch T3 and the sixth switch T7 are PMOS transistors. The channel doping types of the third switch T3 and the sixth switch T7 are the same. When the channel doping types of the third switch T3 and the sixth switch T7 are the same, the first scan signal terminal S1 and the fourth scan signal terminal S4 are the same control terminal. In other words, when the channel doping types of the third switch T3 and the sixth switch T7 are the same, the same light emission control signal terminal S1 can be used to control the third switch T3 and the sixth switch T7 to work synchronously.

[0085] And such Figure 5A As shown, the third switch T3 is an NMOS transistor, and the sixth switch T7 is a PMOS transistor. The channel doping types of the third switch T3 and the sixth switch T7 are different. When the third switch T3 and the sixth switch T7 are different, the first scan signal terminal S1 and the fourth scan signal terminal S4 can be different control terminals. In other words, when the channel doping types of the third switch T3 and the sixth switch T7 are different, the first scan signal terminal S1 and the fourth scan signal terminal S4 can be used to control the third switch T3 and the sixth switch T7 respectively, and the input levels of the first scan signal terminal S1 and the fourth scan signal terminal S4 are opposite.

[0086] Thus, when the channel doping types of the third switch T3 and the sixth switch T7 are the same, the embodiments of this application can use the same control terminal S1 to control the third switch T3 and the sixth switch T7 to work synchronously, further simplifying the control loop of the third switch T3 and the sixth switch T7; while when the channel doping types of the third switch T3 and the sixth switch T7 are different, the embodiments of this application can use two control terminals S1 and S4 with opposite input levels to control the third switch T3 and the sixth switch T7 respectively, ensuring that the third switch T3 and the sixth switch T7 work synchronously.

[0087] In one specific embodiment, in order to reset the gate potential of the driving transistor T1, such as Figure 3 As shown, the scan control module 110 also includes a fourth switch transistor T4; the first terminal of the fourth switch transistor T4 is connected to the gate of the driving transistor T1, the second terminal of the fourth switch transistor T4 is connected to the reference voltage terminal Vref, and the third terminal of the fourth switch transistor T4 is connected to the third scan signal terminal S3. The third switch T3 and the fourth switch T4 are used to adjust the gate potential of the driving transistor T1 and the potential of the second terminal of the driving transistor T1 to the first potential when the transistor is in the on state. The first potential V1 is determined by the reference voltage input to the reference voltage terminal Vref.

[0088] When both the third switch T3 and the fourth switch T4 are in the on state, the gate potential of the driving transistor T1 and the potential of the second terminal of the driving transistor T1 are both adjusted to the first potential, which is determined by the reference voltage input to the reference voltage terminal Vref.

[0089] The fourth switch T4 can be a PMOS transistor or an NMOS transistor, and this application does not impose specific restrictions on the channel doping type of the fourth switch T4. The first terminal of the fourth switch T4 can be either the source or the drain, the second terminal of the fourth switch T4 can be either the source or the drain, and the third terminal of the fourth switch T4 can be the gate of the fourth switch T4. For example, as... Figure 4A As shown, the fourth switch T4 can be a PMOS transistor. The first terminal of the fourth switch T4 is the source, the second terminal is the drain, and the third terminal is the gate. Of course, as... Figure 5A As shown, the fourth switch T4 can also be an NMOS transistor. The first terminal of the fourth switch T4 is the drain, the second terminal is the source, and the third terminal is the gate.

[0090] In one example, such as Figure 4A As shown, the third switch T3 and the fourth switch T4 connected to the first node N1 can be P-channel metal-oxide-semiconductor (PMOS) field-effect transistors made of low-temperature polycrystalline silicon (LTPS). Figure 4A Compared to the pixel circuit shown, in another example, such as Figure 5A As shown, both the third switch T3 and the fourth switch T4 can be N-channel metal-oxide-semiconductor (NMOS) made of indium gallium zinc oxide (IGZO).

[0091] Because IGZO has extremely low off-state current, several orders of magnitude lower than that of a-Si and low-temperature polycrystalline silicon (LTPS), it exhibits excellent power consumption control. When displaying static images, the pixel circuitry requires almost no refresh, and the charge can be maintained for extended periods. This results in extremely low power consumption when displaying static images such as reading or viewing photos. Figure 5AIn the pixel circuit 100 shown, PMOS transistors made of LTPS (such as transistors T2, T5, T7, etc.) are combined with NMOS transistors made of IGZO (such as transistors T3, T4, T6). By utilizing the low off-state current characteristics of IGZO, the refresh frequency of the pixel circuit 100 can be dynamically changed from 1Hz to 120Hz, achieving extremely smooth operation when needed and extremely power saving when not needed.

[0092] In this way, this application can use NMOS made of indium gallium zinc oxide as the third switch T3 and the fourth switch T4 to ensure the voltage stability of the first node N1, especially in low screen refresh rate (e.g., 1Hz) scenarios, to ensure the voltage stability of the first node N1 and save power consumption.

[0093] In practical applications, such as Figure 3 As shown, the pixel circuit 100 has three operating states: reset state, compensation state, and light-emitting state. The operating states of the third switch T3, the second switch T2, the first switch T6, the fourth switch T4, the fifth switch T5, and the sixth switch T7 under different operating states can be found in Table 1 below:

[0094] Table 1 For example, Figure 3 The pixel circuit 100 shown has a first working state, a second working state, and a third working state; the first working state is a reset state, the second working state is a compensation state, and the third working state is a light-emitting state.

[0095] Among them, Figure 3 In the pixel circuit 100 shown, the first scan signal terminal S1 is used to control the gate of the third switch transistor T3, the second scan signal terminal S2 is used to control the gate of the second switch transistor T2, the third scan signal terminal S3 is used to control the gate of the fourth switch transistor T4, the fourth scan signal terminal S4 is used to control the gate of the sixth switch transistor T7, the first light emission control signal terminal EM2 is used to control the gate of the first switch transistor T6, and the second light emission control signal terminal EM1 is used to control the gate of the fifth switch transistor T5.

[0096] In one example Figure 3 The pixel circuit 100 shown operates in three states within a single frame: When the pixel circuit 100 is in its first operating state, the first switch T6, the third switch T3, the fourth switch T4, the fifth switch T5, and the sixth switch T7 are in the on state, while the second switch T2 is in the off state. The potential of the second terminal of the first capacitor C1, the potential of the first terminal of the light-emitting element LED, the gate potential of the driving transistor T1, and the potential of the second terminal of the driving transistor T1 are all adjusted to the first potential V1. In this way, the potentials of the four nodes—the first node N1, the second node N2, the third node N3, and the fourth node N4—are simultaneously reset using the reset voltage V1, improving the stability of the pixel circuit.

[0097] When the pixel circuit 100 is in the second operating state, the second switch T2, the third switch T3, and the sixth switch T7 are in the on state, while the first switch T6, the fourth switch T4, and the fifth switch T5 are in the off state. The gate potential of the driving transistor T1 is adjusted to the second potential V. DD +V TH The potential at the second terminal of the first capacitor C1 is adjusted to the third potential V. Data Thus, the first voltage terminal VDD charges the second capacitor C2 connected to the gate of the driving transistor T1 through the driving transistor T1 and the third switch T3 until the gate potential of the driving transistor T1 is adjusted to the second potential V. DD +V TH The display data input terminal Data charges the first capacitor C1 through the second switch T2 until the potential of the second node N2 (i.e., the second terminal of the first capacitor C1) is adjusted to the third potential V. Data .

[0098] When the pixel circuit 100 is in its third operating state, the first switch T6 and the fifth switch T5 are turned on, the second switch T2, the third switch T3, the fourth switch T4, and the sixth switch T7 are turned off, the driving transistor T1 is turned on, and the light-emitting element LED is emitting light. Thus, the reference voltage terminal Vref, through the first switch T6, changes the potential of the second node N2 from the third potential V. Data Pulled down to the first potential V1, the voltage change ΔV1 at the second node N2 is V1 - V Data Through the coupling effect of the first capacitor C1, the potential of the first node N1 changes accordingly. Under ideal coupling conditions, the voltage change of the first node N1 can be equal to the voltage change ΔV1 of the second node N2. The potential of the first node N1 changes from the second potential V... DD +V TH Pull down to the fourth potential, the driving transistor is turned on, and the voltage of the first voltage terminal VDD flows through the driving transistor T1 and the fifth switch T5 through the light-emitting element LED, causing the light-emitting element LED to emit light.

[0099] Thus, through the coupling effect of the first capacitor C1, the voltage V input to the display data input terminal will be displayed. Data Compared to related technologies, the voltage input at the display data input terminal (Data) is quickly transferred to the gate node of the driving transistor T1. Instead of sequentially passing through the driving transistor and threshold compensation transistor before being written to the gate of the driving transistor, it is directly transferred to the gate of the driving transistor T1 via the first capacitor C1. This improves the writing speed of the voltage input at the display data input terminal (Data), thereby enhancing the display effect of the pixel circuit 100. Specifically, the pixel circuit 100 provides a smooth visual experience, maintaining motion blur-free and frame-skipping-free animations and scrolling even at refresh rates of 120Hz, 144Hz, and even higher. Even at high refresh rates, it maintains accurate color reproduction, smooth grayscale transitions, and uniform brightness. Furthermore, through effective threshold voltage compensation, the risk of pixel circuit aging and burn-in is mitigated, resulting in a longer lifespan.

[0100] In practical applications, taking PMOS transistors T1, T2, T3, T4, T5, T6, and T7 in a pixel circuit as an example, such as... Figure 4A As shown, the first scan signal terminal S1 is used to control the gate of the third switch T3 and the gate of the sixth switch T7, the second scan signal terminal S2 is used to control the gate of the second switch T2, the third scan signal terminal S3 is used to control the gate of the fourth switch T4, and the light emission control signal terminal EM is used to control the gate of the first switch T6 and the gate of the fifth switch T5. Figure 4B for Figure 4A The control timing of the pixel circuit 100 shown is such that the first scan signal terminal S1, the second scan signal terminal S2, the third scan signal terminal S3, and the light emission control signal terminal EM are all active low. Figure 4A The pixel circuit 100 shown operates in three states within a single frame: During time period t2, when pixel circuit 100 is in reset state, the first scan signal terminal S1 is in a low level state, controlling the third switch T3 and the sixth switch T7 to conduct; the second scan signal terminal S2 is in a high level state, controlling the second switch T2 to not conduct; the third scan signal terminal S3 is in a low level state, controlling the fourth switch T4 to conduct; the light emission control signal terminal EM is in a low level state, controlling the first switch T6 and the fifth switch T5 to conduct; at this time, the third switch T3, the first switch T6, the fourth switch T4, the fifth switch T5 and the sixth switch T7 are in a conducting state, the second switch T2 is in a disconnected state, and the potential of the second terminal of the first capacitor C1, the potential of the first terminal of the light-emitting element LED, the gate potential of the driving transistor T1 and the potential of the second terminal of the driving transistor T1 are all adjusted to the first potential V1. In this way, the potentials of the four nodes N1, N2, N3, and N4 are simultaneously reset by the reset voltage V1, thereby improving the stability of the pixel circuit.

[0101] During time period t3, when pixel circuit 100 is in compensation state, the first scan signal terminal S1 is at a low level, controlling the third switch T3 and the sixth switch T7 to conduct; the second scan signal terminal S2 is at a low level, controlling the second switch T2 to conduct; the third scan signal terminal S3 is at a high level, controlling the fourth switch T4 to de-conduct; the light emission control signal terminal EM is at a high level, controlling the first switch T6 and the fifth switch T5 to de-conduct; at this time, the third switch T3, the second switch T2, and the sixth switch T7 are in the conducting state, while the first switch T6, the fourth switch T4, and the fifth switch T5 are in the de-conducting state, and the gate potential of the driving transistor T1 is adjusted to the second potential V. DD +V TH The potential at the second terminal of the first capacitor C1 is adjusted to the third potential V. Data Thus, the first voltage terminal VDD charges the second capacitor C2 connected to the gate of the driving transistor T1 through the driving transistor T1 and the third switch T3 until the gate potential of the driving transistor T1 is adjusted to the second potential V. DD +V TH The display data input terminal Data charges the first capacitor C1 through the second switch T2 until the potential of the second node N2 (i.e., the second terminal of the first capacitor C1) is adjusted to the third potential V. DataIn addition, the time period from t4 to t7 is a reserved time period that can be configured as a compensation state for the pixel circuit 100 to extend the threshold compensation time of the driving transistor T1.

[0102] During the time period from t8 to t12, when the pixel circuit 100 is in the light-emitting state, the first scan signal terminal S1 is at a high level, controlling the third switch T3 and the sixth switch T7 to be off; the second scan signal terminal S2 is at a high level, controlling the second switch T2 to be off; the third scan signal terminal S3 is at a high level, controlling the fourth switch T4 to be off; the light-emitting control signal terminal EM is at a low level, controlling the first switch T6 and the fifth switch T5 to be on. At this time, the first switch T6 and the fifth switch T5 are on, the third switch T3, the second switch T2, the fourth switch T4 and the sixth switch T7 are off, the driving transistor T1 is on, and the light-emitting element LED is in the light-emitting state. Thus, the reference voltage terminal Vref changes the potential of the second node N2 from the third potential V through the first switch T6. Data Pulled down to the first potential V1, the voltage change ΔV1 at the second node N2 is V1 - V Data Through the coupling effect of the first capacitor C1, the potential of the first node N1 changes accordingly. Under ideal coupling conditions, the voltage change of the first node N1 can be equal to the voltage change ΔV1 of the second node N2. The potential of the first node N1 changes from the second potential V... DD +V TH Pull down to the fourth potential, the driving transistor is turned on, and the voltage of the first voltage terminal VDD flows through the driving transistor T1 and the fifth switch T5 through the light-emitting element LED, causing the light-emitting element LED to emit light.

[0103] Thus, through the coupling effect of the first capacitor C1, the voltage V input to the display data input terminal will be displayed. Data Compared with related technologies, the voltage input at the display data input terminal (Data) does not need to pass through the driving transistor and the threshold compensation transistor sequentially before being written to the gate of the driving transistor. Instead, it is directly transferred to the gate of the driving transistor T1 through the first capacitor C1, which improves the writing speed of the voltage input at the display data input terminal (Data) and thus improves the display effect of the pixel circuit 100.

[0104] Furthermore, the gates of the third switch T3 and the sixth switch T7 can be connected to the same control terminal (i.e., S1), and the gates of the third switch T3 and the sixth switch T7 are synchronously controlled by the first scan signal terminal S1; and the gates of the first switch T6 and the fifth switch T5 can be connected to the same control terminal (i.e., EM), and the gates of the first switch T6 and the fifth switch T5 are controlled by the light emission control signal terminal EM, which simplifies the control loop of the pixel circuit.

[0105] In another example, taking transistors T3, T4, and T6 in the pixel circuit as NMOS transistors made of IGZO, and transistors T1, T2, T5, and T7 as PMOS transistors, as follows... Figure 5A As shown, the first scan signal terminal S1 is used to control the gate of the third switch T3, the second scan signal terminal S2 is used to control the gate of the second switch T2, the third scan signal terminal S3 is used to control the gate of the fourth switch T4, the fourth scan signal terminal S4 is used to control the gate of the sixth switch T7, the first light emission control signal terminal EM2 is used to control the gate of the first switch T6, and the second light emission control signal terminal EM1 is used to control the gate of the fifth switch T5. Figure 5B for Figure 5A The control timing of the pixel circuit 100 shown is as follows: the output levels of the first scan signal terminal S1 and the fourth scan signal terminal S4 are opposite; the output levels of the first light emission control signal terminal EM2 and the second light emission control signal terminal EM1 are opposite; the first scan signal terminal S1, the third scan signal terminal S3 and the first light emission control signal terminal EM2 are active high; and the second scan signal terminal S2, the fourth scan signal terminal S4 and the second light emission control signal terminal EM1 are active low. Figure 5A The pixel circuit 100 shown operates in three states within a single frame: During time period t2, when pixel circuit 100 is in reset state, the first scan signal terminal S1 is high, controlling the third switch T3 to turn on; the second scan signal terminal S2 is high, controlling the second switch T2 to turn off; the third scan signal terminal S3 is high, controlling the fourth switch T4 to turn on; the fourth scan signal terminal S4 is low, controlling the sixth switch T7 to turn on; and the first light emission control signal terminal EM2 is high. The first light-emitting control signal terminal EM2 controls the first switch T6 to conduct; the second light-emitting control signal terminal EM1 is at a low level, and the fifth switch T5 is controlled to conduct through the second light-emitting control signal terminal EM1. At this time, the third switch T3, the first switch T6, the fourth switch T4, the fifth switch T5, and the sixth switch T7 are in the conducting state, and the second switch T2 is in the off state. The potential of the second terminal of the first capacitor C1, the potential of the first terminal of the light-emitting element LED, the gate potential of the driving transistor T1, and the potential of the second terminal of the driving transistor T1 are all adjusted to the first potential V1. In this way, the potentials of the four nodes N1, N2, N3, and N4 are simultaneously reset by the reset voltage V1, improving the stability of the pixel circuit.

[0106] During time period t3, when pixel circuit 100 is in compensation state, the first scan signal terminal S1 is high, controlling the third switch T3 to turn on; the second scan signal terminal S2 is low, controlling the second switch T2 to turn on; the third scan signal terminal S3 is low, controlling the fourth switch T4 to turn off; the fourth scan signal terminal S4 is low, controlling the sixth switch T7 to turn on; the first light emission control signal terminal EM2 is low, controlling the first switch T6 to turn off; the second light emission control signal terminal EM1 is high, controlling the fifth switch T5 to turn off. At this time, the third switch T3, the second switch T2, and the sixth switch T7 are on, while the first switch T6, the fourth switch T4, and the fifth switch T5 are off. The gate potential of driving transistor T1 is adjusted to the second potential V. DD +V TH The potential at the second terminal of the first capacitor C1 is adjusted to the third potential V. Data Thus, the first voltage terminal VDD charges the second capacitor C2 connected to the gate of the driving transistor T1 through the driving transistor T1 and the third switch T3 until the gate potential of the driving transistor T1 is adjusted to the second potential V.DD +V TH The display data input terminal Data charges the first capacitor C1 through the second switch T2 until the potential of the second node N2 (i.e., the second terminal of the first capacitor C1) is adjusted to the third potential V. Data In addition, the time period from t4 to t7 is a reserved time period that can be configured as a compensation state for the pixel circuit 100 to extend the threshold compensation time of the driving transistor T1.

[0107] During the time period from t8 to t12, when the pixel circuit 100 is in the light-emitting state, the first scan signal terminal S1 is at a low level, controlling the third switch T3 to not conduct; the second scan signal terminal S2 is at a high level, controlling the second switch T2 to not conduct; the third scan signal terminal S3 is at a low level, controlling the fourth switch T4 to not conduct; and the fourth scan signal terminal S4 is at a high level, controlling the sixth switch T... 7. No conduction; the first light-emitting control signal terminal EM2 is in a high-level state, controlling the first switch transistor T6 to conduct; the second light-emitting control signal terminal EM1 is in a low-level state, controlling the fifth switch transistor T5 to conduct; at this time, the first switch transistor T6 and the fifth switch transistor T5 are in a conducting state, the third switch transistor T3, the second switch transistor T2, the fourth switch transistor T4 and the sixth switch transistor T7 are in a de-energized state, the driving transistor T1 is in a conducting state, and the light-emitting element LED is in a light-emitting state. In this way, the reference voltage terminal Vref changes the potential of the second node N2 from the third potential V through the first switch transistor T6. Data Pulled down to the first potential V1, the voltage change ΔV1 at the second node N2 is V1 - V Data Through the coupling effect of the first capacitor C1, the potential of the first node N1 changes accordingly. Under ideal coupling conditions, the voltage change of the first node N1 can be equal to the voltage change ΔV1 of the second node N2. The potential of the first node N1 changes from the second potential V... DD +V TH Pull down to the fourth potential, the driving transistor is turned on, and the voltage of the first voltage terminal VDD flows through the driving transistor T1 and the fifth switch T5 through the light-emitting element LED, causing the light-emitting element LED to emit light.

[0108] Thus, through the coupling effect of the first capacitor C1, the voltage V input to the display data input terminal will be displayed. DataCompared with related technologies, the voltage input at the display data input terminal (Data) does not need to pass through the driving transistor and the threshold compensation transistor sequentially before being written to the gate of the driving transistor. Instead, it is directly transferred to the gate of the driving transistor T1 through the first capacitor C1, which improves the writing speed of the voltage input at the display data input terminal (Data) and thus improves the display effect of the pixel circuit 100.

[0109] Furthermore, by combining PMOS transistors made of LTPS (such as T2, T5, T7, etc.) with NMOS transistors made of IGZO (such as T3, T4, T6), and utilizing the low off-state current characteristics of IGZO, adaptive refresh rates from 1Hz to over 240Hz are achieved. This significantly reduces power consumption while ensuring smooth operation, thus realizing dynamic energy efficiency management.

[0110] In addition, based on the same concept as the pixel circuit provided in any of the above embodiments, this application also provides a display module.

[0111] For example, such as Figure 6 As shown, the display module 200 may include the pixel circuit 100 provided in any of the above embodiments and may achieve the same function.

[0112] In one specific embodiment, pixel circuit 100 is used as an example. Figure 4A Taking the pixel circuit shown as an example, as Figure 7 As shown, the display module 200 provided in this application embodiment may include, for example, Figure 4A The pixel circuit 100 is shown. The display module 200 may further include: a display driver chip 210, a power management chip 220, a scan driver circuit 230, and a light-emitting driver circuit 240; The display driver chip 210 is connected to the scanning driver circuit 230 and the light-emitting driver circuit 240 respectively. The pixel circuit 100 is connected to the display driver chip 210, the power management chip 220, the scanning driver circuit 230, and the light-emitting driver circuit 240, respectively.

[0113] Among them, the display driver chip 210 controls the output of the display data signal (Data signal) and the Vref voltage signal.

[0114] In addition, the display driver chip 210 also controls the scan driver circuit 230 to output a display scan signal, and the display driver chip 210 also controls the light-emitting driver circuit 240 to output a light-emitting control signal.

[0115] The display scanning signals include S1, S2, and S3 signals, and the light emission control signals include EM signals.

[0116] The power management chip 220 controls the output of the positive voltage VDD and the negative voltage VSS.

[0117] When the display scan signal is valid, the display data signal (Data) of the current row is written into the pixel circuit 100, and then the light-emitting drive circuit 240 is turned on, and the power management chip 220 supplies power to the light-emitting diode (LED) to make it emit light.

[0118] It should be noted that the display module may include the pixel circuit provided in any of the above embodiments and can achieve the same function. To avoid repetition, it will not be described again here.

[0119] In addition, based on the same concept as the display module provided in any of the above embodiments, this application also provides an electronic device.

[0120] For example, such as Figure 8 As shown, the electronic device 300 may include the display module 200 provided in any of the above embodiments and can achieve the same function. To avoid repetition, it will not be described again here.

[0121] In the embodiments of this application, the electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), etc. The embodiments of this application do not specifically limit the scope.

[0122] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0123] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A pixel circuit, characterized in that, include: The system includes a light-emitting element, a driving transistor, a first capacitor, a first switching transistor, a scanning control module, and a light-emitting control module. The light-emitting element is connected to the driving transistor through the light-emitting control module, and the scanning control module is connected to the driving transistor. The first capacitor is disposed in the display data signal transmission path between the display data input terminal and the gate of the driving transistor, and the first end of the first capacitor is connected to the gate of the driving transistor; the second end of the first capacitor is coupled to the display data input terminal. The first terminal of the first switching transistor is connected to the second terminal of the first capacitor, the second terminal of the first switching transistor is connected to the reference voltage terminal, and the third terminal of the first switching transistor is connected to the first light emission control signal terminal. The first capacitor is used to couple the display data voltage signal input from the display data input terminal to the gate of the driving transistor when the first switching transistor is in the on state.

2. The pixel circuit according to claim 1, characterized in that, The first switch is used to adjust the potential of the second terminal of the first capacitor to a first potential when it is in the on state. The first potential is determined by the reference voltage input to the reference voltage terminal.

3. The pixel circuit according to claim 1 or 2, characterized in that, The pixel circuit further includes a second switching transistor, and the scanning control module includes a third switching transistor; the first terminal of the driving transistor is connected to a first voltage terminal. The first terminal of the third switch is connected to the second terminal of the driving transistor, the second terminal of the third switch is connected to the gate of the driving transistor, and the third terminal of the third switch is connected to the first scan signal terminal. The first end of the second switching transistor is connected to the display data input terminal, the second end of the second switching transistor is connected to the second end of the first capacitor, and the third end of the second switching transistor is connected to the second scan signal terminal. The scanning signals input to the first scanning signal terminal and the second scanning signal terminal are different.

4. The pixel circuit according to claim 3, characterized in that, The pixel circuit further includes a second capacitor, the first end of which is connected to the gate of the driving transistor, and the second end of which is connected to a first voltage terminal. The second switch and the third switch are used to charge the first capacitor and the second capacitor when the switch is in the on state, adjust the gate potential of the driving transistor to the second potential, and adjust the potential of the second terminal of the first capacitor to the third potential. The second potential is determined by the sum of the first voltage input at the first voltage terminal and the threshold voltage of the driving transistor; the third potential is determined by the second voltage input at the display data input terminal.

5. The pixel circuit according to claim 4, characterized in that, The light-emitting control module includes a fifth switching transistor; the second terminal of the driving transistor is connected to the first terminal of the fifth switching transistor, the second terminal of the fifth switching transistor is connected to the first terminal of the light-emitting element, the third terminal of the fifth switching transistor is connected to the second light-emitting control signal terminal, and the second terminal of the light-emitting element is connected to the second voltage terminal.

6. The pixel circuit according to claim 5, characterized in that, The first switch and the fifth switch are used to adjust the potential of the second terminal of the first capacitor from the third potential to the first potential when the capacitor is in the on state, thereby adjusting the gate potential of the driving transistor from the second potential to the fourth potential, and turning on the driving transistor to drive the light-emitting element to emit light. The fourth potential is determined by the second potential and the difference between the first potential and the third potential.

7. The pixel circuit according to claim 5, characterized in that, When the first switch and the fifth switch have the same channel doping type, the first light emission control signal terminal and the second light emission control signal terminal are the same control terminal; When the channel doping types of the first switch and the fifth switch are different, the input levels of the first light emission control signal terminal and the second light emission control signal terminal are opposite.

8. The pixel circuit according to claim 5, characterized in that, The scanning control module further includes a sixth switching transistor; the first end of the sixth switching transistor is connected to the first end of the light-emitting element, the second end of the sixth switching transistor is connected to the reference voltage terminal, and the third end of the sixth switching transistor is connected to the fourth scanning signal terminal. The sixth switch is used to adjust the potential of the first terminal of the light-emitting element to a first potential when it is in the on state. The first potential is determined by the reference voltage input to the reference voltage terminal. Wherein, when the channel doping type of the third switch and the sixth switch is the same, the first scan signal terminal and the fourth scan signal terminal are the same control terminal; When the channel doping types of the third switch and the sixth switch are different, the input levels of the first scan signal terminal and the fourth scan signal terminal are opposite.

9. The pixel circuit according to claim 8, characterized in that, The scanning control module further includes a fourth switching transistor; the first terminal of the fourth switching transistor is connected to the gate of the driving transistor, the second terminal of the fourth switching transistor is connected to the reference voltage terminal, and the third terminal of the fourth switching transistor is connected to the third scanning signal terminal. The third and fourth switching transistors are used to adjust the gate potential of the driving transistor and the potential of the second terminal of the driving transistor to a first potential when the transistor is in the on state. The first potential is determined by the reference voltage input from the reference voltage terminal.

10. The pixel circuit according to claim 9, characterized in that, Both the third and fourth switching transistors are N-channel metal-oxide-semiconductor field-effect transistors (NMOS) made of indium gallium zinc oxide.

11. The pixel circuit according to claim 9, characterized in that, When the pixel circuit includes a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, and a sixth switch transistor, the pixel circuit has a first operating state, a second operating state, and a third operating state. When the pixel circuit is in the first working state, the first switch, the third switch, the fourth switch, the fifth switch and the sixth switch are in the on state, the second switch is in the off state, and the potential of the second terminal of the first capacitor, the potential of the first terminal of the light-emitting element, the gate potential of the driving transistor and the potential of the second terminal of the driving transistor are all adjusted to the first potential. When the pixel circuit is in the second operating state, the second switch, the third switch, and the sixth switch are in the on state, the first switch, the fourth switch, and the fifth switch are in the off state, the gate potential of the driving transistor is adjusted to the second potential, and the potential of the second terminal of the first capacitor is adjusted to the third potential. When the pixel circuit is in the third operating state, the first switch and the fifth switch are in the on state, the second switch, the third switch, the fourth switch and the sixth switch are in the off state, the driving transistor is in the on state, and the light-emitting element is in the light-emitting state.

12. A display module, characterized in that, Includes the pixel circuit as described in any one of claims 1-11.

13. An electronic device, characterized in that, Includes the display module as described in claim 12.

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