Overvoltage protection circuit and chip
By using a two-stage overvoltage protection circuit, the problem of damage to the single-phase brushless motor driver chip when the VDD voltage is too high is solved, achieving effective power supply voltage management and energy discharge, and ensuring chip safety.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-15
- Publication Date
- 2026-03-13
AI Technical Summary
In the existing technology, when a single-phase brushless motor driver chip detects that the VDD voltage is too high, it cannot effectively avoid the problem of VDD rising due to the freewheeling current of the power transistor body diode, which can lead to chip damage.
A two-stage overvoltage protection circuit is adopted, including a first protection module and a second protection module. The detection module outputs a signal when the power supply voltage exceeds different thresholds to control the conduction and cutoff of the power transistor, thereby dissipating the power supply voltage and the energy at the output terminal and preventing the power supply voltage from rising further.
It effectively prevents the chip from being damaged by excessive power supply voltage, protects the internal circuitry of the chip, avoids energy release caused by the freewheeling current of the power transistor diode, and ensures the safe operation of the chip.
Smart Images
Figure CN121663424A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit design, and in particular to an overvoltage protection circuit and chip. Background Technology
[0002] For single-phase brushless motor drives, the chip needs to detect the VDD voltage to prevent it from becoming too high, which could cause internal breakdown and damage to the chip. Typically, VDD is divided by resistors to ground, then passed through a comparator with a threshold value set. When VDD exceeds the threshold, the comparator flips, and digital logic then controls the power transistor to turn off.
[0003] The above method can protect the internal circuitry of the chip to some extent, but it will release energy to VDD through the body diode of the power transistor. Because there is no path to ground, VDD will surge even higher. If it exceeds the system breakdown voltage, it will cause breakdown and damage the chip. Summary of the Invention
[0004] This application provides an overvoltage protection circuit and chip that can provide two-stage overvoltage protection for VDD, avoiding the problem of VDD rising due to the freewheeling current of the body diode of the power transistor, which could lead to chip damage.
[0005] To achieve the above objectives, this application adopts the following technical solution:
[0006] In a first aspect, this application provides an overvoltage protection circuit, which may include:
[0007] The first protection module is used to output a first overvoltage signal when the power supply voltage is greater than a first overvoltage threshold.
[0008] The detection module has a first terminal connected to the power supply voltage, a second terminal grounded, and a third terminal connected to the first protection module. It is used to output a second overvoltage signal when the power supply voltage is greater than a second overvoltage threshold, and the second overvoltage threshold is greater than the first overvoltage threshold.
[0009] The second protection module has a first terminal connected to the power supply voltage, a second terminal grounded, a third terminal connected to the power transistor, a fourth terminal connected to the detection module, and a fifth terminal connected to the first protection module. It is used to turn on the power transistor after receiving the first overvoltage signal and the second overvoltage signal to discharge the power supply voltage and the energy at the output terminal.
[0010] In one possible implementation, the detection module includes: a first NMOS transistor, N first Zener diodes, and a first resistor, where N is an integer greater than 1;
[0011] N first Zener diodes are connected in series and are in the same direction. The positive terminals of the N first Zener diodes are connected to the drain of the first NMOS transistor, and the negative terminals of the N first Zener diodes are connected to one end of the first resistor and the second protection module.
[0012] The other end of the first resistor is connected to the power supply voltage;
[0013] The gate of the first NMOS transistor is connected to the first protection module, and its source is grounded.
[0014] In one possible implementation, the power transistor includes an upper transistor and a lower transistor, and the second protection module includes an upper transistor control unit and a lower transistor control unit;
[0015] The upper tube control unit has a first terminal connected to the power supply voltage, a second terminal connected to the detection module and the lower tube control unit, a third terminal connected to the gate of the upper tube, a fourth terminal connected to the output terminal, and a fifth terminal connected to the first protection module. It is used to control the upper tube to conduct according to the first overvoltage signal and the second overvoltage signal.
[0016] The lower tube control unit has a first terminal connected to the power supply voltage, a second terminal connected to the detection module and the upper tube control unit, a third terminal connected to the gate of the lower tube, a fourth terminal grounded, and a fifth terminal connected to the first protection module. It is used to control the lower tube to conduct according to the first overvoltage signal and the second overvoltage signal.
[0017] In one possible implementation, the lower transistor control unit includes: a first PMOS transistor, a second resistor, a second NMOS transistor, and a third NMOS transistor;
[0018] The gate of the first PMOS transistor is connected to the detection module and the upper transistor control unit, the source is connected to the power supply voltage, and the drain is connected to one end of the second resistor.
[0019] The other end of the second resistor is connected to the drain and gate of the second NMOS transistor;
[0020] The source of the second NMOS transistor is grounded;
[0021] The gate of the third NMOS transistor is connected to the first protection module, the drain is connected to the gate and drain of the second NMOS transistor, and the source is connected to the gate of the next transistor.
[0022] In one possible implementation, the upper-side control unit includes: a second PMOS transistor, a third resistor, a fourth NMOS transistor, a level shifting unit, and a fifth NMOS transistor;
[0023] The gate of the second PMOS transistor is connected to the detection module and the lower transistor control unit, the source is connected to the power supply voltage, and the drain is connected to one end of the third resistor.
[0024] The other end of the third resistor is connected to the gate and drain of the fourth NMOS transistor;
[0025] The gate of the fourth NMOS transistor is also connected to the drain of the fifth NMOS transistor, and the source is connected to the first terminal and the output terminal of the level conversion unit.
[0026] The gate of the fifth NMOS transistor is connected to the second terminal of the level conversion unit, and the source is connected to the gate of the upper transistor.
[0027] The third terminal of the level conversion unit is connected to the first protection module, and the fourth terminal is connected to the power supply voltage.
[0028] In one possible implementation, the second protection module further includes: a second Zener diode;
[0029] The positive terminal of the second Zener diode is connected to the detection module, the second terminal of the upper diode control unit, and the second terminal of the lower diode control unit, while the negative terminal is connected to the power supply voltage.
[0030] In one possible implementation, the overvoltage protection circuit also includes a resistor path module;
[0031] The resistor path module has a first terminal connected to the first protection module, a second terminal connected to the power supply voltage, and a third terminal grounded. It is used to open the power supply voltage to ground resistance path after receiving the first overvoltage signal in order to discharge the energy of the power supply voltage.
[0032] In one possible implementation, the resistor path module includes: a fourth resistor and a sixth NMOS transistor;
[0033] One end of the fourth resistor is connected to the power supply voltage, and the other end is connected to the drain of the sixth NMOS transistor;
[0034] The gate of the sixth NMOS transistor is connected to the first protection module, and its source is grounded.
[0035] Secondly, this application provides a chip that may include the overvoltage protection circuit of the first aspect and any possible implementation thereof.
[0036] The overvoltage protection circuit provided in this application includes a first protection module that outputs a first overvoltage signal when the power supply voltage exceeds a first overvoltage threshold, enabling the system to control and shut down the power transistor. When the power supply voltage continues to increase due to freewheeling current in the power transistor's body diode or other reasons, the detection module outputs a second overvoltage signal when it detects that the power supply voltage exceeds a second overvoltage threshold. Upon receiving the first and second overvoltage signals, the second protection module turns on the power transistor to discharge abnormal voltage spikes and energy at the output, thereby preventing the power supply voltage from surging even higher and damaging the chip. Attached Figure Description
[0037] Figure 1A circuit block diagram of an overvoltage protection circuit provided in an embodiment of this application;
[0038] Figure 2 A circuit schematic diagram of an overvoltage protection circuit provided in an embodiment of this application;
[0039] Figure 3 A circuit block diagram of another overvoltage protection circuit provided in an embodiment of this application. Detailed Implementation
[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0041] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values may in practice be based on additional conditions or beyond the stated values.
[0042] Figure 1 This is a circuit block diagram illustrating the overvoltage protection circuit provided in an embodiment of this application. Figure 1 As shown, the overvoltage protection circuit may include: a first protection module 11, a detection module 12, and a second protection module 13.
[0043] The first protection module 11 is used to output a first overvoltage signal OVP when the power supply voltage VDD is greater than a first overvoltage threshold. At this time, the system can control the power transistor to shut down to protect the internal circuitry of the chip.
[0044] The detection module 12 has a first terminal connected to the power supply voltage VDD, a second terminal grounded to GND, and a third terminal connected to the first protection module 11. It is used to output a second overvoltage signal when the power supply voltage VDD exceeds a second overvoltage threshold. The second overvoltage threshold is greater than the first overvoltage threshold.
[0045] The second protection module 13 has a first terminal connected to the power supply voltage VDD, a second terminal grounded to GND, a third terminal connected to a power transistor, a fourth terminal connected to the detection module 12, and a fifth terminal connected to the first protection module 11. It is used to activate the power transistor upon receiving a first overvoltage signal and a second overvoltage signal, thereby dissipating the energy from the power supply voltage VDD and the output terminal OUT. The power transistor may include an upper transistor and a lower transistor, with the output terminal OUT located between the upper and lower transistors.
[0046] The overvoltage protection circuit provided in this application embodiment includes a first protection module that outputs a first overvoltage signal when the power supply voltage exceeds a first overvoltage threshold, so that the system can control the shutdown of the power transistor. When the power supply voltage continues to increase due to freewheeling current in the body diode of the power transistor or other reasons, the detection module outputs a second overvoltage signal when it detects that the power supply voltage exceeds a second overvoltage threshold. After receiving the first and second overvoltage signals, the second protection module turns on the power transistor to discharge abnormal peak energy of the power supply voltage and the output terminal, thereby preventing the power supply voltage from rising even higher and damaging the chip.
[0047] Optional, see reference Figure 1 , Figure 2 This is a circuit diagram of an overvoltage protection circuit provided in an embodiment of this application. Figure 2 As shown, the detection module 12 may include: a first NMOS transistor NM1, N first Zener diodes (Z1, Z2, ..., ZN) and a first resistor R1. Here, N is an integer greater than 1.
[0048] N first Zener diodes are connected in series and are in the same direction. The positive terminals of the N first Zener diodes are connected to the drain of the first NMOS transistor NM1, and the negative terminals of the N first Zener diodes are connected to one end of the first resistor R1 and the second protection module 13.
[0049] The other end of the first resistor R1 is connected to the power supply voltage VDD.
[0050] The gate of the first NMOS transistor NM1 is connected to the first protection module 11, and the source is grounded.
[0051] For example, Figure 2 In this example, N is 5, meaning the detection module 12 includes five first Zener diodes. The five first Zener diodes have identical structures, are connected in series, and are connected in the same direction. Assuming the breakdown voltage of one first Zener diode is V1, then the second overvoltage threshold is five times V1.
[0052] When the power supply voltage VDD is greater than the first overvoltage threshold and less than the second overvoltage threshold, the gate of NM1 receives the first overvoltage signal high level, NM1 is turned on, the five Zener diodes are not broken down, and the second protection module 13 does not start working.
[0053] When the power supply voltage VDD continues to increase due to the freewheeling current of the body diode of the power transistor or other reasons, such as power supply glitches or motor back EMF, and increases to a level greater than the second overvoltage threshold, NM1 is turned on, the five Zener diodes are broken down, and the detection module 12 outputs the second overvoltage signal.
[0054] Optionally, in this embodiment, the power transistor may include an upper transistor and a lower transistor, and the second protection module 13 may include an upper transistor control unit 131 and a lower transistor control unit 132.
[0055] The upper tube control unit 131 has a first terminal connected to the power supply voltage VDD, a second terminal connected to the detection module 12 and the lower tube control unit 132, a third terminal connected to the gate of the upper tube, a fourth terminal connected to the output terminal OUT, and a fifth terminal connected to the first protection module 11. It is used to control the upper tube to conduct according to the first overvoltage signal and the second overvoltage signal.
[0056] The lower tube control unit 132 has a first terminal connected to the power supply voltage VDD, a second terminal connected to the detection module 12 and the upper tube control unit 131, a third terminal connected to the gate of the lower tube, a fourth terminal grounded, and a fifth terminal connected to the first protection module 11. It is used to control the lower tube to conduct according to the first overvoltage signal and the second overvoltage signal.
[0057] In practical applications, once the upper and lower transistors are turned on, the energy of the power supply voltage VDD can be discharged as a constant current source through these transistors to prevent VDD overvoltage from damaging the chip. Furthermore, the energy at the output terminal OUT can be discharged as a constant current source through the lower transistor to prevent excessive voltage at OUT from damaging subsequent circuitry. The chip restarts only after the power supply voltage VDD falls below the first overvoltage threshold.
[0058] It is understandable that the current flowing through the power transistor is usually large, while the transistors of the upper and lower control units are small and have current-limiting resistors, so their current capacity is very small. Therefore, the power supply voltage is mainly discharged through the power transistor, and the energy of the power supply voltage discharged through the upper and lower control units is negligible.
[0059] Optionally, in the embodiments of this application, such as Figure 2 As shown, the lower transistor control unit 132 may include: a first PMOS transistor PM1, a second resistor R2, a second NMOS transistor NM2, and a third NMOS transistor NM3.
[0060] The gate of the first PMOS transistor PM1 is connected to the detection module 12 and the upper transistor control unit 131, the source is connected to the power supply voltage VDD, and the drain is connected to one end of the second resistor R2.
[0061] The other end of the second resistor R2 is connected to the drain and gate of the second NMOS transistor NM2.
[0062] The source of the second NMOS transistor NM2 is grounded.
[0063] The gate of the third NMOS transistor NM3 is connected to the first protection module 11, the drain is connected to the gate and drain of the second NMOS transistor NM2, and the source is connected to the gate of the next transistor.
[0064] After the detection module 12 outputs the second overvoltage signal, the gate voltage of PM1 stabilizes at the breakdown voltage of the five first Zener diodes. Since the gate voltage of PM1 is less than the source voltage VDD of PM1, PM1 is turned on, and NM2 is turned on. The gate of NM3 is at the high level of the first overvoltage signal, so NM3 is turned on. The current of NM2 can be mirrored to the lower transistor NM7, so NM7 is turned on.
[0065] Optionally, in the embodiments of this application, such as Figure 2 As shown, the aforementioned upper transistor control unit 131 may include: a second PMOS transistor PM2, a third resistor R3, a fourth NMOS transistor NM4, a level conversion unit LF, and a fifth NMOS transistor NM5.
[0066] In this circuit, the gate of the second PMOS transistor PM2 is connected to the detection module 12 and the lower transistor control unit 132, the source is connected to the power supply voltage VDD, and the drain is connected to one end of the third resistor R3.
[0067] The other end of the third resistor R3 is connected to the gate and drain of the fourth NMOS transistor NM4.
[0068] The gate of the fourth NMOS transistor NM4 is also connected to the drain of the fifth NMOS transistor NM5, and the source is connected to the first terminal and the output terminal OUT of the level conversion unit LF.
[0069] The gate of the fifth NMOS transistor NM5 is connected to the second terminal of the level shifting unit LF, and the source is connected to the gate of the upper transistor.
[0070] The third terminal of the level conversion unit LF is connected to the first protection module 11, and the fourth terminal is connected to the power supply voltage VDD.
[0071] After the detection module 12 outputs the second overvoltage signal, the gate voltage of PM2 stabilizes at the breakdown voltage of the five first Zener diodes. Since the gate voltage of PM2 is less than the source voltage VDD of PM2, PM2 is turned on, and NM4 is turned on. The level conversion unit LF converts the high level of the first overvoltage signal into the power supply voltage VDD, so that the high-voltage transistor NM5 is turned on. After NM5 is turned on, the current of NM4 can be mirrored to the upper transistor NM8, and NM8 is turned on.
[0072] Optionally, in the embodiments of this application, such as Figure 2 As shown, the second protection module 13 may further include: a second Zener diode ZA.
[0073] The positive terminal of the second Zener diode ZA is connected to the detection module 12, the second terminal of the upper tube control unit 131, and the second terminal of the lower tube control unit 132, while the negative terminal is connected to the power supply voltage VDD.
[0074] The second Zener diode ZA is used to protect PM1 and PM2 from damage due to gate overvoltage.
[0075] Optionally, in the embodiments of this application, reference is made to... Figure 1 , Figure 3 A circuit block diagram illustrating another overvoltage protection circuit provided in an embodiment of this application. (See diagram below.) Figure 3 As shown, the overvoltage protection circuit may also include: resistor path module 14.
[0076] The resistor path module 14 has a first end connected to the first protection module 11, a second end connected to the power supply voltage VDD, and a third end grounded to GND. It is used to open the power supply voltage VDD to ground resistance path after receiving the first overvoltage signal, so as to discharge the energy of the power supply voltage VDD.
[0077] Optionally, in the embodiments of this application, such as Figure 2 As shown, the resistor path module 14 may include: a fourth resistor R4 and a sixth NMOS transistor NM6.
[0078] One end of the fourth resistor R4 is connected to the power supply voltage VDD, and the other end is connected to the drain of the sixth NMOS transistor NM6.
[0079] The gate of the sixth NMOS transistor NM6 is connected to the first protection module 11, and the source is grounded.
[0080] When the gate of NM6 receives the first overvoltage signal, i.e., a high level, NM6 turns on, and VDD forms a ground resistance path through R4, which can discharge the energy of the power supply voltage. However, the energy discharged through this path is limited. When the rate of increase of the power supply voltage is higher than the rate of discharge through this path, the power supply voltage will continue to increase until it exceeds the second overvoltage threshold, at which point the second protection module 13 will be triggered to perform overvoltage protection.
[0081] Optionally, in the embodiments of this application, such as Figure 2 As shown, the first protection module 11 may include: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a ninth NMOS transistor NM9, a comparator, an inverter 1, and an inverter 2.
[0082] R5, R6, and R7 are connected in series. One end of R5 is connected to the power supply voltage VDD, and the other end of R7 is grounded.
[0083] The gate of NM9 is connected to the other end of inverter 2, the source is grounded, and the drain is connected to one end of R7 and the other end of R6.
[0084] The first input of the comparator is connected to the threshold VBG, the second input is connected to the other end of R5 and one end of R6, and the output is connected to one end of inverter 1.
[0085] The other end of inverter 1 is connected to one end of inverter 2.
[0086] R5, R6, and R7 divide the power supply voltage VDD. When the voltage division at one end of R6 is greater than the threshold VBG, i.e., when the power supply voltage VDD is greater than the first overvoltage threshold, the first overvoltage signal OVP is output. It can be understood that the relationship between the first overvoltage threshold and VBG is: the first overvoltage threshold equals VBG divided by the voltage division ratio of R6.
[0087] It should be noted that, in the embodiments of this application, Figure 2 This example illustrates the application of an overvoltage protection circuit in an H-bridge motor drive circuit. In other words, as... Figure 2 As shown, the H-bridge motor drive circuit includes two upper transistors and two lower transistors, with a motor M positioned in the middle of the bridge. Correspondingly, the overvoltage protection circuit includes two second protection modules 13, which control the two pairs of upper and lower transistors respectively. Of course, the overvoltage protection circuit provided in this embodiment can also be applied to single-phase bridge motor drive circuits, multi-phase bridge motor drive circuits, and other circuits involving overvoltage protection functions; this embodiment does not limit its application.
[0088] refer to Figure 2 The circuit principle of the overvoltage protection circuit provided in this application embodiment is as follows:
[0089] R5, R6, and R7 divide the power supply voltage VDD. When the voltage at one end of R6 is greater than the threshold VBG, that is, when the power supply voltage VDD is greater than the first overvoltage threshold, the comparator outputs the first overvoltage signal OVP, which is high.
[0090] When OVP is high, NM1 is turned on. When the power supply voltage VDD is greater than the first overvoltage threshold but less than the second overvoltage threshold, the five Zener diodes are not broken down, and the second protection module 13 does not start working.
[0091] When OVP is high, NM6 is turned on. VDD forms a path to ground through R4, which can discharge the energy of the power supply voltage. If VDD can drop below the first overvoltage threshold, the chip restarts.
[0092] However, considering chip area and cost, NM6 has limited discharge capability. If VDD continues to rise until it exceeds the second overvoltage threshold, all five Zener diodes will break down, the detection module 12 will output a second overvoltage signal, and the second protection module 13 will start working. PM1, NM2, and NM3 will conduct, and the current of NM2 can be mirrored to the lower transistor NM7, turning NM7 on. PM2, NM4, and NM5 will conduct, and the current of NM4 can be mirrored to the upper transistor NM8, turning NM8 on.
[0093] After the upper MOSFET NM8 and the lower MOSFET NM7 are turned on, the energy of the power supply voltage VDD can be discharged as a constant current source through the upper and lower MOSFETs to prevent VDD overvoltage from damaging the chip. Furthermore, the energy of the output terminal OUT can be discharged as a constant current source through the lower MOSFET to prevent excessive voltage at the OUT terminal from damaging subsequent circuits. The chip restarts once the power supply voltage VDD falls below the first overvoltage threshold.
[0094] This application embodiment also provides a chip, which may include, as in... Figures 1-3 Any overvoltage protection circuit in the circuit.
[0095] The aforementioned chip can be a motor drive chip, a power management chip, or other chips that involve overvoltage protection.
[0096] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. An overvoltage protection circuit, characterized in that, include: The first protection module is used to output a first overvoltage signal when the power supply voltage is greater than a first overvoltage threshold. The detection module has a first terminal connected to the power supply voltage, a second terminal grounded, and a third terminal connected to the first protection module. It is used to output a second overvoltage signal when the power supply voltage is greater than a second overvoltage threshold, wherein the second overvoltage threshold is greater than the first overvoltage threshold. The second protection module has a first terminal connected to the power supply voltage, a second terminal grounded, a third terminal connected to the power transistor, a fourth terminal connected to the detection module, and a fifth terminal connected to the first protection module. It is used to turn on the power transistor after receiving the first overvoltage signal and the second overvoltage signal to discharge the power supply voltage and the energy at the output terminal.
2. The overvoltage protection circuit according to claim 1, characterized in that, The detection module includes: a first NMOS transistor, N first Zener diodes and a first resistor, where N is an integer greater than 1; N first Zener diodes are connected in series and are in the same direction. The positive terminals of the N first Zener diodes are connected to the drain of the first NMOS transistor, and the negative terminals of the N first Zener diodes are connected to one end of the first resistor and the second protection module. The other end of the first resistor is connected to the power supply voltage; The gate of the first NMOS transistor is connected to the first protection module, and its source is grounded.
3. The overvoltage protection circuit according to claim 1 or 2, characterized in that, The power transistor includes an upper transistor and a lower transistor, and the second protection module includes an upper transistor control unit and a lower transistor control unit; The upper tube control unit has a first terminal connected to the power supply voltage, a second terminal connected to the detection module and the lower tube control unit, a third terminal connected to the gate of the upper tube, a fourth terminal connected to the output terminal, and a fifth terminal connected to the first protection module. It is used to control the upper tube to conduct according to the first overvoltage signal and the second overvoltage signal. The lower tube control unit has a first terminal connected to the power supply voltage, a second terminal connected to the detection module and the upper tube control unit, a third terminal connected to the gate of the lower tube, a fourth terminal grounded, and a fifth terminal connected to the first protection module. It is used to control the lower tube to conduct according to the first overvoltage signal and the second overvoltage signal.
4. The overvoltage protection circuit according to claim 3, characterized in that, The lower transistor control unit includes: a first PMOS transistor, a second resistor, a second NMOS transistor, and a third NMOS transistor; The gate of the first PMOS transistor is connected to the detection module and the upper transistor control unit, the source is connected to the power supply voltage, and the drain is connected to one end of the second resistor; The other end of the second resistor is connected to the drain and gate of the second NMOS transistor; The source of the second NMOS transistor is grounded; The gate of the third NMOS transistor is connected to the first protection module, the drain is connected to the gate and drain of the second NMOS transistor, and the source is connected to the gate of the lower transistor.
5. The overvoltage protection circuit according to claim 3, characterized in that, The upper control unit includes: a second PMOS transistor, a third resistor, a fourth NMOS transistor, a level conversion unit, and a fifth NMOS transistor; The gate of the second PMOS transistor is connected to the detection module and the lower transistor control unit, the source is connected to the power supply voltage, and the drain is connected to one end of the third resistor; The other end of the third resistor is connected to the gate and drain of the fourth NMOS transistor; The gate of the fourth NMOS transistor is also connected to the drain of the fifth NMOS transistor, and the source is connected to the first terminal and the output terminal of the level conversion unit. The gate of the fifth NMOS transistor is connected to the second terminal of the level conversion unit, and the source is connected to the gate of the upper transistor. The third terminal of the level conversion unit is connected to the first protection module, and the fourth terminal is connected to the power supply voltage.
6. The overvoltage protection circuit according to claim 3, characterized in that, The second protection module also includes: a second Zener diode; The positive terminal of the second Zener diode is connected to the detection module, the second terminal of the upper diode control unit, and the second terminal of the lower diode control unit, while the negative terminal is connected to the power supply voltage.
7. The overvoltage protection circuit according to claim 1 or 2, characterized in that, The overvoltage protection circuit also includes: a resistor path module; The resistor path module has a first end connected to the first protection module, a second end connected to the power supply voltage, and a third end grounded. It is used to open the power supply voltage to ground resistance path after receiving the first overvoltage signal, so as to release the energy of the power supply voltage.
8. The overvoltage protection circuit according to claim 7, characterized in that, The resistor path module includes: a fourth resistor and a sixth NMOS transistor; One end of the fourth resistor is connected to the power supply voltage, and the other end is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the first protection module, and its source is grounded.
9. A chip, characterized in that, Includes the overvoltage protection circuit as described in any one of claims 1-8.