Energy management method and system for primary and secondary fusion capacitor electricity taking

Abstract

The invention discloses an energy management method and system for primary and secondary fusion capacitor electricity taking. The method comprises the following steps: acquiring an electricity taking voltage sampling value, an electricity taking current sampling value and a direct current bus voltage sampling value of an electricity taking coupling branch according to a preset sampling period to form a sampling set; recursive estimation is carried out on the equivalent parameters of the electricity taking coupling branch based on the sampling set to obtain a parasitic parameter set; according to the parasitic parameter set and a preset bus voltage reference value, calculating a tuning control quantity set containing a matching network switching code and a switching frequency of the power taking converter, and according to the tuning control quantity set, updating the working states of the power taking matching network and the power taking converter; and meanwhile, direct-current bus voltage deviation is introduced in the next sampling period to perform graded adjustment on the updating frequency of the parasitic parameter set, so that relatively high power taking efficiency is maintained and the bus is stabilized when the voltage, the environment and the parasitic parameters of the power grid change, and the low-energy power failure or reset probability is reduced.

Description

Technical Field

[0001] This invention relates to the technical field of power system secondary equipment self-powered supply and power electronic energy management and control, and particularly to an energy management method and system for primary and secondary integrated capacitor power supply. Background Technology

[0002] With the promotion of digitalization, intelligence, and integrated primary and secondary power distribution network equipment, the demand for low-power, long-life, and maintenance-free power supply on the terminal side is becoming increasingly prominent. Existing integrated primary and secondary terminals integrate measurement, communication, edge computing, and status monitoring functions. If external power supplies are used or batteries are frequently replaced, the on-site operation and maintenance costs and outage window pressure will increase significantly. Therefore, capacitor power extraction based on electric field coupling is gradually becoming one of the important paths for self-power extraction on the distribution side. This type of scheme relies on physical quantities such as the equivalent coupling capacitance and parasitic leakage conductance of the power extraction coupling branch to establish an energy channel. However, under operating conditions such as grid voltage fluctuations, temperature and humidity changes, pollution, and installation gap drift, parasitic parameters change over time, leading to resonance offset and impedance mismatch. This results in engineering problems such as decreased power extraction efficiency, increased DC bus voltage fluctuations, low-energy power outages, or resets. At the same time, if the power extraction side control relies only on fixed parameters or a single closed-loop tuning, it is easy to experience tuning hysteresis or over-tuning under the superposition of parameter drift and measurement noise, making it difficult to balance the engineering constraints of stable bus and reduced control overhead.

[0003] CN111279577A discloses a capacitive wireless power transmission system based on an adaptive matching network. By linking the matching network structure with the control strategy, the system can maintain a relatively good power transmission state under coupling and load changes. This scheme is biased towards matching and maintaining power transmission efficiency of the wireless power transmission link, and lacks a control closed-loop organization method for the DC bus voltage stabilization target of the primary and secondary integrated terminal. In particular, it does not establish an equivalent parameter recursive estimation link based on the measurable voltage and current of the terminal side, taking into account the characteristics of the drift of parasitic parameters of the power extraction coupling branch with the environment and power grid conditions. It also does not provide a mechanism for dynamically scheduling the parameter estimation update rhythm under different levels of bus deviation. Therefore, in low-power terminal scenarios, it is easy to encounter the dilemma of untimely parameter updates leading to mismatch or excessive updates leading to control overhead and disturbance.

[0004] CN110544942A discloses a reactive power compensation capacitor step-down power extraction device and its working method. In the long-term maintenance-free power supply scenario of primary and secondary integrated terminals, this solution, relying solely on the device structure and static compensation parameters, is difficult to cover the equivalent parameter drift problems caused by changes in operating conditions, such as parasitic leakage conductance and equivalent series resistance. Furthermore, it lacks a control path that organizes the power extraction voltage sampling value, power extraction current sampling value, and DC bus voltage sampling value into a sampling set and recursively identifies the parasitic parameter set based on this. It also does not form a joint tuning strategy that uses the parasitic parameter set to back-deduce the matching network switching code and the power extraction converter switching frequency. As a result, under conditions of bus voltage fluctuation and load pulsation, there may still be fluctuations in power extraction efficiency and insufficient bus stability margin.

[0005] In summary, existing capacitive power extraction and capacitive transmission technologies generally suffer from high mismatch risks due to parasitic parameter drift, insufficient coupling between bus voltage stabilization and tuning objectives, and a lack of adaptive scheduling for parameter update rhythm. To address these issues, this invention proposes an energy management method for integrated primary and secondary capacitive power extraction, which maintains high power extraction efficiency and stable bus operation when grid voltage, environment, and parasitic parameters change, thereby reducing the probability of low-energy power outages or resets. Summary of the Invention

[0006] The purpose of this section is to outline some aspects of the embodiments of the present invention and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section, as well as in the abstract and title of the present application, to avoid obscuring the purpose of this section, the abstract and title of the invention. Such simplifications or omissions shall not be used to limit the scope of the present invention.

[0007] In view of the aforementioned existing problems, the present invention is proposed.

[0008] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides an energy management method for primary and secondary integrated capacitor power supply, wherein: sampling values ​​of power supply voltage, power supply current, and DC bus voltage of the power supply coupling branch are collected according to a preset sampling period to obtain a sampling set; Based on the sampling set, the equivalent parameters of the power-taking coupling branch are recursively estimated to obtain the parasitic parameter set; The set of tuning control quantities is calculated based on the parasitic parameter set and the preset bus voltage reference value. The set of tuning control quantities includes the matching network switching code and the power supply converter switching frequency. The operating states of the power supply matching network and the power supply converter are updated according to the set of tuning control quantities, and the update frequency of the parasitic parameter set is adjusted based on the DC bus voltage deviation in the next sampling period.

[0009] In a second aspect, the present invention provides an energy management system for primary and secondary integrated capacitor power supply, wherein: a sampling module collects sampling values ​​of the power supply voltage, power supply current, and DC bus voltage of the power supply coupling branch according to a preset sampling period to obtain a sampling set; The recursive estimation module recursively estimates the equivalent parameters of the power-taking coupling branch based on the sampling set to obtain the parasitic parameter set; The tuning calculation module calculates a set of tuning control quantities based on the parasitic parameter set and the preset bus voltage reference value. The set of tuning control quantities includes the matching network switching code and the power supply converter switching frequency. The execution and frequency adjustment module updates the operating status of the power supply matching network and the power supply converter according to the set of tuning control quantities, and adjusts the update frequency of the parasitic parameter set based on the DC bus voltage deviation in the next sampling period.

[0010] Preferably, the system further includes one or more processors; The memory stores operable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations, including the flow of the energy management method for primary and secondary integrated capacitor power supply as described above.

[0011] A third aspect of the present invention provides a computer-readable medium for storing software, wherein the software includes instructions executable by one or more computers, the instructions causing the one or more computers to perform operations, the operations including the flow of the energy management method for primary and secondary integrated capacitor power supply as described above.

[0012] The beneficial effects of this invention are as follows: This invention collects sampling values ​​of the power extraction voltage, power extraction current, and DC bus voltage of the power extraction coupling branch according to a preset sampling period and forms a sampling set. This ensures that key electrical quantities on the power extraction side are under the same sampling reference, thereby providing a stable observation entry point for coupling conditions and load fluctuations, and reducing the impact of measurement noise and operating condition disturbances on judgment. By recursively estimating the equivalent parameters of the power extraction coupling branch based on the sampling set, a parasitic parameter set is obtained. This allows the drift states of coupling capacitance, parasitic leakage conductance, and equivalent series resistance to be updated online and transformed into controllable decision-making basis, improving the consistency between tuning decisions and actual physical states. The set of parasitic parameters and the preset bus voltage reference value are used to calculate the set of tuning control quantities, so that the matching network switching code and the switching frequency of the power extraction converter form a coordinated tuning path, thereby maintaining high power extraction efficiency and suppressing bus fluctuations under environmental and grid voltage changes. Furthermore, after updating the operating status of the power extraction matching network and the power extraction converter, the update frequency of the parasitic parameter set is adjusted based on the DC bus voltage deviation in the next sampling cycle, so that the parameter updates are more frequent when the deviation is large and more sparse when the deviation is small. This balances fast tracking of drift and reduction of control overhead, ultimately reducing the probability of low-energy power failure or reset and improving the stability of long-term maintenance-free power supply of the primary and secondary fusion terminal. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a flowchart illustrating the energy management method for primary and secondary integrated capacitor power extraction according to the present invention. Detailed Implementation

[0014] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0015] Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort should fall within the scope of protection of this invention.

[0016] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0017] According to an embodiment of the present invention, in combination Figure 1 The flowchart shown illustrates an energy management method for primary and secondary integrated capacitor power supply, which specifically includes the following steps: S1. Collect the sampling values ​​of the power extraction voltage, power extraction current, and DC bus voltage of the power extraction coupling branch according to the preset sampling period to obtain the sampling set. Note that the following should be noted in this step: S1.1 Set the sampling gate phase and preset sampling period within the switching cycle of the power supply converter, and align the sampling gate phase with the switching synchronization signal of the power supply converter to obtain the sampling gate signal; In a preferred embodiment, the power converter outputs a switching synchronization pulse signal. The controller records the arrival time difference between adjacent synchronization pulses through an input capture circuit and uses this time difference as the switching cycle of the power converter. The sampling gating phase is set using a phase position method, that is, a relative time position is pre-selected as the sampling trigger point in each switching cycle, and the trigger point is fixedly aligned with the same edge of the synchronization pulse. The preset sampling period is set using an integer multiple of the switching cycle, so that each sampling falls on the same phase position, thereby reducing the impact of switching ripple phase drift on sampling consistency. After capturing the edge of the synchronization pulse each time, the controller loads a timing comparison register, outputs the start edge of the sampling gating signal when the relative time position is reached, and loads a comparison event corresponding to the gating width to output the end edge of the gating, thereby obtaining the sampling gating signal.

[0018] For example, the switching frequency of the power converter is set to a frequency value within the range of 10kHz to 200kHz; the sampling gate phase is selected as the middle phase interval within the switching cycle; the preset sampling period is set as an integer multiple of the switching cycle, and the integer multiple is selected as an integer between 10 and 500; the gate width is set to cover the time length of the analog-to-digital converter's sample-and-hold action window, and is configured according to the analog-to-digital converter's sample-and-hold time and trigger synchronization jitter margin.

[0019] S1.2 Within the effective window of the sampling gate signal, the power sampling channel, the power sampling current channel, and the DC bus voltage sampling channel are triggered synchronously, and the three sampling results are hardware latched to obtain the power sampling value, the power sampling current value, and the DC bus voltage value. In a preferred embodiment, the effective window of the sampling gate signal is defined as the time interval during which the sampling gate signal is at an effective level. The power supply voltage sampling channel, the power supply current sampling channel, and the DC bus voltage sampling channel are respectively connected to the three-channel sample-and-hold front end of the same multi-channel analog-to-digital converter, or connected to three parallel analog-to-digital converters. The controller configures the starting edge of the sampling gate signal as the external trigger source of the analog-to-digital converter, so that the three sampling channels enter sample-and-hold and start conversion on the same trigger edge. The hardware latch adopts a shadow register structure: the three conversion results are written to the shadow register and remain unchanged until the next external trigger arrives. At the same time, the contents of the shadow register are moved to a record in the sampling buffer through direct memory access, so that the three sampling results in the same record have the same time base.

[0020] For example, synchronous sampling is triggered once at the start edge of the gated window in each sampling period. After the conversion is completed, the three results are written to the same record in the buffer at once to avoid time offset caused by different software reading order of the three samples.

[0021] S1.3 Perform oversampling and decimation processing on the sampled values ​​of the power supply voltage, power supply current, and DC bus voltage, and output the corresponding equivalent sampling results under the same sampling gate phase; In a preferred embodiment, oversampling is performed using a method of multiple sampling within a single effective window: the controller triggers multiple samplings at fixed intervals within the same gated effective window to obtain oversampling sequences of the power-taking voltage, power-taking current, and DC bus voltage, respectively.

[0022] In a preferred embodiment, the extraction process adopts an in-window averaging output method: the equivalent sampling result of the sampling period is obtained by averaging the sampling sequence of each path, and the three equivalent sampling results are written into the same sampling record; in this way, the sensitivity of the equivalent sampling result to switching ripple spikes and random noise is reduced.

[0023] For example, oversampling can be triggered about five times within the gated window and the average can be taken. When the noise level is high, the number of oversampling times can be increased while maintaining the averaged output.

[0024] S1.4 Encapsulate the equivalent sampling results into a sampling set according to the sampling order. The sampling set contains a sampling gate phase identifier and a sampling period identifier that correspond one-to-one with each equivalent sampling result. In a preferred embodiment, the sampling gated phase identifier is represented by a gated phase index number, used to distinguish whether the system has multiple sets of gated phase polling samples; when the system uses only a single gated phase, the sampling gated phase identifier is fixed to the same value; the sampling period identifier is represented by a sampling sequence number, and the controller increments the sampling sequence number after each preset sampling period is completed; the sampling set is encapsulated in a record structure, and each record contains at least: the sampling gated phase identifier, the sampling period identifier, the equivalent sampling result of the power supply voltage, the equivalent sampling result of the power supply current, and the equivalent sampling result of the DC bus voltage, and is accompanied by a data validity flag; the controller writes the records into the circular buffer in the sampling order to form a sampling set, so that subsequent steps can all index the three data at the same time through the combination of the sampling gated phase identifier and the sampling period identifier.

[0025] For example, when using two sets of gated phase polling sampling, the gated phase index number can be set to two levels and written alternately in adjacent sampling periods; when using a single gated phase, the gated phase index number remains constant.

[0026] S1.5. Differential processing is performed on the DC bus voltage sample values ​​between adjacent sampling sets corresponding to the sampling period identifier to obtain the DC bus voltage deviation. The DC bus voltage deviation and the adjacent sampling sets are established according to the sampling period identifier.

[0027] It should be noted that, based on the sampling period identifier, the DC bus voltage sample value corresponding to the target sampling gated phase identifier is read from the first sampling set and the second sampling set respectively. When the DC bus voltage sample value corresponding to the target sampling gated phase identifier is missing in the second sampling set, a replacement value is selected according to the replacement rule. Specifically, the DC bus voltage sample value in the second sampling set that is consistent with the sampling gated phase identifier is selected to replace the DC bus voltage sample value corresponding to the current sampling period. The difference operation is performed on the DC bus voltage sample value corresponding to the current sampling period and the DC bus voltage sample value corresponding to the previous sampling period to obtain the DC bus voltage deviation.

[0028] In a preferred embodiment, the first sampling set is defined as the sampling period identifier. The first sampling set is defined as the sampling set with sampling period identifier k. The second sampling set is defined as the sampling set with sampling period identifier k. The controller uses the target sampling gate phase identifier m as an index to read the DC bus voltage sampling value corresponding to the previous sampling period from the first sampling set. And read the DC bus voltage sample value corresponding to the current sampling period from the second sampling set. When the DC bus voltage sample value corresponding to the target sampling gated phase identifier m is missing in the second sampling set, or the DC bus voltage sample value is marked as invalid, the controller selects the DC bus voltage sample value that is consistent with the target sampling gated phase identifier m from the second sampling set as the replacement value; when there is no record of the target sampling gated phase identifier m in the second sampling set, the record with the smallest difference between the sampling gated phase identifier and m is selected as the replacement value, and the replacement source is written into the validity flag field of the sampling set.

[0029] Furthermore, after completing the above consistency check, the DC bus voltage deviation is calculated using the following formula: in, This refers to the DC bus voltage deviation. The sampled value of the DC bus voltage is identified by sampling period k and sampling gate phase m. The sampling period is identified as The sampling gate phase identifier is the DC bus voltage sampling value with m as the sampling gate phase identifier; k is the sampling period identifier; m is the sampling gate phase identifier.

[0030] For example, the correspondence between DC bus voltage deviation and adjacent sampling sets is established using a key-value binding method: using a key... Index the current sampling period record and... Write it as a derived field of the record, so that it will be used in subsequent steps in the same way. The index reads the DC bus voltage deviation.

[0031] Preferably, this step aligns the sampling gate phase according to the switch synchronization signal, and performs synchronous latching and equivalent processing on the sampled values ​​of the power supply voltage, power supply current, and DC bus voltage under the same sampling gate phase to form a sampling set with sampling gate phase identifier and sampling period identifier; the DC bus voltage deviation is calculated based on adjacent sampling sets to ensure that the change in DC bus voltage maintains a consistent index relationship with the sampling gate phase, thereby reducing the interference of ripple differences introduced by different switch phases on subsequent estimation and tuning, and reducing the risk of parameter drift caused by inconsistent sampling time reference.

[0032] S2. Based on the sampled set, recursively estimate the equivalent parameters of the power-coupled branch to obtain the parasitic parameter set. It should be noted that in this step: S2.1 Construct a discrete equivalent model of the power extraction coupling branch based on the power extraction voltage and power extraction current sampling values ​​in the sampling set. The discrete equivalent model contains a vector of parameters to be estimated, including the coupling capacitance value, parasitic leakage conductance value, and equivalent series resistance value. Specifically, based on the sampling set, the power-taking voltage sampling value sequence and the power-taking current sampling value sequence with the same sampling gate phase identifier are extracted, and the power-taking voltage sampling value sequence and the power-taking current sampling value sequence are aligned one by one according to the sampling period identifier. The power-taking coupling branch is an equivalent circuit structure of an equivalent series resistance branch and a coupling capacitor branch connected in parallel with a parasitic leakage conductance branch. The power-taking voltage is selected as the state variable and the power-taking current is selected as the observation, resulting in a continuous equivalent relation. The continuous equivalent relation is discretized according to the sampling period identifier to generate a discrete difference equation containing the difference terms of the power-taking voltage sampling value and the difference terms of the power-taking current sampling value in adjacent sampling periods. The discrete difference equation is rearranged into a linear regression form of the parameter vector to be estimated, which includes the coupling capacitor value, the parasitic leakage conductance value, and the equivalent series resistance value. The linear regression form is correlated with the sampling period identifier to obtain the discrete equivalent model of the power-taking coupling branch.

[0033] In a preferred embodiment, the power-taking coupling branch is equivalent to a circuit structure in parallel between a branch with an equivalent series resistance value and a coupling capacitance value connected in series and a branch with a parasitic leakage conductance value. The controller uses the power-taking voltage sample value as a state variable and the power-taking current sample value as an observation value, and establishes a discrete relationship on the same-phase data with the sampling gate phase identifier m. For example, let To obtain the voltage sampling value, To obtain the current sampling value, the sampling period is... By introducing the voltage difference term and the current difference term into the discrete difference equation, we obtain the discrete equivalent relation that can be used for linear regression: in, This is the value of the coupling capacitance; This is the parasitic leakage conductance value; It is the product of the coupling capacitance and the equivalent series resistance. The preset sampling period is defined by k; the sampling period identifier is defined by m; and the sampling gate phase identifier is defined by m. This is the sampled value of the power supply voltage; This is the sampled value of the power supply current; Furthermore, the equivalent series resistance value is obtained from the parameters to be estimated using the following formula: in, This is the equivalent series resistance value; Therefore, the observations are taken as The regression vector is taken as: Wherein, the vector of parameters to be estimated is taken as Thus, a discrete equivalent model corresponding to the sampling period identifier is obtained. .

[0034] As an example, select the same sampling gated phase identifier in the buffer. The record sequence is aligned in increments of k, and the difference terms are calculated and generated. and This is used for recursive update calls.

[0035] S2.2 Generate regression vectors and observations that correspond one-to-one with the sampling set from the discrete equivalent model, and set the parameter vector and covariance matrix to be estimated with preset initial values; In a preferred embodiment, the controller generates a regression vector and observations corresponding one-to-one with the sample set based on the discrete equivalent model in each sampling period. During the startup phase, it sets initial values ​​for the parameter vectors to be estimated. These initial values ​​are preferably based on the device's nominal parameters, factory calibration parameters, or assembly test results, and are stored in the firmware parameter area for retrieval upon power-up. The initial value of the covariance matrix is ​​set in a diagonal matrix form to express the initial uncertainties of the coupling capacitance, parasitic leakage conductance, and equivalent series resistance, respectively. Different diagonal element sizes are allowed for different product series. The mathematical expression for the initial value of the covariance matrix is ​​as follows: in, These are the initial values ​​for the covariance matrix; The initial uncertainty coefficient for the coupling capacitance value; The initial uncertainty coefficient for parasitic leakage conductance; The initial uncertainty coefficients are the parameters related to the equivalent series resistance.

[0036] S2.3 Read the DC bus voltage deviation between adjacent sampling sets, determine the recursive gain gating coefficient based on the DC bus voltage deviation, and scale the covariance matrix according to the recursive gain gating coefficient; In a preferred embodiment, the controller reads the DC bus voltage deviation corresponding to the sampling period identifier between adjacent sampling sets, and determines the recursive gain gating coefficient according to the deviation level to which the deviation amplitude belongs. The recursive gain gating coefficient is preferably determined by a lookup table, where the lookup table input is the deviation level and the lookup table output is a preset scaling factor. The higher the deviation level, the larger the scaling factor value. Before each recursive update, the controller scales the covariance matrix according to the scaling factor to adjust the sensitivity of the recursive update to new observations, and uses the scaled covariance matrix as the covariance input for this recursive update.

[0037] Specifically, the magnitude of the DC bus voltage deviation reflects whether the current tuned bus dynamics are in a stage of significant change. When the deviation magnitude is small, the contribution of sampling noise and ripple to the recursive estimation residual increases. If the covariance matrix is ​​amplified, unnecessary jitter may occur in the update of the estimated parameters. When the deviation magnitude is large, the bus state is changing. After the covariance matrix is ​​amplified, the weight of the recursive estimation on the new observation increases, and the parameter convergence speed is accelerated. In conjunction with this, the update frequency increases when the deviation magnitude is large and decreases when the deviation magnitude is small, so that the covariance scaling intensity and triggering rhythm respond consistently to the same bus deviation state.

[0038] For example, the controller uses a combination of the sampling period identifier and the sampling gate phase identifier as an index field to read the DC bus voltage deviation from the sampling record corresponding to the current sampling period and calculate the deviation magnitude: in, This refers to the magnitude of the deviation. The DC bus voltage deviation is represented by k, the sampling period indicator, and the sampling gate phase indicator. To reduce level jitter caused by transient noise, the controller performs first-order smoothing on the deviation amplitude to obtain the gating decision value: in, This is the gating decision quantity; For smoothing coefficients; This is the gating decision value for the previous sampling period; This represents the amplitude of the current sampling period deviation.

[0039] As an example, the controller presets a set of deviation thresholds, including a first threshold, a second threshold, and a third threshold, and satisfies the condition that the first threshold is less than the second threshold, which is less than the third threshold; the deviation level is represented by a four-level indicator, and the determination rule is as follows: when At that time, it was determined to be the first level; when At that time, it was determined to be the second level; when At that time, it was determined to be level three; when At that time, it was determined to be level four; in, The first threshold; The second threshold; This is the third threshold.

[0040] Furthermore, to avoid repeated level jumps near the threshold boundary, the controller introduces hysteresis bandwidth for level switching. The implementation method is as follows: when the current level is a higher level, only when... Downgrading is only allowed when the current tier decreases and exceeds the corresponding threshold hysteresis bandwidth; when the current tier is a lower tier, downgrading is only permitted when... Upgrading is only allowed when the value rises and exceeds the corresponding threshold plus hysteresis bandwidth.

[0041] For example, the controller presets a table of correspondence between deviation levels and recursive gain gating coefficients in the parameter area, and uses the deviation level as the lookup input to obtain the recursive gain gating coefficients: in, These are the recursive gain gating coefficients; For table lookup operators; This is the deviation level identifier corresponding to the sampling period k; The corresponding table satisfies the monotonicity constraint: in, The recursive gain gating coefficient corresponding to the first level; The recursive gain gating coefficient corresponding to the second level; The recursive gain gating coefficient corresponding to the third level; The recursive gain gating coefficient corresponding to the fourth level; Meanwhile, to avoid numerical overflow or oversensitivity, the controller applies a limit to the lookup table output: in, The recursive gain gating coefficient after limiting; This is the minimum amplitude limit; This is the maximum amplitude limit.

[0042] For example, the covariance matrix scaling uses a multiplicative scaling method: before each recursive update, the controller scales the covariance matrix of the previous sampling period according to the thresholded recursive gain gating coefficient to obtain the covariance input matrix for the current recursive update. in, This is the covariance input matrix for this recursive update; This is the covariance matrix of the previous sampling period; The recursive gain gating coefficient after limiting; To ensure the positive definiteness and symmetry of the covariance matrix, the controller performs symmetry transformation and minimum eigenvalue constraint processing after scaling: in, The covariance matrix after symmetry transformation; For transpose operator; And As the corresponding covariance input in the recursive least squares update formula, the sensitivity of the recursive update to new observations increases with the increase of the bus fluctuation amplitude by means of higher level, larger coefficient and larger covariance.

[0043] It should also be noted that when the DC bus voltage deviation in the sampling set is marked as invalid or an index is missing, the controller uses the previous valid deviation value retention rule to generate the gating decision quantity and fixes the deviation level to the first level or retains the previous level; at the same time, the recursive gain gating coefficient is fixed to the corresponding conservative coefficient to avoid introducing uncontrolled covariance amplification in the case of missing data.

[0044] In a preferred embodiment, the deviation level in this step is consistent with the deviation classification identifier determined in step S4.3. The controller looks up the recursive gain gating coefficient based on the deviation classification identifier and scales the covariance matrix according to the recursive gain gating coefficient.

[0045] S2.4 Perform recursive least squares update on the parameter vector to be estimated to obtain the updated coupling capacitance, parasitic leakage conductance and equivalent series resistance values. In a preferred embodiment, the controller uses recursive least squares to update the parameter vector to be estimated and introduces a forgetting factor to balance steady-state convergence and dynamic tracking performance. The recursive update includes: calculating the gain vector based on the scaled covariance matrix and the current regression vector; correcting the parameter vector to be estimated based on the observed residuals; and updating the covariance matrix synchronously.

[0046] As an example, the recursive least squares update uses a forgetting factor, denoted as . ,and Take a preset constant within (0,1], for each group The controller calculates the gain vector and updates the parameter vector to be estimated using the following formula: in, This is the recursive gain vector; This is the scaled covariance matrix; This is the updated covariance matrix; It is the identity matrix; The updated vector of parameters to be estimated; This is the vector of parameters to be estimated from the previous sampling period; For regression vectors; For observation; is the forgetting factor; k is the sampling period identifier; m is the sampling gating phase identifier.

[0047] After the update is complete, the controller presses... The equivalent series resistance value was calculated and compared with... and Together, they serve as the source of the parasitic parameter set for this period.

[0048] For example, when the bus voltage deviation level increases, a larger recursive gain gating coefficient is obtained by looking up the table. Thus amplifying This update also improves the sensitivity of new observations; when the bus voltage deviation level decreases, The gating coefficient is reduced, and the update is more biased towards historical estimates. That is, when the DC bus voltage deviation increases, the corresponding value of the gating coefficient increases, the covariance scaling increases, and the parameter update is more biased towards the current observation. When the DC bus voltage deviation is small, the corresponding value of the gating coefficient decreases, and the parameter update is more biased towards historical estimates, reducing invalid jitter.

[0049] S2.5. Encapsulate the updated coupling capacitance value, parasitic leakage conductance value, and equivalent series resistance value into a parasitic parameter set.

[0050] In a preferred embodiment, the parasitic parameter set is encapsulated using a recording structure and includes at least: coupling capacitance values. Parasitic leakage conductance value Equivalent series resistance value It also includes a sampling period identifier k and a sampling gate phase identifier m as index fields, so that subsequent tuning control quantity calculations can be read using the same index.

[0051] Preferably, this step provides a parameter update method that can be directly iterated to address the model deviation problem caused by the changes in parasitic leakage conductance and equivalent series resistance with temperature rise, humidity and assembly deviation in the coupled capacitor power supply scenario. This ensures that the source of equivalent parameters on which the tuning calculation depends has temporal consistency and adaptability, thereby reducing the dependence of the tuning process on static nominal parameters and reducing the bus fluctuation amplitude caused by mismatch.

[0052] S3. Calculate the tuning control quantity set based on the parasitic parameter set and the preset bus voltage reference value. The tuning control quantity set includes the matching network switching code and the power supply converter switching frequency. Note that the following should be noted in this step: S3.1 Read the coupling capacitance value, parasitic leakage conductance value and equivalent series resistance value from the parasitic parameter set, and calculate the equivalent input impedance set of the power-taking coupling branch based on the parasitic parameter set under the candidate switching frequency set; In a preferred embodiment, the set of candidate switching frequencies is denoted as ,in and These correspond to the preset lower frequency limit and the preset upper frequency limit, respectively, with adjacent frequencies spaced apart. The controller reads the coupling capacitance value from the parasitic parameter set. Parasitic leakage conductance value With equivalent series resistance value And for each candidate switching frequency Calculate angular frequency The series impedance of the electrically coupled branch is denoted as: The equivalent input impedance of the electrically coupled branch is denoted as: in, For series branch complex impedance; The equivalent input complex impedance; j is the imaginary unit; f is the angular frequency; f is the candidate switching frequency; This is the value of the coupling capacitance; This is the parasitic leakage conductance value; This is the equivalent series resistance value; Pi is a constant. The controller will correspond to each f Write the equivalent input impedance set.

[0053] S3.2. Based on the equivalent input impedance set and the preset matching network codebook, calculate the reflection coefficient corresponding to each matching network switching code, and select the matching network switching code with the smallest reflection coefficient as the candidate matching network switching code. In a preferred embodiment, the preset matching network codebook is stored as a correspondence table of matching network switching codes and component parameters, the matching network switching code is denoted as c, and a set of component parameters is stored for each switching code. and These correspond to the series inductance and parallel capacitance of the matching network, respectively. For a given angular frequency The controller calculates the equivalent load impedance after matching using the following formula: and with a preset reference impedance Calculate the reflection coefficient amplitude based on the following: in, The complex impedance after series transformation; To match the equivalent load complex impedance seen at the network input; This represents the amplitude of the reflection coefficient. Preset reference impedance; The series inductor corresponding to the switching code c; The parallel capacitor corresponding to the switching code c; For modulo operation; The controller traverses the codebook at a preset frequency point or a frequency point specified in F, and selects... The smallest matching network switching code is selected as the candidate matching network switching code.

[0054] S3.3. Based on the candidate matching network switching code, calculate the predicted value of DC bus voltage one by one according to the candidate switching frequency set, and calculate the bus voltage evaluation value based on the predicted value of DC bus voltage and the preset bus voltage reference value. In a preferred embodiment, the preset bus voltage reference value is denoted as... The system power supply level determines the switching code of the candidate matching network. Then, for each candidate switching frequency calculate And construct the predicted power output value based on the power output voltage sampled value obtained from the equivalent sampling; make The sampled voltage value for the current sampling period is denoted as and the predicted power value is denoted as . : in, This is for the operation of taking the real part; This is the predicted power output. Capacitor energy balance prediction is used on the DC bus side: Let the DC bus capacitance value be... The evaluation time interval is The estimated load power is denoted as The efficiency of the power converter is obtained by looking up the preset load level table or operating mode identifier. The predicted value of the DC bus voltage is denoted as : The bus voltage evaluation quantity is denoted as : in, This is the sampled value of the DC bus voltage; This is the predicted value of the DC bus voltage; This is the preset bus voltage reference value; This is the DC bus capacitance value; For the evaluation time interval; To improve the efficiency of the power converter; This is an estimated load power value; The controller iterates through F and selects... The smallest candidate switching frequency is taken as the switching frequency of the power supply converter.

[0055] S3.4 Select the candidate switching frequency with the smallest bus voltage evaluation value as the switching frequency of the power supply converter, and encapsulate the candidate matching network switching code and the power supply converter switching frequency into a set of tuning control quantities.

[0056] In a preferred embodiment, the controller will match the candidate network switching code. With the selected power supply converter switching frequency The data is encapsulated as a set of tuning control quantities, which includes at least the following fields: match network switching code, switching frequency setting value, sampling period identifier k, and sampling gate phase identifier m, so that it can be written and traced at the same index in step S4.

[0057] Preferably, this step uses the parasitic parameter set as input, calculates the equivalent input impedance on the candidate switching frequency set, selects the matching network switching code with a smaller reflection coefficient by combining the matching network codebook, and selects the switching frequency by DC bus voltage prediction and evaluation, thereby forming a set of tuning control quantities that can be directly written and executed. In view of the mismatch and bus voltage deviation caused by the impedance change with parasitic parameters in the coupling capacitor power supply link, a deterministic calculation path for the coordinated selection of switching code and frequency is provided to reduce the power supply reduction and bus voltage fluctuation caused by mismatch.

[0058] S4. Update the operating states of the power supply matching network and the power supply converter based on the tuning control quantity set, and adjust the update frequency of the parasitic parameter set based on the DC bus voltage deviation in the next sampling period. Note that the following points should be noted in this step: S4.1 Read the matching network switching code and power converter switching frequency from the tuning control quantity set, write the matching network switching code into the switching register of the power matching network, and write the power converter switching frequency into the switching frequency setting register of the power converter to obtain the updated working status. In a preferred embodiment, the power supply matching network includes a switch matrix and a switchable inductor-capacitor array. The controller writes the matching network switching code from the tuning control quantity set into the matching network's switching register and triggers the register loading when the switch synchronization boundary arrives, enabling the switch matrix to complete the state switching. The switching frequency of the power supply converter is set by timer parameters. The controller writes the switching frequency into the frequency setting register and loads it into the timer shadow register at the next cycle boundary, thereby obtaining the updated operating state. The updated operating state uses the combination of the matching network switching state and the switching frequency setting state as the recorded content and writes it into the operating state recording area.

[0059] It should be noted that the switch matrix is ​​a switch network composed of multiple bidirectional power switch units, used to establish or disconnect electrical connections between different branches. The power switch units preferably adopt a back-to-back power MOSFET structure or a solid-state relay structure to enable bidirectional conduction capability under AC / high-frequency conditions. Each switch unit corresponds to a control bit, and the controller controls the conduction / turn-off of the control bit through the driver, thereby constructing different connection topologies between the common terminal, the inductor array terminal, the capacitor array terminal, and the power-coupled branch terminal. In this embodiment, to reduce switching transients, the switch matrix preferably adopts a control sequence of first disconnecting and then making, and a fixed dead time is set. The length of the dead time is determined by the turn-off time of the switching device and the parasitic oscillation margin.

[0060] The switchable inductor-capacitor array includes an inductor array and a capacitor array. Specifically, the inductor array preferably consists of multiple inductor units with different inductance values, configured in a binary weighted or segmented weighted manner, so that the matching network can form multiple equivalent series inductance values. The inductor units can be power inductors or air-core inductors, selected according to the operating frequency band and current capacity. The capacitor array preferably consists of multiple capacitor units with different capacitance values, configured in a binary weighted or segmented weighted manner, so that the matching network can form multiple equivalent parallel capacitance values. The capacitor units preferably use high-frequency film capacitors or low-loss ceramic capacitors, selected according to dielectric loss and withstand voltage level. Thus, the matching network switching code corresponds to the connection combination state of the inductor array and capacitor array, and different switching codes correspond to different equivalent matching parameter combinations.

[0061] In a preferred embodiment, the register structure of the power matching network includes a switching shadow register and a switching effective register: the controller writes the matching network switching code into the switching shadow register; when the switch synchronization boundary is detected, the controller outputs a load trigger signal to copy the contents of the switching shadow register to the switching effective register; the switch matrix driver only responds to the output bit of the switching effective register, thereby ensuring that the switching action occurs uniformly at the synchronization boundary and avoiding the intermediate state of some bits changing first and some bits changing later within a switching cycle.

[0062] To further suppress switching transients, the controller executes the following sequence before and after the load trigger signal: first, the switch matrix driver is placed in the shutdown preparation state, a dead time is inserted, a load trigger signal is issued, and then the shutdown preparation state is released; after loading, the status readback register is read for consistency verification, and if the verification fails, the system rolls back to the last valid switching code and records the fault flag.

[0063] The switching frequency of the power converter is determined by the timer period parameter. The controller writes the switching frequency from the set of tuning control quantities into the switching frequency setting register and into the timer shadow register. When the next cycle boundary arrives, the timer hardware loads the contents of the shadow register into the effective register, so that the new switching frequency takes effect at the cycle boundary, thereby avoiding pulse width distortion or synchronization loss caused by rewriting in the middle of the cycle.

[0064] S4.2. In the updated working state, enter the next sampling cycle, obtain the DC bus voltage deviation corresponding to the next sampling cycle according to the sampling cycle identifier, and calculate the absolute value of the DC bus voltage deviation. In a preferred embodiment, the controller enters the next sampling cycle in the updated operating state and presses the button. Read the DC bus voltage deviation corresponding to the next sampling period And calculate its absolute value: in, This is the absolute value of the DC bus voltage deviation; is the DC bus voltage deviation; k is the sampling period identifier; m is the sampling gate phase identifier; the controller writes this absolute value into the deviation evaluation field as the input for updating the frequency level determination.

[0065] A smaller absolute value indicates a gradual change in the bus line; a larger absolute value indicates a dramatic change in the bus line, which will trigger more frequent recursive estimation updates.

[0066] In a preferred embodiment, the controller pre-sets three deviation thresholds that increase from small to large, and the thresholds can be calibrated during debugging. The controller determines the update frequency level identifier based on the range in which the absolute value of the DC bus voltage deviation falls, and obtains the recursive estimated execution interval by looking up a table based on the update frequency level identifier. The execution interval satisfies a monotonic relationship where the first level is the largest and the fourth level is the smallest, and the execution interval corresponding to the third level is greater than one, so as to avoid unnecessary calculations caused by each cycle update during non-severe fluctuation phases.

[0067] S4.3 Define a preset set of deviation thresholds as a first deviation threshold, a second deviation threshold, and a third deviation threshold, and satisfy the condition that the first deviation threshold is less than the second deviation threshold and less than the third deviation threshold; when the absolute value of the DC bus voltage deviation is less than the first deviation threshold, the update frequency level is determined to be the first level; when the absolute value of the DC bus voltage deviation is greater than or equal to the first deviation threshold and less than the second deviation threshold, the update frequency level is determined to be the second level; when the absolute value of the DC bus voltage deviation is greater than or equal to the second deviation threshold and less than the third deviation threshold, the update frequency level is determined to be the third level; when the absolute value of the DC bus voltage deviation is greater than or equal to the third deviation threshold, the update frequency level is determined to be the fourth level. In a preferred embodiment, after entering the next sampling period, the controller reads the DC bus voltage deviation corresponding to the next sampling period and calculates the deviation magnitude: in, This refers to the magnitude of the deviation. The DC bus voltage deviation is represented by k, which is the sampling period indicator. The controller smooths the deviation amplitude to obtain the deviation determination value: in, This is the deviation determination quantity; This is the deviation determination value for the previous sampling period; For smoothing coefficients; The controller determines the deviation classification identifier based on the deviation judgment quantity and the deviation threshold set. The deviation classification identifier includes the first level, the second level, the third level and the fourth level. At the classification boundary, the controller performs the up-level and down-level judgment according to the hysteresis bandwidth (the classification switching margin near the threshold boundary), so that the deviation classification identifier does not switch frequently when the deviation judgment quantity fluctuates near the threshold.

[0068] S4.4 Define the correspondence between the update frequency level identifier (i.e., the deviation level identifier) ​​and the recursive estimation execution interval as follows: the first level corresponds to triggering a recursive estimation once in the K1th sampling period, the second level corresponds to triggering a recursive estimation once in the K2th sampling period, the third level corresponds to triggering a recursive estimation once in the K3th sampling period, and the fourth level corresponds to triggering a recursive estimation once in each sampling period, where K1, K2, and K3 are preset positive integers that satisfy K1 > K2 > K3 and K3 > 1; When the deviation grading identifier changes, the controller updates the current recursive estimation execution interval and writes the execution interval into the control parameter field of the current sampling period to keep the triggering rhythm consistent with the deviation grading identifier.

[0069] S4.5. Accumulate the trigger count based on the sampling period identifier, and generate a recursive estimation trigger flag when the trigger count reaches the counting threshold corresponding to the recursive estimation execution interval. In a preferred embodiment, the controller sets a trigger count and increments the trigger count by one at the arrival of each sampling period; the controller also maintains a counting threshold corresponding to the current update frequency level, and the counting threshold is taken as the number of periods corresponding to the current recursive estimation execution interval; when the trigger count reaches the counting threshold, the controller generates a recursive estimation trigger flag and writes it into the control flag field of the current sampling period; when the counting threshold is not reached, no recursive estimation trigger flag is generated.

[0070] For example, when the execution interval is once every eight sampling periods, the trigger count is accumulated from zero to eight to generate a trigger flag, and the trigger count is cleared to zero after a recursive estimation update is completed in the current sampling period.

[0071] S4.6 When the recursive estimation trigger flag is generated, the parasitic parameter set is updated once within the sampling period, and the trigger count is cleared; when the recursive estimation trigger flag is not generated, the parasitic parameter set of the previous sampling period is used.

[0072] In a preferred embodiment, when the recursive estimation trigger flag is generated, the controller calls the recursive estimation process to update the parasitic parameter set once within the sampling period, and clears the trigger count after the update is completed; when the recursive estimation trigger flag is not generated, the controller uses the parasitic parameter set from the previous sampling period to participate in the subsequent tuning control quantity calculation, thereby ensuring that the parasitic parameter set maintains a consistent version when there is no trigger, and avoiding index confusion caused by multiple versions of the parasitic parameter set existing in the same sampling period.

[0073] Preferably, this step updates the operating state by writing the tuning control set into the matching network and the power supply converter, and determines the update frequency level based on the absolute value of the DC bus voltage deviation in the next sampling period. Then, a recursive estimation trigger flag is generated by trigger counting to schedule the update time of the parasitic parameter set. This reduces unnecessary recursive updates during the phase of slow bus changes and increases the recursive update density during the phase of drastic bus changes. An executable rhythm control mechanism is provided to address the contradiction between the estimation update overhead and the tuning response speed, reducing parameter jitter and computational burden caused by frequent updates, and shortening the duration of the mismatch state.

[0074] In the application of the above embodiments, other aspects of the present invention also propose an energy management system for primary and secondary integrated capacitor power supply, including: The sampling module collects the sampling values ​​of the power extraction voltage, power extraction current, and DC bus voltage of the power extraction coupling branch according to a preset sampling period to obtain a sampling set; The recursive estimation module recursively estimates the equivalent parameters of the power-coupled branch based on the sample set, and obtains the parasitic parameter set. The tuning calculation module calculates the tuning control quantity set based on the parasitic parameter set and the preset bus voltage reference value. The tuning control quantity set includes the matching network switching code and the power supply converter switching frequency. The execution and frequency adjustment module updates the operating status of the power supply matching network and power supply converter according to the set of tuning control quantities, and adjusts the update frequency of the parasitic parameter set based on the DC bus voltage deviation in the next sampling cycle.

[0075] The system also includes one or more processors and memory.

[0076] The memory is used to store operable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations, including the flow of the energy management method for primary and secondary integrated capacitor power supply of the foregoing embodiments, in particular... Figure 1 The flowchart of the method is shown.

[0077] Other aspects disclosed in the embodiments of the present invention also propose a computer-readable medium for storing software including instructions executable by one or more computers, which, upon execution, cause the one or more computers to perform operations including the flow of the energy management method for primary and secondary integrated capacitor power extraction of the foregoing embodiments, particularly... Figure 1 The flowchart of the method is shown.

[0078] It should be recognized that embodiments of the present invention may be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium.

[0079] The method can be implemented using standard programming techniques, including a non-transitory computer-readable storage medium configured with a computer program in the computer program, wherein the storage medium is configured such that the computer operates in a specific and predefined manner.

[0080] Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system; however, if required, the program can be implemented in assembly or machine language.

[0081] In any case, the language can be either compiled or interpreted.

[0082] Furthermore, for this purpose, the program can run on programmed application-specific integrated circuits.

[0083] The processes described herein (or variations and / or combinations thereof) can be executed under the control of one or more computer systems configured with executable instructions, and can be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program includes a plurality of instructions executable by one or more processors.

[0084] Furthermore, the method can be implemented in any suitable computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices.

[0085] Various aspects of the present invention can be implemented in machine-readable code stored on a non-transitory storage medium or device, whether portable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein.

[0086] Furthermore, machine-readable code, or parts thereof, can be transmitted via wired or wireless networks.

[0087] When such media includes instructions or programs that combine with a microprocessor or other data processor to implement the steps described above, the invention described herein includes these and other different types of non-transitory computer-readable storage media.

[0088] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An energy management method for primary and secondary integrated capacitor power extraction, characterized in that, include: Collect the sampling values ​​of the power extraction voltage, power extraction current, and DC bus voltage of the power extraction coupling branch according to the preset sampling period to obtain the sampling set; Based on the sampling set, the equivalent parameters of the power extraction coupling branch are recursively estimated to obtain the parasitic parameter set; The set of tuning control quantities is calculated based on the parasitic parameter set and the preset bus voltage reference value. The set of tuning control quantities includes the matching network switching code and the power supply converter switching frequency. The operating states of the power supply matching network and the power supply converter are updated according to the set of tuning control quantities, and the update frequency of the parasitic parameter set is adjusted based on the DC bus voltage deviation in the next sampling period.

2. The energy management method for primary and secondary integrated capacitor power extraction according to claim 1, characterized in that, The sample set is obtained by: Within the switching cycle of the power converter, a sampling gate phase and a preset sampling period are set, and the sampling gate phase is aligned with the switching synchronization signal of the power converter to obtain a sampling gate signal; Within the effective window of the sampling gate signal, the power sampling channel, the power sampling current channel, and the DC bus voltage sampling channel are synchronously triggered, and the three sampling results are hardware latched to obtain the power sampling voltage value, the power sampling current value, and the DC bus voltage value. Oversampling and decimation processing are performed on the power supply voltage sample value, the power supply current sample value, and the DC bus voltage sample value, and the corresponding equivalent sampling results are output under the same sampling gate phase; The equivalent sampling results are encapsulated into a sampling set according to the sampling order. The sampling set contains a sampling gate phase identifier and a sampling period identifier that correspond one-to-one with each equivalent sampling result. Between adjacent sampling sets corresponding to the sampling period identifier, the DC bus voltage sampling values ​​are differentially processed to obtain the DC bus voltage deviation. The DC bus voltage deviation and the adjacent sampling sets are established in a corresponding relationship according to the sampling period identifier.

3. The energy management method for primary and secondary integrated capacitor power extraction according to claim 2, characterized in that, The DC bus voltage deviation is obtained by: Based on the sampling period identifier, the DC bus voltage sampling value corresponding to the target sampling gate phase identifier is read from the first sampling set and the second sampling set respectively. When the DC bus voltage sampling value corresponding to the target sampling gate phase identifier is missing in the second sampling set, a replacement value is selected according to the replacement rule, wherein the DC bus voltage sampling value in the second sampling set that is consistent with the sampling gate phase identifier is selected to replace the DC bus voltage sampling value corresponding to the current sampling period. The DC bus voltage deviation is obtained by performing a differential operation between the DC bus voltage sample value corresponding to the current sampling period and the DC bus voltage sample value corresponding to the previous sampling period.

4. The energy management method for primary and secondary integrated capacitor power extraction according to claim 2, characterized in that, The parasitic parameter set is obtained, including: Based on the sampling values ​​of the power extraction voltage and the power extraction current in the sampling set, a discrete equivalent model of the power extraction coupling branch is constructed. The discrete equivalent model includes a parameter vector to be estimated, including the coupling capacitance value, the parasitic leakage conductance value, and the equivalent series resistance value. The discrete equivalent model generates regression vectors and observations that correspond one-to-one with the sampling set, and sets the parameter vector to be estimated and the covariance matrix with preset initial values. The DC bus voltage deviation is read between adjacent sampling sets, a recursive gain gating coefficient is determined based on the DC bus voltage deviation, and the covariance matrix is ​​scaled according to the recursive gain gating coefficient. A recursive least squares update is performed on the parameter vector to be estimated to obtain the updated coupling capacitance, parasitic leakage conductance and equivalent series resistance values. The updated coupling capacitance value, the parasitic leakage conductance value, and the equivalent series resistance value are encapsulated into a parasitic parameter set.

5. The energy management method for primary and secondary integrated capacitor power extraction according to claim 4, characterized in that, The method for constructing the discrete equivalent model includes: Based on the sampling set, extract the power-taking voltage sampling value sequence and the power-taking current sampling value sequence with the same sampling gate phase identifier, and align the power-taking voltage sampling value sequence and the power-taking current sampling value sequence one by one according to the sampling period identifier; The power extraction coupling branch is an equivalent circuit structure consisting of an equivalent series resistance branch and a coupling capacitor branch connected in parallel with a parasitic leakage conductance branch. The power extraction voltage is selected as the state quantity and the power extraction current is selected as the observation quantity, resulting in a continuous equivalent relationship. The continuous equivalent relation is discretized based on the sampling period identifier to generate a discrete difference equation containing the difference terms of the sampling voltage and the sampling current of adjacent sampling periods. The discrete difference equation is rearranged into a linear regression form of the parameter vector to be estimated, which includes the coupling capacitance value, parasitic leakage conductance value and equivalent series resistance value. By establishing a correspondence between the linear regression form and the sampling period identifier, a discrete equivalent model of the power extraction coupling branch is obtained.

6. The energy management method for primary and secondary integrated capacitor power extraction according to claim 4, characterized in that, Calculating the set of tuning control quantities includes: The coupling capacitance value, parasitic leakage conductance value, and equivalent series resistance value are read from the parasitic parameter set, and the equivalent input impedance set of the power-taking coupling branch is calculated based on the parasitic parameter set under the candidate switching frequency set. Based on the equivalent input impedance set and the preset matching network codebook, the reflection coefficient corresponding to each matching network switching code is calculated, and the matching network switching code with the smallest reflection coefficient is selected as the candidate matching network switching code. Based on the candidate matching network switching code, the predicted DC bus voltage is calculated one by one according to the candidate switching frequency set, and the bus voltage evaluation value is calculated based on the predicted DC bus voltage and the preset bus voltage reference value. The candidate switching frequency with the smallest bus voltage evaluation value is selected as the switching frequency of the power supply converter, and the candidate matching network switching code and the power supply converter switching frequency are encapsulated into a set of tuning control quantities.

7. The energy management method for primary and secondary integrated capacitor power extraction according to claim 6, characterized in that, Adjusting the update frequency of the parasitic parameter set includes: Read the matching network switching code and the power converter switching frequency from the tuning control quantity set, write the matching network switching code into the switching register of the power matching network, and write the power converter switching frequency into the switching frequency setting register of the power converter to obtain the updated working state; In the updated working state, the next sampling cycle is entered. The DC bus voltage deviation corresponding to the next sampling cycle is obtained according to the sampling cycle identifier, and the absolute value of the DC bus voltage deviation is calculated. A preset set of deviation thresholds is defined as a first deviation threshold, a second deviation threshold, and a third deviation threshold, wherein the first deviation threshold is less than the second deviation threshold and less than the third deviation threshold. When the absolute value of the DC bus voltage deviation is less than the first deviation threshold, the update frequency level is determined to be the first level. When the absolute value of the DC bus voltage deviation is greater than or equal to the first deviation threshold and less than the second deviation threshold, the update frequency level is determined to be the second level. When the absolute value of the DC bus voltage deviation is greater than or equal to the second deviation threshold and less than the third deviation threshold, the update frequency level is determined to be the third level. When the absolute value of the DC bus voltage deviation is greater than or equal to the third deviation threshold, the update frequency level is determined to be the fourth level. The correspondence between the update frequency level identifier and the recursive estimation execution interval is defined as follows: the first level corresponds to triggering a recursive estimation once in the K1th sampling period, the second level corresponds to triggering a recursive estimation once in the K2th sampling period, the third level corresponds to triggering a recursive estimation once in the K3th sampling period, and the fourth level corresponds to triggering a recursive estimation once in each sampling period, where K1, K2, and K3 are preset positive integers that satisfy K1 > K2 > K3 and K3 > 1; The trigger count is accumulated based on the sampling period identifier, and a recursive estimation trigger flag is generated when the trigger count reaches the counting threshold corresponding to the recursive estimation execution interval. When the recursive estimation trigger flag is generated, a recursive estimation update is performed on the parasitic parameter set within the sampling period, and the trigger count is cleared to zero; when the recursive estimation trigger flag is not generated, the parasitic parameter set of the previous sampling period is used.

8. An energy management system for primary and secondary integrated capacitor power extraction, characterized in that, include: The sampling module collects the sampling values ​​of the power extraction voltage, power extraction current, and DC bus voltage of the power extraction coupling branch according to a preset sampling period to obtain a sampling set; The recursive estimation module recursively estimates the equivalent parameters of the power-taking coupling branch based on the sampling set to obtain the parasitic parameter set; The tuning calculation module calculates a set of tuning control quantities based on the parasitic parameter set and the preset bus voltage reference value. The set of tuning control quantities includes the matching network switching code and the power supply converter switching frequency. The execution and frequency adjustment module updates the operating status of the power supply matching network and the power supply converter according to the set of tuning control quantities, and adjusts the update frequency of the parasitic parameter set based on the DC bus voltage deviation in the next sampling period.

9. The energy management system for primary and secondary integrated capacitor power extraction according to claim 8, characterized in that, The system also includes one or more processors; The memory stores operable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations, including the flow of the energy management method for primary and secondary integrated capacitor power supply as described in any one of claims 1 to 7.

10. A computer-readable medium for storing software, characterized in that: The software includes instructions executable by one or more computers, which, through execution, cause the one or more computers to perform operations including the flow of the energy management method for primary and secondary integrated capacitor power supply as described in any one of claims 1 to 7.

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