Driving system and method based on half-bridge topology high-power device

Abstract

The invention belongs to the technical field of electronic components, and particularly relates to a driving system and method based on a half-bridge topology high-power device, and the system comprises a control unit which is used for generating a PWM control signal, and carrying out the dynamic adjustment of the dead time of a power switch; the isolation driving unit is connected with the control unit and is used for electrically isolating the PWM signal generated by the control unit; and the power switch unit is connected with the isolation driving unit, adopts a half-bridge topological structure, and is used for realizing electric energy conversion according to the electrically isolated PWM signal so as to drive external equipment. Real-time parameters such as working voltage, current, device temperature and load state are collected through the control unit, the optimal dead time is calculated through a weighting algorithm after normalization processing, a PWM control signal is generated according to the optimal dead time, traditional fixed dead time design is thoroughly abandoned, straight-through short circuit of upper and lower bridge arm switches of a half bridge is avoided, and the risk of short circuit faults is remarkably reduced.

Description

Technical Field

[0001] This invention belongs to the field of electronic component technology, specifically relating to a driving system and method for high-power devices based on a half-bridge topology. Background Technology

[0002] With the rapid development of power electronics technology, high-power device drive systems are widely used in many fields such as industrial manufacturing, new energy, and transportation, and are a core component to ensure the stable operation of various electrical equipment.

[0003] Traditional high-power device drive systems have significant drawbacks. In terms of control, most systems employ a rather crude approach to power switch dead time control, using a fixed dead time setting. However, actual operating conditions are complex and variable, and a fixed dead time is difficult to adapt to different loads, voltages, and temperature conditions. This can easily lead to shoot-through of the upper and lower bridge arm power switches, causing short-circuit faults, seriously threatening system safety, and reducing device lifespan.

[0004] In signal transmission, the PWM signal between the control unit and the power switch unit often lacks effective electrical isolation. This makes the weak electrical signal on the control side susceptible to strong electrical interference from the power side, and ground noise can couple into the control signal, causing signal distortion, affecting the precise control of the power switch, resulting in a decrease in power conversion efficiency and failing to meet the high-quality power requirements of external devices. Summary of the Invention

[0005] To address the aforementioned shortcomings of the prior art, this invention provides a driving system and method based on a half-bridge topology high-power device.

[0006] In a first aspect, the present invention provides a driving system based on a half-bridge topology high-power device, comprising: The control unit is used to generate PWM control signals and dynamically adjust the dead time of the power switch; An isolation drive unit, connected to the control unit, is used to electrically isolate the PWM signals generated by the control unit; The power switching unit, connected to the isolation drive unit, adopts a half-bridge topology and is used to convert electrical energy based on the electrically isolated PWM signal to drive external devices.

[0007] A further improvement to this technical solution is that the isolation drive unit includes an isolation drive circuit and a power isolation circuit, wherein the power isolation circuit provides isolated power to the isolation drive circuit.

[0008] Further improvements to this technical solution include an isolation drive circuit comprising a PWM interface J1, a resistor R1, an isolation drive chip U1, resistors R2 and R3, capacitors C1, C2, and C3, resistors R4, C4, and C5, resistors R5 and R6, a Zener diode D1, a capacitor C6, resistors R7 and R8, a Zener diode D2, a connector H1, and an output interface J2. The first terminals of resistors R1, R2, and R3 are all connected to the PWM signal output terminal of the control unit via PWM interface J1. The second terminal of resistor R1 is connected to the first pin of isolation driver chip U1 and grounded through capacitor C1. The second terminal of resistor R2 is connected to the second pin of isolation driver chip U1 and grounded through capacitor C2. The second terminal of resistor R3 is connected to the third pin of isolation driver chip U1 and grounded through capacitor C3. The fourth pin of isolation driver chip U1 is connected to the first terminal of resistor R4 and the first terminal of capacitor C4. The second terminal of resistor R4 is connected to the fifth pin of isolation driver chip U1, and the second terminal of capacitor C4 is grounded. The sixth pin of isolation driver chip U1 is connected to a 12V power supply and grounded through capacitor C5. The seventh pin of the isolation driver chip U1 is connected to the first terminals of resistors R5 and R6. The second terminal of resistor R6 is connected to the negative terminal of Zener diode D1. The positive terminal of Zener diode D1 and the second terminal of resistor R5 are both connected to the first pin of connector H1 and the first pin of output interface J2. The eighth pin of the isolation driver chip U1 is connected to a 12V power supply and grounded through capacitor C6. The ninth pin of the isolation driver chip U1 is connected to the first terminals of resistors R7 and R8. The second terminal of resistor R8 is connected to the negative terminal of Zener diode D2. The positive terminal of Zener diode D2 and the second terminal of resistor R7 are both connected to the second pin of connector H1 and the second pin of output interface J2. The isolation driver circuit is connected to the power switch unit through output interface J2.

[0009] A further improvement to this technical solution is that the isolation driver chip U1 adopts an isolated gate driver with the model number UCC21520DW.

[0010] Further improvements to this technical solution include a power isolation circuit comprising a first power isolation sub-circuit, a second power isolation sub-circuit, and a power interface J3. The first power isolation sub-circuit includes capacitors C7 and C8, a power isolation chip U2, capacitors C9 and C10, and the second power isolation sub-circuit includes capacitors C11, C12, a power isolation chip U3, capacitors C13 and C14. The input pin of the power isolation chip U2 is connected to the 5V power supply pin of the power interface J3 and grounded through parallel capacitors C7 and C8. The output pin of the power isolation chip U2 is connected to the sixth pin of the isolation driver chip U1 and grounded through parallel capacitors C9 and C10. The input pin of the power isolation chip U3 is connected to the 5V power supply pin of the power interface J3 and grounded through parallel capacitors C11 and C12. The output pin of the power isolation chip U3 is connected to the eighth pin of the isolation driver chip U1 and grounded through parallel capacitors C13 and C14.

[0011] Further improvements to this technical solution include a power switching unit comprising an input interface circuit, an upper bridge arm switching circuit, a lower bridge arm switching circuit, and an output interface J4. The input terminals of both the upper and lower bridge arm switching circuits are connected to the isolation drive circuit via the input interface circuit, and the output terminals of both the upper and lower bridge arm switching circuits are connected to external devices via the output interface J4.

[0012] Further improvements to this technical solution include an upper bridge arm switching circuit comprising resistor R9, resistor R10, Zener diode D3, upper bridge arm MOSFET Q1, bidirectional suppression diode TVS1, resistor R11, Zener diode D4, capacitor C15, and resistor R12. The first terminals of resistors R9 and R10 are both connected to the sixth pin of the isolation driver chip U1 through the input interface circuit. The second terminal of resistor R10 is connected to the negative terminal of Zener diode D3. The positive terminal of Zener diode D3, the second terminal of resistor R9, the first terminal of bidirectional suppressor diode TVS1, and the first terminal of resistor R11 are all connected to the gate of upper bridge arm MOSFET Q1. The second terminal of bidirectional suppressor diode TVS1, the second terminal of resistor R11, the source of upper bridge arm MOSFET Q1, the positive terminal of Zener diode D4, and the first terminal of resistor R12 are all grounded. The drain of upper bridge arm MOSFET Q1 is connected to the first pin of output interface J4, the negative terminal of Zener diode D4, and the first terminal of capacitor C15. The second terminal of capacitor C15 is connected to the second terminal of resistor R12.

[0013] Further improvements to this technical solution include a lower bridge arm switching circuit comprising resistor R13, resistor R14, Zener diode D5, lower bridge arm MOSFET Q2, bidirectional suppression diode TVS2, resistor R15, Zener diode D6, capacitor C16, and resistor R16. The first terminals of resistors R13 and R14 are both connected to the eighth pin of the isolation driver chip U1 through the input interface circuit. The second terminal of resistor R14 is connected to the negative terminal of Zener diode D5. The positive terminal of Zener diode D5, the second terminal of resistor R13, the first terminal of bidirectional suppressor diode TVS2, and the first terminal of resistor R15 are all connected to the gate of the upper bridge arm MOSFET Q2. The second terminal of bidirectional suppressor diode TVS2, the second terminal of resistor R15, the source of lower bridge arm MOSFET Q2, the positive terminal of Zener diode D6, and the first terminal of resistor R16 are all grounded. The drain of lower bridge arm MOSFET Q2 is connected to the second pin of output interface J4, the negative terminal of Zener diode D6, and the first terminal of capacitor C16. The second terminal of capacitor C16 is connected to the second terminal of resistor R16.

[0014] Secondly, the present invention provides a driving method for high-power devices based on a half-bridge topology, comprising: S1. The control unit collects the real-time operating parameters of the system where the high-power circuit is located. The real-time operating parameters include at least the operating voltage, operating current, device temperature and load status of the high-power circuit. Based on the collected real-time operating parameters, the control unit calculates the optimal dead time to adapt to the current operating conditions through a preset algorithm, and generates the corresponding PWM control signal according to the optimal dead time. The PWM control signal includes the upper bridge arm PWM signal used to drive the upper bridge arm switch in the power switching unit and the lower bridge arm PWM signal used to drive the lower bridge arm switch. S2. The PWM control signal is transmitted to the isolation drive unit, and the signal is isolated by electrical isolation to block the ground noise propagation path between the control side and the power side. S3. The electrically isolated PWM signal is transmitted to the power switching unit to drive the upper and lower bridge arm power switching transistors, which adopt a half-bridge topology, to alternately turn on and off, thereby completing the power conversion and driving external devices.

[0015] Further improvements to this technical solution include step S1, which includes: S11. The control unit collects the operating voltage of the high-power circuit in real time through voltage sensors, current sensors, temperature sensors, and load detection circuits. Operating current Device temperature and load status And perform preliminary filtering on the collected raw data; S12. Normalize the filtered parameters, converting them to per-unit or percentage forms. Specifically, this includes: normalizing the operating voltage... Divide by rated voltage Obtain the normalized voltage , will the operating current Divide by the rated current Obtain the normalized current To control the temperature of the device Divide by the pre-stored maximum allowable temperature of the device Obtain the normalized temperature Load status Divide by maximum load Obtain normalized load ; S13. Substitute the normalized parameters into the dead time calculation formula to calculate the optimal dead time; the calculation formula is: ; in, These are weighting coefficients used to reflect the degree of influence of each parameter on the dead time; S14. Based on the calculated optimal dead time Generate the upper bridge arm PWM signal and the lower bridge arm PWM signal, and control the time interval between the two signals to be equal to... This is to avoid short circuits between the upper and lower bridge arms.

[0016] The beneficial effects of this invention are as follows: This invention collects real-time parameters such as operating voltage, current, device temperature, and load status through a control unit. After normalization processing, these parameters are input into a weighted algorithm to calculate the optimal dead time, and a PWM control signal is generated accordingly, completely abandoning the traditional fixed dead time design. This dynamic adjustment mechanism can accurately adapt to different operating conditions: when the load increases, voltage fluctuates, or temperature rises, it automatically optimizes the dead time to avoid shoot-through short circuits in the upper and lower bridge arm switches of the half-bridge, significantly reducing the risk of short-circuit faults. At the same time, it reduces switching losses caused by improper dead time settings, extends the service life of core components such as power MOSFETs, and ensures long-term stable operation of the system.

[0017] The isolated drive unit achieves complete electrical isolation between the control side and the power side through a dual isolation design of "isolation drive circuit + power isolation circuit": On the one hand, it uses an isolated gate driver (model UCC21520DW) and a signal conditioning circuit composed of resistors and capacitors to isolate the PWM signal transmission, preventing strong electrical noise from the power side from coupling to the weak electrical signal on the control side; on the other hand, the power isolation circuit provides independent isolated power supplies to different pins of the isolation drive chip through two power isolation chips, U2 and U3, and further stabilizes the power supply through capacitor filtering, completely cutting off the ground noise propagation path. This dual isolation design effectively avoids PWM signal distortion, ensures that the power switching transistors are precisely switched on and off according to the preset timing, improves power conversion efficiency, and meets the high-quality power requirements of external devices.

[0018] The upper and lower bridge arms of the power switching unit are equipped with multiple protection circuits consisting of gate resistors, Zener diodes, TVS diodes and capacitors. These circuits can effectively suppress voltage spikes during the switching process, absorb reverse recovery charges, clamp the gate voltage, protect the MOSFET from breakdown or false triggering, and extend the service life of the power devices. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is the schematic diagram of the isolation drive circuit.

[0021] Figure 2 This is a schematic diagram of a power isolation circuit.

[0022] Figure 3 This is the circuit schematic of the power switching unit.

[0023] Figure 4 This is a schematic flowchart illustrating a method according to an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the specific embodiments. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0026] like Figure 1 , Figure 2 and Figure 3 As shown, the present invention provides a driving system based on a half-bridge topology high-power device, comprising: The control unit is used to generate PWM control signals and dynamically adjust the dead time of the power switch; An isolation drive unit, connected to the control unit, is used to electrically isolate the PWM signals generated by the control unit; The power switching unit, connected to the isolation drive unit, adopts a half-bridge topology and is used to convert electrical energy based on the electrically isolated PWM signal to drive external devices.

[0027] The isolation drive unit includes an isolation drive circuit and a power isolation circuit, with the power isolation circuit providing isolated power to the isolation drive circuit.

[0028] Specifically, the isolation drive circuit includes a PWM interface J1, resistor R1, isolation drive chip U1, resistors R2 and R3, capacitors C1, C2, C3, R4, C4, C5, R5, R6, Zener diode D1, C6, R7, R8, Zener diode D2, connector H1, and output interface J2. The first ends of resistors R1, R2, and R3 are all connected to the PWM signal output of the control unit via the PWM interface J1. The second end of resistor R1 is connected to the first pin of the isolation drive chip U1 and grounded through capacitor C1. The second end of resistor R2 is connected to the second pin of the isolation drive chip U1 and grounded through capacitor C2. The second end of resistor R3 is connected to the third pin of the isolation drive chip U1 and grounded through capacitor C3. The fourth pin of the isolation drive chip U1 is connected to the first end of resistor R4 and the first end of capacitor C4. The second terminal of the capacitor C4 is connected to the fifth pin of the isolation driver chip U1. The second terminal of the capacitor C4 is grounded. The sixth pin of the isolation driver chip U1 is connected to the 12V power supply and grounded through the capacitor C5. The seventh pin of the isolation driver chip U1 is connected to the first terminals of resistors R5 and R6. The second terminal of resistor R6 is connected to the negative terminal of Zener diode D1. The positive terminal of Zener diode D1 and the second terminal of resistor R5 are both connected to the first pin of connector H1 and the first pin of output interface J2. The eighth pin of the isolation driver chip U1 is connected to the 12V power supply and grounded through the capacitor C6. The ninth pin of the isolation driver chip U1 is connected to the first terminals of resistors R7 and R8. The second terminal of resistor R8 is connected to the negative terminal of Zener diode D2. The positive terminal of Zener diode D2 and the second terminal of resistor R7 are both connected to the second pin of connector H1 and the second pin of output interface J2. The isolation driver circuit is connected to the power switch unit through output interface J2. The isolation driver chip U1 is an isolated gate driver of model UCC21520DW.

[0029] PWM Interface J1: This serves as the connection port between the control unit and the isolated drive circuit, used for inputting PWM signals.

[0030] Resistors R1, R2, and R3: These serve as input matching resistors to adjust the signal impedance and prevent reflection interference.

[0031] Isolation driver chip U1: It adopts the UCC21520DW isolated gate driver. This chip has dual-channel output, high isolation voltage and adjustable dead time function, and is the core component for realizing signal isolation.

[0032] Capacitors C1, C2, and C3: High-frequency decoupling capacitors, connected between the input pin of U1 and ground respectively, to filter out high-frequency noise.

[0033] Resistor R4 and capacitor C4 form an RC filter network, connected to the fourth and fifth pins of U1, to stabilize the internal logic power supply of the chip.

[0034] Capacitors C5 and C6: Power supply decoupling capacitors, connected between pin 6 and pin 8 of U1 and ground respectively, to suppress power supply fluctuations. Connector H1 and output interface J2: used to output the conditioned drive signal to the power switching unit.

[0035] In addition, the power isolation circuit includes a first power isolation sub-circuit, a second power isolation sub-circuit, and a power interface J3. The first power isolation sub-circuit includes capacitors C7 and C8, power isolation chip U2, capacitors C9 and C10. The second power isolation sub-circuit includes capacitors C11 and C12, power isolation chip U3, capacitors C13 and C14. The input pin of power isolation chip U2 is connected to the 5V power supply pin of power interface J3 and grounded through parallel capacitors C7 and C8. The output pin of power isolation chip U2 is connected to the sixth pin of isolation driver chip U1 and grounded through parallel capacitors C9 and C10. The input pin of power isolation chip U3 is connected to the 5V power supply pin of power interface J3 and grounded through parallel capacitors C11 and C12. The output pin of power isolation chip U3 is connected to the eighth pin of isolation driver chip U1 and grounded through parallel capacitors C13 and C14. Both power isolation chips U2 and U3 are B0512S type power isolation chips.

[0036] After the system is powered on, the 5V power supply from the control side is input to the input sides of U2 and U3 through power interface J3: Input filtering: C7, C8, C11, and C12 first filter out high-frequency noise in the 5V power supply to ensure that the power input to U2 and U3 is clean; Isolation Conversion: U2 and U3 achieve "electrical energy-magnetic energy-electrical energy" isolation conversion through an internal high-frequency transformer (operating frequency 100kHz), converting the 5V non-isolated power supply on the control side to a 12V isolated power supply, while using the isolation characteristics of the transformer to block the electrical connection between the control side and the power side. Output filtering: The 12V power output from U2 and U3 is filtered by C9, C10, C13 and C14 for high and low frequency, and then sent to the sixth and eighth pins of the isolation driver chip U1 to provide stable power supply for the upper and lower bridge arm drive circuits of U1. Dynamic adaptation: When the isolated driver chip U1 generates a large instantaneous current due to driving the power MOSFET, C9 and C13 can quickly release their charge to replenish the instantaneous current demand, avoid output voltage drop (drop amplitude ≤ 0.5V), and ensure the stability of the U1 drive signal.

[0037] The isolated drive unit achieves complete electrical isolation between the control side and the power side through a dual isolation design of "isolation drive circuit + power isolation circuit": On the one hand, it uses an isolated gate driver (model UCC21520DW) and a signal conditioning circuit composed of resistors and capacitors to isolate the PWM signal transmission, preventing strong electrical noise from the power side from coupling to the weak electrical signal on the control side; on the other hand, the power isolation circuit provides independent isolated power supplies to different pins of the isolation drive chip through two power isolation chips, U2 and U3, and further stabilizes the power supply through capacitor filtering, completely cutting off the ground noise propagation path. This dual isolation design effectively avoids PWM signal distortion, ensures that the power switching transistors are precisely switched on and off according to the preset timing, improves power conversion efficiency, and meets the high-quality power requirements of external devices.

[0038] Furthermore, the power switching unit includes an input interface circuit, an upper bridge arm switching circuit, a lower bridge arm switching circuit, and an output interface J4. The input interface circuit includes an input interface J5 and a connector H2. The input terminals of the upper bridge arm switching circuit and the lower bridge arm switching circuit are both connected to the isolation drive circuit through the input interface circuit. The output terminals of the upper bridge arm switching circuit and the lower bridge arm switching circuit are both connected to external devices through the output interface J4.

[0039] The upper bridge arm switching circuit includes resistors R9 and R10, Zener diode D3, upper bridge arm MOSFET Q1, bidirectional suppressor diode TVS1, resistor R11, Zener diode D4, capacitor C15, and resistor R12. The first ends of resistors R9 and R10 are connected to the sixth pin of the isolation driver chip U1 through the input interface circuit. The second end of resistor R10 is connected to the negative terminal of Zener diode D3. The positive terminal of Zener diode D3, the second end of resistor R9, the first end of bidirectional suppressor diode TVS1, and the first end of resistor R11 are all connected to the gate of upper bridge arm MOSFET Q1. The second end of bidirectional suppressor diode TVS1, the second end of resistor R11, the source of upper bridge arm MOSFET Q1, the positive terminal of Zener diode D4, and the first end of resistor R12 are all grounded. The drain of upper bridge arm MOSFET Q1 is connected to the first pin of output interface J4, the negative terminal of Zener diode D4, and the first end of capacitor C15. The second end of capacitor C15 is connected to the second end of resistor R12.

[0040] Furthermore, the lower bridge arm switching circuit includes resistors R13 and R14, Zener diode D5, lower bridge arm MOSFET Q2, bidirectional suppressor diode TVS2, resistor R15, Zener diode D6, capacitor C16, and resistor R16. The first terminals of resistors R13 and R14 are both connected to the eighth pin of the isolation driver chip U1 through the input interface circuit. The second terminal of resistor R14 is connected to the negative terminal of Zener diode D5. The positive terminal of Zener diode D5, the second terminal of resistor R13, the first terminal of bidirectional suppressor diode TVS2, and the first terminal of resistor R15 are all connected to the gate of upper bridge arm MOSFET Q2. The second terminal of bidirectional suppressor diode TVS2, the second terminal of resistor R15, the source of lower bridge arm MOSFET Q2, the positive terminal of Zener diode D6, and the first terminal of resistor R16 are all grounded. The drain of lower bridge arm MOSFET Q2 is connected to the second pin of output interface J4, the negative terminal of Zener diode D6, and the first terminal of capacitor C16. The second terminal of capacitor C16 is connected to the second terminal of resistor R16.

[0041] R9 and R13 are used to limit the forward drive current output from the isolation drive unit to the gate of the MOSFET, so as to avoid the gate charge being injected too quickly, which would cause abnormal switching speed of the MOSFET (e.g., excessive di / dt during turn-on, resulting in voltage spikes).

[0042] R10 and R14, together with Zener diodes D3 and D5, limit the reverse gate voltage and prevent reverse breakdown of the MOSFET gate and source.

[0043] Zener diodes D3 and D5 have their anodes connected to the gate of the MOSFET and their cathodes connected to resistors R10 / R14. This is used to clamp the gate positive voltage and prevent the gate-source of the MOSFET from breaking down due to excessively high output voltage from the isolation drive unit. Zener diodes D4 and D6 have their anodes grounded and their cathodes connected to the drain of the MOSFET. This is used to clamp the turn-off voltage spike at the drain of the MOSFET and protect the drain and source of the MOSFET.

[0044] Bidirectional suppression diodes (TVS1, TVS2): Connected in parallel between the gate and source of the MOSFET, these fast recovery diodes provide a fast turn-off path. When the driver chip requires the MOSFET to turn off, the bidirectional suppression diodes can quickly discharge the gate charge, accelerating the turn-off process and reducing turn-off losses.

[0045] Gate discharge resistors (R11, R15): Connected in parallel between the gate and source of the MOSFET, they are used to quickly discharge residual gate charge when the drive signal is disconnected, ensuring reliable turn-off of the MOSFET and avoiding turn-off delay due to residual gate charge.

[0046] C15, C16, together with R12, R16, form an RC snubber network to absorb high-frequency voltage spikes at the drain of the MOSFET (such as dv / dt noise during switching). R12 and R16 limit the charging and discharging current of the RC network to prevent the capacitor from generating excessive current and damaging the component when absorbing voltage spikes.

[0047] The upper and lower bridge arms of the power switching unit are equipped with multiple protection circuits consisting of gate resistors, Zener diodes, TVS diodes and capacitors. These circuits can effectively suppress voltage spikes during the switching process, absorb reverse recovery charges, clamp the gate voltage, protect the MOSFET from breakdown or false triggering, and extend the service life of the power devices.

[0048] Figure 4 This is a schematic flowchart illustrating a driving method for high-power devices based on a half-bridge topology provided by the present invention. Wherein, Figure 4 The executing entity can be a drive system based on a half-bridge topology high-power device. Depending on different requirements, the order of steps in this flowchart can be changed, and some steps can be omitted.

[0049] like Figure 4 As shown, the method includes: S1. The control unit collects the real-time operating parameters of the system where the high-power circuit is located. The real-time operating parameters include at least the operating voltage, operating current, device temperature and load status of the high-power circuit. Based on the collected real-time operating parameters, the control unit calculates the optimal dead time to adapt to the current operating conditions through a preset algorithm, and generates the corresponding PWM control signal according to the optimal dead time. The PWM control signal includes the upper bridge arm PWM signal used to drive the upper bridge arm switch in the power switching unit and the lower bridge arm PWM signal used to drive the lower bridge arm switch. S2. The PWM control signal is transmitted to the isolation drive unit, and the signal is isolated by electrical isolation to block the ground noise propagation path between the control side and the power side. S3. The electrically isolated PWM signal is transmitted to the power switching unit to drive the upper and lower bridge arm power switching transistors, which adopt a half-bridge topology, to alternately turn on and off, thereby completing the power conversion and driving external devices.

[0050] To facilitate understanding of the present invention, the following description further illustrates the driving method based on a half-bridge topology high-power device, using the principle of the driving method based on a half-bridge topology high-power device and the process of driving external devices based on a half-bridge topology high-power device in the embodiments.

[0051] First, step S1 includes: S11. The control unit collects the operating voltage of the high-power circuit in real time through voltage sensors, current sensors, temperature sensors, and load detection circuits. Operating current Device temperature and load status And perform preliminary filtering on the collected raw data; S12. Normalize the filtered parameters, converting them to per-unit or percentage forms. Specifically, this includes: normalizing the operating voltage... Divide by rated voltage Obtain the normalized voltage , will the operating current Divide by the rated current Obtain the normalized current To control the temperature of the device Divide by the pre-stored maximum allowable temperature of the device Obtain the normalized temperature Load status Divide by maximum load Obtain normalized load ; S13. Substitute the normalized parameters into the dead time calculation formula to calculate the optimal dead time; the calculation formula is: ; in, These are weighting coefficients used to reflect the degree of influence of each parameter on the dead time; S14. Based on the calculated optimal dead time Generate the upper bridge arm PWM signal and the lower bridge arm PWM signal, and control the time interval between the two signals to be equal to... This is to avoid short circuits between the upper and lower bridge arms.

[0052] This invention collects real-time parameters such as operating voltage, current, device temperature, and load status through a control unit. After normalization processing, these parameters are input into a weighted algorithm to calculate the optimal dead time, and a PWM control signal is generated accordingly, completely abandoning the traditional fixed dead time design. This dynamic adjustment mechanism can accurately adapt to different operating conditions: when the load increases, voltage fluctuates, or temperature rises, it automatically optimizes the dead time to avoid shoot-through short circuits in the upper and lower bridge arm switches of the half-bridge, significantly reducing the risk of short-circuit faults. At the same time, it reduces switching losses caused by improper dead time settings, extends the service life of core components such as power MOSFETs, and ensures long-term stable operation of the system.

[0053] The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, which, when executed, may include some or all of the steps provided in the embodiments of the present invention. The storage medium may be a magnetic disk, an optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0054] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium such as a USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, or other media capable of storing program code. It includes several instructions to cause a computer terminal (which may be a personal computer, server, or a second terminal, network terminal, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0055] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

[0056] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the present invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should also be covered within the protection scope of the present invention.

Claims

1. A driving system based on a half-bridge topology high-power device, characterized in that, include: The control unit is used to generate PWM control signals and dynamically adjust the dead time of the power switch; An isolation drive unit, connected to the control unit, is used to electrically isolate the PWM signals generated by the control unit; The power switching unit, connected to the isolation drive unit, adopts a half-bridge topology and is used to convert electrical energy based on the electrically isolated PWM signal to drive external devices.

2. The driving system based on a half-bridge topology high-power device according to claim 1, characterized in that, The isolation drive unit includes an isolation drive circuit and a power isolation circuit, with the power isolation circuit providing isolated power to the isolation drive circuit.

3. The driving system based on a half-bridge topology high-power device according to claim 2, characterized in that, The isolation drive circuit includes a PWM interface J1, a resistor R1, an isolation drive chip U1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a capacitor C3, a resistor R4, a capacitor C4, a capacitor C5, a resistor R5, a resistor R6, a Zener diode D1, a capacitor C6, a resistor R7, a resistor R8, a Zener diode D2, a connector H1, and an output interface J2. The first terminals of resistors R1, R2, and R3 are all connected to the PWM signal output terminal of the control unit via PWM interface J1. The second terminal of resistor R1 is connected to the first pin of isolation driver chip U1 and grounded through capacitor C1. The second terminal of resistor R2 is connected to the second pin of isolation driver chip U1 and grounded through capacitor C2. The second terminal of resistor R3 is connected to the third pin of isolation driver chip U1 and grounded through capacitor C3. The fourth pin of isolation driver chip U1 is connected to the first terminal of resistor R4 and the first terminal of capacitor C4. The second terminal of resistor R4 is connected to the fifth pin of isolation driver chip U1, and the second terminal of capacitor C4 is grounded. The sixth pin of isolation driver chip U1 is connected to a 12V power supply and grounded through capacitor C5. The seventh pin of the isolation driver chip U1 is connected to the first terminals of resistors R5 and R6. The second terminal of resistor R6 is connected to the negative terminal of Zener diode D1. The positive terminal of Zener diode D1 and the second terminal of resistor R5 are both connected to the first pin of connector H1 and the first pin of output interface J2. The eighth pin of the isolation driver chip U1 is connected to a 12V power supply and grounded through capacitor C6. The ninth pin of the isolation driver chip U1 is connected to the first terminals of resistors R7 and R8. The second terminal of resistor R8 is connected to the negative terminal of Zener diode D2. The positive terminal of Zener diode D2 and the second terminal of resistor R7 are both connected to the second pin of connector H1 and the second pin of output interface J2. The isolation driver circuit is connected to the power switch unit through output interface J2.

4. The driving system based on a half-bridge topology high-power device according to claim 3, characterized in that, The isolation driver chip U1 uses an isolated gate driver with the model number UCC21520DW.

5. The driving system based on a half-bridge topology high-power device according to claim 3, characterized in that, The power isolation circuit includes a first power isolation sub-circuit, a second power isolation sub-circuit, and a power interface J3. The first power isolation sub-circuit includes capacitors C7 and C8, a power isolation chip U2, capacitors C9 and C10, and the second power isolation sub-circuit includes capacitors C11 and C12, a power isolation chip U3, capacitors C13 and C14. The input pin of the power isolation chip U2 is connected to the 5V power supply pin of the power interface J3 and grounded through parallel capacitors C7 and C8. The output pin of the power isolation chip U2 is connected to the sixth pin of the isolation driver chip U1 and grounded through parallel capacitors C9 and C10. The input pin of the power isolation chip U3 is connected to the 5V power supply pin of the power interface J3 and grounded through parallel capacitors C11 and C12. The output pin of the power isolation chip U3 is connected to the eighth pin of the isolation driver chip U1 and grounded through parallel capacitors C13 and C14.

6. The driving system based on a half-bridge topology high-power device according to claim 3, characterized in that, The power switching unit includes an input interface circuit, an upper bridge arm switching circuit, a lower bridge arm switching circuit, and an output interface J4. The input terminals of the upper bridge arm switching circuit and the lower bridge arm switching circuit are both connected to the isolation drive circuit through the input interface circuit. The output terminals of the upper bridge arm switching circuit and the lower bridge arm switching circuit are both connected to external devices through the output interface J4.

7. The driving system based on a half-bridge topology high-power device according to claim 6, characterized in that, The upper bridge arm switching circuit includes resistor R9, resistor R10, Zener diode D3, upper bridge arm MOSFET Q1, bidirectional suppression diode TVS1, resistor R11, Zener diode D4, capacitor C15, and resistor R12. The first terminals of resistors R9 and R10 are both connected to the sixth pin of the isolation driver chip U1 through the input interface circuit. The second terminal of resistor R10 is connected to the negative terminal of Zener diode D3. The positive terminal of Zener diode D3, the second terminal of resistor R9, the first terminal of bidirectional suppressor diode TVS1, and the first terminal of resistor R11 are all connected to the gate of upper bridge arm MOSFET Q1. The second terminal of bidirectional suppressor diode TVS1, the second terminal of resistor R11, the source of upper bridge arm MOSFET Q1, the positive terminal of Zener diode D4, and the first terminal of resistor R12 are all grounded. The drain of upper bridge arm MOSFET Q1 is connected to the first pin of output interface J4, the negative terminal of Zener diode D4, and the first terminal of capacitor C15. The second terminal of capacitor C15 is connected to the second terminal of resistor R12.

8. The driving system based on a half-bridge topology high-power device according to claim 6, characterized in that, The lower bridge arm switching circuit includes resistor R13, resistor R14, Zener diode D5, lower bridge arm MOSFET Q2, bidirectional suppression diode TVS2, resistor R15, Zener diode D6, capacitor C16, and resistor R16. The first terminals of resistors R13 and R14 are both connected to the eighth pin of the isolation driver chip U1 through the input interface circuit. The second terminal of resistor R14 is connected to the negative terminal of Zener diode D5. The positive terminal of Zener diode D5, the second terminal of resistor R13, the first terminal of bidirectional suppressor diode TVS2, and the first terminal of resistor R15 are all connected to the gate of the upper bridge arm MOSFET Q2. The second terminal of bidirectional suppressor diode TVS2, the second terminal of resistor R15, the source of lower bridge arm MOSFET Q2, the positive terminal of Zener diode D6, and the first terminal of resistor R16 are all grounded. The drain of lower bridge arm MOSFET Q2 is connected to the second pin of output interface J4, the negative terminal of Zener diode D6, and the first terminal of capacitor C16. The second terminal of capacitor C16 is connected to the second terminal of resistor R16.

9. A driving method for high-power devices based on a half-bridge topology, characterized in that, include: S1. The control unit collects the real-time operating parameters of the system where the high-power circuit is located. The real-time operating parameters include at least the operating voltage, operating current, device temperature and load status of the high-power circuit. Based on the collected real-time operating parameters, the control unit calculates the optimal dead time to adapt to the current operating conditions through a preset algorithm, and generates the corresponding PWM control signal according to the optimal dead time. The PWM control signal includes the upper bridge arm PWM signal used to drive the upper bridge arm switch in the power switching unit and the lower bridge arm PWM signal used to drive the lower bridge arm switch. S2. The PWM control signal is transmitted to the isolation drive unit, and the signal is isolated by electrical isolation to block the ground noise propagation path between the control side and the power side. S3. The electrically isolated PWM signal is transmitted to the power switching unit to drive the upper and lower bridge arm power switching transistors, which adopt a half-bridge topology, to alternately turn on and off, thereby completing the power conversion and driving external devices.

10. The driving method for high-power devices based on a half-bridge topology according to claim 9, characterized in that, Step S1 includes: S11. The control unit collects the operating voltage of the high-power circuit in real time through voltage sensors, current sensors, temperature sensors, and load detection circuits. Operating current Device temperature and load status And perform preliminary filtering on the collected raw data; S12. Normalize the filtered parameters, converting them to per-unit or percentage forms. Specifically, this includes: normalizing the operating voltage... Divide by rated voltage Obtain the normalized voltage , will the operating current Divide by the rated current Obtain the normalized current To control the temperature of the device Divide by the pre-stored maximum allowable temperature of the device Normalized temperature Load status Divide by maximum load Obtain normalized load ; S13. Substitute the normalized parameters into the dead time calculation formula to calculate the optimal dead time; the calculation formula is: ； in, These are weighting coefficients used to reflect the degree of influence of each parameter on the dead time; S14. Based on the calculated optimal dead time Generate the upper bridge arm PWM signal and the lower bridge arm PWM signal, and control the time interval between the two signals to be equal to... This is to avoid short circuits between the upper and lower bridge arms.

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