Driving chip and power module

Abstract

The invention relates to the technical field of electronics, and discloses a driving chip and a power module, and the driving chip comprises a high-low side driving circuit, a PFC driving circuit and a protection circuit. The protection circuit is electrically connected with the high-low side driving circuit and the PFC driving circuit, so that the operation states of the two driving circuits can be monitored at the same time; secondly, when the protection circuit detects abnormal working conditions (such as overcurrent of the PFC driving circuit and undervoltage of the high-side and low-side driving circuits), protection control signals can be synchronously output to the two driving circuits through electrical connection, so that the problem that one driving circuit is not matched with the other driving circuit in a normal working state when the protection is triggered is solved; the working reliability of the driving chip and the whole power module is improved, and the fault risk caused by mismatching of the working states of the modules is reduced.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a driver chip and a power module. Background Technology

[0002] In the field of power electronics, driver chips, as the core components connecting control signals and power devices, are widely used in scenarios such as variable frequency home appliances and industrial drives. They need to simultaneously realize power conversion drive, power factor correction drive, and fault protection functions. However, in the existing technology, the functional modules of most driver chips are independent of each other, and the protection circuit can only perform simple overcurrent or undervoltage monitoring on a single module. The operating states of the high and low side drive circuits and the PFC drive circuit are prone to mismatch, which can lead to secondary faults such as false triggering of power devices and voltage overshoot, making it difficult to meet the high-efficiency and stable operating requirements of power modules. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to solve at least one of the technical problems mentioned above.

[0004] The solution to the technical problem of this invention is: A first aspect of the present invention provides a driver chip, comprising: The system includes a high-side and low-side drive circuit, a PFC drive circuit, and a protection circuit. The protection circuit is electrically connected to the high-side and low-side drive circuit and the PFC drive circuit. The high-side and low-side drive circuit converts external control signals into drive signals. The PFC drive circuit adjusts the gate drive signal of the PFC switching device according to external PFC control commands. The protection circuit monitors the high-side and low-side drive circuit and the PFC drive circuit, and triggers a protection action when an abnormal operating condition is detected.

[0005] The beneficial effects of the first aspect of the present invention are as follows: In the driver chip of the present invention, the protection circuit is electrically connected to the high- and low-side drive circuits and the PFC drive circuit, enabling it to simultaneously monitor the operating status of the two drive circuits; secondly, when the protection circuit detects abnormal operating conditions (such as overcurrent in the PFC drive circuit or undervoltage in the high- and low-side drive circuits), it can synchronously output protection control signals to the two drive circuits through electrical connection, avoiding the mismatch problem of one drive circuit triggering protection while the other is still working normally; the high- and low-side drive circuits are used to convert external control signals into drive signals required by the power conversion unit, and the PFC drive circuit is used to adjust the gate drive signal of the PFC switching device according to external instructions. Under the coordinated control of the protection circuit, the two achieve the unification of drive logic, ultimately improving the working reliability of the driver chip and the entire power module, and reducing the risk of failure caused by the mismatch of operating states between modules.

[0006] As some sub-solutions of the above technical solution, the high-low side driving circuit includes a Schmitt threshold circuit, a level conversion circuit, a dead-zone interlock circuit, a pulse circuit, an undervoltage detection circuit, a delay circuit, a gate circuit, and an output circuit. The output terminal of the Schmitt threshold circuit is connected to the input terminal of the level conversion circuit; the output terminal of the level conversion circuit is connected to the input terminal of the dead-zone interlock circuit; the output terminal of the dead-zone interlock circuit is connected to the input terminals of the pulse circuit and the delay circuit; the output terminal of the pulse circuit is connected to the input terminal of the undervoltage detection circuit; the output terminal of the delay circuit is connected to the first input terminal of the gate circuit; the second input terminal of the gate circuit is connected to the protection circuit; and the output terminals of the gate circuit and the undervoltage detection circuit are connected to the output circuit. The Schmitt threshold circuit is used to perform level shaping on the externally input control signal; the level conversion circuit is used to convert the low-voltage side control signal into a drive level adapted to the high-voltage side switching device; the dead-zone interlock circuit is used to prevent the high- and low-side switching devices of the same bridge arm from being turned on simultaneously; the pulse circuit is used to convert the continuous control signal into a pulse drive signal that conforms to the on / off characteristics of the switching device; the undervoltage detection circuit is used to control the on / off of the drive signal according to the supply voltage of the high- and low-side drive circuits; the delay circuit is used to adjust the delay of the drive signal after dead-zone interlock; the gate circuit is used to receive the delayed drive signal and the fault control signal of the protection circuit, and prevent the drive signal from being transmitted to the output circuit when the fault control signal is valid; the output circuit is used to amplify the pulse drive signal and output it to the external device.

[0007] As some sub-solutions of the above technical solution, the PFC driving circuit includes a multi-stage voltage delay driving circuit, an oscillation circuit, and a driving output circuit; the output terminal of the oscillation circuit is connected to the clock signal terminal of the multi-stage voltage delay driving circuit, the output terminal of the multi-stage voltage delay driving circuit is connected to the input terminal of the driving output circuit, and the protection terminal of the driving output circuit is connected to the protection circuit; the multi-stage voltage delay driving circuit is used to adjust the output voltage signal in stages according to the external PFC control command and the clock signal output by the oscillation circuit; the oscillation circuit is used to generate the clock signal; and the driving output circuit is used to amplify the voltage signal output by the multi-stage voltage delay driving circuit into a gate driving signal adapted to the PFC switching device.

[0008] As some sub-solutions of the above technical solution, the protection circuit includes an ITRIP overcurrent protection circuit, a PFC overcurrent protection circuit, a temperature detection protection circuit, an undervoltage protection circuit, a fault logic circuit, and an error reporting circuit. The input terminal of the fault logic circuit is connected to the output terminals of the ITRIP overcurrent protection circuit, the PFC overcurrent protection circuit, the temperature detection protection circuit, and the undervoltage protection circuit. The output terminal of the fault logic circuit is connected to the input terminal of the error reporting circuit, the second input terminal of the gate circuit, and the protection terminal of the drive output circuit. The ITRIP overcurrent protection circuit monitors the operating current of the power module and outputs an overcurrent signal to the fault logic circuit when the power module experiences an overcurrent. The circuit includes: a PFC overcurrent protection circuit for monitoring the operating current of the PFC device and outputting a PFC overcurrent signal to the fault logic circuit when the PFC device experiences overcurrent; a temperature detection protection circuit for collecting the temperature of the driver chip and external associated power devices and outputting an overtemperature signal to the fault logic circuit when the temperature exceeds a preset overheat threshold; an undervoltage protection circuit for monitoring the power supply voltage of the driver chip and outputting an undervoltage signal to the fault logic circuit when the voltage falls below a preset undervoltage threshold; a fault logic circuit for receiving fault signals output by each protection circuit and generating corresponding control signals; and an error reporting circuit for receiving the control signals from the fault logic circuit and converting them into externally identifiable fault indication signals.

[0009] A second aspect of the present invention provides a power module, the power module including any of the driving chips described above; the power module further includes a power conversion unit, a PFC unit, a rectifier unit, and a bootstrap unit; the high-low side driving circuit is connected to the power conversion unit and the bootstrap unit, the PFC driving circuit is connected to the PFC unit; the rectifier unit is connected to the PFC unit, and the PFC unit is connected to the power conversion unit; the power conversion unit is used to convert the DC power output by the PFC unit into AC current adapted to the external load; the PFC unit is used to perform power factor correction on the DC power output by the rectifier unit; the rectifier unit is used to convert externally input AC power into DC power; the bootstrap unit is used to provide a stable floating ground power supply for the high-low side driving circuit of the driving chip.

[0010] As some sub-solutions of the above technical solution, the power conversion unit includes multiple sets of bridge arm switching assemblies; each set of bridge arm switching assemblies includes at least two power switching devices and a freewheeling diode connected in reverse parallel with the power switching devices; the gate of the power switching device is connected to the output terminal of the high-low side drive circuit, and the series node of two power switching devices in the same set of bridge arm switching assemblies serves as the AC output terminal of the power conversion unit and is connected to the external load; the power switching devices are used to alternately turn on and off under the control of the high-low side drive circuit of the drive chip to realize the conversion of DC to AC; the freewheeling diode is used to provide a freewheeling path for the inductive current of the external load when the power switching device is turned off.

[0011] As some sub-solutions of the above technical solution, the PFC unit includes a PFC power switch device, a rectifier diode, and an energy storage element; the gate of the PFC power switch device is connected to the PFC drive circuit, the drain of the PFC power switch device is connected to the rectifier unit and the anode of the rectifier diode, the cathode of the rectifier diode is connected to one end of the energy storage element and the power conversion unit, and the other end of the energy storage element is connected to the source of the PFC power switch device and ground; the PFC power switch device is used to switch on and off at high frequency under the control of the PFC drive circuit to adjust the current waveform of the PFC unit; the rectifier diode is used to prevent reverse current flow; and the energy storage element is used to stabilize the output voltage of the PFC unit.

[0012] As some sub-solutions of the above technical solution, the rectifier unit includes four rectifier diodes connected in a bridge topology; the AC input terminal of the rectifier unit is connected to an external AC power supply, and the DC output terminal of the rectifier unit is connected to the PFC unit; the rectifier unit is used to convert externally input AC power into DC power.

[0013] The power module according to the second aspect of the present invention, since it includes the driver chip of the above-described technical solution, also has corresponding beneficial effects. Attached Figure Description

[0014] Figure 1 This is a circuit schematic diagram of the driver chip provided by the present invention; Figure 2 This is a circuit schematic diagram of the power module provided by the present invention; Figure 3 This is a schematic diagram of the packaging structure provided by the present invention; The reference numerals in the attached diagram are as follows: 0202-Schmidt threshold circuit, 0203-Level conversion circuit, 0204-Dead-time interlock circuit, 0205-Pulse circuit, 0206-Undervoltage detection circuit, 0207-Output circuit, 0208-Delay circuit, 0209-Gate circuit, 0211-ITRIP overcurrent protection circuit, 0212-PFC overcurrent protection circuit, 0213-Temperature detection protection circuit, 0214-Undervoltage protection circuit, 0215-Error reporting. Circuit, 0216-Fault logic circuit, 0217-Multi-level voltage delay drive circuit, 0218-Oscillation circuit, 0219-Drive output circuit, 0101-Driver chip, 0102-Power conversion unit, 0103-PFC unit, 0104-Rectifier unit, 23-Circuit aluminum substrate, 24-Insulating layer, 25-Circuit wiring, 26-Texture, 27-Circuit element, 28-Metal wire, 29-Pin, 30-Power module, 31-Sealing resin. Detailed Implementation

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments have been briefly explained above. Obviously, the described drawings are only a part of the embodiments of the present invention, and not all of them. Those skilled in the art can obtain other design schemes and drawings based on these drawings without creative effort.

[0016] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Furthermore, all connections / linkages mentioned herein do not simply refer to direct connection of components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this invention can be combined interactively without contradicting each other.

[0017] Reference Figures 1 to 3 The embodiments of the present invention are described below; A first aspect of the present invention provides a driver chip 0101, comprising: The system includes a high-side and low-side drive circuit, a PFC drive circuit, and a protection circuit. The protection circuit is electrically connected to the high-side and low-side drive circuit and the PFC drive circuit. The high-side and low-side drive circuit converts external control signals into drive signals. The PFC drive circuit adjusts the gate drive signal of the PFC switching device according to external PFC control commands. The protection circuit monitors the high-side and low-side drive circuit and the PFC drive circuit, and triggers a protection action when an abnormal operating condition is detected.

[0018] In the first aspect of the present invention, the protection circuit is electrically connected to the high- and low-side drive circuits and the PFC drive circuit, enabling it to simultaneously monitor the operating status of the two drive circuits. Secondly, when the protection circuit detects an abnormal operating condition (such as overcurrent in the PFC drive circuit or undervoltage in the high- and low-side drive circuits), it can synchronously output protection control signals to both drive circuits through the electrical connection, avoiding the mismatch problem where one drive circuit has triggered protection while the other is still operating normally. The high- and low-side drive circuits are used to convert external control signals into drive signals required by the power conversion unit 0102, and the PFC drive circuit is used to adjust the gate drive signal of the PFC switching device according to external instructions. Under the coordinated control of the protection circuit, the two achieve unified drive logic, ultimately improving the operational reliability of the drive chip 0101 and the entire power module 30, and reducing the risk of failure caused by mismatch in the operating states between modules.

[0019] Specifically, the high / low side driving circuit includes a Schmitt threshold circuit 0202, a level conversion circuit 0203, a dead-zone interlock circuit 0204, a pulse circuit 0205, an undervoltage detection circuit 0206, a delay circuit 0208, a gate circuit 0209, and an output circuit 0207. The output terminal of the Schmitt threshold circuit 0202 is connected to the input terminal of the level conversion circuit 0203. The output terminal of the level conversion circuit 0203 is connected to the input terminal of the dead-zone interlock circuit 0204. The output terminal of the dead-zone interlock circuit 0204 is connected to the input terminals of the pulse circuit 0205 and the delay circuit 0208. The output terminal of the pulse circuit 0205 is connected to the input terminal of the undervoltage detection circuit 0206. The output terminal of the delay circuit 0208 is connected to the first input terminal of the gate circuit 0209. The second input terminal of the gate circuit 0209 is connected to the protection circuit. The output terminal of the gate circuit 0209 is connected to the undervoltage detection circuit 0207. The output terminal of circuit 0206 is connected to the output circuit 0207; the Schmitt threshold circuit 0202 is used to perform level shaping on the externally input control signal; the level conversion circuit 0203 is used to convert the low-voltage side control signal into a drive level adapted to the high-voltage side switching device; the dead-zone interlock circuit 0204 is used to prevent the high and low side switching devices of the same bridge arm from being turned on simultaneously; the pulse circuit 0205 is used to convert the continuous control signal into a pulse drive signal that conforms to the switching characteristics of the switching device; the undervoltage detection circuit 0206 is used to control the on / off state of the drive signal according to the power supply voltage of the high and low side drive circuits; the delay circuit 0208 is used to adjust the delay of the drive signal after dead-zone interlock; the gate circuit 0209 is used to receive the delayed drive signal and the fault control signal of the protection circuit, and prevents the drive signal from being transmitted to the output circuit 0207 when the fault control signal is valid; the output circuit 0207 is used to amplify the pulse drive signal and output it to an external device. In this embodiment, the three high-side drive channels and three low-side drive channels of the high-side and low-side drive circuits all adopt the same circuit topology. Taking one high-side drive channel (corresponding to driving the high-side IGBT2 of the 0102 bridge arm) and one low-side drive channel (corresponding to driving the low-side IGBT3 of the A bridge arm) as an example, the connection method of each circuit is as follows: The input of the Schmitt threshold circuit 0202 is connected to the low-voltage PWM control signal output by the external MCU, and its output is connected to the input of the level conversion circuit 0203 through metal wiring to ensure lossless transmission of the shaped signal. The output of the level conversion circuit 0203 is soldered to the high-side signal input of the dead-zone interlock circuit 0204. At the same time, the output of the level conversion circuit 0203 of the low-side drive channel is also connected to the low-side signal input of the same dead-zone interlock circuit 0204, so as to realize the centralized interlocking of the high and low side signals of the same bridge arm. The high-side signal output of the dead-zone interlock circuit 0204 is divided into two paths: one path is connected to the input of the pulse circuit 0205, and the other path is connected to the input of the delay circuit 0208; the low-side signal output is only connected to the other input of the delay circuit 0208 to adapt to the timing difference between high and low-side drives. The output of the pulse circuit 0205 is connected to the signal input of the undervoltage detection circuit 0206. The power sampling terminal of the undervoltage detection circuit 0206 is simultaneously connected to the bootstrap power supply terminal (VB1) of the high and low side drive circuit and the reference ground (VS1) to monitor the bootstrap voltage in real time. The output of the delay circuit 0208 is connected to the first input (signal terminal) of the gate circuit 0209. The second input (enable terminal) of the gate circuit 0209 is connected to the output of the fault logic circuit 0216 of the protection circuit through the metal line 28 to receive the fault control signal (active high). The output of gate circuit 0209 and the output of undervoltage detection circuit 0206 are connected to the signal aggregation terminal of output circuit 0207. The power output terminal of output circuit 0207 is directly connected to the gate of external IGBT2 through metal wire 28 to provide it with drive current. The working principles of each circuit are as follows: Schmitt threshold circuit 0202: When the external HIN1 signal experiences level jitter due to electromagnetic interference, the Schmitt threshold circuit 0202 shapes the signal using preset high and low thresholds: eliminating glitches at the signal edges, ensuring that the control signals received by subsequent circuits are free from noise interference, and preventing IGBTs from being falsely triggered due to signal jitter.

[0020] Level conversion circuit 0203: The low-voltage PWM signal output by the external MCU cannot directly drive the IGBT. The level conversion circuit 0203 converts the low-voltage signal into a high-voltage drive level through an internally integrated charge pump circuit. Its power supply is connected to the VDD power supply of the driver chip 0101. Through capacitor energy storage and alternating conduction of the switching transistor, the logic state of the low-voltage signal is mapped to a high-voltage level. For example, when the input is 5V, the output is 15V (corresponding to the IGBT turn-on instruction), and when the input is 0V, the output is 0V (corresponding to the IGBT turn-off instruction), thus realizing the adaptation between low-voltage control and high-voltage drive.

[0021] Dead-time interlock circuit 0204: If the high-side IGBT and low-side IGBT of the same bridge arm are turned on simultaneously, it will cause a direct short circuit between VCC and ground. Therefore, the dead-time interlock circuit 0204 forces the interlock through hardware logic. When the high-side drive signal is high, the NAND gate inside the circuit immediately blocks the output of the low-side signal, ensuring that the low-side drive signal needs to be delayed before it becomes high. Conversely, when the low-side signal is high, the high-side signal also needs to be delayed before it can be output. This delay time is achieved through the RC delay network inside the dead-time interlock circuit 0204, eliminating the risk of bridge arm short circuit from the hardware level. Pulse circuit 0205: Continuous high-level drive signals can cause excessive charge accumulation on the IGBT gate, prolonging the turn-off time and increasing losses. Pulse circuit 0205 converts the continuous high-level signal after dead-time interlocking into a narrow pulse signal. When the IGBT needs to be turned on, it outputs a narrow pulse signal to quickly charge the IGBT gate to the threshold voltage. After the pulse ends, it maintains the voltage, which ensures stable IGBT conduction and reduces gate power consumption. Undervoltage detection circuit 0206: The undervoltage detection circuit 0206 samples the voltage between the bootstrap power supply terminals VB1 and VS1 in real time through the voltage divider resistor. When the bootstrap capacitor discharges and the voltage drops below the minimum voltage for reliable IGBT turn-on, the comparator inside the circuit outputs a low level, cutting off the drive signal output by the pulse circuit 0205, preventing the IGBT from being incompletely turned on due to insufficient gate voltage. Delay circuit 0208: The signal transmission paths of the high-side and low-side drive circuits are different (the high-side requires a bootstrap circuit, while the low-side is directly grounded), causing the low-side drive signal to be faster than the high-side signal. The delay circuit 0208 internally uses 5 inverters connected in series to form an RC delay network, which adds an extra delay to the low-side drive signal, so that the edges of the high-side and low-side signals on the same bridge arm are completely aligned. This delay can also be adjusted by an external resistor according to the IGBT model to adapt to power devices with different switching speeds. Gate 0209: Gate 0209 adopts a two-input AND gate structure. Its first input receives the delayed normal drive signal, and its second input receives the fault control signal from the protection circuit (high level during normal operation, low level during fault). When the protection circuit detects abnormalities such as overcurrent or overtemperature, the fault control signal becomes low, and the AND gate output immediately becomes low, cutting off the drive signal transmission. Even if the delayed drive signal is still high, it cannot trigger the output circuit 0207 through gate 0209 to achieve forced shutdown under fault conditions. Output circuit 0207: The IGBT gate has a parasitic capacitance (approximately 1nF), requiring sufficient drive current for rapid charging and discharging. Output circuit 0207 employs a complementary symmetrical DMOS transistor structure. When receiving a high-level signal from gate circuit 0209 or undervoltage detection circuit 0206, the upper DMOS transistor turns on, outputting a forward current to charge the IGBT gate. When receiving a low-level signal, the lower DMOS transistor turns on, providing an inverted current to accelerate gate discharge, thereby ensuring that the IGBT switching time is controlled within 100ns and reducing switching losses. One possible operating mode for the specific coordination of the circuits in the high- and low-side drive circuits is as follows: The external MCU outputs a high level HIN1, which is shaped into a jitter-free low-voltage signal by the Schmitt threshold circuit 0202. The level conversion circuit 0203 converts the low-voltage signal into a high-voltage signal and inputs it to the dead-zone interlock circuit 0204. The dead-zone interlock circuit 0204 detects that the low-side signal is low and is not blocked, so it outputs the high-voltage signal in two paths to the pulse circuit 0205 and the delay circuit 0208. The pulse circuit 0205 generates a pulse signal corresponding to the high-voltage signal and inputs it to the undervoltage detection circuit 0206. The undervoltage detection circuit 0206 allows the pulse signal to pass. The delay circuit 0208 does not have an additional delay for the signal (no compensation is needed on the high side) and inputs it to the first input terminal of the gate circuit 0209. The protection circuit is fault-free, and the second input terminal is high. The gate circuit 0209 outputs a pulse signal. The upper DMOS transistor of the output circuit 0207 is turned on, outputting a positive current to charge the gate of IGBT2. IGBT2 is reliably turned on, completing the entire driving process.

[0022] Specifically, the PFC driving circuit includes a multi-stage voltage delay driving circuit 0217, an oscillation circuit 0218, and a driving output circuit 0219. The output terminal of the oscillation circuit 0218 is connected to the clock signal terminal of the multi-stage voltage delay driving circuit 0217, the output terminal of the multi-stage voltage delay driving circuit 0217 is connected to the input terminal of the driving output circuit 0219, and the protection terminal of the driving output circuit 0219 is connected to the protection circuit. The multi-stage voltage delay driving circuit 0217 is used to adjust the output voltage signal in stages according to the external PFC control command and the clock signal output by the oscillation circuit 0218. The oscillation circuit 0218 is used to generate the clock signal. The driving output circuit 0219 is used to amplify the voltage signal output by the multi-stage voltage delay driving circuit 0217 into a gate driving signal adapted to the PFC switching device.

[0023] In this embodiment, the connection method of each circuit inside the PFC driver circuit is as follows: The clock signal output terminal of the oscillation circuit 0218 is directly soldered to the clock signal terminal of the multi-stage voltage delay drive circuit 0217 through metal wiring, using differential signal transmission to avoid interference from power supply noise; the power supply terminal of the oscillation circuit 0218 is connected to the VDD power supply (15V) of the driver chip 0101. The two voltage output terminals (V_G1, V_E1) of the multi-stage voltage delay drive circuit 0217 are connected to the gate drive input terminal and emitter drive input terminal of the drive output circuit 0219, respectively. Meanwhile, the parameter configuration terminals (TON_1_H, TON_1_L, VON_REF, etc.) of this circuit are led out to the outside of the circuit through pin 29. The protection terminal (FLT_IN) of the drive output circuit 0219 is connected to the output terminal of the fault logic circuit 0216 of the protection circuit through the metal line 28, and receives a low-level active fault shutdown signal; its power output terminal is divided into two paths, one path (PFCG) is connected to the gate of the PFC device, and the other path (PFCE) is connected to the emitter of the power transistor in the power module 30, forming a complete drive loop.

[0024] The working principle of each circuit inside the PFC driver circuit is as follows: The oscillation circuit 0218 adopts a ring oscillator topology to generate a 10MHz high-frequency clock signal, providing a time reference for the multi-stage voltage delay drive circuit 0217.

[0025] The multi-stage voltage delay drive circuit 0217 is the core of the PFC drive circuit. It receives external PFC control commands and clock signals from the oscillation circuit 0218 to regulate the voltage during the switching process of the power transistor. The voltage parameters are input externally through the TON_1_H (high-order time of the first turn-on phase) and TON_1_L (low-order time of the first turn-on phase) ports. The internal ADC module converts the voltage parameters into digital time instructions and, combined with a 10MHz clock signal, calculates the delay time of the first turn-on phase (IC unchanged phase). Similarly, the delay of the second turn-on phase (di / dt phase) is configured through TON_2_H and TON_2_L, the delay of the first turn-off phase (IC unchanged phase) is configured through TOFF_1_H and TOFF_1_L, and the delay of the second turn-off phase (di / dt phase) is configured through TOFF_2_H and TOFF_2_L. The reference voltage for the turn-on di / dt phase is input through the VON_REF port, and the reference voltage for the turn-off di / dt phase is input through the VOFF_REF port. When the PFCIN high-level command is received, the multi-stage voltage delay drive circuit 0217 first enters the first turn-on stage, outputting high voltage to drive the output circuit 0219 to accelerate the charging of the IGBT1 gate and shorten the turn-on delay; after the delay time is reached, it switches to the second turn-on stage, reducing the output voltage to the turn-on di / dt stage reference voltage, thereby suppressing the IC rise rate (di / dt) by reducing the gate drive voltage and preventing current spikes from exceeding the rated current of IGBT1; When PFCIN goes low, the circuit first enters the first turn-off stage, outputting a negative voltage to accelerate the release of gate charge of IGBT1 and shorten the turn-off time. After the delay is reached, it switches to the second turn-off stage, switching the output voltage to the reference voltage of the turn-off di / dt stage, and suppressing the voltage overshoot (du / dt) when IGBT1 is turned off by negative voltage clamping.

[0026] The drive output circuit 0219 adopts a complementary symmetrical DMOS power transistor structure. Its core function is to amplify the voltage signal output by the multi-stage voltage delay drive circuit 0217 into a drive current that is compatible with IGBT1, while responding to the fault signal of the protection circuit.

[0027] The coordination between the PFC drive circuit and the protection circuit: When the protection circuit detects PFC overcurrent (PFCTRIP signal is valid), overtemperature (temperature detection protection circuit 0213 output signal), or undervoltage (undervoltage protection circuit 0214 output signal), the fault logic circuit 0216 outputs a low-level signal to the protection terminal (FLT_IN) of the drive output circuit 0219. The circuit immediately turns off the DMOS transistor, cuts off the gate drive signal, and pulls the gate of IGBT1 to ground potential (0V), forcing IGBT1 to turn off, thus preventing the device from burning out due to the continued fault.

[0028] Specifically, the protection circuit includes an ITRIIP overcurrent protection circuit 0211, a PFC overcurrent protection circuit 0212, a temperature detection protection circuit 0213, an undervoltage protection circuit 0214, a fault logic circuit 0216, and an error reporting circuit 0215. The input terminal of the fault logic circuit 0216 is connected to the output terminals of the ITRIIP overcurrent protection circuit 0211, the PFC overcurrent protection circuit 0212, the temperature detection protection circuit 0213, and the undervoltage protection circuit 0214. The output terminal of the fault logic circuit 0216 is connected to the input terminal of the error reporting circuit 0215, the second input terminal of the gate circuit 0209, and the protection terminal of the drive output circuit 0219. The ITRIIP overcurrent protection circuit 0211 monitors the operating current of the power module 30 and outputs an overcurrent signal to the relevant circuit when the power module 30 experiences an overcurrent. The fault logic circuit 0216 is described above; the PFC overcurrent protection circuit 0212 is used to monitor the operating current of the PFC device and output a PFC overcurrent signal to the fault logic circuit 0216 when the PFC device is overcurrent; the temperature detection protection circuit 0213 is used to collect the temperature of the driver chip 0101 and external associated power devices, and output an overtemperature signal to the fault logic circuit 0216 when the temperature is higher than a preset overheat threshold; the undervoltage protection circuit 0214 is used to monitor the power supply voltage of the driver chip 0101 and output an undervoltage signal to the fault logic circuit 0216 when the voltage is lower than a preset undervoltage threshold; the fault logic circuit 0216 is used to receive the fault signals output by each protection circuit and generate corresponding control signals; the error reporting circuit 0215 is used to receive the control signals of the fault logic circuit 0216 and convert them into externally identifiable fault indication signals.

[0029] In this embodiment, the ITRIIP overcurrent protection circuit 0211 is used to monitor the operating current of the power conversion unit 0102 (such as IGBT2-IGBT7); by connecting a sampling resistor in series between the source of the low-side IGBT (such as IGBT3, IGBT5, IGBT7) of the power conversion unit 0102 and ground, the voltage signal across the sampling resistor is connected to the circuit input terminal through a differential amplifier; the ITRIIP overcurrent protection circuit 0211 (0211) has a built-in comparator and a preset overcurrent threshold voltage. When the sampled voltage is greater than the overcurrent threshold voltage, the comparator outputs a high-level overcurrent signal; the overcurrent signal is transmitted to the fault logic circuit 0216 after Schmitt triggering; The PFC overcurrent protection circuit 0212 is used to monitor the operating current of IGBT1. It adopts a similar architecture to the ITRIIP overcurrent protection circuit 0211, but is adapted to the high-frequency switching characteristics of the PFC unit 0103. By connecting a sampling resistor in series between the emitter of IGBT1 and ground, the sampled voltage is filtered by a high-frequency filter capacitor (1nF) to remove switching noise before being input to the circuit. The PFC overcurrent protection circuit 0212 has a built-in comparator and a preset PFC overcurrent threshold voltage. When the sampled voltage is greater than the PFC overcurrent threshold voltage, a high-level PFC overcurrent signal is output to the fault logic circuit 0216. The temperature detection and protection circuit 0213 has a built-in temperature sensor that is combined with an external sampling point to achieve comprehensive temperature measurement of the driver chip 0101 and power devices. The circuit has two built-in PN junction temperature sensors, one of which is in close contact with the core of the driver chip 0101 (monitoring the chip junction temperature), and the other is in contact with the heat dissipation surface of the IGBT1 through a metal heat-conducting sheet (monitoring the temperature of the power devices). The temperature detection and protection circuit 0213 has a built-in comparator and a preset overheat threshold (corresponding to the sensor threshold voltage). When the output voltage of any sensor is less than the threshold voltage, the circuit outputs a high-level overheat signal. The undervoltage protection circuit 0214 collects the main power supply voltage (VDD), high-side drive bootstrap voltage (VB1-VB3, 15V), and PFC drive power supply voltage (VCC1) of the driver chip 0101 through voltage divider resistors. The undervoltage protection circuit 0214 has a built-in comparator and presets the undervoltage threshold for each voltage. When any sampled voltage is less than the undervoltage threshold, the circuit outputs a high-level undervoltage signal. The fault logic circuit 0216 adopts an OR gate logic and timing control architecture, which connects four fault signals—ITRIP overcurrent, PFCTRIP overcurrent, overtemperature, and undervoltage—to the OR gate. As long as any of the signals is high, the protection action is triggered. The fault logic circuit 0216 generates three output signals: a low-level shutdown signal is output to gate circuit 0209 to cut off the power conversion unit 0102 drive; a low-level shutdown signal is output to PFC drive output circuit 0219 to cut off IGBT1 drive; and a high-level trigger signal is output to error reporting circuit 0215. The error reporting circuit 0215 is used to convert the internal signal of the fault logic circuit 0216 into an externally recognizable standard signal. It adopts an open-drain NMOS transistor structure. When it receives a high-level trigger signal from the fault logic circuit 0216, the NMOS transistor is turned on and the FLT pin 29 outputs a low level (fault state). When there is no fault, the NMOS transistor is turned off and the FLT pin 29 outputs a high level through an external pull-up resistor (normal state).

[0030] A second aspect of the present invention provides a power module 30, the power module 30 including any of the driving chips 0101 described above; the power module 30 further includes a power conversion unit 0102, a PFC unit 0103, a rectification unit 0104, and a bootstrap unit; the high-low side driving circuit is connected to the power conversion unit 0102 and the bootstrap unit, the PFC driving circuit is connected to the PFC unit 0103; the rectification unit 0104 is connected to the PFC unit 0103, and the PFC unit 0103 is connected to the power conversion unit 0102; the power conversion unit 0102 is used to convert the DC power output by the PFC unit 0103 into AC current adapted to the external load; the PFC unit 0103 is used to perform power factor correction on the DC power output by the rectification unit 0104; the rectification unit 0104 is used to convert externally input AC power into DC power; the bootstrap unit is used to provide a stable floating ground power supply for the high-low side driving circuit of the driving chip 0101.

[0031] Specifically, the power conversion unit 0102 includes multiple sets of bridge arm switching assemblies; each set of bridge arm switching assemblies includes at least two power switching devices and a freewheeling diode connected in reverse parallel with the power switching devices; the gate of the power switching device is connected to the output terminal of the high-low side drive circuit, and the series node of two power switching devices in the same set of bridge arm switching assemblies serves as the AC output terminal of the power conversion unit 0102 and is connected to an external load; the power switching devices are used to alternately turn on and off under the control of the high-low side drive circuit of the drive chip 0101 to realize the conversion of DC to AC; the freewheeling diode is used to provide a freewheeling path for the inductive current of the external load when the power switching devices are turned off.

[0032] Specifically, the PFC unit 0103 includes a PFC power switch, a rectifier diode, and an energy storage element; the gate of the PFC power switch is connected to the PFC drive circuit, the drain of the PFC power switch is connected to the rectifier unit 0104 and the anode of the rectifier diode, the cathode of the rectifier diode is connected to one end of the energy storage element and the power conversion unit 0102, and the other end of the energy storage element is connected to the source of the PFC power switch and ground; the PFC power switch is used to switch on and off at high frequency under the control of the PFC drive circuit to adjust the current waveform of the PFC unit 0103; the rectifier diode is used to prevent reverse current flow; and the energy storage element is used to stabilize the output voltage of the PFC unit 0103.

[0033] Specifically, the rectifier unit 0104 includes four rectifier diodes connected in a bridge topology; the AC input terminal of the rectifier unit 0104 is connected to an external AC power supply, and the DC output terminal of the rectifier unit 0104 is connected to the PFC unit 0103; the rectifier unit 0104 is used to convert externally input AC power into DC power.

[0034] This embodiment combines Figure 2 The overall architecture, unit connections, and working logic of the power module 30 are explained in detail. The power module 30 uses the driver chip 0101 as the control core and integrates power conversion unit 0102 (IGBT2-IGBT7), PFC unit 0103 (IGBT1, FRD1, FRD2), rectifier unit 0104 (D1-D4) and bootstrap unit 0105. The positive terminal of the DC output of rectifier unit 0104 (DBP, Figure 2 Power module 30 (pin 46) is connected to the anode of FRD1 of PFC unit 0103 via copper foil wiring, and the negative terminal (DB N) is connected to the anode of FRD1. Figure 2 The power module 30 pin 45) and the source of IGBT1 (-VCC) Figure 2 Connect to pin 20 of power module 30 to form a power supply link of "AC, rectification, PFC"; The energy storage capacitor of PFC unit 0103 is connected to the cathode of FRD2, and the output terminal (VCC2, Figure 2 Pin 17 of power module 30 is connected to the drain of IGBT2, IGBT4 and IGBT6 of power conversion unit 0102 through a wide copper foil to provide a stable DC power supply for power conversion. The HO1-HO3 ports of the driver chip 0101 (0101) are connected to the gates of IGBT2, IGBT4, and IGBT6, the LO1-LO3 ports are connected to the gates of IGBT3, IGBT5, and IGBT7, and the PFCG port is connected to the gate of IGBT1 to realize the transmission of drive signals. The capacitors (0105) of the bootstrap unit are connected in parallel to the driver chip 0101-VS1 ( Figure 2 Power module 30 pins 12 and 13), VB2-VS2 ( Figure 2 Power module 30 pins 8 and 9), VB3-VS3 ( Figure 2 Between pins 4 and 5 of power module 30, a floating ground power supply is provided for the high-side drive circuit.

[0035] The following is one embodiment of the power module 30: External AC power is converted into pulsating DC power by rectifier unit 0104. PFC unit 0103 corrects the current waveform to a sine wave in phase with the voltage by frequently switching IGBT1 on and off, and improves the power factor. The corrected DC power is input to power conversion unit 0102. The driver chip 0101 controls IGBT2-IGBT7 to conduct alternately through HO / LO signals to generate three-phase AC power to drive an external three-phase motor (such as an air conditioner compressor motor). The bootstrap unit replenishes power to the high-side drive in real time. The protection circuit monitors the current, temperature and voltage of each unit throughout the process to ensure stable operation of the module.

[0036] The following is based on Figure 1 Taking the A-arm (IGBT2+IGBT3+FRD3+FRD4) of the medium power conversion unit 0102 as an example, the hardware implementation and working principle of the bridge arm switching assembly are explained: Each bridge arm switching assembly includes two N-channel IGBTs and two fast recovery diodes (FRDs): the anode of FRD3 is connected to the source of IGBT2, and the cathode is connected to the drain of IGBT2; the anode of FRD4 is connected to the source of IGBT3, and the cathode is connected to the drain of IGBT3, forming an anti-parallel structure for freewheeling and suppressing voltage spikes; the gate of IGBT2 is connected to the 0101 port of the driver chip, and a pull-down resistor is connected in parallel between the gate and the source to prevent the gate from being floating when power is off; the gate of IGBT3 is connected to the LO1 port, and similarly, a pull-down resistor is connected in parallel; the drain of IGBT2 is connected to the VCC2 port (…). Figure 2 The power module 30 is connected to pin 17. The source of IGBT2 is connected to the drain of IGBT3. This series connection is led out as the U-phase output terminal. Figure 2 Pin 13 of power module 30 is connected to the U-phase winding of an external motor; the source of IGBT3 is led out as the U-port ( Figure 2 Power module 30 pin 23 is connected to ground; Driver chip 0101 and LO1 output complementary PWM signals, as follows: During the IGBT2 turn-on phase, HO1 outputs 15V, LO1 outputs 0V, the gate of IGBT2 is charged and turned on, and the current path is “VCC2→IGBT2→U phase winding→U-→IGBT3 (turn-off)→ground”, and the motor U phase winding is energized. During the IGBT3 turn-on phase, HO1 outputs 0V, LO1 outputs 15V, the IGBT3 gate is charged and turned on, and the inductive current of the motor winding freewheels through “U phase winding → U- → IGBT3 → FRD3 → U phase winding” to prevent voltage overshoot when IGBT2 is turned off. During the dead-time phase, both HO1 and LO1 output 0V. At this time, FRD3 and FRD4 simultaneously carry over current to prevent short circuits in the bridge arms and ensure continuous current.

[0037] The following is based on Figure 2 Taking PFC unit 0103 (IGBT1, FRD1, FRD2) as an example, its working principle is explained: The drain of IGBT1 is connected to the cathodes of FRD1 and FRD2, and the PFC1 port is also brought out. Figure 2 Power module 30 pin 1), used to connect to the P terminal of rectifier unit 0104; IGBT1 gate is connected to the driver chip 0101 port, and source is connected to the FRD2 anode and -VCC port ( Figure 2 Connect pin 20 of power module 30; connect the anode of FRD1 to the DBP terminal; The driver chip 0101 controls the high-frequency switching of IGBT1 via the PFCG signal to achieve current waveform correction. The specific working principle is as follows: During the conduction phase (IGBT1 is turned on), the DC power output by the rectifier unit 0104 forms a loop through “DB P→FRD1→IGBT1→-VCC→DB N”, the IGBT1 conduction voltage decreases, and the current rises rapidly. During the turn-off phase (IGBT1 is turned off), the inductor releases energy, and the current continues through "inductor → FRD2 → -VCC → inductor"; By adjusting the conduction time of IGBT1, the input current waveform is made to track the voltage waveform, thereby improving the power factor.

[0038] The following is based on Figure 2 Taking the intermediate rectifier unit 0104 (D1-D4) as an example, its working principle is explained as follows: Rectifier unit 0104 uses four silicon rectifier diodes to form a single-phase bridge topology; the cathode of D1 is connected to the anode of D2, and the output is the AC / S port. Figure 2 Power module 30, pin 44); Cathode D4 is connected to anode D3, and the connection is made to the AC R port ( Figure 2 Power module 30, pin 47), two ports are connected to external AC power; the anodes of D1 and D4 are connected, and the output is the DB N port ( Figure 2 Power module 30, pin 45); Cathodes D2 and D3 are connected and led out as DBP ports ( Figure 2 Power module 30 (pin 46) outputs pulsating DC power to PFC unit 0103; During the positive half-cycle (AC R positive, AC S negative): the current path is "AC R→D3→DBP→load→DBN→D1→ACS", D3 and D1 are on, D2 and D4 are off, and DBP outputs a positive voltage; During the negative half-cycle (AC R negative, AC S positive): the current path is "AC S→D2→DBP→load→DB N→D4→ACR", D2 and D4 are on, D3 and D1 are off, and DBP outputs a positive voltage.

[0039] Reference Figure 3 The present invention also provides a packaging structure for encapsulating the power module 30 described above; the packaging structure includes an aluminum substrate 23, an insulating layer 24, circuit wiring 25, circuit elements 27, metal wires 28, pins 29, and sealing resin 31. The circuit aluminum substrate 23 serves as the physical base and heat dissipation carrier of the module and is made of aluminum. Its back side is formed with uneven texture 26 by laser etching and polishing to increase the heat dissipation area. At the same time, it supports the insulating layer 24, circuit wiring 25 and all circuit components 27. An insulating layer 24 is disposed on the upper surface of the circuit aluminum substrate 23 to achieve electrical insulation between the aluminum substrate (low potential) and the circuit wiring 25 (high potential) to avoid the risk of high voltage breakdown. The circuit wiring 25 is formed on the upper surface of the insulating layer 24 and is made by etching copper foil. The overall wiring pattern is adapted to the electrical architecture of the power module 30 and is used to connect various circuit components 27 to realize the signal and power transmission of the driver chip 0101, power conversion unit 0102, PFC unit 0103, etc. All core components of the power module 30 are fixed at preset positions on the circuit wiring 25. Metal wire 28 (such as gold wire or copper wire) is used to connect the pin 29 of circuit element 27 to circuit wiring 25 to realize the electrical path between each element and wiring; if the circuit aluminum substrate 23 needs to be connected to the ground potential, the insulating layer 24 is drilled through, and metal wire 28 is used to form a connection between the ground potential of circuit wiring 25 and aluminum substrate 23. Pin 29 is made of copper and has a plated surface. It is electrically connected to circuit wiring 25 to enable the module to connect to external circuits. During the manufacturing stage, specific positions of pin 29 are connected by reinforcing ribs 33 to prevent circuit components 27 from being damaged by electrostatic discharge during subsequent processing. The reinforcing ribs 33 are removed after packaging. The sealing resin 31 is made of thermoplastic resin or thermosetting resin. It completely seals the internal parts of the circuit aluminum substrate 23, insulating layer 24, circuit wiring 25, circuit element 27, metal wire 28 and pin 29 by injection molding or transfer molding, leaving only the external connection end of pin 29 exposed. The packaging structure manufacturing process is as follows: First, the circuit aluminum substrate 23 is pre-treated by cutting the aluminum material into an appropriate size as the circuit substrate. The back side of the substrate is laser-etched and polished to form a texture 26. Then, an insulating layer 24 is set on the surface of the circuit aluminum substrate 23, and a copper foil is formed on the insulating layer 24. The copper foil is etched to form circuit wiring 25. Solder paste is then applied to specific locations on the circuit wiring 25 to prepare for soldering of components and wiring. Then, the pins 29 are prepared and placed. The copper material is made into an appropriate shape and surface plated to serve as pins 29 (multiple pins 29 are connected by reinforcing ribs 33); circuit elements 27 and pins 29 are placed on the solder paste. After pin 29 is positioned, the solder paste is cured by reflow soldering, and the circuit element 27 and pin 29 are fixed on the circuit wiring 25. Then, the flux remaining on the circuit board is removed by cleaning methods such as spraying and ultrasonic cleaning. Then, use metal wire 28 to form an electrical connection between circuit element 27 and circuit wiring 25; Finally, the above elements are sealed using injection molding with thermoplastic resin or transfer molding with thermosetting resin; the reinforcing ribs 33 of pin 29 are removed, and pin 29 is machined into the desired shape; Necessary tests are conducted using testing equipment to verify whether the electrical and insulation performance of the module meets the requirements. Products that pass the tests are the final power modules, while unqualified products are rejected.

[0040] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A driver chip, characterized in that, include: High and low side drive circuits, PFC drive circuits, and protection circuits; The protection circuit is electrically connected to the high and low side drive circuit and the PFC drive circuit; The high-low side drive circuit is used to convert external control signals into drive signals; the PFC drive circuit is used to adjust the gate drive signal of the PFC switching device according to the external PFC control command; the protection circuit is used to monitor the high-low side drive circuit and the PFC drive circuit, and trigger protection action when abnormal operating conditions are detected.

2. The driver chip according to claim 1, characterized in that: The high and low side drive circuits include a Schmitt threshold circuit, a level conversion circuit, a dead-zone interlock circuit, a pulse circuit, an undervoltage detection circuit, a delay circuit, a gate circuit, and an output circuit. The output of the Schmitt threshold circuit is connected to the input of the level conversion circuit. The output of the level conversion circuit is connected to the input of the dead-zone interlock circuit. The output of the dead-zone interlock circuit is connected to the input of the pulse circuit and the input of the delay circuit. The output of the pulse circuit is connected to the input of the undervoltage detection circuit. The output of the delay circuit is connected to the first input of the gate circuit. The second input of the gate circuit is connected to the protection circuit. The output of the gate circuit and the output of the undervoltage detection circuit are connected to the output circuit. The Schmitt threshold circuit is used to perform level shaping on the externally input control signal; the level conversion circuit is used to convert the low-voltage side control signal into a drive level adapted to the high-voltage side switching device; the dead-zone interlock circuit is used to prevent the high- and low-side switching devices of the same bridge arm from being turned on simultaneously; the pulse circuit is used to convert the continuous control signal into a pulse drive signal that conforms to the on / off characteristics of the switching device; the undervoltage detection circuit is used to control the on / off of the drive signal according to the supply voltage of the high- and low-side drive circuits. The delay circuit is used to adjust the delay of the drive signal after dead-zone interlocking; the gate circuit is used to receive the delayed drive signal and the fault control signal of the protection circuit, and to prevent the drive signal from being transmitted to the output circuit when the fault control signal is valid; the output circuit is used to amplify the pulse drive signal and output it to external devices.

3. The driver chip according to claim 2, characterized in that: The PFC drive circuit includes a multi-stage voltage delay drive circuit, an oscillation circuit, and a drive output circuit. The output terminal of the oscillation circuit is connected to the clock signal terminal of the multi-stage voltage delay drive circuit, the output terminal of the multi-stage voltage delay drive circuit is connected to the input terminal of the drive output circuit, and the protection terminal of the drive output circuit is connected to the protection circuit. The multi-stage voltage delay drive circuit is used to adjust the output voltage signal in stages according to the external PFC control command and the clock signal output by the oscillation circuit. The oscillation circuit is used to generate a clock signal; the drive output circuit is used to amplify the voltage signal output by the multi-stage voltage delay drive circuit into a gate drive signal adapted to the PFC switching device.

4. The driver chip according to claim 3, characterized in that: The protection circuit includes an ITRIP overcurrent protection circuit, a PFC overcurrent protection circuit, a temperature detection protection circuit, an undervoltage protection circuit, a fault logic circuit, and an error reporting circuit. The input terminal of the fault logic circuit is connected to the output terminal of the ITRIIP overcurrent protection circuit, the output terminal of the PFC overcurrent protection circuit, the output terminal of the temperature detection protection circuit, and the output terminal of the undervoltage protection circuit. The output terminal of the fault logic circuit is connected to the input terminal of the error reporting circuit, the second input terminal of the gate circuit, and the protection terminal of the drive output circuit. The ITRIP overcurrent protection circuit is used to monitor the operating current of the power module and output an overcurrent signal to the fault logic circuit when the power module is overcurrent; the PFC overcurrent protection circuit is used to monitor the operating current of the PFC device and output a PFC overcurrent signal to the fault logic circuit when the PFC device is overcurrent. The temperature detection and protection circuit is used to collect the temperature of the driver chip and external associated power devices, and outputs an over-temperature signal to the fault logic circuit when the temperature is higher than the preset overheat threshold; the undervoltage protection circuit is used to monitor the power supply voltage of the driver chip, and outputs an undervoltage signal to the fault logic circuit when the voltage is lower than the preset undervoltage threshold. The fault logic circuit is used to receive fault signals output by each protection circuit and generate corresponding control signals; the error reporting circuit is used to receive the control signals of the fault logic circuit and convert them into externally identifiable fault indication signals.

5. A power module, characterized in that, The power module includes the driver chip as described in any one of claims 1-4; the power module further includes a power conversion unit, a PFC unit, a rectification unit, and a bootstrap unit; The high- and low-side drive circuits are connected to the power conversion unit and the bootstrap unit; the PFC drive circuit is connected to the PFC unit; the rectifier unit is connected to the PFC unit; and the PFC unit is connected to the power conversion unit. The power conversion unit is used to convert the DC power output by the PFC unit into AC current adapted to the external load; the PFC unit is used to perform power factor correction on the DC power output by the rectifier unit; the rectifier unit is used to convert the externally input AC power into DC power; the bootstrap unit is used to provide a stable floating ground power supply for the high and low side drive circuits of the driver chip.

6. The power module according to claim 5, characterized in that: The power conversion unit includes multiple sets of bridge arm switching assemblies; each set of bridge arm switching assemblies includes at least two power switching devices and a freewheeling diode connected in anti-parallel to the power switching devices; the gate of the power switching device is connected to the output terminal of the high-low side drive circuit, and the series node of two power switching devices in the same set of bridge arm switching assemblies serves as the AC output terminal of the power conversion unit and is connected to the external load; the power switching devices are used to alternately turn on and off under the control of the high-low side drive circuit of the drive chip to realize the conversion of DC to AC; the freewheeling diode is used to provide a freewheeling path for the inductive current of the external load when the power switching devices are turned off.

7. The power module according to claim 6, characterized in that: The PFC unit includes a PFC power switch, a rectifier diode, and an energy storage element. The gate of the PFC power switch is connected to the PFC drive circuit, the drain of the PFC power switch is connected to the rectifier unit and the anode of the rectifier diode, the cathode of the rectifier diode is connected to one end of the energy storage element and the power conversion unit, and the other end of the energy storage element is connected to the source of the PFC power switch and ground. The PFC power switch is used to switch on and off at high frequency under the control of the PFC drive circuit to adjust the current waveform of the PFC unit. The rectifier diode is used to prevent reverse current flow. The energy storage element is used to stabilize the output voltage of the PFC unit.

8. The power module according to claim 7, characterized in that: The rectifier unit includes four rectifier diodes connected in a bridge topology; the AC input terminal of the rectifier unit is connected to an external AC power supply, and the DC output terminal of the rectifier unit is connected to the PFC unit; the rectifier unit is used to convert externally input AC power into DC power.

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