High-voltage gate driving chip integrated with bootstrap function and process implementation method thereof

Abstract

The invention provides a high-voltage gate driving chip integrated with a bootstrap function and a process implementation method of the high-voltage gate driving chip. A charging path for an external capacitor is added to the power supply end and the ground end of the high-voltage level shifting circuit, the reference ground of the high-voltage level shifting circuit is a variable level and is controlled by an internal control signal, input signals on the high side and the low side pass through an input stage and then output to the bootstrap control circuit, and when the input signals on the high side are low levels, the bootstrap control circuit outputs the signals to the bootstrap control circuit. The bootstrap control circuit controls the reference ground potential of the level shift circuit and performs unidirectional charging on the external bootstrap capacitor. According to the scheme, the charging efficiency is high, the circuit structure is simple, the chip area is reduced, and the cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of half-bridge driver circuit technology, and in particular to a high-voltage gate driver chip with integrated bootstrap function and its process implementation method. Background Technology

[0002] Half-bridge driver circuits are widely used in motor drives, electronic ballasts, and switching power supplies. They drive two power MOSFETs or IGBTs connected in a totem-pole configuration, causing them to conduct alternately. Internally, besides the high-voltage level shifting circuit (located at the edge of the isolation structure and operating at several hundred volts) which serves as the interface between the high and low sides, the other circuit modules are located in the high-voltage region (powered by the high-side power supply) and the low-voltage region (powered by the low-side power supply), both operating at 10 to 20 volts. To improve power efficiency, a single power supply is used. The low-voltage region is directly powered by the DC power supply VCC, while the high-voltage region, in a floating state, is powered through a bootstrap capacitor. Figure 1 As shown, when the lower transistor (low-side transistor) M2 in the half-bridge structure is turned on and the upper transistor (high-side transistor) M1 is turned off, the DC power supply VCC flows through the bootstrap diode D. B And the lower transistor M2 and the bootstrap capacitor C B During charging, when the upper transistor is turned on and the lower transistor is turned off, the bootstrap capacitor C... B Power supply to the high-side circuit.

[0003] The external bootstrap circuit consists of bootstrap diode D. B and bootstrap capacitor C B However, while a bootstrap diode can be incorporated, it increases circuit cost. Its forward voltage drop affects the final charging voltage drop across the capacitor, and its reverse recovery current causes leakage current in the bootstrap capacitor. Furthermore, because the peak current capacity required by the bootstrap diode is too large and its breakdown voltage too high, it cannot be integrated into a chip. Patent 7215189B proposes a bootstrap diode emulator with dynamic back-gate bias, such as... Figure 2 As shown, alternative Figure 1 The bootstrap diode D in B The bootstrap diode emulator in this technology uses an integrated high-voltage LDMOS switch to charge the bootstrap capacitor. However, the gate control circuit and dynamic back gate control circuit used in this scheme to control the gate and back gate of the high-voltage LDMOS switch are relatively complex and inefficient. In addition, the bootstrap diode emulation circuit uses two high-voltage switching LDMOS devices, resulting in a large chip footprint and high cost. Furthermore, the on-resistance of the LDMOS device used to charge the bootstrap capacitor is relatively high, leading to insufficient charging speed. This makes this technology unsuitable for certain applications, such as high-frequency half-bridge drive circuits. Summary of the Invention

[0004] The purpose of this invention is to address the problems existing in the prior art by providing a novel bootstrap technology and its implementation method. This invention fully utilizes the characteristics of the level shifting circuit structure in the half-bridge circuit to improve the traditional bootstrap technology and achieve bootstrap charging function.

[0005] The technical solution to achieve the objective of this invention is as follows: On one hand, a high-voltage gate driver chip with integrated bootstrap function is provided. The chip includes a low-side channel logic circuit, a high-side channel low-dipper logic circuit, a high-voltage level shift circuit, a high-side channel high-dipper logic circuit, and a bootstrap control circuit. The low-side input signal LIN, after passing through the low-side channel logic circuit, outputs two sets of signals. One set of signals is the low-side output signal LO, which controls the low-side power switching device of the bridge circuit. The other set of signals serves as one of the input signals of the bootstrap control circuit. The high-side input signal HIN, after passing through the high-side channel low-dipper logic circuit, also outputs two sets of signals. One set of signals serves as the input signal of the high-voltage level shift circuit. The other set of signals serves as one of the input signals of the bootstrap control circuit. The output signal of the high-voltage level shift circuit serves as the input signal of the high-side channel high-dipper logic circuit. The output signal of the high-side channel high-dipper logic circuit is the high-side output signal HO, which controls the high-side power switching device of the bridge circuit.

[0006] Furthermore, the reference power supply level of the high-voltage level shifting circuit is a floating signal VB, and the reference ground level is the output signal of the bootstrap control circuit.

[0007] Furthermore, the reference power supply level of the low-side channel logic circuit, the high-side channel low-band logic circuit, and the bootstrap control circuit is the ordinary power supply signal VCC, and the reference ground level is the ordinary ground signal COM.

[0008] Furthermore, the reference power supply level of the high-side channel high-basin logic circuit is a floating signal VB, and the reference ground level is a floating signal VS.

[0009] On the other hand, a process implementation method for a high-voltage gate driver chip with integrated bootstrap function is provided. The low-side channel logic circuit, the high-side channel low-basin logic circuit, and the bootstrap control circuit are implemented in the low-basin. The high-voltage level shifting circuit is implemented by a power MOS device, and the high-side channel high-basin logic circuit is implemented in the high-basin. The low-basin includes a substrate of a first doped type, a buried layer of a second doped type, a well of a second doped type, and a well of a first doped type. The high-basin includes a buried layer of a second doped type, a well of a second doped type, and a well of a first doped type. The power MOS device includes a well of a first doped type, a buried layer of a second doped type, a body contact, a source contact, a drain contact, a gate, and a well of a second doped type. The output of the bootstrap control circuit is connected to the body contact of the power MOS device.

[0010] Furthermore, the low basin contains one or more second-doped type wells and first-doped type wells, but the first-doped type wells are always surrounded by second-doped type wells and second-doped type buried layers.

[0011] Furthermore, the second doped type trap in the high basin is electrically connected to the floating signal VB.

[0012] Furthermore, when the HO output is low, the bootstrap control circuit outputs a signal voltage connected to the body contact of the power MOS device, which is the ordinary power supply signal VCC. This signal charges the bootstrap capacitor through the parasitic diode formed by the first doped substrate and the second doped buried layer or the second doped well.

[0013] Furthermore, when the LO output is low, the signal voltage output by the bootstrap control circuit and connected to the body contact of the power MOS device is the normal ground signal COM.

[0014] Compared with the prior art, the significant advantages of this invention are:

[0015] (1) The present invention makes full use of the characteristics of the high voltage level shift circuit structure. Under the premise of ensuring the normal operation of the high voltage level shift circuit, it realizes the function of charging the bootstrap capacitor by the low-side power supply through the high voltage level shift circuit. The design is very ingenious. The solution greatly simplifies the circuit structure, reduces the chip area, and lowers the cost.

[0016] (2) In this invention, the charging of the bootstrap capacitor is controlled by the bootstrap control circuit. As long as the high-side input signal is low, the bootstrap capacitor can be charged regardless of the high or low level of the low-side input signal. This scheme has high charging efficiency and can ensure the normal operation of the high-side circuit.

[0017] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 It is the basic topology of a half-bridge driver circuit driving an external power transistor and a bootstrap circuit.

[0019] Figure 2 This is a structural diagram of a traditional integrated bootstrap circuit in a high-voltage gate drive circuit.

[0020] Figure 3 This is a circuit structure diagram of the high-voltage gate drive bootstrap circuit technology of the present invention in one embodiment.

[0021] Figure 4 This is one embodiment of the high-voltage gate driver chip process implementation method that integrates the bootstrap function of the present invention.

[0022] Figure 5This is a waveform diagram of the bootstrap control circuit of the present invention in one embodiment.

[0023] Figure 6 This is one embodiment of the integrated bootstrap circuit of the present invention.

[0024] Figure 7 This is a second embodiment of the integrated bootstrap circuit of the present invention.

[0025] Figure 8 This is one embodiment of the bootstrap control circuit of the present invention.

[0026] Figure 9 This is a simulation waveform diagram of the integrated bootstrap circuit of the present invention in one embodiment. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] It should be noted that if the embodiments of the present invention involve descriptions such as "first" and "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" and "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0029] In one embodiment, combined Figure 3A high-voltage gate driver chip with integrated bootstrap function is provided. The chip includes a low-side channel logic circuit 001, a high-side channel low-dipper logic circuit 002, a high-voltage level shift circuit 003, a high-side channel high-dipper logic circuit 004, and a bootstrap control circuit 005. The low-side input signal LIN passes through the low-side channel logic circuit 001 and outputs two sets of signals. One set of signals is the low-side output signal LO, which controls the low-side power switching device of the bridge circuit. The other set of signals serves as one of the input signals of the bootstrap control circuit 005. The high-side input signal HIN passes through the high-side channel low-dipper logic circuit 002 and also outputs two sets of signals. One set of signals serves as the input signal of the high-voltage level shift circuit 003, and the other set of signals serves as one of the input signals of the bootstrap control circuit 005. The output signal of the high-voltage level shift circuit 003 serves as the input signal of the high-side channel high-dipper logic circuit 004. The output signal of the high-side channel high-dipper logic circuit 004 is the high-side output signal HO, which controls the high-side power switching device of the bridge circuit.

[0030] Furthermore, in one embodiment, the reference power supply level of the high-voltage level shifting circuit 003 is a floating signal VB, and the reference ground level is the output signal of the bootstrap control circuit 005.

[0031] Furthermore, in one embodiment, the reference power supply level of the low-side channel logic circuit 001, the high-side channel low-side logic circuit 002, and the bootstrap control circuit 005 is the ordinary power supply signal VCC, and the reference ground level is the ordinary ground signal COM.

[0032] Furthermore, in one embodiment, the reference power supply level of the high-side channel high-basin logic circuit 004 is a floating signal VB, and the reference ground level is a floating signal VS.

[0033] In one embodiment, a process implementation method for a high-voltage gate driver chip with integrated bootstrapping function is provided, combined with... Figure 4 The low-side channel logic circuit 001, the high-side channel low-basin logic circuit 002, and the bootstrap control circuit 005 are implemented in the low-basin. The high-voltage level shift circuit 003 is implemented by a power MOS device. The high-side channel high-basin logic circuit 004 is implemented in the high-basin. The low-basin includes a substrate 101 of a first doped type, a buried layer 102 of a second doped type, a well 103 of a second doped type, and a well 104 of a first doped type. The high-basin includes a buried layer 112 of a second doped type, a well 113 of a second doped type, and a well 114 of a first doped type. The power MOS device includes a well 105 of a first doped type, a buried layer 106 of a second doped type, a body contact 107, a source contact 108, a drain contact 109, a gate 110, and a well 111 of a second doped type. The output of the bootstrap control circuit 005 is connected to the body contact 107 of the power MOS device.

[0034] Furthermore, in one embodiment, the low basin contains one or more second-doped type wells 103 and first-doped type wells 104, but the first-doped type wells 104 are always surrounded by the second-doped type wells 103 and the second-doped type buried layer 102.

[0035] Furthermore, in one embodiment, the second doped type trap 113 in the high basin is electrically connected to the floating signal VB.

[0036] Furthermore, in one embodiment, when the HO output is low, the bootstrap control circuit 005 outputs a signal voltage connected to the power MOS device body contact 107, which is the normal power supply signal VCC. The bootstrap capacitor is charged through the parasitic diode formed by the first doped type substrate 101 and the second doped type buried layer 112 or the second doped type well 113.

[0037] Furthermore, in one embodiment, when the LO output is low, the bootstrap control circuit 005 outputs a signal voltage connected to the power MOS device body contact 107 as the normal ground signal COM.

[0038] Figure 5 This is a waveform diagram of the output COM1 of the bootstrap control circuit of the present invention, along with HIN and LIN. HIN and LIN are input with a square wave signal. When HIN is high, the output of COM1 is low.

[0039] For example, Figure 6 This is one embodiment of the integrated bootstrap circuit of the present invention. The high-side channel low-side logic circuit consists of a high-side signal input circuit and a narrow pulse generation circuit, while the low-side channel logic circuit consists of a low-side signal input circuit, a low-side delay circuit, and a low-side signal output circuit.

[0040] Preferably, the bootstrap control circuit adopts... Figure 8The structure of the bootstrap control circuit includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6. The gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are connected to an input signal CIN1. The drains of the third PMOS transistor MP3 and the third NMOS transistor MN3 are connected to the gates of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5. The gates of the fourth NMOS transistor MN4 and the fourth PMOS transistor MP4 are connected to another input terminal CIN2 of the bootstrap control circuit. The source of the fifth NMOS transistor MP5 is connected to the drain of the fourth NMOS transistor MN4. The drains of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the fifth NMOS transistor MN5 are connected to the gates of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6. The drain of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6 are connected as the output of the bootstrap control circuit. The sources of the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are connected to the low-side power supply VCC. The sources of the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the sixth NMOS transistor MN6 are connected to the common ground COM.

[0041] Here, preferably, in combination Figure 6 In this invention, the high-voltage level shifting circuit comprises two identical independent parts. The first high-voltage switching device MN1, the first Zener diode Z1, and the first resistor R1 form one branch, while the second high-voltage switching device MN2, the second Zener diode Z2, and the second resistor R2 form the other branch. The gate of the first high-voltage switching device MN1 is connected to an output signal of the narrow pulse generation circuit, and the source of the first high-voltage switching device MN1 is connected to the output terminal COM1 of the bootstrap control circuit. The drain of the first high-voltage switching device MN1 is connected to one end of the first resistor R1 and one end of the first Zener diode Z1, serving as the high-voltage level shifting circuit. One output terminal of the voltage-level shift circuit, the other end of the first resistor R1 and the other end of the first Zener diode Z1 are connected to the high-side floating power supply VB. The gate of the second high-voltage switching device MN2 is connected to another output signal of the narrow pulse generation circuit, the source of the second high-voltage switching device MN2 is connected to the output terminal COM1 of the bootstrap control circuit, and the drain of the second high-voltage switching device MN2 is connected to one end of the second resistor R2 and one end of the second Zener diode Z2, thus serving as another output terminal of the high-voltage level shift circuit. The other end of the second resistor R2 and the other end of the second Zener diode Z2 are connected to the high-side floating power supply VB. A high-voltage-resistant first diode D is added between one output terminal of the high-voltage level shift circuit and COM1. B1A second high-voltage diode, D, was added between the other output terminal of the high-voltage level shifting circuit and COM1. B2 The first diode device D B1 Second diode device D B2 The clamping diode in the high-voltage level shifting circuit forms two charging paths. The bootstrap control circuit controls the high and low levels of COM1, and the external bootstrap capacitor C is charged through these two charging paths. B Charging is performed. Here, the first diode device D... B1 Second diode device D B2 It can be a parasitic device.

[0042] The high-side input signal HIN passes through the high-side signal input circuit and outputs a signal to the narrow pulse generation circuit. The narrow pulse generation circuit outputs two pulse signals to the high-voltage level shift circuit. The high-voltage level shift circuit then transmits these two pulse signals to the high-side channel high-frequency logic circuit. The high-side channel high-frequency logic circuit outputs the HO signal, used to control the external power transistor. The low-side input signal LIN passes through the low-side signal input circuit and outputs a signal to the low-side delay circuit. The low-side delay circuit outputs a signal to the low-side signal output circuit, which outputs the LO signal, used to control the external power transistor. The output signal of the high-side signal input circuit serves as one input signal CIN1 of the bootstrap control circuit, and the output signal of the low-side signal input circuit serves as the other input signal CIN2 of the bootstrap control circuit. The output signal COM1 of the bootstrap control circuit serves as the reference ground for the high-voltage level shift circuit; COM1 is a variable level.

[0043] The specific operating waveforms of Embodiment 1 of the integrated bootstrap circuit of this invention are as follows: Figure 9 As shown, when the high-side input signal HIN is low, the bootstrap control circuit controls the level of COM1 through the first diode device D. B1 Second diode device D B2 And the two charging paths formed by the clamping diode in the high-voltage level shift circuit, for the external bootstrap capacitor C B Charging begins, causing the high-side floating signal VB to gradually increase. When the high-side input signal HIN is high, the charging circuit stops charging the external bootstrap capacitor C. B During charging, the high-side floating power supply voltage remains basically unchanged. When the high-side circuit is working normally, the high level of its output HO changes with the high-side floating signal VB.

[0044] For example, Figure 7 This is a second embodiment of the integrated bootstrap circuit of the present invention. This scheme is based on the first embodiment described above with simple modifications, except that a first diode device D is added between the output terminal of the high-voltage level shift circuit and the output terminal COM1 of the bootstrap control circuit. B1Second diode device D B2 A third diode D was also added between the high-side floating signal VB and the output terminal COM1 of the bootstrap control circuit. B3 Here, the first diode device D B1 Second diode device D B2 and the third diode D B3 Parasitic devices may be used, but are not limited to those that are parasitic.

[0045] The high-side input signal HIN, after passing through the high-side signal input circuit, outputs a signal to the narrow pulse generation circuit. The narrow pulse generation circuit outputs two pulse signals to the high-voltage level shift circuit. The high-voltage level shift circuit then transmits these two pulse signals to the high-side channel high-frequency logic circuit. The high-side channel high-frequency logic circuit outputs the HO signal, used to control the external power transistor. The low-side input signal LIN, after passing through the low-side signal input circuit, outputs a signal to the low-side delay circuit. The low-side delay circuit outputs a signal to the low-side signal output circuit, which outputs the LO signal, used to control the external power transistor. The output signal of the high-side signal input circuit serves as one input signal CIN1 of the bootstrap control circuit, and the output signal of the low-side signal input circuit serves as the other input signal CIN2 of the bootstrap control circuit. The output signal COM1 of the bootstrap control circuit serves as the reference ground for the high-voltage level shift circuit; COM1 is a variable level. In this scheme, the first diode device D... B1 Second diode device D B2 The clamping diode in the high-voltage level shift circuit forms two charging paths, and the third diode D... B3 A charging path is formed, and the bootstrap control circuit controls the high and low levels of COM1. Through these three charging paths, the external bootstrap capacitor C is charged. B Charge it.

[0046] Here, the operating waveform of the integrated bootstrap circuit implementation method two can be referred to the implementation method one.

[0047] The present invention has high charging efficiency, simple circuit structure, and reduces chip area and cost.

[0048] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention without departing from its spirit and scope should be included within the protection scope of the present invention.

Claims

1. A high-voltage gate driver chip with integrated bootstrap function, characterized in that, The chip includes a low-side channel logic circuit (001), a high-side channel low-basin logic circuit (002), a high-voltage level shift circuit (003), a high-side channel high-basin logic circuit (004), and a bootstrap control circuit (005). The low-side input signal LIN passes through the low-side channel logic circuit (001) and outputs two sets of signals. One set of signals is the low-side output signal LO, which controls the low-side power switching device of the bridge circuit. The other set of signals is used as one of the input signals of the bootstrap control circuit (005). The high-side input signal HIN passes through the high-side channel low-basin logic circuit (002) and also outputs two sets of signals. One set of signals is used as the input signal of the high-voltage level shift circuit (003), and the other set of signals is used as one of the input signals of the bootstrap control circuit (005). The output signal of the high-voltage level shift circuit (003) is used as the input signal of the high-side channel high-basin logic circuit (004). The output signal of the high-side channel high-basin logic circuit (004) is the high-side output signal HO, which controls the high-side power switching device of the bridge circuit.

2. The high-voltage gate driver chip with integrated bootstrap function according to claim 1, characterized in that, The reference power supply level of the high-voltage level shift circuit (003) is the floating signal VB, and the reference ground level is the output signal of the bootstrap control circuit (005).

3. The high-voltage gate driver chip with integrated bootstrapping function according to claim 2, characterized in that, The reference power supply level of the low-side channel logic circuit (001), the high-side channel low-basin logic circuit (002), and the bootstrap control circuit (005) is the ordinary power supply signal VCC, and the reference ground level is the ordinary ground signal COM.

4. The high-voltage gate driver chip with integrated bootstrapping function according to claim 3, characterized in that, The reference power supply level of the high-side channel high-basin logic circuit (004) is a floating signal VB, and the reference ground level is a floating signal VS.

5. A method for implementing the high-voltage gate driver chip with integrated bootstrapping function as described in any one of claims 1 to 4, characterized in that, The low-side channel logic circuit (001), the high-side channel low-basin logic circuit (002), and the bootstrap control circuit (005) are implemented in the low basin. The high-voltage level shift circuit (003) is implemented by a power MOS device. The high-side channel high-basin logic circuit (004) is implemented in the high basin. The low basin includes a substrate (101) of a first doped type, a buried layer (102) of a second doped type, a well (103) of a second doped type, and a well (104) of a first doped type. The high basin includes a buried layer (112) of a second doped type, a well (113) of a second doped type, and a well (114) of a first doped type. The power MOS device includes a well (105) of a first doped type, a buried layer (106) of a second doped type, a body contact (107), a source contact (108), a drain contact (109), a gate (110), and a well (111) of a second doped type. The output of the bootstrap control circuit (005) is connected to the body contact (107) of the power MOS device.

6. The process implementation method according to claim 5, characterized in that, The low basin contains one or more second-doped type wells (103) and first-doped type wells (104), but the first-doped type wells (104) are always surrounded by the second-doped type wells (103) and the second-doped type buried layer (102).

7. The process implementation method according to claim 6, characterized in that, The second doped type trap (113) in the high basin is electrically connected to the floating signal VB.

8. The process implementation method according to claim 7, characterized in that, When the HO output is low, the bootstrap control circuit (005) outputs a signal voltage connected to the body contact (107) of the power MOS device, which is the ordinary power supply signal VCC. The bootstrap capacitor is charged through the parasitic diode formed by the first doped type substrate (101) and the second doped type buried layer (112) or the second doped type well (113).

9. The process implementation method according to claim 8, characterized in that, When the LO output is low, the signal voltage output by the bootstrap control circuit (005) and connected to the power MOS device body contact (107) is the normal ground signal COM.

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