Charge pump, memory, memory system and electronic equipment

Abstract

The invention discloses a charge pump, a memory, a storage system and electronic equipment, and relates to the technical field of storage. The charge pump (100) comprises an input circuit (1), a first low-pass filter (2), a second low-pass filter (3) and an output circuit (4). One end of the first low-pass filter (2) is coupled with the input circuit (1), and the other end of the first low-pass filter (2) is coupled with the output circuit (4); one end of the second low-pass filter (3) is coupled with the input circuit (1), and the other end of the second low-pass filter (3) is coupled with the output circuit (4). According to the charge pump, the performance of the charge pump is optimized by designing the low-pass filter in the charge pump.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a charge pump, memory, storage system and electronic device. Background Technology

[0002] A charge pump is a circuit that uses the energy storage characteristics of a capacitor to generate an output voltage, and it has wide applications in memory.

[0003] However, due to the characteristics of the components in the charge pump, the signal at certain locations in the charge pump is often distorted, making it difficult for the output signal of the charge pump to meet the expected standard and affecting the performance of the charge pump. Summary of the Invention

[0004] This application provides a charge pump, a memory, a storage system, and an electronic device. The technical solutions provided by this application are as follows:

[0005] According to one aspect of the embodiments of this application, a charge pump is provided, the charge pump comprising: an input circuit, a first low-pass filter, a second low-pass filter, and an output circuit; one end of the first low-pass filter is coupled to the input circuit, and the other end of the first low-pass filter is coupled to the output circuit; one end of the second low-pass filter is coupled to the input circuit, and the other end of the second low-pass filter is coupled to the output circuit;

[0006] The input circuit is configured to output a first intermediate signal and a second intermediate signal;

[0007] The first low-pass filter is configured to filter the first intermediate signal to obtain a first filtered signal;

[0008] The second low-pass filter is configured to filter the second intermediate signal to obtain a second filtered signal;

[0009] The output circuit is configured to generate a first output signal and a second output signal based on the first filtered signal and the second filtered signal.

[0010] According to one aspect of the embodiments of this application, a memory is provided, the memory comprising: a memory cell array and peripheral circuitry, the peripheral circuitry comprising the charge pump described above.

[0011] According to one aspect of the embodiments of this application, a storage system is provided, the storage system including a controller and the aforementioned memory, the controller being coupled to the memory to control the memory to store data.

[0012] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device including a host and a storage system coupled to the host, the storage system including a controller and the aforementioned memory, the controller being coupled to the memory to control the memory to store data.

[0013] The technical solutions provided in this application can bring the following technical effects:

[0014] By designing low-pass filters (first low-pass filter and second low-pass filter) in the charge pump to compensate for the distortion of the intermediate signals (first intermediate signal and second intermediate signal) output by the input circuit, the output circuit can generate output signals (first output signal and second output signal) based on the filtered signals (first filtered signal and second filtered signal) output by the low-pass filter, thereby optimizing the performance of the charge pump. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a charge pump circuit provided in one embodiment of this application.

[0016] Figure 2 This is a schematic diagram of a first intermediate signal and a second intermediate signal provided in one embodiment of this application.

[0017] Figure 3 This is a schematic diagram of the third and fourth output signals provided in one embodiment of this application.

[0018] Figure 4 This is a schematic diagram of a charge pump provided in one embodiment of this application.

[0019] Figure 5 This is a schematic diagram of a first filtered signal and a second filtered signal provided in one embodiment of this application.

[0020] Figure 6 This is a schematic diagram of a first output signal and a second output signal provided in one embodiment of this application.

[0021] Figure 7 This is a schematic diagram showing a comparison of the charge pump circuit and the output signal of the charge pump provided in one embodiment of this application.

[0022] Figure 8 This is a schematic diagram of a memory provided in one embodiment of this application.

[0023] Figure 9 This is a schematic diagram of a peripheral circuit provided in one embodiment of this application.

[0024] Figure 10 This is a structural block diagram of an electronic device provided in one embodiment of this application.

[0025] Figure 11 This is a structural block diagram of an electronic device provided in another embodiment of this application.

[0026] Legend:

[0027] 100. Charge Pump 1. Input Circuit

[0028] 2. First low-pass filter; 3. Second low-pass filter

[0029] 4. Output circuit 20. First resistor

[0030] 21. First capacitor; 30. Second resistor

[0031] 31. Second capacitor; 5. First input structure

[0032] 6. Second input structure; 10. First current source

[0033] 11. Second current source 12. First NMOS transistor

[0034] 13. Second NMOS transistor 14. Third NMOS transistor

[0035] 15. Fourth NMOS transistor 16. First PMOS transistor

[0036] 17. Second PMOS transistor 18. Third PMOS transistor

[0037] 19. Fourth PMOS transistor; 40. Third capacitor

[0038] 41. Fourth capacitor; 42. Fifth PMOS transistor

[0039] 43. Sixth PMOS transistor 44. Fifth NMOS transistor

[0040] 45. Sixth NMOS transistor 46. Seventh NMOS transistor

[0041] 47. Eighth NMOS transistor 48. Third resistor

[0042] 49. Fourth resistor; 50. Charge pump circuit Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0044] A charge pump is a circuit that uses the energy storage properties of a capacitor to generate an output voltage. In some embodiments, a charge pump is used to identify or detect the difference between two input signals.

[0045] In some embodiments, the charge pump acts as a boost or buck converter, amplifying or reducing the voltage difference between two input signals. For example, after two signals are input to the charge pump, the pump will produce an output signal with a larger voltage difference.

[0046] In some embodiments, the charge pump is used to identify the pulse width difference between two clock signals in the memory. For example, after two clock signals are input to the charge pump, the charge pump outputs two voltage signals, and the voltage difference between these two signals reflects the aforementioned pulse width difference.

[0047] Please refer to Figure 1 The diagram shows a schematic of a charge pump circuit provided in one embodiment of this application.

[0048] The charge pump circuit 50 includes an input circuit 1 and an output circuit 4. In the charge pump circuit 50, the input circuit 1 is configured to output a first intermediate signal and a second intermediate signal, and the output circuit 4 is configured to generate a third output signal and a fourth output signal based on the first intermediate signal and the second intermediate signal.

[0049] In some embodiments, the output circuit 4 includes a third capacitor (40) and a fourth capacitor (41). The output circuit 4 is further configured to charge the third capacitor (40) according to a first intermediate signal to generate a third output signal; and to charge the fourth capacitor (41) according to a second intermediate signal to generate a fourth output signal.

[0050] In some embodiments, the charge pump circuit 50 is used to identify the pulse width difference between the first clock signal and the second clock signal input to the charge pump circuit 50. In some embodiments, the voltage difference between the third output signal and the fourth output signal generated by the charge pump circuit 50 is used to reflect the pulse width difference between the first clock signal and the second clock signal. For example, if the voltage of the third output signal is greater than the voltage of the fourth output signal, then the pulse width of the first input signal is greater than the pulse width of the second input signal; if the voltage of the third output signal is less than the voltage of the fourth output signal, then the pulse width of the first input signal is less than the pulse width of the second input signal.

[0051] However, due to the voltage division effect of the first current source 10, the second current source 11, the first NMOS (N-Metal-Oxide-Semiconductor) transistor 12, the second NMOS transistor 13, the third NMOS transistor 14, and the fourth NMOS transistor 15 in the input circuit 1, the first and second intermediate signals will be distorted. For example... Figure 2 As shown, Figure 2The light-colored lines correspond to the first intermediate signal, and the dark-colored lines correspond to the second intermediate signal. It can be seen that both the first and second intermediate signals are cut off at 420mV, limiting their amplitude. These first and second intermediate signals are used as the bias voltage provided to the output circuit 4 to control the charging of the third capacitor 40 and the fourth capacitor 41, thus obtaining the following... Figure 3 The third output signal (light-colored line) and the fourth output signal (dark-colored line) are shown. When there is a pulse width difference between the first clock signal and the second clock signal, the distortion of the first and second intermediate signals will cause the input clock signal pulse width information to be lost, resulting in an insignificant voltage difference between the third and fourth output signals. Consequently, the charge pump circuit 50 has poor performance in identifying pulse width differences.

[0052] Some standards require that the voltage difference of the charge pump output signal be greater than 8mV when the pulse width difference between the two input clock signals is greater than or equal to 2ps. In some embodiments, the following scheme is proposed to improve the charge pump circuit 50 to meet this standard:

[0053] 1. Increasing the current provided by the first current source 10 and the second current source 11 in the input circuit 1. However, in addition to increasing power consumption, this improvement will also increase the current source area, which will cause problems in the layout matching of the charge pump circuit 50.

[0054] 2. By increasing the channel width of the first PMOS (P-Metal-Oxide-Semiconductor) transistor 16, the second PMOS transistor 17, the third PMOS transistor 18, and the fourth PMOS transistor 19 in the input circuit 1, the positive feedback strength of the input circuit 1 in response to differences in the pulse width of the input signal is increased. However, this improvement is difficult to be effective across all frequency bands of the input signal and increases the layout area of ​​the charge pump circuit 50.

[0055] 3. By increasing the channel width of the seventh NMOS transistor 46 and the eighth NMOS transistor 47 in the output circuit 4, the positive feedback strength of the output circuit 4 for the voltage difference between the two output signals is increased. However, this improvement is prone to causing the charge pump circuit 50 to fail and is difficult to implement.

[0056] 4. Adjust the capacitance values ​​of the third capacitor 40 and the fourth capacitor 41. This improvement has little effect on the gain of the output voltage difference and cannot make the charge pump circuit 50 meet the expected standard.

[0057] In summary, the above improvements have problems such as increasing the layout area of ​​the charge pump circuit 50, failing to cover the full frequency band of the charge pump circuit 50's operation, unsatisfactory results, and high implementation costs. Further consideration is needed on how to improve the design of the charge pump circuit 50.

[0058] Please refer to Figure 4 This illustrates a schematic diagram of a charge pump provided in another embodiment of this application.

[0059] The charge pump 100 includes an input circuit 1, a first low-pass filter 2, a second low-pass filter 3, and an output circuit 4. One end of the first low-pass filter 2 is coupled to the input circuit 1, and the other end of the first low-pass filter 2 is coupled to the output circuit 4; one end of the second low-pass filter 3 is coupled to the input circuit 1, and the other end of the second low-pass filter 3 is coupled to the output circuit 4.

[0060] Input circuit 1 is configured to output a first intermediate signal and a second intermediate signal.

[0061] In some embodiments, the input circuit 1 is further configured to process a first clock signal and a second clock signal of the input charge pump 100 to output a first intermediate signal and a second intermediate signal.

[0062] In some embodiments, the first clock signal and the second clock signal are complementary and have the same frequency.

[0063] In some embodiments, the amplitude of the high level of the first clock signal is the same as the amplitude of the high level of the second clock signal, and the amplitude of the low level of the first clock signal is the same as the amplitude of the low level of the second clock signal. The complementarity of the first and second clock signals means that at each time domain location, the sum of the amplitudes of the first and second clock signals remains constant.

[0064] In some embodiments, the complementarity of the first clock signal and the second clock signal means that at the same time domain location, the levels of the first clock signal and the second clock signal are opposite. That is, if the first clock signal is high, the second clock signal is low, and if the first clock signal is low, the second clock signal is high.

[0065] In some embodiments, the input circuit 1 includes a first input structure 5 and a second input structure 6. The number of metal-oxide-semiconductor (MOS) transistors included in the first input structure 5 is the same as the number of MOS transistors included in the second input structure 6. One end of the first low-pass filter 2 is coupled to the first input structure 5, and one end of the second low-pass filter 3 is coupled to the second input structure 6.

[0066] In some embodiments, the number of NMOS transistors included in the first input structure 5 is the same as the number of NMOS transistors included in the second input structure 6, and the number of PMOS transistors included in the first input structure 5 is the same as the number of PMOS transistors included in the second input structure 6.

[0067] In some embodiments, the first input structure 5 includes: a first current source 10, a first NMOS transistor 12, and a second NMOS transistor 13; the second input structure 6 includes: a second current source 11, a third NMOS transistor 14, and a fourth NMOS transistor 15.

[0068] The first current source 10 is coupled to the source of the first NMOS transistor 12 and the source of the second NMOS transistor 13, respectively, and the second current source 11 is coupled to the source of the third NMOS transistor 14 and the source of the fourth NMOS transistor 15, respectively.

[0069] In some embodiments, the first current source and the second current source provide the same current, that is, the source currents of the first NMOS transistor 12, the second NMOS transistor 13, the third NMOS transistor 14 and the fourth NMOS transistor 15 are all the same.

[0070] The gates of the first NMOS transistor 12 and the third NMOS transistor 14 are coupled to the first input terminal of the charge pump 100, respectively.

[0071] In some embodiments, the first clock signal is input from the first input terminal.

[0072] The gates of the second NMOS transistor 13 and the fourth NMOS transistor 15 are coupled to the second input terminal of the charge pump 100, respectively.

[0073] In some embodiments, the second clock signal is input from the second input terminal.

[0074] In the above embodiment, the first input structure 5 and the second input structure 6 are implemented to input the first clock signal and the second clock signal into the charge pump 100 in the form of differential input, so that the first intermediate signal and the second intermediate signal output by the input circuit 1 can carry the pulse information of the first clock signal and the second clock signal, thereby realizing the identification of the pulse width difference between the first clock signal and the second clock signal.

[0075] In some embodiments, the first input structure 5 further includes a first PMOS transistor 16 and a second PMOS transistor 17; the second input structure further includes a third PMOS transistor 18 and a fourth PMOS transistor 19.

[0076] The sources of the first PMOS transistor 16, the second PMOS transistor 17, the third PMOS transistor 18, and the fourth PMOS transistor 19 are coupled to a first voltage source. The first voltage source provides the operating voltage (e.g., 1.05V) for the charge pump 100.

[0077] The drain of the first NMOS transistor 12, the drain of the third NMOS transistor 14, the drain of the first PMOS transistor 16, the drain of the second PMOS transistor 17, and the gate of the third PMOS transistor 18 are respectively coupled to one end of the first low-pass filter 2.

[0078] In some embodiments, the drain of the first PMOS transistor 16 is coupled to the gate of the first PMOS transistor 16. That is, the drain of the first NMOS transistor 12, the drain of the third NMOS transistor 14, the drain of the first PMOS transistor 16, the gate of the first PMOS transistor 16, the drain of the second PMOS transistor 17, and the gate of the third PMOS transistor 18 are respectively coupled to one end of the first low-pass filter 2.

[0079] The drain of the second NMOS transistor 13, the drain of the fourth NMOS transistor 15, the gate of the second PMOS transistor 17, the drain of the third PMOS transistor 18, and the drain of the fourth PMOS transistor 19 are respectively coupled to one end of the second low-pass filter 3.

[0080] In some embodiments, the drain of the fourth PMOS transistor 19 and the gate of the fourth PMOS transistor 19 are coupled, that is, the drain of the second NMOS transistor 13, the drain of the fourth NMOS transistor 15, the gate of the second PMOS transistor 17, the drain of the third PMOS transistor 18, the drain of the fourth PMOS transistor 19, and the gate of the fourth PMOS transistor 19 are respectively coupled to one end of the second low-pass filter 3.

[0081] In the above embodiment, the PMOS transistors in the first input structure 5 and the second input structure 6 are cross-coupled, realizing positive feedback for the differential input, thereby accelerating the edge change rate of the first intermediate signal and the second intermediate signal, making the first intermediate signal and the second intermediate signal closer to the input clock signal, and thus optimizing the charge pump performance.

[0082] The first low-pass filter 2 and the second low-pass filter 3 are both low-pass filters. A low-pass filter is a filter used to transmit low-frequency signals and attenuate high-frequency signals. That is, a low-pass filter allows signals below the cutoff frequency to pass through, but signals above the cutoff frequency cannot pass through.

[0083] The first low-pass filter 2 is configured to filter the first intermediate signal to obtain the first filtered signal.

[0084] The second low-pass filter 3 is configured to filter the second intermediate signal to obtain the second filtered signal.

[0085] In some embodiments, the first low-pass filter 2 includes M resistors and M capacitors, and the second low-pass filter 3 includes N resistors and N capacitors, where M and N are both positive integers, and the M capacitors and N capacitors are respectively coupled to the ground terminal.

[0086] In some embodiments, M equals N.

[0087] In some embodiments, M and N are both integers greater than 1, meaning that the first low-pass filter 2 and the second low-pass filter 3 are both high-order low-pass filters.

[0088] In some embodiments, the first low-pass filter 2 includes M first-order RC (Resistance-Capacitance) low-pass filters connected in sequence, and the second low-pass filter 3 includes N first-order RC low-pass filters connected in sequence. Each first-order RC low-pass filter includes a resistor and a capacitor. For the first low-pass filter 2, the first of the M first-order RC low-pass filters is coupled to the input circuit 1, and the Mth first-order RC low-pass filter is coupled to the output circuit 4. For the second low-pass filter 3, the first of the N first-order RC low-pass filters is coupled to the input circuit 1, and the Nth first-order RC low-pass filter is coupled to the output circuit 4.

[0089] In some embodiments, M and N are both 1, meaning that the first low-pass filter 2 and the second low-pass filter 3 are both first-order RC low-pass filters.

[0090] In some embodiments, the first low-pass filter 2 includes a first resistor 20 and a first capacitor 21. One end of the first resistor 20 is coupled to the input circuit 1, and the other end of the first resistor 20 is coupled to the output circuit 4. One end of the first capacitor 21 is coupled to the ground terminal, and the other end of the first capacitor 21 is coupled to the first resistor 20 and the output circuit 4, respectively.

[0091] The second low-pass filter 3 includes a second resistor 30 and a second capacitor 31. One end of the second resistor 30 is coupled to the input circuit 1, and the other end of the second resistor 30 is coupled to the output circuit 4. One end of the second capacitor 31 is coupled to the ground terminal, and the other end of the second capacitor 31 is coupled to both the second resistor 30 and the output circuit 4.

[0092] For example, the first low-pass filter 2 and the second low-pass filter 3 are used to filter the... Figure 2 The first and second intermediate signals shown are filtered to obtain the following: Figure 5 The first filtered signal (light-colored line) and the second filtered signal (dark-colored line) shown are compared to the first intermediate signal and the second intermediate signal. It can be seen that the first filtered signal and the second filtered signal are restored to an approximately sinusoidal form, with a reduced amplitude and no longer restricted.

[0093] In addition, due to the distortion compensation effect of the first low-pass filter 2 and the second low-pass filter 3, and the signal swing reduction effect, the operating current of the charge pump 100 is also relatively small, thereby reducing the power consumption of the charge pump 100.

[0094] For example, please refer to Table 1 below, which shows the operating current of charge pump 100 and charge pump circuit 50.

[0095] Table 1

[0096] Charge pump 100 Charge pump circuit 50 1.41mA 1.08mA

[0097] As can be seen, compared with the charge pump circuit 50, the charge pump 100 has reduced operating current and power consumption due to the addition of the first low-pass filter 2 and the second low-pass filter 3.

[0098] In the above embodiment, the first low-pass filter 2 and the second low-pass filter 3 are both first-order RC low-pass filters, that is, only a pair of resistors and capacitors are needed to compensate for signal distortion in the charge pump through low-pass filtering, which will hardly cause the area of ​​the charge pump to increase, thus optimizing the performance of the charge pump at a lower cost.

[0099] In some embodiments, the first low-pass filter 2 further includes a first switch structure, one end of which is coupled to the first capacitor 21, and the other end of which is coupled to the first resistor 20 and the output circuit 4, respectively. The second low-pass filter 3 further includes a second switch structure, one end of which is coupled to the second capacitor 31, and the other end of which is coupled to the second resistor 30 and the output circuit 4, respectively.

[0100] In the above embodiment, by setting a first switch structure in the first low-pass filter 2 and a second switch structure in the second low-pass filter 2, the low-pass filter can be controlled to connect to the charge pump 100 using the switch structure. That is, the low-pass filter will only connect to the charge pump 100 to perform low-pass filtering when the switch structure is closed. When the switch structure is open, the charge pump 100 only adds a pair of resistors compared to the charge pump circuit 50, without any substantial change, making the risk of circuit design controllable.

[0101] The output circuit 4 is configured to generate a first output signal and a second output signal based on the first filtered signal and the second filtered signal.

[0102] In some embodiments, the voltage difference between the first output signal and the second output signal is used to reflect the pulse width difference between the first clock signal and the second clock signal. For example, if the voltage of the first output signal is greater than the voltage of the second output signal, then the pulse width of the first clock signal is greater than the pulse width of the second clock signal; if the voltage of the first output signal is less than the voltage of the second output signal, then the pulse width of the first clock signal is less than the pulse width of the second clock signal.

[0103] In some embodiments, the output circuit 4 includes a third capacitor 40 and a fourth capacitor 41.

[0104] The third capacitor 40 and the fourth capacitor 41 are energy storage capacitors in the charge pump 100 used to store energy to generate the output voltage.

[0105] The output circuit 4 is further configured to charge the third capacitor 40 according to the first filtered signal to generate a first output signal; and to charge the fourth capacitor 41 according to the second filtered signal to generate a second output signal.

[0106] In other words, the first filter signal and the second filter signal are control signals used to control the charging of the energy storage capacitor in the charge pump 100. When there is a difference between the first filter signal and the second filter signal, these differences will be reflected in the voltage difference formed by the third capacitor 40 and the fourth capacitor 41.

[0107] In some embodiments, the output circuit 4 further includes: a fifth PMOS transistor 42, a sixth PMOS transistor 43, a fifth NMOS transistor 44, a sixth NMOS transistor 45, a seventh NMOS transistor 46, an eighth NMOS transistor 47, a third resistor 48, and a fourth resistor 49.

[0108] The source of the fifth PMOS transistor 42 is coupled to the first voltage source, and the gate of the fifth PMOS transistor 42 is coupled to the other end of the first low-pass filter 2. The source of the sixth PMOS transistor 43 is coupled to the first voltage source, and the gate of the sixth PMOS transistor 43 is coupled to the other end of the second low-pass filter 3.

[0109] The drain of the fifth NMOS transistor 44, the drain of the seventh NMOS transistor 46, one end of the third capacitor 40 and one end of the third resistor 48 are coupled to the source of the fifth PMOS transistor 42, respectively. The drain of the sixth NMOS transistor 45, the drain of the eighth NMOS transistor 47, one end of the fourth capacitor 41 and one end of the fourth resistor 49 are coupled to the source of the sixth PMOS transistor 43, respectively.

[0110] The source of the fifth NMOS transistor 44, the source of the sixth NMOS transistor 45, the source of the seventh NMOS transistor 46, the source of the eighth NMOS transistor 47, the other end of the third capacitor 40, and the other end of the fourth capacitor 41 are respectively coupled to the ground terminal.

[0111] The other end of the third resistor 48 and the gate of the eighth NMOS transistor 47 are coupled to the first output terminal of the charge pump 100, and the first output signal is output from the first output terminal.

[0112] The other end of the fourth resistor 49 and the gate of the seventh NMOS transistor 46 are coupled to the second output terminal of the charge pump 100, and the second output signal is output from the second output terminal.

[0113] By setting a third resistor 48 at the first output terminal and a fourth resistor 49 at the second output terminal, a low-pass filter structure can also be formed at the output terminal of the charge pump 100 (e.g., Figure 4 As shown, the third capacitor 40 and the third resistor 48 form a low-pass filter, and the fourth capacitor 41 and the fourth resistor 49 form a low-pass filter structure, thereby optimizing the waveform of the output signal and keeping the voltage difference between the first output signal and the second output signal stable.

[0114] In some embodiments, the gate and drain of the fifth NMOS transistor 44 are coupled, that is, the drain and gate of the fifth NMOS transistor 44 are respectively coupled to the source of the fifth PMOS transistor 42. The drain and gate of the sixth NMOS transistor 45 are coupled, that is, the gate and gate of the sixth NMOS transistor 45 are respectively coupled to the source of the sixth PMOS transistor 43.

[0115] In some embodiments, the channel width of the fifth NMOS transistor 44 is the same as the channel width of the eighth NMOS transistor 47. The channel widths of the sixth NMOS transistor 45 and the seventh NMOS transistor 46 are the same.

[0116] In the above embodiment, the first filter signal provides a bias voltage to the gate of the fifth PMOS transistor 42, and the second filter signal provides a bias voltage to the gate of the sixth PMOS transistor 43. When the average values ​​of the voltages of the first filter signal and the second filter signal are inconsistent, since the sources of the fifth PMOS transistor 42 and the sixth PMOS transistor 43 are both coupled to the same voltage source (i.e., the first voltage source), the average value of the current through the fifth PMOS transistor 42 is also different from the average value of the current through the sixth PMOS transistor 43. Furthermore, since the current through the fifth PMOS transistor 42 charges the third capacitor 40, and the current through the sixth PMOS transistor 43 charges the fourth capacitor 41, the voltage generated by the energy stored in the third capacitor 40 and the voltage generated by the energy stored in the fourth capacitor 41 form a voltage difference, thereby forming a voltage difference between the first output signal and the second output signal. Furthermore, since the voltage generated by the third capacitor 40 is the bias voltage of the fifth NMOS transistor 44, the voltage generated by the fourth capacitor 41 is the bias voltage of the sixth NMOS transistor 45, the first output signal is the gate bias voltage provided by the eighth NMOS transistor 47, and the second output signal is the gate bias voltage provided by the seventh NMOS transistor 46, when the voltage generated by the third capacitor 40 and the voltage generated by the fourth capacitor 41 are different (i.e., the bias voltages provided to the fifth NMOS transistor 44 and the sixth NMOS transistor 45 are different), and there is a voltage difference between the first output signal and the second output signal (i.e., the bias voltages provided to the seventh NMOS transistor 46 and the eighth NMOS transistor 47 are different), the fifth NMOS transistor 44, the sixth NMOS transistor 45, the seventh NMOS transistor 46, and the eighth NMOS transistor 47 can achieve positive feedback for the voltage difference of the output signals, making the voltage difference between the first output signal and the second output signal more obvious.

[0117] The technical solution provided in this application provides that by designing a low-pass filter (first low-pass filter 2 and second low-pass filter 3) in the charge pump 100 to compensate for the distortion of the intermediate signal (first intermediate signal and second intermediate signal) output by the input circuit 1, the output circuit 4 can generate an output signal (first output signal and second output signal) based on the filtered signal (first filtered signal and second filtered signal) output by the low-pass filter, thereby optimizing the performance of the charge pump 100.

[0118] The following examples illustrate the performance optimization achieved by the charge pump 100 in this application compared to the charge pump circuit 50.

[0119] For example, in the charge pump 100 of the above embodiment, a method such as Figure 5 The first and second filter signals shown are used to provide bias voltage to the output circuit 4, which can be used to obtain the following: Figure 6 The first output signal (light-colored line) and the second output signal (dark-colored line) are shown.

[0120] Since the first filter signal and the second filter signal can retain the pulse information of the first clock signal and the second clock signal of the input charge pump 100 relatively completely, when there is a pulse width difference between the first clock signal and the second clock signal, the output circuit 4 can generate an output signal with a more obvious voltage difference based on the first filter signal and the second filter signal.

[0121] For example, please refer to Figure 7 This illustration shows a schematic diagram comparing the output signals of charge pump circuit 50 and charge pump 100 under the same input signal, according to an embodiment of this application. In this example, the input signals of charge pump circuit 50 and charge pump 100 are both a first clock signal and a second clock signal with a pulse width difference of 2 ps.

[0122] exist Figure 7 In this circuit, the output signals below 400mV are the first and second output signals generated by charge pump 100, while the output signals above 400mV are the third and fourth output signals generated by charge pump circuit 50. It is evident that the voltage difference between the first and second output signals is greater than the voltage difference between the third and fourth output signals. Therefore, when both are used to identify the pulse width difference between the first and second clock signals, charge pump 100 achieves better performance.

[0123] For example, please refer to Table 2 below, which shows the minimum voltage difference between the third and fourth output signals of the charge pump circuit 50, the minimum voltage difference between the first and second clock signals of the charge pump 100, and the gain of the minimum voltage difference of the charge pump 100 output relative to the minimum voltage difference of the charge pump circuit 50 when the input signals are both the first clock signal and the second clock signal, and the pulse width difference between the first clock signal and the second clock signal of the charge pump 100 is 2 ps.

[0124] Table 2

[0125]

[0126] It can be seen that, in the worst case (i.e., when the output voltage difference is minimized in multiple experiments), the voltage difference output by charge pump 100 is 2.833 times that output by charge pump circuit 50, which meets the standard of greater than or equal to 8mV and achieves a significant performance improvement.

[0127] Please refer to Figure 8 The diagram illustrates a memory provided in one embodiment of this application. The memory 200 includes a memory cell array 110 and peripheral circuitry 120, the peripheral circuitry 120 including a charge pump 100.

[0128] In some embodiments, the memory 200 includes a plurality of banks and peripheral circuitry 120. Each bank includes a plurality of storage cells arranged in an array, i.e., each bank includes at least one storage cell array 110.

[0129] In addition to the charge pump 100 described above, the peripheral circuit 120 may also include a decoder (row decoder, column decoder), input / output controller, multiplexer, sense amplifier, word line driver, and any other circuits configured to operate on the memory cell or to control operations on the memory cell, which is not limited in this application.

[0130] In some embodiments, please refer to Figure 9 The peripheral circuit 120 also includes: PFD (Phase Frequency Detector) 101 and comparator 102.

[0131] In some embodiments, the peripheral circuitry 120 includes a DCM (Duty Cycle Monitor). The DCM includes the aforementioned PFD 101, charge pump 100, and comparator 102, and is configured to monitor the duty cycle of the clock signal in the memory 200.

[0132] In some embodiments, the DCM is configured to detect the relationship between the WCK (Write Clock) signal of the memory 200 and the ideal duty cycle.

[0133] In some embodiments, the ideal duty cycle is 50%.

[0134] PFD101 is configured to: obtain a first clock signal and a second clock signal for the input charge pump based on multiple frequency division signals of the WCK signal in the memory; the frequencies of the first clock signal and the second clock signal are the same as the frequency of the WCK signal, and the duty cycles of the first clock signal and the second clock signal are related to the duty cycle of the WCK signal.

[0135] The WCK signal is used to control the timing of write operations in memory. Multiple frequency-divided signals of the WCK signal refer to multiple signals with different frequencies derived from the WCK signal. For example, please refer to... Figure 9 CK0, CK90, CK180, and CK270 are four frequency division signals with different frequencies obtained based on the WCK signal.

[0136] In some embodiments, the duty cycle of the first clock signal is the same as that of the WCK signal, and the first and second clock signals are complementary. Therefore, by detecting the pulse width difference between the first and second clock signals, the relationship between the WCK signal and the ideal duty cycle can be identified.

[0137] Comparator 102 is configured to obtain a comparison result signal based on the first and second output signals of charge pump 100. The comparison result signal is used to indicate the relationship between the duty cycle of the WCK signal and the ideal duty cycle.

[0138] In some embodiments, comparator 102 is configured to compare the voltage of a first output signal and the voltage of a second output signal to obtain a comparison result signal.

[0139] For example, when the voltage of the first output signal is greater than the voltage of the second output signal, the comparison result signal output by comparator 102 indicates that the duty cycle of the WCK signal is greater than the ideal duty cycle. When the first output signal is less than the second output signal, the comparison result signal output by comparator 102 indicates that the duty cycle of the WCK signal is less than the ideal duty cycle.

[0140] In the above embodiment, by designing PFD101 to restore multiple frequency division signals of WCK into a first clock signal and a second clock signal that can reflect the duty cycle of the WCK signal, the duty cycle of the WCK signal can be detected based on the frequency division signals of the WCK signal when it is inconvenient to directly detect the WCK signal. This allows the DCM to be placed close to the memory cell array 110, rather than close to the location where the WCK signal is generated, thereby improving the actual effectiveness of the DCM in detecting the duty cycle of the WCK signal.

[0141] In some embodiments, the peripheral circuit 120 further includes a duty cycle adjustment circuit.

[0142] In some embodiments, the duty cycle adjustment circuit is coupled to the output of comparator 102.

[0143] The duty cycle adjustment circuit is configured to adjust the duty cycle of the WCK signal based on the comparison result signal output by the comparator. For example, if the comparison result signal indicates that the duty cycle of the WCK signal is greater than the ideal duty cycle, the duty cycle adjustment circuit decreases the duty cycle of the WCK signal; if the comparison result signal indicates that the duty cycle of the WCK signal is less than the ideal duty cycle, the duty cycle adjustment circuit increases the duty cycle of the WCK signal.

[0144] The charge pump 100 provided in this application can output a voltage difference greater than 0.8mV when the pulse width difference of the input clock signal is greater than or equal to 2ps, thereby improving the accuracy of DCM detection of the duty cycle of the WCK signal. It is particularly suitable for DRAM (Dynamic Random Access Memory) where high precision control of the duty cycle of the WCK signal is required. However, it should be understood that the function of the charge pump 100 is not limited to the detection of the WCK signal duty cycle, and the memory 200 is not limited to DRAM. For example, the memory 200 can also be SRAM (Static Random Access Memory), NAND Flash (Not AND Flash), NOR Flash (Not OR Flash), or any other memory including a charge pump; this application does not limit this.

[0145] In some embodiments, a storage system is also provided, which may include a controller and a memory provided in any embodiment of the present application, wherein the controller is coupled to the memory to control the memory to store data.

[0146] Please refer to Figure 10This illustration shows a structural block diagram of an electronic device provided in one embodiment of this application. The electronic device 1000 includes a storage system 250 and a host 300. The storage system 250 includes a controller 350 and a memory 200 provided in any embodiment of this application. The electronic device 1000 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage system therein. The host 300 can be a processor of the electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 300 can be configured to send data to or receive data from the memory 200. In some embodiments, the controller 350 is coupled to the memory 200 and the host 300 and is configured to control the memory 200. The controller 350 manages data stored in the memory 200 and communicates with the host 300. The controller 350 can be configured to control the operation of the memory 200, such as read, write, and refresh operations. The controller 350 can also be configured to manage various functions regarding data stored or to be stored in the memory 200, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the controller 350 is also configured to determine the maximum memory capacity that the electronic device can use, the number of memory groups, the memory type and speed, the memory particle data depth and data width, and other important parameters. Any other suitable functions can also be performed by the controller 350. The controller 350 can communicate with external devices (e.g., the host 300) according to a specific communication protocol.For example, the controller 350 can communicate with external devices through at least one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integration Design Environment (IDE), FireWire, etc. Furthermore, it should be noted that the memory 200 coupled to the controller 350 can be one or more; this application does not limit this.

[0147] Please refer to Figure 11 This illustration shows a structural block diagram of an electronic device provided in another embodiment of this application. The electronic device 1100 includes a storage system 400, a host 300, and a memory 200 provided in any embodiment of this application. The host 300 may be a processor of the electronic device, such as a CPU, and is coupled to both the memory 200 and the storage system 400. In some embodiments, the memory 200 may be memory used to temporarily store computational data of the processor (host 300), and the memory 200 may be volatile memory (VM), such as DRAM. The storage system 400 may include non-volatile memory (NVM) different from the memory 200, such as flash memory. The storage system 400 may also include a controller coupled to the non-volatile memory, such as a flash memory controller. In some embodiments, the storage system 400 may also include a controller for the memory 200, such as a DRAM controller, which can be used to control the temporary storage of data stored in the storage system 400 into the memory 200. Additionally, it should be noted that the memory 200 coupled to the host 300 can be one or more, and this application does not limit this.

[0148] In summary, the memory provided in this application embodiment can be coupled to the host via a controller or directly to the host, and this application does not limit this.

[0149] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0150] The above description is an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A charge pump, characterized in that, The charge pump (100) includes: an input circuit (1), a first low-pass filter (2), a second low-pass filter (3), and an output circuit (4); one end of the first low-pass filter (2) is coupled to the input circuit (1), and the other end of the first low-pass filter (2) is coupled to the output circuit (4); one end of the second low-pass filter (3) is coupled to the input circuit (1), and the other end of the second low-pass filter (3) is coupled to the output circuit (4); The input circuit (1) is configured to output a first intermediate signal and a second intermediate signal; The first low-pass filter (2) is configured to filter the first intermediate signal to obtain a first filtered signal; The second low-pass filter (3) is configured to filter the second intermediate signal to obtain a second filtered signal; The output circuit (4) is configured to generate a first output signal and a second output signal based on the first filtered signal and the second filtered signal.

2. The charge pump according to claim 1, characterized in that, The first low-pass filter (2) includes M resistors and M capacitors, and the second low-pass filter (3) includes N resistors and N capacitors, where M and N are both positive integers, and the M capacitors and the N capacitors are respectively coupled to the ground terminal.

3. The charge pump according to claim 1, characterized in that, The first low-pass filter (2) includes a first resistor (20) and a first capacitor (21); one end of the first resistor (20) is coupled to the input circuit (1), and the other end of the first resistor (20) is coupled to the output circuit (4); one end of the first capacitor (21) is coupled to the ground terminal, and the other end of the first capacitor (21) is coupled to the first resistor (20) and the output circuit (4) respectively. The second low-pass filter (3) includes a second resistor (30) and a second capacitor (31); one end of the second resistor (30) is coupled to the input circuit (1), and the other end of the second resistor (30) is coupled to the output circuit (4); one end of the second capacitor (31) is coupled to the ground terminal, and the other end of the second capacitor (31) is coupled to the second resistor (30) and the output circuit (4) respectively.

4. The charge pump according to claim 3, characterized in that, The first low-pass filter (2) further includes a first switch structure, one end of which is coupled to the first capacitor (21), and the other end of which is coupled to the first resistor (20) and the output circuit (4). The second low-pass filter (3) further includes a second switch structure, one end of which is coupled to the second capacitor (31), and the other end of which is coupled to the second resistor (30) and the output circuit (4).

5. The charge pump according to claim 1, characterized in that, The input circuit (1) includes a first input structure (5) and a second input structure (6). The number of metal oxide semiconductor MOS transistors included in the first input structure (5) is the same as the number of MOS transistors included in the second input structure (6). One end of the first low-pass filter (2) is coupled to the first input structure (5), and one end of the second low-pass filter (3) is coupled to the second input structure (6).

6. The charge pump according to claim 5, characterized in that, The first input structure (5) includes: a first current source (10), a first N-type metal-oxide-semiconductor NMOS transistor (12), and a second NMOS transistor (13); the second input structure (6) includes: a second current source (11), a third NMOS transistor (14), and a fourth NMOS transistor (15); The first current source (10) is coupled to the source of the first NMOS transistor (12) and the source of the second NMOS transistor (13), respectively; the second current source (11) is coupled to the source of the third NMOS transistor (14) and the source of the fourth NMOS transistor (15), respectively. The gate of the first NMOS transistor (12) and the gate of the third NMOS transistor (14) are respectively coupled to the first input terminal of the charge pump (100); The gates of the second NMOS transistor (13) and the fourth NMOS transistor (15) are respectively coupled to the second input terminal of the charge pump (100).

7. The charge pump according to claim 6, characterized in that, The first input structure (5) further includes a first P-type metal-oxide-semiconductor PMOS transistor (16) and a second PMOS transistor (17); the second input structure (6) further includes a third PMOS transistor (18) and a fourth PMOS transistor (19); The source of the first PMOS transistor (16), the source of the second PMOS transistor (17), the source of the third PMOS transistor (18), and the source of the fourth PMOS transistor (19) are respectively coupled to the first voltage source; The drain of the first NMOS transistor (12), the drain of the third NMOS transistor (14), the drain of the first PMOS transistor (16), the drain of the second PMOS transistor (17), and the gate of the third PMOS transistor (18) are respectively coupled to one end of the first low-pass filter (2). The drain of the second NMOS transistor (13), the drain of the fourth NMOS transistor (15), the gate of the second PMOS transistor (17), the drain of the third PMOS transistor (18), and the drain of the fourth PMOS transistor (19) are respectively coupled to one end of the second low-pass filter (3).

8. The charge pump according to claim 1, characterized in that, The output circuit includes: a third capacitor (40) and a fourth capacitor (41); The output circuit (4) is further configured to charge the third capacitor (40) according to the first filtered signal to generate the first output signal; and to charge the fourth capacitor (41) according to the second filtered signal to generate the second output signal.

9. The charge pump according to claim 8, characterized in that, The output circuit (4) further includes: a fifth PMOS transistor (42), a sixth PMOS transistor (43), a fifth NMOS transistor (44), a sixth NMOS transistor (45), a seventh NMOS transistor (46), an eighth NMOS transistor (47), a third resistor (48), and a fourth resistor (49); The source of the fifth PMOS transistor (42) is coupled to the first voltage source, and the gate of the fifth PMOS transistor (42) is coupled to the other end of the first low-pass filter (2); the source of the sixth PMOS transistor (43) is coupled to the first voltage source, and the gate of the sixth PMOS transistor (43) is coupled to the other end of the second low-pass filter (3); The drain of the fifth NMOS transistor (44), the drain of the seventh NMOS transistor (46), one end of the third capacitor (40) and one end of the third resistor (48) are respectively coupled to the source of the fifth PMOS transistor (42), and the drain of the sixth NMOS transistor (45), the drain of the eighth NMOS transistor (47), one end of the fourth capacitor (41) and one end of the fourth resistor (49) are respectively coupled to the source of the sixth PMOS transistor (43); The source of the fifth NMOS transistor (44), the source of the sixth NMOS transistor (45), the source of the seventh NMOS transistor (46), the source of the eighth NMOS transistor (47), the other end of the third capacitor (40), and the other end of the fourth capacitor (41) are respectively coupled to the ground terminal; The other end of the third resistor (48) and the gate of the eighth NMOS transistor (47) are respectively coupled to the first output terminal of the charge pump (100), and the first output signal is output from the first output terminal; The other end of the fourth resistor (49) and the gate of the seventh NMOS transistor (46) are respectively coupled to the second output terminal of the charge pump (100), and the second output signal is output from the second output terminal.

10. The charge pump according to any one of claims 1 to 9, characterized in that, The input circuit (1) is further configured to process a first clock signal and a second clock signal input to the charge pump (100) to output a first intermediate signal and a second intermediate signal, the first clock signal and the second clock signal being complementary and having the same frequency.

11. A memory, characterized in that, The memory includes a memory cell array and peripheral circuitry, the peripheral circuitry including a charge pump as described in any one of claims 1 to 10.

12. The memory according to claim 11, characterized in that, The peripheral circuit also includes a frequency and phase detector (PFD) and a comparator, wherein the PFD is coupled to the input terminal of the charge pump and the comparator is coupled to the output terminal of the charge pump. The PFD is configured to: obtain a first clock signal and a second clock signal input to the charge pump based on multiple frequency division signals of the write clock WCK signal of the memory; the frequencies of the first clock signal and the second clock signal are the same as the frequency of the WCK signal, and the duty cycles of the first clock signal and the second clock signal are related to the duty cycle of the WCK signal; The comparator is configured to obtain a comparison result signal based on the first and second output signals of the charge pump, the comparison result signal being used to indicate the relationship between the duty cycle of the WCK signal and the ideal duty cycle.

13. A storage system, characterized in that, The storage system includes a controller and a memory as described in claim 11 or 12, the controller being coupled to the memory to control the memory to store data.

14. An electronic device, characterized in that, The electronic device includes a host and a storage system coupled to the host, the storage system including a controller and a memory as described in claim 11 or 12, the controller being coupled to the memory to control the memory to store data.

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