A wideband full-duplex receiver sharing interference cancellation circuitry

Abstract

The present application belongs to the technical field of radio frequency microwave integrated circuit design, and specifically relates to a wideband full duplex receiver sharing an interference cancellation circuit. The full duplex receiver of the present application is composed of a receiver module and an interference cancellation circuit. The receiver comprises a transconductance, a mixer, a transimpedance amplifier and a frequency conversion loop. The interference cancellation circuit comprises an input matching network, an input down-mixer, a quadrature selection phase shifter and a baseband variable gain low-pass filter. The interference cancellation circuit transfers the adjustment of the delay and gain in the radio frequency domain to the baseband, so that the overall area and power consumption are small, and the delay amount of 3.86-8.33 ns can be realized in a wide radio frequency band of 0.5-3.5 GHz. Meanwhile, the interference cancellation circuit is synthesized by the mixer in the frequency conversion loop of the receiver to form a double-path cancellation mode, which avoids the interference cancellation circuit being directly connected to the front end of the receiver module, and the noise figure deterioration of the receiver module is very small, only 0.9-1.2 dB.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency microwave integrated circuit design technology, and specifically relates to a broadband full-duplex receiver with a shared interference cancellation circuit. Background Technology

[0002] With the rapid development of wireless communication standards, the amount of data in wireless communication services has exploded, making the wireless spectrum extremely congested. To better utilize the sub-6GHz frequency bands with better propagation characteristics, full-duplex communication technology has been proposed. However, although full-duplex offers advantages in signal transmission performance compared to half-duplex, implementing a full-duplex system also presents significant challenges. Due to the simultaneous transmission and reception characteristics of a full-duplex system, filtering out self-interference signals in a typical full-duplex transceiver system cannot rely on low-pass or band-pass filters as is done with channel selection at the receiver front end. This necessitates the application of self-interference cancellation technology in full-duplex systems.

[0003] With the development of chip-level full-duplex receivers, some intractable problems have emerged. Firstly, the design of the cancellation circuit in a full-duplex system has become increasingly challenging, requiring it to simulate the signal transmission characteristics in the channel as accurately as possible to completely eliminate transmitter leakage interference after reconstruction. Simultaneously, the on-chip cancellation circuit must maintain adjustability as much as possible, placing high demands on the accuracy, range, and method of adjustment (amplitude, phase, delay). Secondly, the design of the self-interference cancellation circuit must ensure sufficient cancellation depth while minimizing its impact on the receiver front-end itself (mainly including gain and noise effects) to guarantee the overall performance of the full-duplex receiver system. Summary of the Invention

[0004] The purpose of this invention is to provide a broadband full-duplex receiver with shared interference cancellation based on a high delay cancellation circuit.

[0005] The broadband full-duplex receiver with shared interference cancellation circuit provided by this invention has the structure shown in the attached figure. Figure 1 As shown. It mainly consists of a receiver module and an interference cancellation circuit module, wherein:

[0006] (1) The receiver module mainly includes: a transconductance unit, a mixer, a transimpedance amplifier, and a frequency conversion loop, the structure of which is described in [reference needed]. Figure 2 As shown. Wherein:

[0007] The transconducting unit (G) M ), used to amplify radio frequency signals and provide a lower noise figure; specifically, transconductance unit (G MIt forms the receiver input amplifier stage, which performs broadband amplification on the input RF signal, providing a certain gain while contributing a small noise figure, and minimizing distortion when large signals are input.

[0008] The mixer is used to mix radio frequency signals and downmix them to baseband.

[0009] A transimpedance amplifier (TIA) is used to filter and amplify the down-mixed baseband signal to ultimately form an analog baseband signal.

[0010] The frequency conversion loop is used for input matching of the receiver front end;

[0011] In the receiver, the low-noise transconductance unit (G) at the front end M It does not have input matching capability; the frequency conversion loop includes a matching network composed of input resistors and an upmixer; the inverted signal from the transimpedance amplifier (TIA) passes through the matching network, is upmixed again, and is connected to the input of the receiving front end, thereby realizing input matching of the receiving front end.

[0012] (2) The interference cancellation circuit includes an input matching network and an input downmixer, a quadrature selection phase shifter, and a variable gain active low-pass filter (LPF) unit in the baseband section, the specific composition of which is shown in the attached figure. Figure 3 As shown; where:

[0013] The two inputs (TX) of the interference cancellation circuit P TX N () is a pair of differential input ports that receive differential input signals converted by an off-chip balun;

[0014] The input matching network, composed of differential resistors R1, is connected between the differential inputs of the cancellation circuit to match the input RF signal before transmitting it to the input downmixer. The differential RF input signal is downmixed by a passive mixer controlled by four-phase clocks φ0 to φ3, resulting in two orthogonal baseband differential signals (I and Q). A differential capacitor C1, located between the orthogonal differential paths, serves as a delay adjustment unit for the baseband section. After downmixing and initial delay adjustment, the signal enters a quadrature selection phase shifter, which performs quadrature selection on the downmixed I and Q quadrature signals. The phase-selected signal then enters a baseband variable gain active low-pass filter (LPF) unit, where the I and Q low-pass filter units respectively perform gain control and further delay adjustment on the quadrature signals. The adjusted signal is then output to the receiver module as an orthogonal differential signal for self-interference cancellation.

[0015] The variable gain active low-pass filter unit (LPF) is used for amplitude adjustment and signal bandwidth determination; this variable gain active low-pass filter unit is a Gm-C filter based on an open-loop transconductance amplifier, consisting of an input differential capacitor C2 and a variable gain fully differential transconductance unit (Gm-C). M_LPF ) and variable output differential capacitor C L It is cascaded together. The capacitor C is among them. L As one of the capacitors used to adjust the baseband delay, the transconductance G M_LPF This allows adjustment of the baseband gain. Fully differential transconductance unit (G M_LPF It consists of a 6-bit complementary CMOS transconductance array controlled by switches. The specific circuit structure of each unit is shown in the attached figure. Figure 4 As shown. In the fully differential transconductance unit (G M_LPF In this circuit, the gates and drains of NMOS transistors M1-M2 and PMOS transistors M3-M4 are connected in parallel, serving as the input and output nodes of the transconductance unit, respectively. The sources of NMOS transistors M1-M2 are grounded via a switch, and the sources of PMOS transistors M3-M4 are connected to the power supply via a switch. This connection forms a complementary transconductance aligning unit, enabling the circuit to achieve greater transconductance with a smaller current. Resistor Rf is a feedback self-biasing resistor connected between the input and output of the transconductance unit, ensuring that the DC level of both the output and input common-mode voltages is stabilized at 1 / 2 of the power supply voltage.

[0016] The broadband full-duplex receiver designed in this invention has the following connection method and specific implementation method, as shown in the appendix. Figure 1 and attached Figure 5 As shown, the interference cancellation circuit down-mixes the input signal and then reconstructs it in the baseband section. The reconstructed signal is then introduced into the frequency conversion loop in the receiver module for self-interference cancellation. Specifically, the interference cancellation circuit and the up-mixer in the frequency conversion loop form cancellation path I, which introduces the reconstructed signal into the RF input of the receiver module for self-interference cancellation. The interference cancellation circuit and the matching network in the frequency conversion loop form cancellation path II, which also introduces the reconstructed signal into the RF input of the receiver module for self-interference cancellation. This interference cancellation process uses only one cancellation circuit module to implement both cancellation paths; that is, cancellation path I and cancellation path II share a single interference cancellation circuit. This invention is called a broadband full-duplex receiver with a shared interference cancellation circuit.

[0017] In the full-duplex receiver proposed in this invention, the delay and amplitude adjustment of the interference cancellation circuit are switched to baseband adjustment, resulting in a smaller overall area and lower power consumption. Furthermore, compared to methods using passive RC or active Gm-RC to achieve RF delay, the cancellation circuit in this invention can achieve a larger delay in the RF domain. Additionally, the shared cancellation method avoids directly connecting the cancellation circuit to the front end of the receiver module, thus providing dual-path cancellation while minimizing the degradation of the receiver module's noise figure. Attached Figure Description

[0018] Figure 1 This is a block diagram of the broadband full-duplex receiver structure of the shared interference cancellation circuit of the present invention.

[0019] Figure 2 This is a structural diagram of the receiver module in the full-duplex receiver of the present invention.

[0020] Figure 3 This is a structural diagram of the interference cancellation circuit module in the full-duplex receiver of the present invention.

[0021] Figure 4 This is a structural diagram of the active filter in the interference cancellation circuit module of the present invention.

[0022] Figure 5 This is a detailed structural diagram of the broadband full-duplex receiver based on the shared interference cancellation circuit of the present invention.

[0023] Figure 6 This is a schematic diagram illustrating the principle of the quadrant selection phase shifter in this invention.

[0024] Figure 7 This represents the maximum delay result generated by the elimination circuit module in the radio frequency domain in a specific embodiment of the present invention.

[0025] Figure 8 This is the self-interference cancellation performance result in a specific example of the present invention.

[0026] Figure 9 This is the result of the receiver module noise figure before and after interference cancellation in a specific embodiment of the present invention. Detailed Implementation

[0027] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0028] As attached Figure 1 The diagram shown is a block diagram of the broadband full-duplex receiver based on shared cancellation proposed in this invention. It mainly includes a receiver module and a cancellation circuit module.

[0029] The specific implementation of the receiver module is shown in the appendix. Figure 2As shown. The specific components are: a transconductance unit as the input amplification stage, a down-mixer, a transimpedance amplifier (TIA) in the baseband section, and a frequency conversion loop. The frequency conversion loop consists of a matching circuit and an up-mixer, where the matching network is composed of resistor R. FB Composition. Due to the transconductance unit G M Since no input matching is provided, its input impedance is very high. Therefore, near the local oscillator frequency of the LO, the overall impedance of the receiver can be derived through the mapping effect of the passive mixer in the frequency conversion loop, and can be expressed as:

[0030]

[0031] Where R F and C F These are the feedback resistor and feedback capacitor values ​​of the transimpedance amplifier TIA, respectively. From equation (1), it can be seen that the impedance of the baseband transimpedance amplifier TIA is mapped to the receiver input through the frequency conversion loop. Since the baseband gain characteristic is a low-pass filter characteristic, the receiver input port will exhibit a low impedance characteristic near the local oscillator frequency. The cutoff frequency of this low impedance is the same as the cutoff frequency of TIA, thus it is a narrowband match. However, this match can be adjusted with the LO frequency throughout the entire operating frequency band, exhibiting frequency-agile characteristics.

[0032] The specific implementation of the interference cancellation circuit module is shown in the appendix. Figure 3 As shown. The specific components are: an input matching network, an input down-mixer, a quadrature selection phase shifter unit, and a baseband variable gain low-pass filter unit. The input matching network consists of differential resistors R1, ensuring good matching of the input RF signal within the required frequency band and reducing return loss. The input down-mixer consists of a passive mixer controlled by four-phase clocks φ0 to φ3, used to down-mix the input RF signal to baseband. The quadrature selection phase shifter consists of a quadrature selector composed of a set of switches, specifically implemented by using four switches to determine which quadrant the separated and reconstituted I and Q signals will fall into. The baseband variable gain low-pass filter unit consists of a Gm-C filter composed of an open-loop transconductance amplifier (e.g., ...). Figure 4 As shown, the baseband signals of the I and Q channels are filtered, and controllable delay and gain adjustments are performed simultaneously.

[0033] In the full-duplex receiver proposed in this invention, the RF signal input to the cancellation circuit is matched by the input matching resistor R1. The input signal is then mixed to the baseband by a four-phase double-balanced downmixer and then upmixed to the receiver input by a synchronized four-phase single-balanced mixer. The baseband adjustment circuit is divided into three parts: capacitor C1, a phase-shifting section, and an active filter. The phase-shifting section is implemented by a quadrature selection phase shifter composed of a set of switches. Specifically, it uses four switching transistors to determine which quadrant the separated and reconstituted I and Q signals will fall into. The principle of phase shifting combined with the low-pass filter is shown in the attached figure. Figure 6 As shown, the quadrature phase shifter selects the polarity of the I and Q signals, while the variable gain active low-pass unit controls the signal amplitude. The combination of these two technologies enables phase shift characteristics in different quadrants. When both I and Q signals are in-phase, the final synthesized signal will be in the first quadrant. In this case, precise phase adjustment can be determined by adjusting the amplitudes of the I and Q signals separately, with a phase adjustment range of 0° to 90°. When the I and Q signals are in-phase and out-of-phase respectively, the final synthesized signal will be in the fourth quadrant, with a phase adjustment range of 270° to 360°.

[0034] In the cancellation circuit of the full-duplex receiver, the main function of the active filter is to adjust the amplitude and determine the signal bandwidth; its filtering characteristics determine the out-of-band characteristics of the cancellation circuit. The variable gain filter unit in the cancellation circuit proposed in this invention is based on a Gm-C filter design using a transconductance amplifier, as shown in the attached figure. Figure 4 As shown, transconductance unit G M_LPF It consists of a 6-bit complementary CMOS transconductance array controlled by switches, used as a gain adjustment method for the baseband signal, while capacitor C... L As one of the capacitors used to adjust the baseband delay, it works together with capacitor C1 to adjust the delay. If R... sw and R p The equivalent resistances R are respectively represented as the downmixer and the phase shifter. in C1 and C2 are the equivalent input resistance and equivalent input capacitance before the transconductance unit in the low-pass filter. L This is the control capacitor for the time delay. The transfer function of the entire cancellation circuit can be expressed as:

[0035]

[0036] It can be seen that the amplitude adjustment of the elimination circuit proposed in this invention can be achieved by adjusting the transconductance value G of the transconductance unit. m_LPF This can be achieved, and the delay can be adjusted via capacitors C1 and C2. L Control, its delay can be expressed as:

[0037] τ=R in R sw(C1+C2)+R p (R sw C1+R in C2)+R L C L (3)

[0038] In equation (3), there are two delay terms for C1, and part of the delay is generated by the large input resistance of the transconductance unit and the capacitor C1. Therefore, the baseband section can use the capacitor C1 with a large capacitance to achieve a large delay.

[0039] The specific implementation of the broadband full-duplex receiver based on the shared interference cancellation circuit proposed in this invention is attached. Figure 5 As shown. The output of the baseband section of the cancellation circuit achieves shared cancellation by sharing an upmixer module with the receiver's frequency conversion loop. It can be observed that the full-duplex receiver in this invention also forms two cancellation paths after the cancellation circuit module and the receiver module's frequency conversion loop share an upmixer. The first path is the RF domain cancellation path formed by the shared cancellation circuit module through the upmixer to the RF input port, which is an auxiliary path. Figure 5 The blue cancellation path I. By adjusting the phase, delay, and gain of the baseband section in the shared cancellation circuit, the RF domain self-interference signal can be reconstructed, thus achieving cancellation. Another path is the baseband domain cancellation path from the feedback resistor in the frequency conversion loop of the shared cancellation circuit module to the output of the transconductance amplifier (TIA), as shown in the attached diagram. Figure 5 The green cancellation path II. Since the two paths share a single cancellation circuit, this can be called a shared cancellation method. Besides generating dual cancellation paths for greater cancellation capacity, another advantage of shared cancellation is that it avoids directly connecting the RF domain cancellation circuit to the receiver front end, reducing the significant degradation of the receiver's noise figure.

[0040] In the specific examples described above, the full-duplex receiver based on the shared cancellation method can ultimately operate in the 0.5–3.5 GHz frequency band, exhibiting a wide RF operating range. Simultaneously, within the 0.5–3.5 GHz band, the cancellation circuit achieves high latency with relatively low power consumption and area. Compared to previous self-interference cancellation structures based on time-domain reconstruction, the cancellation circuit of this invention shifts the latency adjustment to the baseband domain, enabling the maximum latency of the entire module to reach 3.86–8.33 ns within the operating frequency band, as shown in the appendix. Figure 7 As shown, this invention overcomes the problem that relying solely on RC to achieve delays at high frequencies in the radio frequency band cannot reach nanosecond levels. Regarding full-duplex performance, the shared cancellation method proposed in this invention achieves dual-path cancellation using only one cancellation module. Within a bandwidth of 0.5–3.5 GHz, it can achieve self-interference cancellation performance better than 25 dB at different carrier frequencies, as shown in the attached figure. Figure 8As shown. Meanwhile, due to the characteristics of the shared cancellation method, the noise figure degradation of the receiver front-end caused by the cancellation circuit is only 0.9–1.2 dB, as shown in the attached figure. Figure 9 As shown.

Claims

1. A wideband full-duplex receiver sharing interference cancellation circuitry, characterized by, The receiver module and the interference cancellation circuit module Consist of: The receiver module, comprising: a transconductance unit, a mixer, a transimpedance amplifier and a frequency conversion loop, wherein: The transconductance unit (G M ) is used for amplifying radio frequency signals and providing a small noise coefficient; specifically, the transconductance unit (G M ) constitutes a receiver input amplification stage, amplifies the input radio frequency signals in a wide band, and tries to be as little distorted as possible when the amplified signals are input. The mixer is used for mixing the radio frequency signal and down-converting it to baseband; The transimpedance amplifier (TIA) is used for filtering and amplifying the down-converted baseband signal to form an analog baseband signal finally; The frequency conversion loop is used for input matching of the receiver front end; The frequency conversion loop comprises a matching network composed of input resistors and an up-mixer; the in-phase signal from the transimpedance amplifier (TIA) passes through the matching network, is up-converted again and is connected to the input of the receiver front end, so as to realize input matching of the receiver front end; The interference cancellation circuit comprises an input matching network and an input down-converter, a quadrature selection phase shifter and a variable gain active low pass filter unit (LPF) of the baseband part, wherein: The two inputs of the interference cancellation circuit are a pair of differential input ports which receive a differential input signal converted by a balun outside the chip; The input matching network is composed of a differential resistor R1 and is connected between the differential inputs of the cancellation circuit to match the input radio frequency signal and then transmit the signal to the input down-converter; the differential radio frequency input signal is down-converted into two quadrature baseband differential signals after passing through the passive mixer controlled by the four-phase clock φ0-φ3; a differential capacitor C1 is located between the quadrature differential paths as a delay adjustment unit of the baseband part; the signal after down-conversion and preliminary delay adjustment enters the quadrature selection phase shifter which is used for quadrant selection of the IQ quadrature signal after down-conversion; the signal after phase selection enters the baseband variable gain active low pass filter unit (LPF) which controls the gain and further delays the quadrature signal in the IQ two paths; the signal after the above adjustment is output to the receiver module in the form of quadrature differential signal for self-interference cancellation.

2. The wide-band full-duplex receiver sharing interference cancellation circuitry of claim 1, wherein, The variable gain active low pass filter unit (LPF) is used for amplitude adjustment and signal bandwidth determination; the variable gain active low pass filter unit is a Gm-C filter based on an open loop transconductance amplifier, which is composed of an input differential capacitor C2, a variable gain full differential transconductance unit (G M_LPF ) and a variable output differential capacitor C L ; wherein: Capacitor C L As one of the capacitors to adjust the amount of delay of the baseband part, a fully differential transconductance unit (G M_LPF ) is used to adjust the gain size of the baseband part; the fully differential transconductance unit (G M_LPF ) is composed of a 6-bit complementary CMOS transconductance array controlled by a switch; wherein the gates and drains of NMOS tubes M1-M2 and PMOS tubes M3-M4 are connected in parallel, respectively as the input and output nodes of the transconductance unit; the sources of NMOS tubes M1-M2 are connected to ground through a switch, and the sources of PMOS tubes M3-M4 are connected to the power supply through a switch, thus connected to form a complementary form of transconductance array unit, so that the circuit obtains greater transconductance under smaller current; the resistance Rf is a feedback type self-biasing resistance, connected between the input and output of the transconductance unit, so that the output and input common mode DC level can be stabilized at 1 / 2 of the power supply voltage.

3. The wide-band full-duplex receiver sharing interference cancellation circuitry of claim 2, wherein, The interference cancellation circuit reconstructs the input signal after down-conversion in the baseband part and introduces the reconstructed signal into the frequency conversion loop in the receiver module for self-interference cancellation; wherein, the interference cancellation circuit and the up-mixer in the frequency conversion loop form the cancellation path I to introduce the reconstructed signal into the radio frequency input of the receiver module for self-interference cancellation; the interference cancellation circuit and the matching network in the frequency conversion loop form the cancellation path II to introduce the reconstructed signal into the radio frequency input of the receiver module for self-interference cancellation; only one interference cancellation circuit is used to realize the two cancellation paths, i.e. the cancellation path I and the cancellation path II share one interference cancellation circuit in the interference cancellation process.

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