Ultrahigh-gain photovoltaic interface converter and high-voltage charging device for building integrated photovoltaics (BIPV) system

Abstract

The invention belongs to the technical field of DC-DC boost, and relates to an ultrahigh-gain photovoltaic interface converter for a BIPV system and a high-voltage charging device. In the converter, a positive electrode of an input filter capacitor is connected with two inductors, and a negative electrode is connected with source electrodes of two switch tubes; the other end of the first inductor is connected to the negative electrode of the first capacitor, the drain electrode of the first switching tube and the relay-current-limiting resistor branch; the other end of the second inductor is connected to a fourth capacitor cathode, a first diode anode and a second switch tube drain; the anode of the first capacitor is connected with the cathode of the second capacitor, the cathode of the first diode and the anode of the second diode; the anode of the second capacitor is connected with the cathode of the fourth capacitor and the cathode of the third diode. The anode of the fourth capacitor is connected with the cathode of the third capacitor, the cathode of the second diode and the anode of the third diode; the third capacitor anode is connected with the fourth diode cathode. According to the converter, ultra-high voltage gain 4 / (1-D) can be achieved by adopting a small number of devices, automatic current sharing of an input inductor can be achieved, and input current ripples are small.

Description

Technical Field

[0001] This invention belongs to the field of DC-DC boost technology and relates to an ultra-high gain photovoltaic interface converter and high voltage charging device for BIPV systems. Background Technology

[0002] In the crucial process of carbon neutrality transformation in the building sector, Building-Integrated Photovoltaics (BIPV) technology is undergoing a revolutionary shift from an auxiliary component to the building itself. my country's General Code for Energy Conservation and Renewable Energy Utilization in Buildings (GB55015-2021) innovatively mandates that all new buildings must integrate photovoltaic systems. This policy breakthrough not only elevates photovoltaic systems to a fundamental building component but also, through binding indicators for carbon neutrality throughout the entire lifecycle, forces building design paradigms to evolve towards energy-efficient buildings. With the industrialization breakthroughs of 182 / 210mm large-size silicon wafers and perovskite tandem technology, power generation per unit building area has increased by 30-45%, effectively resolving the contradiction between limited photovoltaic area and growing energy demand. Furthermore, leading companies such as LONGi and Jinko have established a complete "silicon-module-system" chain, reducing BIPV costs to 4 yuan / W (a 40% decrease compared to 2020). This three-dimensional driving force of policy enforcement, technological iteration, and industrial collaboration signifies that BIPV has transcended the traditional "photovoltaic+" add-on model and is reconstructing the technological logic of building envelope systems. Deep integration of photovoltaic technology with the building itself will become an inevitable choice for the development of green buildings.

[0003] In typical scenarios where BIPV empowers building energy self-sufficiency, 800V high-voltage architecture is becoming an inevitable choice for system upgrades. Taking electric vehicle supercharging stations as an example, a single 120kW DC fast charging pile needs to carry 300A of current under a 400V system, while using an 800V platform can reduce the operating current to 150A, and reduce the cable cross-sectional area by 60% (from 95mm²). 2 Reduced to 35mm 2 This not only reduces copper usage by 45kg per pile but also improves power distribution system efficiency by 2.3 percentage points. For high-density load scenarios such as building data centers, the 800V DC direct supply solution reduces the AC / DC conversion stage compared to traditional 400V AC power distribution, improving system energy efficiency by 5-7%. Combined with liquid cooling technology, the power density of a single cabinet can reach over 40kW.

[0004] This voltage level transition places stringent requirements on dedicated power electronic devices for BIPV. Current BIPV modules exhibit low-voltage, high-current output characteristics (open-circuit voltage 48±2V, operating current 12-15A), meaning the photovoltaic interface converter needs to achieve a 20-fold boost ratio (48V→800V) in a single stage, while maintaining low current and voltage stress to reduce conduction and switching losses, improve solar energy utilization efficiency, lower the levelized cost of electricity (LCOE), and truly achieve economic self-sufficiency in building energy systems. Furthermore, because the photovoltaic converter is integrated with the BIPV module, its size needs to be minimized to reduce installation space and construction difficulty, requiring a smaller number of components. Moreover, BIPV systems operate in harsh environments (high temperatures and direct sunlight) but have a lifespan of up to 20 years, necessitating the photovoltaic converter to be capacitor-free. This is because the electrolyte in electrolytic capacitors evaporates rapidly at high temperatures, leading to a rapid decrease in capacitance and eventual failure.

[0005] To meet the aforementioned performance requirements, scholars from various countries have proposed numerous ultra-high gain photovoltaic interface converter schemes with low voltage and current stress in recent years. These schemes can be broadly classified into two categories: transformer-based (including coupled inductor-based) and transformerless types. Compared to the former, using a transformerless converter as the main circuit topology of a photovoltaic converter is more suitable. This is because its magnetic components are smaller and relatively simpler to design, resulting in lower cost and higher efficiency. Moreover, transformerless converters do not suffer from voltage spikes caused by transformer leakage inductance, do not require active or passive clamping circuits, and have a simpler structure and control, leading to higher reliability.

[0006] Some literature proposes cascading an active switching inductor unit with a two-stage voltage multiplier to construct a low-stress, ultra-high-gain boost converter. However, the inductance of the switches cannot be uniform, resulting in high voltage spikes and ringing in the switching transistors. Therefore, some researchers have combined the active switching inductor unit with a two-stage switched capacitor unit, utilizing the clamping effect of the latter to solve the above problems. However, this improved topology cannot eliminate the inherent drawbacks of active switching inductor converters: 1) One switch needs to be float-driven, increasing the required isolation power supply and driver; 2) The input current exhibits abrupt changes, necessitating the use of large-capacity (over 100µF) electrolytic capacitors to smooth the input voltage and improve the accuracy of maximum power point tracking, which leads to a significant decrease in system reliability.

[0007] Compared to active switching inductor topologies, the interleaved parallel high-gain Boost converter not only reduces the current stress on the input inductor and switching transistors, but also provides continuous input current. Furthermore, it effectively reduces input current ripple by utilizing the interleaved conduction of the switching transistors, while doubling the equivalent switching frequency. This significantly reduces the required input filter capacitance, achieving electrolytic capacitor-free operation.

[0008] One paper proposes extending the traditional two-phase capacitor-in-series Boost converter to a four-phase converter, thereby halving the current stress and doubling the boost capability, resulting in a voltage gain of 4 / (1-D). This converter requires 16 devices (4S, 4D, 4L, and 4C), thus not improving size or cost. Furthermore, it must adhere to specific duty cycle constraints, making control relatively complex. Moreover, when D drops below 0.75, the voltage stress on three switches abruptly changes from Uo / 4 to Uo / 2.

[0009] One paper proposes a novel four-phase interleaved parallel high-gain topology by connecting the input terminals of a two-phase capacitor-in-series Boost converter and its mirror topology in parallel and the output terminals in series. Compared to the four-phase capacitor-in-series Boost converter scheme, when D>0.5, the voltage stress of all switches remains constant at Uo / 4, without any abrupt changes. However, the voltage gain and the number of devices are exactly the same in both schemes.

[0010] Therefore, it is necessary to develop an interleaved parallel boost converter that can achieve ultra-high voltage gain, low power transistor voltage stress, and low average inductor current stress with fewer components. Summary of the Invention

[0011] In view of this, the purpose of the present invention is to provide an ultra-high gain photovoltaic interface converter and a high-voltage charging device for BIPV systems. The ultra-high gain photovoltaic interface converter can achieve ultra-high voltage gain with fewer components and can be applied to high-voltage charging devices based on BIPV systems to charge using photovoltaic energy.

[0012] In a first aspect, the present invention provides an ultra-high gain photovoltaic interface converter for a BIPV system, the ultra-high gain photovoltaic interface converter comprising a first inductor L1, a second inductor L2, an input filter capacitor Cin, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first switch S1, a second switch S2, a relay K, a current limiting resistor Ra, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4; The positive terminal of the input filter capacitor Cin is connected to one end of the first inductor L1 and one end of the second inductor L2, serving as the positive terminal of the input of the ultra-high gain photovoltaic interface converter. The negative terminal of the input filter capacitor Cin is connected to the source of the first switch S1 and the source of the second switch S2, serving as the negative terminal of the input of the ultra-high gain photovoltaic interface converter. The other end of the first inductor L1 is connected to the negative terminal of the first capacitor C1, the drain of the first switching transistor S1, the positive terminal of the relay K, and the positive terminal of the current limiting resistor Ra. The drain of the first switching transistor S1 is connected to the negative terminal of the relay K and the negative terminal of the current limiting resistor Ra. The other end of the second inductor L2 is connected to the negative terminal of the fourth capacitor C4, the anode of the first diode D1, and the drain of the second switch S2, serving as the negative terminal of the output of the ultra-high gain photovoltaic interface converter. The positive terminal of the first capacitor C1 is connected to the negative terminal of the second capacitor C2, the cathode of the first diode D1, and the anode of the second diode D2; The positive terminal of the second capacitor C2 is connected to the negative terminal of the fourth capacitor C4 and the cathode of the third diode D3; The positive terminal of the fourth capacitor C4 is connected to the negative terminal of the third capacitor C3, the cathode of the second diode D2, and the anode of the third diode D3. The positive terminal of the third capacitor C3 is connected to the cathode of the fourth diode D4, serving as the positive terminal of the output of the ultra-high gain photovoltaic interface converter.

[0013] In some embodiments of the present invention, the inductance values ​​of the first inductor L1 and the second inductor L2 are both L, satisfying: In the formula, Uo represents the output voltage of the ultra-high gain photovoltaic interface converter; Uin,min represents the minimum input voltage of the ultra-high gain photovoltaic interface converter; D represents the duty cycle of the drive signal of all switches in the ultra-high gain photovoltaic interface converter; α represents the inductor current ripple rate of the ultra-high gain photovoltaic interface converter; fs represents the switching frequency of the ultra-high gain photovoltaic interface converter; and Po,max represents the maximum output power of the ultra-high gain photovoltaic interface converter.

[0014] In some embodiments of the present invention, the resistance value R of the current-limiting resistor Ra satisfies: In the formula, Iin,max is the maximum value of the input current of the ultra-high gain photovoltaic interface converter.

[0015] In some embodiments of the present invention, the control method of the ultra-high gain photovoltaic interface converter includes the following steps: S1. Sample the instantaneous output voltage value uo,f of the ultra-high gain photovoltaic interface converter and compare it with the reference value uo,ref to obtain the error signal e; S2. The error signal e is sent to the PI controller, and after passing through the unidirectional limiting circuit, the modulation signal ur is obtained; S3. After intersecting the modulation signal ur with the first unipolar triangular carrier uc1 and the second unipolar triangular carrier uc2 respectively, the auxiliary PWM drive signal ugs,Sa of the first switch S1 and the PWM drive signal ugs,S2 of the second switch S2 can be obtained; the amplitude of the first unipolar triangular carrier uc1 and the second unipolar triangular carrier uc2 are both uc, the frequency is the same, and the phase difference is 180°. S4. Perform a NOT operation on the PWM drive signal ugs,S2, and then perform an OR operation on the auxiliary PWM drive signal ugs,Sa to obtain the PWM drive signal ugs,S1 of the first switch S1. S5. Perform a NOT operation on the PWM drive signals ugs and S2, then pass them through an RC low-pass filter and AND them with the output signal. By comparing uc, the driving signal uK of relay K is obtained.

[0016] In some embodiments of the present invention, the ideal voltage gain G of the ultra-high gain photovoltaic interface converter is: In the formula, Uin represents the average value of the input voltage of the ultra-high gain photovoltaic interface converter.

[0017] A second aspect of the present invention provides a control method for the above-mentioned ultra-high gain photovoltaic interface converter, the control method comprising the following steps: S1. Sample the instantaneous output voltage value uo,f of the ultra-high gain photovoltaic interface converter and compare it with the reference value uo,ref to obtain the error signal e; S2. The error signal e is sent to the PI controller, and after passing through the unidirectional limiting circuit, the modulation signal ur is obtained; S3. After intersecting the modulation signal ur with the first unipolar triangular carrier uc1 and the second unipolar triangular carrier uc2 respectively, the auxiliary PWM drive signal ugs,Sa of the first switch S1 and the PWM drive signal ugs,S2 of the second switch S2 can be obtained; the amplitude of the first unipolar triangular carrier uc1 and the second unipolar triangular carrier uc2 are both uc, the frequency is the same, and the phase difference is 180°. S4. Perform a NOT operation on the drive signal ugs,S2, and then perform an OR operation on the auxiliary PWM drive signal ugs,Sa to obtain the PWM drive signal ugs,S1 of the first switch S1. S5. Perform a NOT operation on the PWM drive signals ugs and S2, then pass them through an RC low-pass filter and AND them with the output signal. By comparing uc, the driving signal uK of relay K is obtained.

[0018] A third aspect of the present invention provides an application of the above-described ultra-high gain photovoltaic interface converter in a high-voltage charging device based on a BIPV system.

[0019] In a fourth aspect, the present invention provides a high-voltage charging device based on a BIPV system, the high-voltage charging device including the aforementioned ultra-high gain photovoltaic interface converter, the input end of the ultra-high gain photovoltaic interface converter being connected to a BIPV photovoltaic module, and the output end of the ultra-high gain photovoltaic interface converter being connected to the charging interface of the device to be charged.

[0020] Compared with the prior art, the present invention has the following technical effects: (1) A switched capacitor boost circuit is inserted into the midpoint of the bridge arm of the two-phase interleaved parallel Boost converter. With fewer components (only two inductors), an ultra-high voltage gain of 4 / (1-D) is achieved. Each switched capacitor charging and discharging circuit contains an input inductor. The current spikes caused by the charging and discharging of the switched capacitors are completely eliminated by utilizing the property of the inductor to impede current change. In addition, the proposed circuit also realizes automatic current sharing of the input inductor, reduces the average current stress of the inductor, and has the characteristics of common ground drive of the switching transistors and small input current ripple.

[0021] (2) The ultra-high gain photovoltaic interface converter of the present invention is applied to a high-voltage charging device based on BIPV system, which can realize 800V high-voltage charging of electric vehicles when the maximum power point voltage of BIPV photovoltaic module is 24V-50V. Attached Figure Description

[0022] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 A circuit structure diagram of an ultra-high gain photovoltaic interface converter provided in one embodiment of the present invention; Figure 2 for Figure 1 The diagram shows the equivalent circuit diagrams of each mode of the steady-state operation process of the ultra-high gain photovoltaic interface converter during one switching cycle when the duty cycle D < 0.5. Figure 3 for Figure 1 The diagram shows the equivalent circuit diagrams of each mode of the steady-state operation process of the ultra-high gain photovoltaic interface converter during one switching cycle when the duty cycle D>0.5. Figure 4 for Figure 1 The diagram shows the main waveforms of the ultra-high gain photovoltaic interface converter within one switching cycle when the duty cycle D>0.5. Figure 5 for Figure 1The control block diagram of the ultra-high gain photovoltaic interface converter control method is shown below; Figures 6-9 for Figure 1 The simulation waveform of the ultra-high gain photovoltaic interface converter is shown when the duty cycle D>0.5. Figures 10-11 for Figure 1 The simulation waveform of the ultra-high gain photovoltaic interface converter is shown when the duty cycle D < 0.5. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] An embodiment of the first aspect of the present invention provides an ultra-high gain photovoltaic interface converter for a BIPV system, the circuit structure of which is as follows: Figure 1 As shown, the ultra-high gain photovoltaic interface converter includes a first inductor L1, a second inductor L2, an input filter capacitor Cin, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first switch S1, a second switch S2, a relay K, a current-limiting resistor Ra, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The positive terminal of the input filter capacitor Cin is connected to one end of the first inductor L1 and one end of the second inductor L2, serving as the positive terminal of the input of the ultra-high gain photovoltaic interface converter. The negative terminal of the input filter capacitor Cin is connected to the source of the first switch S1 and the source of the second switch S2, serving as the negative terminal of the input of the ultra-high gain photovoltaic interface converter. The other end of the first inductor L1 is connected to the negative terminal of the first capacitor C1, the drain of the first switch S1, and the relay K. The positive terminal of relay K and the positive terminal of current-limiting resistor Ra are connected; the drain of the first switching transistor S1 is connected to the negative terminal of relay K and the negative terminal of current-limiting resistor Ra; the other end of the second inductor L2 is connected to the negative terminal of the fourth capacitor C4, the anode of the first diode D1, and the drain of the second switching transistor S2, serving as the negative terminal of the output terminal of the ultra-high gain photovoltaic interface converter; the positive terminal of the first capacitor C1 is connected to the negative terminal of the second capacitor C2, the cathode of the first diode D1, and the anode of the second diode D2; the positive terminal of the second capacitor C2 is connected to the negative terminal of the fourth capacitor C4 and the cathode of the third diode D3; the positive terminal of the fourth capacitor C4 is connected to the negative terminal of the third capacitor C3, the cathode of the second diode D2, and the anode of the third diode D3; the positive terminal of the third capacitor C3 is connected to the cathode of the fourth diode D4, serving as the positive terminal of the output terminal of the ultra-high gain photovoltaic interface converter.

[0025] Figure 1 The ultra-high gain photovoltaic interface converter shown has a duty cycle D < 0.5 for all switches during the soft-start phase. The equivalent circuit diagram is as follows. Figure 2 As shown, Figure 2 In the diagram, (a) shows the equivalent circuit when the first switch S1 is on and the second switch S2 is off, and (b) shows the equivalent circuit when the first switch S1 is off and the second switch S2 is on. According to (a), when the second switch S2 is off, the first switch S1 and the current-limiting resistor R... a The series branch formed can establish a freewheeling path for the first inductor L1 and the second inductor L2, thereby discharging the energy stored in the inductors and avoiding overvoltage breakdown of the power switch due to the lack of energy release, so that the converter can work normally.

[0026] Since ultra-high gain photovoltaic interface converters typically operate with a duty cycle D > 0.5, this invention only performs modal analysis for the case where the duty cycle D > 0.5.

[0027] Assumptions: The switching transistors, energy storage elements, diodes, and inductors are all ideal devices; the input filter capacitor Cin, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are sufficiently large, and voltage ripple can be ignored; the currents of the first inductor L1 and the second inductor L2 are continuous; the connection point between the negative terminal of the input filter capacitor Cin and the source terminals of the first switch S1 and the second switch S2 is a zero potential reference point.

[0028] Based on the above assumptions, when the duty cycle D > 0.5, Figure 1 The ultra-high gain photovoltaic interface converter shown can be divided into four modes during a switching cycle in its steady-state operation. The equivalent circuit is as follows: Figure 3 As shown, its main waveform is as follows Figure 4 As shown.

[0029] Mode 1, t0~t1 stage: (equivalent circuit as follows) Figure 3 (a) shown) At time t0, both the first switch S1 and the second switch S2 are turned on, while the auxiliary switch Sa is turned off. The first diode D1, the second diode D2, the third diode D3, the fourth diode D4, and the auxiliary diode Da are all turned off, and the third capacitor C3 and the fourth capacitor C4 discharge to provide energy to the output. The first inductor L1 and the second inductor L2 experience a positive voltage Uin, therefore the currents iL1 and iL2 of both inductors increase linearly. At this time, we have: (1) In the formula, L1 is the inductance of the first inductor and L2 is the inductance of the second inductor.

[0030] At time t1, mode 1 ends. The duration of mode 1 is: In the formula, Ts is the switching period.

[0031] Mode 2, t1~t2 stage: (equivalent circuit as follows) Figure 3 (b) At time t1, the second switch S2 is turned off, and the first diode D1 and the third diode D3 are turned on; the first inductor current iL1 continues to rise while maintaining its original conversion rate; the second inductor L2 bears a negative voltage Uin-UC1, so the current iL2 begins to decrease linearly; a portion of the energy of the second inductor L2, along with the fourth capacitor C4, is transferred to the first capacitor C1 and the second capacitor C2 through the first diode D1 and the third diode D3, respectively. At this time, we have: (2) In the formula, UC1 is the average voltage of the first capacitor C1.

[0032] At time t2, mode 2 ends. The duration of mode 2 is: .

[0033] Mode 3, t2~t3 stage: (equivalent circuit as follows) Figure 3 (a) shown) The working principle and equivalent circuit of this mode are the same as those of mode 1, so they will not be described again here.

[0034] Mode 4, t3~t4 stage: (equivalent circuit as follows) Figure 3 (c) shown) At time t3, the first switch S1 is turned off, and the second diode D2 and the fourth diode D4 are turned on; the second inductor current iL2 continues to rise while maintaining its original conversion rate; the first inductor L1 bears a negative voltage Uin + UC1 - UC4, so the current iL1 begins to decrease linearly; a portion of the energy of the first inductor L1, along with the first capacitor C1 and the second capacitor C2, is transferred to the third capacitor C3 and the fourth capacitor C4 through the second diode D2 and the fourth diode D4, respectively. At this time, we have: (3) In the formula, UC4 is the average voltage of the fourth capacitor C4.

[0035] Mode 4 ends at time t4. Duration of Mode 4: .

[0036] Based on the above working principles, the following is a summary: Figure 1 The steady-state characteristics of the ultra-high gain photovoltaic interface converter shown are analyzed under CCM.

[0037] Based on the volt-second balance of the first inductor L1 and the second inductor L2, and combining equations (1) to (3), we can obtain: (4) In addition, by Figure 3 Modal analysis yields the following results: (5) According to equations (4) and (5), the voltage gain of the ultra-high gain photovoltaic interface converter proposed in this invention can be obtained as follows: (6) Furthermore, based on modal analysis and equation (6), the voltage stresses of the first switch S1 and the second switch S2, the voltage stresses of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4, and the voltage stresses of the first diode D1, the second diode D2, the third diode D3 and the fourth diode D4 in the ultra-high gain photovoltaic interface converter proposed in this invention are as follows: (7) In the formula, US1 is the voltage stress of the first switch S1, US2 is the voltage stress of the second switch S2, UD1 is the voltage stress of the first diode D1, UD2 is the voltage stress of the second diode D2, UD3 is the voltage stress of the third diode D3, UD4 is the voltage stress of the fourth diode D4, UC1 is the voltage stress of the first capacitor C1, UC2 is the voltage stress of the second capacitor C2, UC3 is the voltage stress of the third capacitor C3, and UC4 is the voltage stress of the fourth capacitor C4.

[0038] Based on the average current equivalent circuit, the average current stress of the ultra-high gain photovoltaic interface converter proposed in this invention can be obtained as follows: (8) In the formula, ID1 is the average current of the first diode, ID2 is the average current of the second diode, ID3 is the average current of the third diode, ID4 is the average current of the fourth diode, IL1 is the average current of the first inductor, IL2 is the average current of the second inductor, IS1 is the average current of the first switch, IS2 is the average current of the second switch, Iin is the average value of the input current, and Io is the average value of the output current.

[0039] Based on the analysis of mode 2 and mode 4, we can conclude that: (9) Since D1 and D3 conduct only during mode 2, and D2 and D4 conduct only during mode 4, therefore: (10) From equations (10) and (8), the current stresses of the first switch S1, the second switch S2, the first inductor L1, and the second inductor L2 are: (11) From equation (1), we can see that the inductance of both the first inductor L1 and the second inductor L2 is L, and the peak-to-peak current satisfies: (12) From equation (12), the inductance L satisfies: (13) In this invention, the inductance of the first inductor L1 and the second inductor L2 are equal, and the voltage stress and current stress of the power transistor are equal. Therefore, similar devices can be used interchangeably, which is convenient for mass production.

[0040] Furthermore, the current-limiting resistor Ra needs to be selected appropriately. This is because if Ra is too large, the voltage stress on the second switching transistor S2 will be too high when D < 0.5; if it is too small, the inductor current will be too large, potentially leading to inductor saturation. Therefore, the value of Ra, R, needs to follow these guidelines: (14) In the formula, Iin,max is the maximum value of the input current of the ultra-high gain photovoltaic interface converter.

[0041] In a second aspect of the present invention, a method is provided. Figure 1 The control method for the ultra-high gain photovoltaic interface converter shown is illustrated in the control block diagram below. Figure 5 As shown, it includes the following steps: S1. Sample the instantaneous value uo,f of the ultra-high gain photovoltaic interface converter and compare it with the reference value uo,ref to obtain the error signal e; S2. The error signal e is sent to the PI controller, and after passing through the unidirectional limiting circuit, the modulation signal ur is obtained; S3. After intersecting the modulation signal ur with the first unipolar triangular carrier uc1 and the second unipolar triangular carrier uc2 respectively, the auxiliary PWM drive signal ugs,Sa of the first switch S1 and the PWM drive signal ugs,S2 of the second switch S2 can be obtained; the amplitude of the first unipolar triangular carrier uc1 and the second unipolar triangular carrier uc2 are both uc, the frequency is the same, and the phase difference is 180°. S4. Perform a NOT operation on the drive signals ugs,S2, and then perform an OR operation on the drive signals ugs,Sa to obtain the drive signal ugs,S1 of the first switch S1. S5. Perform a NOT operation on the drive signals ugs and S2, then pass them through an RC low-pass filter and AND them with the output signal. By comparing the signals, the driving signal uK of relay K is obtained.

[0042] To verify the correctness of the above theoretical analysis and the effectiveness of the above control method, the converter described in this invention was simulated and verified using Saber simulation software. Its design specifications are as follows: input voltage Uin = 40V, output voltage Uo = 800V, maximum output power Po,max = 500W, switching frequency fs = 50kHz, inductance L of all inductors is 0.3mH, current-limiting resistor Ra has resistance R values ​​of 6.4Ω and 16Ω at the extreme ends of the range, input filter capacitor Cin is 20μF, first capacitor C1 is 20μF, and second capacitor C2, third capacitor C3, and fourth capacitor C4 are all 4.7μF.

[0043] Simulation waveform diagram as follows Figures 6-11 As shown. Among them, Figures 6-9 for Figure 1 The simulation waveform of the ultra-high gain photovoltaic interface converter is shown when the duty cycle D>0.5. Figures 10-11 for Figure 1 The simulation waveform of the ultra-high gain photovoltaic interface converter is shown when the duty cycle D < 0.5.

[0044] Figure 6 The simulation waveforms of the input voltage uin, output voltage uo, first inductor current iL1, second inductor current iL2, and input current iin are given. As can be seen, when the duty cycle D≈0.8 and the input voltage Uin=40V, the output voltage Uo=800.3V of the ultra-high gain photovoltaic interface converter proposed in this invention, and the measured voltage gain Uo / Uin=800.3 / 40≈20, are basically consistent with the theoretical value G=4 / (1-D)=20, achieving a high gain. It can be seen that the inductor currents iL1 and iL2 are both continuous. The average value of the first inductor current iL1 is IL1=6.26A, and the average value of the second inductor current iL2 is IL2=6.26A, which are basically consistent with the theoretical values. The ripple rate of the input current is 12.8%, which is much lower than the ripple rate of the first inductor current iL1 ΔiL1 / IL1≈34.08% and the ripple rate of the second inductor current iL2 ΔiL2 / IL2≈34.08%. At the same time, the inductor currents are continuous and the waveforms are 180° apart. Figure 7 The waveforms of the drain-source voltage uS1 and current iS1 of the first switch S1 and the drain-source voltage uS2 and current iS2 of the second switch S2 are shown when the ultra-high gain photovoltaic interface converter is operating. It can be seen that the average current stress of the first switch S1 is 6.26A, and the average current stress of the second switch S2 is also 6.26A. Furthermore, the voltage stress of the first switch S1 and the second switch S2 are basically equal, approximately 1 / 4 of the output voltage Uo, which is consistent with the theoretical value. Figures 8-9 The simulated waveforms of diode terminal voltages uD1, uD2, uD3, and uD4, and capacitor terminal voltages uC1, uC2, uC3, and uC4 are given respectively. It can be seen that the voltage stress of the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are basically equal, about 1 / 2 times the output voltage Uo, and the first capacitor C1 is about 1 / 4 times the output voltage Uo, all consistent with the theoretical values.

[0045] Figure 10 and Figure 11 The simulation waveforms are shown for R=6.4Ω and R=16Ω, respectively. It can be seen that the voltage stress of the first switch S1 and the second switch S2 during the soft start process does not exceed 200V, and there is no high current surge to saturate the inductor, thus verifying the rationality of the proposed Ra value range.

[0046] according to Figures 6-9 It can be seen that when the duty cycle D > 0.5, the control method provided by this invention can enable... Figure 1 The ultra-high gain photovoltaic interface converter shown has a continuous input current and a frequency-doubled equivalent switching frequency, which can reduce the input filter capacitance, reduce conduction losses under high output voltage conditions, improve the converter's conversion efficiency, and achieve electrolytic capacitor-free operation, thereby reducing converter cost and improving converter reliability. According to... Figures 10-11 It can be seen that when the duty cycle D < 0.5, Figure 1 The ultra-high gain photovoltaic interface converter shown can operate normally.

[0047] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An ultra-high gain photovoltaic interface converter for BIPV systems, characterized in that, The ultra-high gain photovoltaic interface converter includes a first inductor L1, a second inductor L2, an input filter capacitor Cin, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first switch S1, a second switch S2, a relay K, a current limiting resistor Ra, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The positive terminal of the input filter capacitor Cin is connected to one end of the first inductor L1 and one end of the second inductor L2, serving as the positive terminal of the input of the ultra-high gain photovoltaic interface converter. The negative terminal of the input filter capacitor Cin is connected to the source of the first switch S1 and the source of the second switch S2, serving as the negative terminal of the input of the ultra-high gain photovoltaic interface converter. The other end of the first inductor L1 is connected to the negative terminal of the first capacitor C1, the drain of the first switching transistor S1, the positive terminal of the relay K, and the positive terminal of the current limiting resistor Ra. The drain of the first switching transistor S1 is connected to the negative terminal of the relay K and the negative terminal of the current limiting resistor Ra. The other end of the second inductor L2 is connected to the negative terminal of the fourth capacitor C4, the anode of the first diode D1, and the drain of the second switch S2, serving as the negative terminal of the output of the ultra-high gain photovoltaic interface converter. The positive terminal of the first capacitor C1 is connected to the negative terminal of the second capacitor C2, the cathode of the first diode D1, and the anode of the second diode D2; The positive terminal of the second capacitor C2 is connected to the negative terminal of the fourth capacitor C4 and the cathode of the third diode D3; The positive terminal of the fourth capacitor C4 is connected to the negative terminal of the third capacitor C3, the cathode of the second diode D2, and the anode of the third diode D3. The positive terminal of the third capacitor C3 is connected to the cathode of the fourth diode D4, serving as the positive terminal of the output of the ultra-high gain photovoltaic interface converter.

2. The ultra-high gain photovoltaic interface converter as described in claim 1, characterized in that, The inductance values ​​of the first inductor L1 and the second inductor L2 are both L, satisfying the following: In the formula, Uo represents the output voltage of the ultra-high gain photovoltaic interface converter; Uin,min represents the minimum input voltage of the ultra-high gain photovoltaic interface converter; D represents the duty cycle of the drive signal of all switches in the ultra-high gain photovoltaic interface converter; α represents the inductor current ripple rate of the ultra-high gain photovoltaic interface converter; fs represents the switching frequency of the ultra-high gain photovoltaic interface converter; and Po,max represents the maximum output power of the ultra-high gain photovoltaic interface converter.

3. The ultra-high gain photovoltaic interface converter as described in claim 1, characterized in that, The resistance R of the current-limiting resistor Ra satisfies: In the formula, Iin,max is the maximum value of the input current of the ultra-high gain photovoltaic interface converter.

4. The ultra-high gain photovoltaic interface converter as described in claim 1, characterized in that, The control method for the ultra-high gain photovoltaic interface converter includes the following steps: S1. Sample the instantaneous output voltage value uo,f of the ultra-high gain photovoltaic interface converter and compare it with the reference value uo,ref to obtain the error signal e; S2. The error signal e is sent to the PI controller, and after passing through the unidirectional limiting circuit, the modulation signal ur is obtained; S3. After intersecting the modulation signal ur with the first unipolar triangular carrier uc1 and the second unipolar triangular carrier uc2 respectively, the auxiliary PWM drive signal ugs,Sa of the first switch S1 and the PWM drive signal ugs,S2 of the second switch S2 can be obtained; the amplitude of the first unipolar triangular carrier uc1 and the second unipolar triangular carrier uc2 are both uc, the frequency is the same, and the phase difference is 180°. S4. Perform a NOT operation on the PWM drive signal ugs,S2, and then perform an OR operation on the auxiliary PWM drive signal ugs,Sa to obtain the PWM drive signal ugs,S1 of the first switch S1. S5. Perform a NOT operation on the PWM drive signals ugs and S2, then pass them through an RC low-pass filter and AND them with the output signal. By comparing the signals, the driving signal uK of relay K is obtained.

5. The ultra-high gain photovoltaic interface converter as described in claim 4, characterized in that, The ideal voltage gain G of the ultra-high gain photovoltaic interface converter is: In the formula, Uin represents the average value of the input voltage of the ultra-high gain photovoltaic interface converter.

6. A control method for an ultra-high gain photovoltaic interface converter as described in claim 1, characterized in that, The control method includes the following steps: S1. Sample the instantaneous output voltage value uo,f of the ultra-high gain photovoltaic interface converter and compare it with the reference value uo,ref to obtain the error signal e; S2. The error signal e is sent to the PI controller, and after passing through the unidirectional limiting circuit, the modulation signal ur is obtained; S3. After intersecting the modulation signal ur with the first unipolar triangular carrier uc1 and the second unipolar triangular carrier uc2 respectively, the auxiliary PWM drive signal ugs,Sa of the first switch S1 and the PWM drive signal ugs,S2 of the second switch S2 can be obtained; the amplitude of the first unipolar triangular carrier uc1 and the second unipolar triangular carrier uc2 are both uc, the frequency is the same, and the phase difference is 180°. S4. Perform a NOT operation on the drive signal ugs,S2, and then perform an OR operation on the auxiliary PWM drive signal ugs,Sa to obtain the PWM drive signal ugs,S1 of the first switch S1. S5. Perform a NOT operation on the PWM drive signals ugs and S2, then pass them through an RC low-pass filter and AND them with the output signal. By comparing the signals, the driving signal uK of relay K is obtained.

7. The application of the ultra-high gain photovoltaic interface converter as described in any one of claims 1-5 in a high-voltage charging device based on a BIPV system.

8. A high-voltage charging device based on a BIPV system, characterized in that, The high-voltage charging device includes an ultra-high gain photovoltaic interface converter as described in any one of claims 1-5, wherein the input end of the ultra-high gain photovoltaic interface converter is connected to a BIPV photovoltaic module, and the output end of the ultra-high gain photovoltaic interface converter is connected to the charging interface of the device to be charged.

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