Step-down switched mode power supply

Abstract

The invention relates to a buck switched mode power supply. A buck-type switched mode power supply includes a switching unit formed of a first switch configured to be periodically set to an on state by a first control signal modulated by a pulse width or pulse frequency modulation type. The amplifier generates an error voltage representing a difference between a reference voltage and an output voltage of a power supply intended to be applied to an input of the amplifier. The delay circuit applies a delay to the first control signal to reduce a difference between the error voltage and the reference voltage. The delay modulation circuit modulates a value of the delay according to a difference between the error voltage and a reference voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to French patent application FR2409717, filed on September 12, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to the field of switch-mode power supplies (SMPS), and more particularly to DC-DC converters, and more specifically to buck switch-mode power supplies (also known as buck converters or buck choppers). Background Technology

[0004] A buck switch-mode power supply typically includes a switching unit comprising a first so-called "high-side" transistor and a second so-called "low-side" transistor series coupled between the input potential and ground. The complementary first and second transistors (one n-type and the other p-type) are alternately and complementaryly set to on and off states (one transistor on, the other off) by complementary first and second control signals applied to their gates. A low-pass LC filter is coupled to the connection node of this unit, i.e., to the connection point where the two transistors are coupled. The output voltage of the power supply is obtained across the filter capacitor.

[0005] The control signal applied to the transistor is either pulse width modulation (PWM) or pulse frequency modulation (PFM). The resulting output voltage level is a function of the duration of the transistor's on and off states during the period of the control signal. The modulation parameters of these control signals define the power supply's conversion ratio.

[0006] In situations where a strong load is coupled to the power supply output, a larger output current is required. In this case, the power supply uses PWM-type modulation signals to operate and control the transistors of the switching unit; the frequency of these control signals is fixed. The power supply includes a circuit that generates an error voltage and another circuit that generates a ramp voltage. The value of this error voltage depends on the difference between the output voltage and a reference voltage corresponding to a target output voltage. This ramp voltage rises from zero, and upon reaching the error voltage value, it defines the duration of a first state of the control signals during which the switching unit charges the capacitors coupled to the connection nodes of the switching unit.

[0007] In situations where a small load is coupled to the power supply output, a lower output current is required. The power supply then uses a PFM-type modulated signal to operate and control the transistors in the switching unit.

[0008] In this type of switching power supply, if the error voltage and the reference voltage are not equal during such changes, the output voltage of the power supply will fluctuate sharply during the modulation changes of the control signal (switching between PWM modulation and PFM modulation).

[0009] To avoid this problem, US Patent No. 10,944,324 (also EP 3,644,486 A1) teaches the introduction of a delay to modify the value of the error voltage, thereby reducing the difference between the error voltage value and the reference voltage value. This delay is defined as equal to the propagation time of the comparator between the error voltage and the ramp voltage. This delay forces the power supply's control loop to artificially increase the error voltage to achieve the same duty cycle, bringing the error voltage closer to the reference voltage, thus improving the transition between PWM modulation and PFM modulation.

[0010] The drawback of the technical solution provided in the above references is that by introducing such a delay to limit the maximum value of the duty cycle obtained for PWM modulation, the performance of the power supply may be limited.

[0011] Therefore, there is a need in the art to provide a technical solution that eliminates at least some of the disadvantages of existing technical solutions. Summary of the Invention

[0012] In one embodiment, a buck switch-mode power supply includes at least: a switching unit including at least a first switch configured to be periodically switched to an on state by a first control signal modulated by a modulation of the pulse width modulation (PWM) or pulse frequency modulation (PFM) type; an amplifier configured to generate an error voltage representing the difference between a reference voltage and an output voltage of a power supply intended to be applied to the input of the amplifier; a delay circuit configured to apply a delay to the first control signal to reduce the difference between the error voltage and the reference voltage; and a delay modulation circuit configured to modulate the value of the delay based on the difference between the error voltage and the reference voltage.

[0013] According to a specific embodiment, the delay modulation circuit is configured to deliver a current or voltage as an output having a value proportional to the difference between the error voltage and the reference voltage.

[0014] According to a specific embodiment, the delay modulation circuit is configured to reduce the delay value proportionally to the difference between the error voltage and the reference voltage.

[0015] According to a specific embodiment, the delay modulation circuit includes at least one differential amplifier, which includes a non-inverting input configured to receive an error voltage and an inverting input configured to receive a reference voltage.

[0016] According to one specific embodiment, the switching unit includes at least a second switch configured to be periodically set to an on state by a second control signal modulated by a modulation of a PWM type or a PFM type, complementary to the first switch.

[0017] According to one specific embodiment, the switch-mode power supply further includes at least one inductor and at least one capacitor. The inductor includes a first electrode coupled to a connection node of the switching unit, and the capacitor is coupled to a second electrode of the inductor. The output voltage of the power supply is intended to be obtained across the capacitor.

[0018] According to a specific embodiment, the switch-mode power supply further includes at least one comparator configured to receive an error voltage and a periodically increasing voltage ramp as input during the period of a first control signal.

[0019] According to one embodiment, the switch-mode power supply further includes at least one circuit for generating a control signal configured to generate at least a first control signal based on the output signal of a comparator and the output signal of a delay circuit.

[0020] According to a specific embodiment, the switch-mode power supply further includes a voltage ramp generation circuit configured to generate a ramp voltage, and the voltage ramp generation circuit has an output coupled to a non-inverting input of a comparator.

[0021] According to one specific embodiment, the switch-mode power supply further includes circuitry for generating a periodic signal, the circuitry being configured to deliver a periodic signal having a frequency equal to that of the first control signal at the inputs of the delay circuitry and the voltage ramp generation circuitry.

[0022] According to one specific embodiment, the delay circuit includes at least: a CMOS inverter configured to receive a periodic signal delivered by a periodic signal generation circuit as input; a capacitor element coupled to the output terminal of the inverter; a Schmitt trigger including an input coupled to the output terminal of the inverter and having an output forming the output of the delay circuit; a MOS transistor configured to deliver a current having a maximum value lower than the maximum value of the transistor in the inverter as output and coupled in series with one of the transistors in the inverter; and a current source configured to draw a current having a value proportional to the difference between the error voltage and the reference voltage from the connection node between the MOS transistor and the inverter.

[0023] In one embodiment, a method for converting an input voltage into an output voltage having a value lower than the input voltage includes at least: controlling at least one switching unit, the switching unit including at least one first switch that is periodically set to an on state by a first control signal modulated by a modulation of the pulse width modulation (PWM) or pulse frequency modulation (PFM) type; generating an error voltage representing the difference between a reference voltage and an output voltage of a power supply; generating a delay that reduces the interval between the error voltage and the reference voltage; modulating the value of the delay as a function of the difference between the error voltage and the reference voltage; and applying the modulated delay to the first control signal.

[0024] According to one specific embodiment, modulation of the delay value includes generating a current or voltage having a value proportional to the difference between the error voltage and the reference voltage. Attached Figure Description

[0025] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of example and not limitation with reference to the accompanying drawings, in which:

[0026] Figure 1 A switch-mode power supply is schematically shown;

[0027] Figure 2 An example of an embodiment of a voltage ramp generation circuit for a switch-mode power supply is schematically shown;

[0028] Figure 3 An example of an embodiment of a delay circuit for a switch-mode power supply is schematically shown;

[0029] Figure 4 An example of an embodiment of a delay modulation circuit for a switch-mode power supply is schematically shown;

[0030] Figure 5 An example of the output current of a delay modulation circuit in a switch-mode power supply is shown; and

[0031] Figure 6 An example of a signal acquired in a switch-mode power supply is shown. Detailed Implementation

[0032] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals, and may be provided with the same structure, dimensions, and material properties.

[0033] For clarity, only steps and components useful for understanding the described embodiments are shown and described in detail. In particular, the formation of various elements and components of the switch-mode power supply is not described in detail. Those skilled in the art will be able to form these elements in detail based on the descriptions given herein.

[0034] Unless otherwise stated, when referring to two elements connected together, it means a direct connection without any intermediate elements other than conductors; when referring to two elements coupled together, it means that the two elements can be connected or coupled via one or more other elements. Furthermore, the term "coupled" is used here to refer to electrical coupling between multiple electrical and / or electronic components (assemblies, circuits, etc.).

[0035] Unless otherwise specified, “approximately,” “roughly,” “substantially,” and “on the order of…” mean plus or minus 10%, preferably plus or minus 5%. Similarly, unless otherwise specified, the ranges of values ​​shown include limitations of these ranges.

[0036] The following combination Figure 1 A switch-mode power supply 100 according to a specific embodiment is described below. Only a portion of the elements, circuits, and components of the power supply 100 are described below, and as such... Figure 1 As shown, power supply 100 may include other electrical or electronic components, circuits, and assemblies.

[0037] Power supply 100 corresponds to a buck-type switching mode power supply, that is, a buck converter.

[0038] exist Figure 1 In the example shown, the power supply 100 includes a switching unit 101, which includes a first power transistor 102 and a second power transistor 104. The two transistors 102 and 104 are of opposite types; one is n-type and the other is p-type. Figure 1 In the example, the first transistor 102 corresponds to a PMOS transistor, and the second transistor 104 corresponds to an NMOS transistor.

[0039] As a variation, the switching unit 101 may include switches other than MOS transistors (IGBTs, bipolar transistors, etc.). Furthermore, one of the two switches in the switching unit 101 may be replaced with a diode.

[0040] Transistors 102 and 104 are connected in series between the electrical input potential of power supply 100 and ground to form an input voltage V applied across switching unit 101. IN .

[0041] In the example of the described embodiment, a first control signal and a second control signal are intended to be applied to the gates of transistors 102 and 104 (the first control signal is applied to the gate of the first transistor 102, and the second control signal is applied to the gate of the second transistor 104), thereby controlling the switching of control unit 101. During operation of power supply 100, when transistors 102 and 104 are controlled by a control signal modulated by PWM-type modulation, they are intended to be in a complementary state (one of the two transistors 102 and 104 is on, and the other is off). During the use of PFM-type modulation, both transistors 102 and 104 may be in the off state.

[0042] exist Figure 1 In the example, the power supply 100 also includes an inductor 106, such as an inductor, which has a first electrode coupled to a connection node 108 of the switching unit 101 (the node to which the two transistors 102 and 104 are coupled) and a second electrode coupled to an output terminal 110 of the power supply 100, at which the output current of the power supply 100 is intended to be obtained.

[0043] exist Figure 1 In the example, power supply 100 also includes a capacitor element 112 (e.g., a capacitor) coupled between output terminal 110 and ground, and the output voltage V OUT The purpose is to obtain this across the two ends of the capacitor element. The capacitor element 112, together with the inductor element 106, forms a low-pass filter.

[0044] In the specific embodiment described, the power supply 100 further includes an amplifier 114 configured to generate a representation of the reference voltage V. REF With output voltage V OUT The difference between the error voltage V ERR In this example, amplifier 114 includes an integrator with a control loop that provides correction to stabilize power supply 100. Figure 1 In the example, the reference voltage V REF The voltage is intended to be applied to the non-inverting input of amplifier 114, and the output voltage V OUT The error voltage V is intended to be applied to the inverting input of amplifier 114. ERR Corresponding to a DC voltage centered on a reference voltage, when the reference voltage V REF The value is lower than the output voltage V OUT When the value is lower than the reference voltage V, the error voltage value is lower than the reference voltage V. REF The value of , while when the reference voltage V REF The value is higher than the output voltage V OUT When the value is higher than the reference voltage V, the error voltage value is higher than the reference voltage V. REF The value of .

[0045] The reference voltage V to be applied to the input of amplifier 114 REF The value is chosen to be equal to the output voltage V. OUT The target value. For example, the input voltage V. IN It can be equal to 3V, and the output voltage V OUT (and therefore the reference voltage V) REF () can be equal to 1V. In this example, the conversion ratio of power supply 100 is 1 / 3.

[0046] exist Figure 1 In the example, power supply 100 also includes comparator 116, which includes an inverting input and a non-inverting input coupled to the output of amplifier 114, with an error voltage V. ERR The intended purpose is to apply a periodic voltage ramp V to the output of the voltage ramp generation circuit 118, which is then applied to the inverting input. RAMP The voltage is intended to be applied to this non-inverting input. The voltage obtained at the output of comparator 116 corresponds to a square wave signal, when the periodic voltage ramp V... RAMP The value is lower than the error voltage V ERR At that time, the square wave signal has a first value (corresponding to...) Figure 1 (in the example of the low state), while when the periodic voltage ramp V RAMP The value becomes higher than the error voltage V ERR At that time, the square wave signal has a second value (corresponding to...) Figure 1 (High state in the example).

[0047] Therefore, the duration of the low state of the output signal of comparator 116 corresponds to the periodic voltage ramp V. RAMP The value is increased to achieve the error voltage V ERR The time of the value. Now, assume the error voltage V ERR Generated as reference voltage V REF With output voltage V OUT The duration of the low state of the comparator 116's output signal, which is a function of the difference between the reference voltages V and V, is also the duration of the reference voltage V. REF With output voltage V OUT The duty cycle of the comparator is a function of the difference between the reference voltages. Therefore, the output signal of comparator 116 is a periodic square wave signal, the duty cycle of which depends on the reference voltage V. REF With output voltage V OUT The difference between them.

[0048] The following text will combine Figure 2 An embodiment of a periodic voltage ramp generation circuit 118 is described.

[0049] In this example, circuit 118 includes transistor 120. Figure 2 (NMOS transistor in the example). Ramp control signal V CLK (This corresponds to a square wave signal) intended to be applied to the gate of transistor 120. Circuit 118 also includes a current source 122 coupled between the power supply potential VCC and the drain of transistor 120, and configured to deliver a bias current Ip. Circuit 118 also includes a capacitor 124 intended to be charged by the bias current Ip, and coupled between the drain of transistor 120 and ground. Periodic voltage ramp V RAMP The aim is to obtain it across capacitor 124.

[0050] exist Figure 2 In the embodiment of circuit 118 shown, when the ramp control signal V CLK When transistor 120 is in a low state (“0”) to be turned off, the bias current Ip delivered by current source 122 charges capacitor 124, and V RAMP The value increases linearly. When the ramp control signal switches to a high state ("1") to set transistor 120 to the on state, the periodic voltage ramp V increases. RAMP The value falls back to zero. The period of the ramp control signal is equal to the period of the control signal intended to be applied to the gates of transistors 102 and 104.

[0051] Other alternative embodiments of the voltage ramp generation circuit 118 are possible.

[0052] Power supply 100 also includes a delay circuit 126 configured to introduce a delay into control signals when control signals intended to be applied to the gates of transistors 102, 104 of unit 101 are modulated by PWM modulation to facilitate a transition of control signals from one modulation, PWM modulation, to the other, thereby reducing the error voltage V. ERR With reference voltage V REF The difference between them.

[0053] exist Figure 1 In the example, a delayed clock signal is delivered at the output of delay circuit 126 and applied to the input of control signal generation circuit 128. Circuit 128 is configured to generate a first control signal and a second control signal, intended to be applied to the gates of transistors 102 and 104 in unit 101, based on the signal delivered at the output of comparator 116 and the delayed clock signal delivered at the output of delay circuit 126. For example, the first and second control signals cause the first transistor 102 to turn on and the second transistor 104 to turn off during the rising edge of the delayed clock signal. Then, when the delayed clock signal changes state and presents a falling edge, the second transistor 104 turns on and the first transistor 102 turns off.

[0054] The control circuit 128 includes, for example, a digital controller of the finite state machine (FSM) type. As a variation, when the switching unit 101 includes a single switch, the circuit 128 can be configured to output a single control signal.

[0055] The power supply 100 also includes a delay modulation circuit 130, which is configured to adjust according to the error voltage V. ERR With reference voltage V REF The difference between them is used to modulate the value of the delay defined in the delayed clock signal delivered by the delay circuit 126. Figure 1 In the example shown, the delay modulation circuit 130 includes a differential amplifier having a non-inverting input and an inverting input, and an error voltage V. ERR The reference voltage V is intended to be applied to the non-inverting input. REF The current is intended to be applied to the inverting input. In this example, a current called Iadd is captured at the output of the delay modulation circuit 130, and the value of this current is related to the error voltage V. ERR The value of the reference voltage V REF The difference between the values ​​is proportional. As a variation, the delay modulation circuit 130 can output a value proportional to the error voltage V. ERR The value of the reference voltage V REF The voltage value is proportional to the difference between the values.

[0056] In an example of the embodiment, the power supply 100 further includes a ramp control signal V configured to output. CLK The corresponding periodic square wave signal generation circuit 132 generates a periodic square wave signal. In Figure 1 In the example, the ramp control signal V CLK It is also applied to the input of the delay circuit 126.

[0057] In power supply 100, the different paths taken by various signals and voltages result in errors in voltage V. ERR With reference voltage V REF A time delay is generated between them. In the described embodiment, this delay is particularly due to comparator 116, which is formed by multiple transistors and is relative to the periodic square wave signal V. CLK The periodic generation has a relatively long processing time. Therefore, there is a given signal propagation time between the input and output of comparator 116.

[0058] To overcome this drawback, the delay circuit 126 is configured to output a clock signal based on a delay modulated by the delay modulation circuit 130, the delay value of which is within the range from the signal propagation time in the comparator 116 to zero. In the described example, the delay modulation circuit 130 is configured to work with the error voltage VERR With reference voltage V REF The difference between the values ​​proportionally reduces the delay value, and reduces the delay value in the following manner: when the error voltage V ERR The value is lower than the reference voltage V REF The delay is greatest when the error voltage V is at its maximum value. ERR The value is equal to the reference voltage V. REF When the value is , the delay value decreases and tends to zero.

[0059] For example, the value of the signal propagation time in comparator 116 can be estimated during the calibration phase of power supply 100. Then, delay circuit 126 can be configured to apply a delay equal to the value of the signal propagation time in comparator 116 by default, and delay modulation circuit 130 then applies a coefficient having a value in the range of 0 to 1 to this delay.

[0060] Figure 3 An example of an embodiment of the delay circuit 126 is schematically illustrated.

[0061] In this example, the delay circuit 126 includes an inverter 134, which is formed by a PMOS transistor and an NMOS transistor series coupled between the power supply potential VCC and ground. The gates of the transistors in the inverter 134 are coupled together to form a ramp control signal V applied to them. CLK The input terminal of the delay circuit 126. In addition, the node 136 coupled to the transistor of the inverter 134 forms the output terminal of the inverter 134.

[0062] exist Figure 3 In this example, the delay circuit 126 also includes a Schmitt trigger 138, the input of which is coupled to node 136, and its output forms the output of the delay circuit 126 on which the delayed clock signal is delivered. Furthermore, in this example, the delay circuit 126 includes a capacitive element 140 coupled between node 136 and ground (GND).

[0063] The delay circuit 126 also includes a second transistor 141, which is an NMOS type second transistor, and this second transistor includes an active region with a size smaller than that of the NMOS transistor in the inverter 134. Figure 3 In the example, the second transistor 141 is coupled in series with the NMOS transistor of the inverter 134. The delay circuit 126 also includes a current source 143 that draws a current Iadd, the value of which is related to the error voltage V. ERR The value of the reference voltage V REF The difference between the values ​​is proportional. This current source 143 corresponds, for example, to a transistor controlled to draw current Iadd. In this example, if V... CLKWhen in a high state, capacitor 140 discharges through the NMOS transistor of inverter 134 and the second transistor 141. The second transistor 141 has a small size, and the discharge of capacitor 140 is slow, resulting in a delay. The current Iadd is added to the current of transistor 141 to accelerate the discharge of capacitor 140 through the NMOS transistor of inverter 134. If the error voltage V... ERR The value is equal to or close to the reference voltage V. REF The value of I is then due to add The error voltage V is equal to or close to 0, therefore the acquired delay is the maximum. ERR The value is much greater than the reference voltage V. REF The value of , then the current I add Significantly, the acquired delay decreases as the discharge of capacitor 140 accelerates.

[0064] Other alternative embodiments of the delay circuit 126 are also possible. For example, the delay circuit 126 may include a structure similar to comparator 116, in which the propagation time of the signal is replicated.

[0065] Figure 4 An example of an embodiment of the delay modulation circuit 130 is schematically shown in the figure.

[0066] exist Figure 4 In the delay modulation circuit 130, a differential pair 142 is included. This differential pair is formed by two CMOS transistors, and a voltage V is applied to the gate of each transistor. REF and V ERR . Figure 4 The illustrated delay modulation circuit 130 also includes current mirrors 144, 146, and 148, also formed from CMOS transistors. In this example, relative to the reference voltage V... REF Error voltage V ERR The higher the current, the more current is delivered by the PMOS transistor 146.2 of the current mirror 146, and the less current is consumed by the NMOS transistor 148.2. The delay modulation circuit 130 also includes another MOS transistor 150 coupled to the NMOS transistor 148.2 of the current mirror 148. The difference between the current supplied by the PMOS transistor 146.2 and the current consumed by the NMOS transistor 148.2 corresponds to the current I flowing through the transistor 150. add And corresponding to the current used to modulate the delay value based on the difference between the error voltage and the reference voltage. Figure 5 The current I obtained using this delay modulation circuit 130 is schematically shown. add In this example, the current I add The value and the difference V ERR -V REFIt increases in a linear proportion.

[0067] Figure 6 Examples of signals acquired in power supply 100 are shown, which have significant charging current (Fig. b) and low or zero charging current (Fig. a).

[0068] exist Figure 6 In Figure a), reference numeral 200 indicates the voltage ramp V obtained at the output of circuit 118. RAMP In the attached figure, reference numeral 202 indicates the error voltage V under PWM modulation. ERR The value of the reference voltage V under PFM modulation conditions REF The value is given, and reference numeral 204 indicates the current flowing through inductor 106. In Figure a), it is assumed that power supply 100 provides a very small output current, or that the power supply voltage V is constant. IN It's very high. Therefore, the first delay 206 occurs at the voltage ramp V. RAMP Exceeding the error voltage V ERR The time between the value of 204 and the time when the value of current 204 stops increasing and begins to decrease, and the second delay 207 occurs when the clock signal switches to a high state to ramp up the voltage V. RAMP The time between resetting to zero and the time when the value of current 204 stops decreasing and increases again. The first delay 206 is mainly due to the response time of comparator 116, and the second delay 207 is due to the delay introduced by delay circuit 126.

[0069] exist Figure 6 In Figure b), power supply 100 outputs a high current or has a voltage close to V. OUT Power supply voltage V IN Therefore, the error voltage V ERR The value is higher than that shown in Figure a). In Figure b), the first delay 206 appears at the voltage ramp V. RAMP Exceeding the error voltage V ERR The time between the value of the current 204 and the time when the value of the current 204 stops increasing and begins to decrease, but the second delay 207 observed in Figure a) does not appear.

[0070] In the specific embodiment described, the power supply 100 operates in a closed loop and, if necessary, can cause the duty cycle of one or more signals used to control one or more switches of the switching unit to have a high value, thereby causing the output voltage V to... OUT Equal to reference voltage V REF Regardless of the input voltage V IN What is the value of ?

[0071] Furthermore, in the example of the described embodiment, the power supply 100 is configured to generate a voltage ramp V controlled by a periodic square wave signal.RAMP The voltage ramp V RAMP With error voltage V ERR A comparison is made, and multiple control signals sent to the switching unit 101 are generated based on this comparison to cause the output voltage V to be adjusted. OUT Equal to reference voltage V REF .

[0072] However, due to the inherent signal propagation time, especially within comparator 116, the duty cycle obtained at the output of comparator 116 is higher than the theoretically obtained duty cycle, and corresponds to the voltage ramp V. RAMP From the error voltage V ERR Rise time. Error voltage V ERR The voltage slope V tends to decrease, causing the voltage ramp to V to decrease. RAMP The error voltage V is reached earlier than in the ideal case of a power supply with no inherent propagation time. ERR The value is adjusted to compensate for this delay.

[0073] Without correction for the generated delay, the control loop of power supply 100 will tend to reduce the error voltage V. ERR In order to control the output voltage V OUT The required duty cycle value. Therefore, especially based on the input voltage V IN Error voltage V ERR With reference voltage V REF There are differences.

[0074] When power supply 100 is turned on, the fact that a delay is applied to the control signals(s) of switching unit 101 advantageously allows a voltage ramp to be generated before the switch(s) or one of the switches in unit 101 is turned on by the control signals(s), thereby compensating for the inherent propagation time of the power supply 100 circuit and reducing the error voltage V. ERR With reference voltage V REF The difference between them, and reduce or even eliminate the input voltage V IN The impact on the quality of the transition between PWM modulation and PFM modulation. These transitions between PWM modulation and PFM modulation become more stable, and in the output voltage V OUT The resulting oscillations are less.

[0075] In the provided power supply 100, the delay and error voltage V of the (multiple) control signals applied to the switching unit 101 ERR With reference voltage V REF The difference between them decreases together, which allows for a high duty cycle of (multiple) control signals when needed, thereby achieving better performance of power supply 100 without affecting the bandwidth of power supply 100.

[0076] For example, Power 100 could be designed for use in the automotive industry, particularly electric vehicles.

[0077] For example, Power Supply 100 can be used in industrial applications, such as for the development of green energy or for the electrification of infrastructure, such as for charging stations or for integration with solar energy. The device can also be used in the Internet of Things (IoT) and smart home sectors. For example, the device is designed to be integrated into the power supply and energy circuitry of devices.

[0078] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0079] Finally, based on the functional indications given above, the actual implementation of the embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. A step-down switching mode power supply, comprising: The switching unit includes a first switch, which is configured to be periodically set to an on state by a first control signal modulated by a modulation type; An amplifier is configured to generate an error voltage representing the difference between a reference voltage and the output voltage of the power supply. A delay circuit is configured to apply a delay to the first control signal, the delay reducing the difference between the error voltage and the reference voltage; as well as A delay modulation circuit is configured to modulate the value of the delay based on the difference between the error voltage and the reference voltage.

2. The switching mode power supply according to claim 1, wherein the modulation type is pulse width modulation (PWM).

3. The switch-mode power supply according to claim 1, wherein the modulation type is pulse frequency modulation (PFM).

4. The switch-mode power supply of claim 1, wherein the delay modulation circuit is configured to deliver a current or voltage having a value proportional to the difference between the error voltage and the reference voltage as an output.

5. The switch-mode power supply of claim 1, wherein the delay modulation circuit is configured to reduce the value of the delay in proportion to the difference between the error voltage and the reference voltage.

6. The switch-mode power supply of claim 1, wherein the delay modulation circuit includes at least one differential amplifier, the at least one differential amplifier including a non-inverting input configured to receive the error voltage and an inverting input configured to receive the reference voltage.

7. The switch-mode power supply of claim 1, wherein the switch unit includes a second switch configured to be periodically set to the on state by a second control signal modulated by the modulation type, complementary to the first switch.

8. The switching power supply according to claim 1, further comprising: An inductive element, including a first electrode coupled to a connection node of the switching unit; as well as A capacitor element is coupled to the second electrode of the inductor element, and the output voltage of the power supply is obtained across the capacitor element.

9. The switch-mode power supply of claim 1, further comprising a comparator configured to receive, during the period of the first control signal, the following as inputs: the error voltage and a periodically increasing voltage ramp.

10. The switch-mode power supply according to claim 9, further comprising a control signal generation circuit, the control signal generation circuit being configured to generate the first control signal in response to the output signal of the comparator and the output signal of the delay circuit.

11. The switch-mode power supply of claim 9, further comprising a voltage ramp generation circuit configured to generate the ramp voltage and having an output coupled to a non-inverting input of the comparator.

12. The switch-mode power supply of claim 9 further includes a periodic signal generation circuit configured to deliver a periodic signal to the input of the delay circuit and the voltage ramp generation circuit, the periodic signal having a frequency equal to the frequency of the first control signal.

13. The switch-mode power supply of claim 12, wherein the delay modulation circuit is configured to deliver a current or voltage having a value proportional to the difference between the error voltage and the reference voltage as an output, and wherein the delay circuit comprises: An inverter is configured to receive the periodic signal delivered by the periodic signal generation circuit as input; A capacitor element is coupled to the output terminal of the inverter; A Schmitt trigger includes an input coupled to the output terminal of the inverter and has an output that forms the output of the delay circuit; A transistor, coupled in series with one of the transistors in the inverter, is configured to deliver a current as an output that has a maximum value lower than the maximum value of the transistor in the inverter; as well as A current source is configured to draw a current from the connection node between the transistor and the inverter, having a value proportional to the difference between the error voltage and the reference voltage.

14. A method for converting an input voltage into an output voltage, the output voltage having a value lower than the input voltage, the method comprising: Control at least one switching unit, the at least one switching unit including at least one first switch, the at least one first switch being periodically set to an on state by a first control signal modulated by a modulation type; Generate an error voltage representing the difference between the reference voltage and the output voltage of the power supply; A delay is generated, which reduces the difference between the error voltage and the reference voltage; The value of the modulation delay is a function of the difference between the error voltage and the reference voltage; as well as The modulated delay is applied to the first control signal.

15. The conversion method according to claim 14, wherein the modulation type is pulse width modulation (PWM).

16. The conversion method according to claim 14, wherein the modulation type is pulse frequency modulation (PFM).

17. The conversion method of claim 14, wherein the value of modulating the delay comprises: Generate a current or voltage having a value proportional to the difference between the error voltage and the reference voltage.

18. The conversion method of claim 14, wherein the value of modulating the delay comprises: The value of the delay is reduced proportionally to the value of the difference between the error voltage and the reference voltage.

19. The conversion method of claim 14, wherein the value of modulating the delay comprises: Determine the difference between the error voltage and the reference voltage.

20. The conversion method according to claim 14, further comprising: The error voltage is compared with the periodically increasing voltage ramp during the period of the first control signal; as well as The first control signal is generated in response to the comparison and the output signal generated by the delay.

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