A pre-charge low leakage control circuit and method
By controlling the back-gate connection of the MOS switch in the pre-charge buffer, the leakage current problem caused by the back-gate effect is solved, resulting in a more stable input current and lower signal distortion, thus improving the performance of the switched capacitor circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 苏州领慧立芯科技有限公司
- Filing Date
- 2026-02-09
- Publication Date
- 2026-05-19
AI Technical Summary
Existing precharge buffers in switched capacitor circuits suffer from leakage current problems caused by the back-gate effect, which affects the stability of the input current and signal distortion.
By controlling the operating phase of the circuit, the back gate of the MOS switch is connected to different operating nodes to ensure that it maintains the same potential as the input of the precharge buffer when it is turned on, thereby reducing or eliminating the effect of the back gate effect.
It effectively reduces the leakage current of MOS switches, improves the input current stability and signal sampling accuracy of switched capacitor circuits, and reduces signal distortion.
Smart Images
Figure CN121664166B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design technology, and specifically to a pre-charge low leakage control circuit and method. Background Technology
[0002] Precharge buffers are often used to charge switched capacitor circuits and reduce input current, as illustrated in patent application CN116961671A (which discloses a low-distortion precharge sampling circuit and a ΣΔ modulator). Figure 1 As shown.
[0003] Where Cs is the sampling capacitor and Cint is the integrating capacitor. Φ1 is the sampling phase and Φ2 is the integration phase. A1 and A2 are unity-gain buffers used to pre-charge the sampling capacitor, reducing the drive requirements of inputs IN+ and IN-. Φp is the pre-charging phase, located in the first half of the sampling phase Φ1. The switch between the input and Cs is controlled by Φp_bar and is in an open-circuit state. A1 and A2 pre-charge the capacitors at both ends. After pre-charging, the outputs of A1 and A2 are disconnected, and the inputs IN+ and IN- are connected to the sampling capacitor for high-precision signal sampling.
[0004] Without using a pre-charge circuit, the equivalent input current is:
[0005] Ieq=Cs Vin Fs;
[0006] Vin is the input differential voltage Vin=(Vin+ - Vin-), and Fs is the sampling clock frequency; a simple calculation: when Cs=5pF, Vin=5V, Fs=2MHz, the equivalent input current is 50uA.
[0007] Using a pre-charge buffer can significantly reduce the input current and lower the driving capability requirements of the input stage circuit. Assuming that the residual error after pre-charging is 10mV, and without considering the effects of factors such as switch charge injection, the equivalent input current is 100nA, which is about 1 / 500 of that without using a pre-charge structure.
[0008] The back-gate of a MOS switch is fixed to ground (NMOS switch) or power supply (PMOS switch). Due to the back-gate effect, the switch's turn-on impedance Ron changes significantly with the input voltage, exhibiting considerable nonlinearity. Connecting the back-gate of a MOS switch to the input voltage can eliminate the back-gate effect, and the change in the input voltage Ron impedance will also be relatively reduced.
[0009] Figure 2The diagram illustrates the relationship between the complementary transmission gate (T-gate) switch and the input voltage. As can be seen from the diagram, the impedance change is small when the back gate follows the input. This difference is even greater for low-voltage power supplies.
[0010] When the back grid of a switch is not connected to a fixed voltage and can follow the input, it can effectively reduce the impedance change of the switch, thereby reducing signal distortion. However, if the connection of the back grid is not handled properly, it will increase the leakage current of the input, affecting applications that are sensitive to input current, such as various pressure and temperature sensors.
[0011] Based on this technical background, the present invention studies a pre-charge low leakage control circuit and method. Summary of the Invention
[0012] To address the shortcomings of existing technologies, this invention proposes a pre-charge low leakage control circuit and method. This control circuit can connect the back gate of the MOS switch to different operating nodes according to the operating phase of the control circuit, ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the pre-charge buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit.
[0013] To achieve the above objectives, a first aspect of the present invention provides a pre-charge low leakage control circuit, comprising:
[0014] The source of the MOS switch is electrically connected to the input terminal of the precharge buffer, and the drain is electrically connected to the output terminal of the precharge buffer. The MOS switch is an NMOS switch, a PMOS switch, or a CMOS switch.
[0015] A control switch network includes multiple control switches, one end of which is electrically connected to the input terminal of a switched capacitor circuit. The control switch network is used to connect the back gate of the MOS switch to different operating nodes according to the operating phase of the control circuit, ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit.
[0016] A second aspect of the present invention provides a pre-charge low leakage control method in the above-described control circuit, comprising:
[0017] The source of the MOS switch is electrically connected to the input terminal of the precharge buffer as the first port, and the drain is electrically connected to the output terminal of the precharge buffer as the second port. The MOS switch is an NMOS switch, a PMOS switch, or a CMOS switch.
[0018] One end of one of the multiple control switches is electrically connected to the input terminal of the switched capacitor circuit. The back gate of the MOS switch is connected to different working nodes according to the working phase of the control circuit. This ensures that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit.
[0019] The beneficial effects of this invention include:
[0020] The pre-charge low leakage current control circuit proposed in this invention can connect the back gate of the MOS switch to different working nodes according to the working phase of the control circuit, ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the pre-charge buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit.
[0021] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description
[0022] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.
[0023] Figure 1 This is a schematic diagram of the structure and operating phase timing relationship of an existing switched capacitor charging circuit with a pre-charge buffer.
[0024] Figure 2 This is a schematic diagram showing the relationship between the impedance of a complementary transmission gate (T-gate) switch and the input voltage.
[0025] Figure 3 This is a schematic diagram showing the structure and operating phase timing relationship of a specific embodiment of the pre-charge low leakage control circuit proposed in this invention.
[0026] Figure 4 This is a schematic diagram of another specific embodiment of the pre-charge low leakage control circuit proposed in this invention.
[0027] Figure 5 This is a schematic diagram of the third specific embodiment of the pre-charge low leakage control circuit proposed in this invention.
[0028] Figure 6 This is a schematic diagram showing the structure and operating phase timing relationship of the fourth specific embodiment of the pre-charge low leakage control circuit proposed in this invention.
[0029] Figure 7This is a schematic diagram of the fifth specific embodiment of the pre-charge low leakage control circuit proposed in this invention.
[0030] Figure 8 This is a schematic diagram of the sixth specific embodiment of the pre-charge low leakage control circuit proposed in this invention.
[0031] Explanation of reference numerals in the attached figures:
[0032] A0 - Precharge buffer, SW_C - Switched capacitor circuit, NS - NMOS switch, PS - PMOS switch, CS - CMOS switch, K1 - First control switch, K2 - Second control switch, K3 - Third control switch, K4 - Fourth control switch, K5 - Fifth control switch, K6 - Sixth control switch, K7 - Seventh control switch;
[0033] IN - Input terminal of the precharge buffer, Out_int - Output terminal of the precharge buffer, Out - Output of the MOS switch, Ф1 - Precharge phase, Ф2 - Sampling phase. - The inverted phase of the sampling phase, Ф2s - the second back-gate phase, Ф2e - the first back-gate phase. -The out-of-phase phase of the second back grid phase, - The inverted phase of the first back grid phase;
[0034] VDD - Power supply, GND - Ground. Detailed Implementation
[0035] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.
[0036] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in its normal operating state, while "inner" and "outer" refer to their position relative to the device's outline. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0037] This invention provides a pre-charge low leakage control circuit, such as... Figure 3-8 As shown, it includes:
[0038] The source of the MOS switch is electrically connected to the input terminal IN of the precharge buffer, and the drain is electrically connected to the output terminal Out_int of the precharge buffer. The MOS switch can be an NMOS switch (NS), a PMOS switch (PS), or a CMOS switch (CS).
[0039] The control switch network includes multiple control switches, one end of which is electrically connected to the input terminal of the switched capacitor circuit SW_C. The control switch network is used to connect the back gate of the MOS switch to different working nodes according to the working phase of the control circuit, so as to ensure that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the precharge buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit.
[0040] According to the present invention, the operating phase of the control circuit includes a pre-charge phase Ф1 and a sampling phase Ф2;
[0041] The pre-charge phase Ф1 and the sampling phase Ф2 are out of phase.
[0042] The gate of the MOS switch is controlled by the sampling phase Ф2 and / or the inverted phase of the sampling phase. control.
[0043] According to the present invention, when the MOS switch is an NMOS switch NS, the source of the NMOS switch NS is electrically connected to the input terminal IN of the precharge buffer, the drain is electrically connected to the output terminal Out_int of the precharge buffer, and the gate is controlled by the sampling phase Ф2.
[0044] The multiple control switches include a first control switch K1, a second control switch K2, and a third control switch K3;
[0045] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of it is simultaneously connected to the input terminal of the switched capacitor circuit SW_C, the drain of the NMOS switch NS, and one end of the second control switch K2, while the other end is connected to the output terminal Out_int of the pre-charge buffer.
[0046] The second control switch K2 is controlled by the first back gate phase Ф2e, which leads the sampling phase Ф2, and its period and duty cycle are the same as those of the sampling phase Ф2. The other end of the second control switch K2 is simultaneously electrically connected to the back gate of the NMOS switch NS and one end of the third control switch K3.
[0047] The third control switch K3 is the inverted phase of the first back gate phase. The control is provided, and its other end is electrically connected to ground (GND).
[0048] or,
[0049] The multiple control switches include a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, and a fifth control switch K5;
[0050] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of it is simultaneously connected to the input terminal of the switched capacitor circuit SW_C and the drain of the NMOS switch NS, while the other end is connected to the output terminal Out_int of the pre-charge buffer.
[0051] The second control switch K2 is controlled by the second back grid phase Ф2s. The period of the back grid phase is the same as the period of the sampling phase Ф2, and its duty cycle is less than the duty cycle of the sampling phase Ф2. One end of the second control switch K2 is electrically connected to one end of the first control switch K1, and the other end is electrically connected to one end of the third control switch K3 and one end of the fourth control switch K4.
[0052] The third control switch K3 is the inverted phase of the second back gate phase. It controls the circuit, and its other end is electrically connected to the source of the NMOS switch NS;
[0053] The fourth control switch K4 is controlled by the sampling phase Ф2, and its other end is simultaneously electrically connected to the back gate of the NMOS switch NS and one end of the fifth control switch K5.
[0054] The fifth control switch K5 is controlled by the pre-charge phase Ф1, and its other end is electrically connected to ground GND.
[0055] According to the present invention, when the MOS switch is a PMOS switch PS, the source of the PMOS switch PS is electrically connected to the input terminal IN of the precharge buffer, the drain is electrically connected to the output terminal Out_int of the precharge buffer, and the gate is connected to the inverted phase of the sampling phase. control;
[0056] The multiple control switches include a first control switch K1, a second control switch K2, and a third control switch K3;
[0057] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of it is simultaneously connected to the input terminal of the switched capacitor circuit SW_C, the drain of the PMOS switch PS, and one end of the second control switch K2, while the other end is connected to the output terminal Out_int of the pre-charge buffer.
[0058] The second control switch K2 is controlled by the first back gate phase Ф2e, which leads the sampling phase Ф2, and its period and duty cycle are the same as those of the sampling phase Ф2. The other end of the second control switch K2 is simultaneously electrically connected to the back gate of the PMOS switch PS and one end of the third control switch K3.
[0059] The third control switch K3 is the inverted phase of the first back gate phase. It is controlled, and its other end is electrically connected to the power supply VDD;
[0060] or,
[0061] The multiple control switches include a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, and a fifth control switch K5;
[0062] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of it is simultaneously connected to the input terminal of the switched capacitor circuit SW_C and the drain of the PMOS switch PS, while the other end is connected to the output terminal Out_int of the pre-charge buffer.
[0063] The second control switch K2 is controlled by the second back grid phase Ф2s. The period of the back grid phase is the same as the period of the sampling phase Ф2, and its duty cycle is less than the duty cycle of the sampling phase Ф2. One end of the second control switch K2 is electrically connected to one end of the first control switch K1, and the other end is electrically connected to one end of the third control switch K3 and one end of the fourth control switch K4.
[0064] The third control switch K3 is the inverted phase of the second back gate phase. It controls the circuit, and its other end is electrically connected to the source of the PMOS switch PS.
[0065] The fourth control switch K4 is controlled by the sampling phase Ф2, and its other end is simultaneously electrically connected to the back gate of the PMOS switch PS and one end of the fifth control switch K5.
[0066] The fifth control switch K5 is controlled by the pre-charge phase Ф1, and its other end is electrically connected to ground GND.
[0067] According to the present invention, when the MOS switch is a CMOS switch CS, the CMOS switch CS includes an NMOS sub-switch and a PMOS sub-switch. The sources of the NMOS sub-switch and the PMOS sub-switch are electrically connected to each other and to the input terminal IN of the precharge buffer, and their drains are electrically connected to each other and to the output terminal Out_int of the precharge buffer. The gate of the NMOS sub-switch is controlled by the sampling phase Ф2, and the gate of the PMOS sub-switch is controlled by the inverted phase of the sampling phase. control;
[0068] The multiple control switches include a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, and a fifth control switch K5;
[0069] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of it is simultaneously connected to the input terminal of the switched capacitor circuit SW_C, the drain of the NMOS sub-switch, the drain of the PMOS sub-switch, one end of the second control switch K2, and one end of the fourth control switch K4, while the other end is connected to the output terminal Out_int of the pre-charge buffer.
[0070] The second control switch K2 and the fourth control switch K4 are both controlled by the first back gate phase Ф2e. The back gate phase leads the sampling phase Ф2, and its period and duty cycle are the same as those of the sampling phase Ф2. The other end of the second control switch K2 is simultaneously electrically connected to the back gate of the NMOS switch NS and one end of the third control switch K3. The other end of the fourth control switch K4 is simultaneously electrically connected to the back gate of the PMOS switch PS and one end of the fifth control switch K5.
[0071] The third control switch K3 and the fifth control switch K5 are both inverted phases of the first back gate phase. The other end of the third control switch K3 is electrically connected to ground GND, and the other end of the fifth control switch K5 is electrically connected to the power supply VDD.
[0072] or,
[0073] The multiple control switches include a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, a fifth control switch K5, a sixth control switch K6, and a seventh control switch K7;
[0074] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of it is simultaneously connected to the input terminal of the switched capacitor circuit SW_C, the drain of the NMOS sub-switch, and the drain of the PMOS sub-switch. The other end is simultaneously connected to the output terminal Out_int of the pre-charge buffer, one end of the second control switch K2, and one end of the fourth control switch K4.
[0075] The second control switch K2 is controlled by the second back gate phase Ф2s. The period of the second back gate phase Ф2s is the same as the period of the sampling phase Ф2, and its duty cycle is less than the duty cycle of the sampling phase Ф2. One end of the second control switch K2 is electrically connected to one end of the first control switch K1, and the other end is simultaneously electrically connected to one end of the third control switch K3, one end of the fourth control switch K4, and one end of the sixth control switch K6.
[0076] The third control switch K3 is the inverted phase of the second back gate phase. It controls the operation, and its other end is simultaneously electrically connected to the source of both the NMOS sub-switch and the PMOS sub-switch.
[0077] The fourth control switch K4 and the sixth control switch K6 are both controlled by the sampling phase Ф2. The other end of the fourth control switch K4 is simultaneously electrically connected to the back gate of the NMOS sub-switch and one end of the fifth control switch K5. The other end of the sixth control switch K6 is simultaneously electrically connected to the back gate of the PMOS sub-switch and one end of the seventh control switch K7.
[0078] The fifth control switch K5 and the seventh control switch K7 are both controlled by the pre-charge phase Ф1. The other end of the fifth control switch K5 is electrically connected to ground GND, and the other end of the seventh control switch K7 is electrically connected to the power supply VDD.
[0079] or,
[0080] The multiple control switches include a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, and a fifth control switch K5;
[0081] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of it is simultaneously connected to the input terminal of the switched capacitor circuit SW_C, the drain of the NMOS sub-switch, and the drain of the PMOS sub-switch. The other end is simultaneously connected to the output terminal Out_int of the pre-charge buffer, one end of the second control switch K2, and one end of the fourth control switch K4.
[0082] The second control switch K2 and the fourth control switch K4 are both controlled by the sampling phase Ф2. One end of the second control switch K2 is electrically connected to one end of the first control switch K1, and the other end is simultaneously electrically connected to the back gate of the NMOS switch NS and one end of the third control switch K3. One end of the fourth control switch K4 is electrically connected to one end of the first control switch K1, and the other end is simultaneously electrically connected to the back gate of the PMOS switch PS and one end of the fifth control switch K5.
[0083] The third control switch K3 and the fifth control switch K5 are both controlled by the pre-charge phase Ф1. The other end of the third control switch K3 is electrically connected to ground GND, and the other end of the fifth control switch K5 is electrically connected to the power supply VDD.
[0084] The present invention also provides a pre-charge low leakage control method in the above-described control circuit, characterized in that it includes:
[0085] Connect the source of the MOS switch as the first port to the input terminal IN of the precharge buffer, and connect the drain as the second port to the output terminal Out_int of the precharge buffer. The MOS switch can be an NMOS switch NS, a PMOS switch PS, or a CMOS switch CS.
[0086] One end of one of the multiple control switches is electrically connected to the input terminal of the switched capacitor circuit SW_C. The back gate of the MOS switch is connected to different working nodes according to the working phase of the control circuit. This ensures that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the precharge buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit.
[0087] According to the present invention, it further includes:
[0088] Controlled by sampling phase Ф2 and / or the inverted phase of the sampling phase. Controlling the gate of the MOS switch, wherein the inverted phase of the sampling phase This is the pre-charge phase Ф1.
[0089] According to the present invention, when the MOS switch is an NMOS switch NS, the source of the NMOS switch NS is electrically connected to the input terminal IN of the precharge buffer, the drain is electrically connected to the output terminal Out_int of the precharge buffer, and the gate is controlled by the sampling phase Ф2.
[0090] One end of one of the multiple control switches is electrically connected to the input terminal of the switched capacitor circuit SW_C. The back gate of the MOS switch is connected to different operating nodes according to the operating phase of the control circuit, ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the pre-charge buffer. This includes:
[0091] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of the first control switch K1 is simultaneously connected to the input terminal of the switched capacitor circuit SW_C, the drain of the NMOS switch NS, and one end of the second control switch K2, while the other end is connected to the output terminal Out_int of the pre-charge buffer.
[0092] The second control switch K2 is controlled by the first back gate phase Ф2e. The back gate phase leads the sampling phase Ф2, and its period and duty cycle are the same as those of the sampling phase Ф2. The other end of the second control switch K2 is simultaneously electrically connected to the back gate of the NMOS switch NS and one end of the third control switch K3.
[0093] The inverted phase of the first back gate phase Control the third control switch K3 and connect the other end of the third control switch K3 to ground GND, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the precharge buffer.
[0094] Or, including:
[0095] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of the first control switch K1 is simultaneously connected to the input terminal of the switched capacitor circuit SW_C and the drain of the NMOS switch NS, and the other end is connected to the output terminal Out_int of the pre-charge buffer.
[0096] The second control switch K2 is controlled by the second back gate phase Ф2s. The period of the back gate phase is the same as the period of the sampling phase Ф2, and its duty cycle is less than the duty cycle of the sampling phase Ф2. One end of the second control switch K2 is electrically connected to one end of the first control switch K1, and the other end is simultaneously electrically connected to one end of the third control switch K3 and one end of the fourth control switch K4.
[0097] The inverted phase of the second back gate phase Control the third control switch K3, and electrically connect the other end of the third control switch K3 to the source of the NMOS switch NS;
[0098] The sampling phase Ф2 controls the fourth control switch K4, and the other end of the fourth control switch K4 is simultaneously electrically connected to the back gate of the NMOS switch NS and one end of the fifth control switch K5.
[0099] The fifth control switch K5 is controlled by the pre-charge phase Ф1, and the other end of the fifth control switch K5 is electrically connected to ground GND, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the pre-charge buffer.
[0100] According to the present invention, when the MOS switch is a PMOS switch PS, the source of the PMOS switch PS is electrically connected to the input terminal IN of the precharge buffer, the drain is electrically connected to the output terminal Out_int of the precharge buffer, and the gate is connected to the inverted phase of the sampling phase. control;
[0101] One end of one of the multiple control switches is electrically connected to the input terminal of the switched capacitor circuit SW_C. The back gate of the MOS switch is connected to different operating nodes according to the operating phase of the control circuit, ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the pre-charge buffer. This includes:
[0102] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of the first control switch K1 is simultaneously connected to the input terminal of the switched capacitor circuit SW_C, the drain of the PMOS switch PS, and one end of the second control switch K2, while the other end is connected to the output terminal Out_int of the pre-charge buffer.
[0103] The second control switch K2 is controlled by the first back gate phase Ф2e. The back gate phase leads the sampling phase Ф2, and its period and duty cycle are the same as those of the sampling phase Ф2. The other end of the second control switch K2 is simultaneously electrically connected to the back gate of the PMOS switch PS and one end of the third control switch K3.
[0104] The inverted phase of the first back gate phase Control the third control switch K3 and connect the other end of the third control switch K3 to the power supply VDD, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the precharge buffer.
[0105] Or, including:
[0106] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of the first control switch K1 is simultaneously connected to the input terminal of the switched capacitor circuit SW_C and the drain of the PMOS switch PS, and the other end is connected to the output terminal Out_int of the pre-charge buffer.
[0107] The second control switch K2 is controlled by the second back gate phase Ф2s. The period of the back gate phase is the same as the period of the sampling phase Ф2, and its duty cycle is less than the duty cycle of the sampling phase Ф2. One end of the second control switch K2 is electrically connected to one end of the first control switch K1, and the other end is simultaneously electrically connected to one end of the third control switch K3 and one end of the fourth control switch K4.
[0108] The inverted phase of the second back gate phase Control the third control switch K3, and electrically connect the other end of the third control switch K3 to the source of the PMOS switch PS;
[0109] The sampling phase Ф2 controls the fourth control switch K4, and the other end of the fourth control switch K4 is simultaneously electrically connected to the back gate of the PMOS switch PS and one end of the fifth control switch K5.
[0110] The fifth control switch K5 is controlled by the pre-charge phase Ф1, and the other end of the fifth control switch K5 is electrically connected to ground GND, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the pre-charge buffer.
[0111] According to the present invention, when the MOS switch is a CMOS switch CS, the CMOS switch CS includes an NMOS sub-switch and a PMOS sub-switch. The sources of the NMOS sub-switch and the PMOS sub-switch are electrically connected to each other and electrically connected to the input terminal IN of the precharge buffer. The drains are electrically connected to each other and electrically connected to the output terminal Out_int of the precharge buffer. The gate of the NMOS sub-switch is controlled by the sampling phase Ф2, and the gate is controlled by the inverted phase of the sampling phase. The gate of the PMOS sub-switch is controlled;
[0112] One end of one of the multiple control switches is electrically connected to the input terminal of the switched capacitor circuit SW_C. The back gate of the MOS switch is connected to different operating nodes according to the operating phase of the control circuit, ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the pre-charge buffer. This includes:
[0113] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of the first control switch K1 is simultaneously connected to the input terminal of the switched capacitor circuit SW_C, the drain of the NMOS sub-switch, the drain of the PMOS sub-switch, one end of the second control switch K2, and one end of the fourth control switch K4, while the other end is connected to the output terminal Out_int of the pre-charge buffer.
[0114] The second control switch K2 and the fourth control switch K4 are controlled by the first back gate phase Ф2e. The back gate phase leads the sampling phase Ф2, and its period and duty cycle are the same as those of the sampling phase Ф2. The other end of the second control switch K2 is simultaneously connected to the back gate of the NMOS switch NS and one end of the third control switch K3. The other end of the fourth control switch K4 is simultaneously connected to the back gate of the PMOS switch PS and one end of the fifth control switch K5.
[0115] The inverted phase of the first back gate phase Control the third control switch K3 and the fifth control switch K5, connect the other end of the third control switch K3 to ground GND, and connect the other end of the fifth control switch K5 to the power supply VDD, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the precharge buffer;
[0116] Or, including:
[0117] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of the first control switch K1 is simultaneously connected to the input terminal of the switched capacitor circuit SW_C, the drain of the NMOS sub-switch, and the drain of the PMOS sub-switch. The other end is simultaneously connected to the output terminal Out_int of the pre-charge buffer, one end of the second control switch K2, and one end of the fourth control switch K4.
[0118] The second control switch K2 is controlled by the second back-gate phase Ф2s. The period of the back-gate phase is the same as the period of the sampling phase Ф2, and its duty cycle is less than that of the sampling phase Ф2. One end of the second control switch K2 is electrically connected to one end of the first control switch K1, and the other end is simultaneously electrically connected to one end of the third control switch K3, one end of the fourth control switch K4, and one end of the sixth control switch K6.
[0119] The inverted phase of the second back gate phase Control the third control switch K3, and simultaneously connect the other end of the third control switch K3 to the source of both the NMOS sub-switch and the PMOS sub-switch.
[0120] The sampling phase Ф2 controls the fourth control switch K4 and the sixth control switch K6, and simultaneously connects the other end of the fourth control switch K4 to the back gate of the NMOS sub-switch and one end of the fifth control switch K5, and simultaneously connects the other end of the sixth control switch K6 to the back gate of the PMOS sub-switch and one end of the seventh control switch K7.
[0121] The fifth control switch K5 and the seventh control switch K7 are controlled by the pre-charge phase Ф1. The other end of the fifth control switch K5 is electrically connected to ground GND, and the other end of the seventh control switch K7 is electrically connected to the power supply VDD. This ensures that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the pre-charge buffer.
[0122] Or, including:
[0123] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of the first control switch K1 is simultaneously connected to the input terminal of the switched capacitor circuit SW_C, the drain of the NMOS sub-switch, and the drain of the PMOS sub-switch. The other end is simultaneously connected to the output terminal Out_int of the pre-charge buffer, one end of the second control switch K2, and one end of the fourth control switch K4.
[0124] The sampling phase Ф2 controls the second control switch K2 and the fourth control switch K4. One end of the second control switch K2 is electrically connected to one end of the first control switch K1, and the other end is simultaneously electrically connected to the back gate of the NMOS switch NS and one end of the third control switch K3. One end of the fourth control switch K4 is electrically connected to one end of the first control switch K1, and the other end is simultaneously electrically connected to the back gate of the PMOS switch PS and one end of the fifth control switch K5.
[0125] The precharge phase Ф1 controls the third control switch K3 and the fifth control switch K5, and connects the other end of the third control switch K3 to ground GND and the other end of the fifth control switch K5 to the power supply VDD, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal IN of the precharge buffer.
[0126] The present invention will now be described in more detail through specific embodiments.
[0127] Example 1
[0128] like Figure 3As shown, this embodiment provides a pre-charge low leakage control circuit. The operating phase of the control circuit includes a pre-charge phase Ф1 and a sampling phase Ф2. The pre-charge phase Ф1 and the sampling phase Ф2 are opposite phases to each other. The MOS switch is an NMOS switch NS. Its source is electrically connected to the input terminal IN of the pre-charge buffer, and its drain is electrically connected to the output terminal Out_int of the pre-charge buffer. The gate is controlled by the sampling phase Ф2.
[0129] The multiple control switches include a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, and a fifth control switch K5;
[0130] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of it is electrically connected to the input terminal of the switched capacitor circuit SW_C, and the other end is electrically connected to the drain of the NMOS switch NS.
[0131] The second control switch K2 is controlled by the second back grid phase Ф2s. The period of the back grid phase is the same as the period of the sampling phase Ф2, and its duty cycle is less than the duty cycle of the sampling phase Ф2. One end of the second control switch K2 is electrically connected to one end of the first control switch K1, and the other end is electrically connected to one end of the third control switch K3 and one end of the fourth control switch K4.
[0132] The third control switch K3 is the inverted phase of the second back gate phase. It controls the circuit, and its other end is electrically connected to the source of the NMOS switch NS;
[0133] The fourth control switch K4 is controlled by the sampling phase Ф2, and its other end is simultaneously electrically connected to the back gate of the NMOS switch NS and one end of the fifth control switch K5.
[0134] The fifth control switch K5 is controlled by the pre-charge phase Ф1, and its other end is electrically connected to ground GND.
[0135] In this embodiment, the back gate of the NMOS switch NS is controlled by multiple control switches to connect to different nodes according to the pre-charge working phase.
[0136] During the pre-charge phase Φ1, the NMOS switch NS is off, and the back gate is connected to ground GND. After pre-charging, the NMOS switch NS turns on (operating in sampling phase Φ2). The back gate is first briefly connected to the output Out_int of the pre-charge buffer A0 (controlled by the second back gate phase Φ2s). The pre-charge buffer A0 makes the back gate voltage reach the potential of the input IN, and then connects it to the input terminal IN of the pre-charge buffer (controlled by the inverted phase of the second back gate phase). (Control); Through this timing control, when the NMOS switch NS is turned on, the back gate can always maintain the same potential as the input, and no additional current will be introduced due to the switching of the back gate in different phases.
[0137] Example 2
[0138] As shown in Figure 4, the difference between this embodiment and Embodiment 1 is that the NMOS switch NS is replaced by a PMOS switch PS, and the gate is replaced by the inverted phase of the sampling phase. When the PMOS switch PS is in the off phase, the back gate is connected to the power supply VDD.
[0139] Example 3
[0140] like Figure 5 As shown, this embodiment differs from Embodiment 1 in that the NMOS switch NS is replaced by a CMOS switch CS, and the CMOS switch CS includes an NMOS sub-switch and a PMOS sub-switch. The sources of the NMOS and PMOS sub-switches are electrically connected to each other and to the input terminal IN of the precharge buffer, and their drains are electrically connected to each other and to the output terminal Out_int of the precharge buffer. The gate of the NMOS sub-switch is controlled by the sampling phase Ф2, and the gate of the PMOS sub-switch is controlled by the inverted phase of the sampling phase. When the PMOS sub-switch is in the off phase, the back gate is connected to the power supply VDD.
[0141] Example 4
[0142] like Figure 6 As shown, this embodiment provides a pre-charge low leakage control circuit. The operating phase of the control circuit includes a pre-charge phase Ф1 and a sampling phase Ф2. The pre-charge phase Ф1 and the sampling phase Ф2 are opposite phases to each other. The MOS switch is an NMOS switch NS. Its source is electrically connected to the input terminal IN of the pre-charge buffer, and its drain is electrically connected to the output terminal Out_int of the pre-charge buffer. The gate is controlled by the sampling phase Ф2.
[0143] The multiple control switches include a first control switch K1, a second control switch K2, and a third control switch K3;
[0144] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of it is electrically connected to the input terminal of the switched capacitor circuit SW_C, while the other end is simultaneously electrically connected to the drain of the NMOS switch NS and one end of the second control switch K2.
[0145] The second control switch K2 is controlled by the first back gate phase Ф2e, which leads the sampling phase Ф2, and its period and duty cycle are the same as those of the sampling phase Ф2. The other end of the second control switch K2 is simultaneously electrically connected to the back gate of the NMOS switch NS and one end of the third control switch K3.
[0146] The third control switch K3 is the inverted phase of the first back gate phase. It is controlled, and its other end is electrically connected to ground (GND).
[0147] In this embodiment, the back gate of the NMOS switch NS is connected to different nodes according to the pre-charge working phase through switch control.
[0148] During the pre-charge phase Φ1, the NMOS switch NS is in the off state, and the back gate is connected to ground GND. Before the pre-charge is about to end, the back gate of the NMOS switch NS is controlled by the second control switch K2 to open in advance by the first back gate phase Φ2e. The back gate is connected to the output Out of the MOS switch (i.e., the NMOS switch NS). At this time, out is still driven by the pre-charge buffer A0, and the back gate voltage is charged by the pre-charge buffer A0 to the same potential as the input terminal IN of the pre-charge buffer. Then the pre-charge phase Φ1 ends, and the main path switch is turned on (controlled by the sampling phase Φ2).
[0149] This structure has a similar effect to the previous one, allowing the back grid to follow the input voltage when the switch is on, while avoiding the introduction of additional leakage current when the back grid switches.
[0150] Example 5
[0151] like Figure 7 As shown, this embodiment differs from Embodiment 4 in that the NMOS switch NS is replaced by a CMOS switch CS, and the CMOS switch CS includes an NMOS sub-switch and a PMOS sub-switch. The sources of the NMOS and PMOS sub-switches are electrically connected to each other and to the input terminal IN of the precharge buffer, and their drains are electrically connected to each other and to the output terminal Out_int of the precharge buffer. The gate of the NMOS sub-switch is controlled by the sampling phase Ф2, and the gate of the PMOS sub-switch is controlled by the inverted phase of the sampling phase. When the PMOS sub-switch is in the off phase, the back gate is connected to the power supply VDD.
[0152] Example 6
[0153] like Figure 8As shown, this embodiment provides a pre-charge low-leakage control circuit. The operating phases of the control circuit include a pre-charge phase Ф1 and a sampling phase Ф2, which are opposite phases. The MOS switch is a CMOS switch CS, which includes an NMOS sub-switch and a PMOS sub-switch. The sources of the NMOS and PMOS sub-switches are electrically connected to each other and to the input terminal IN of the pre-charge buffer, and their drains are electrically connected to each other and to the output terminal Out_int of the pre-charge buffer. The gate of the NMOS sub-switch is controlled by the sampling phase Ф2, and the gate of the PMOS sub-switch is controlled by the inverse phase of the sampling phase Ф2. control
[0154] The multiple control switches include a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, and a fifth control switch K5;
[0155] The first control switch K1 is controlled by the pre-charge phase Ф1, and one end of it is electrically connected to the input terminal of the switched capacitor circuit SW_C, while the other end is simultaneously electrically connected to the drain of the NMOS sub-switch and the drain of the PMOS sub-switch.
[0156] The second control switch K2 and the fourth control switch K4 are both controlled by the sampling phase Ф2. One end of the second control switch K2 is electrically connected to one end of the first control switch K1, and the other end is simultaneously electrically connected to the back gate of the NMOS switch NS and one end of the third control switch K3. One end of the fourth control switch K4 is electrically connected to one end of the first control switch K1, and the other end is simultaneously electrically connected to the back gate of the PMOS switch PS and one end of the fifth control switch K5.
[0157] The third control switch K3 and the fifth control switch K5 are both controlled by the pre-charge phase Ф1. The other end of the third control switch K3 is electrically connected to ground GND, and the other end of the fifth control switch K5 is electrically connected to the power supply VDD.
[0158] In this embodiment, when the back gate of the CMOS switch CS is turned on, it is connected to the output terminal out_int of the precharge buffer. Because the output of the precharge buffer A0 follows the change of the input, the voltage of the back gate of the switch is the same as the voltage of the input terminal IN of the precharge buffer. The advantage of this connection is that the switching of the back gate is not directly connected to the input, and the charge injection to the input is minimized. The disadvantage is that for low-power designs, if the input changes rapidly, the output of the precharge buffer A0 may not be able to keep up in time.
[0159] The pre-charge low leakage current control circuit proposed in the embodiments of the present invention can connect the back gate of the MOS switch to different working nodes according to the working phase of the control circuit, so as to ensure that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the pre-charge buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit.
[0160] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.
Claims
1. A pre-charge low-leakage control circuit, characterized in that, include: The source of the MOS switch is electrically connected to the input terminal of the precharge buffer, and the drain is electrically connected to the output terminal of the precharge buffer. The MOS switch is an NMOS switch, a PMOS switch, or a CMOS switch. A control switch network includes multiple control switches, one end of which is electrically connected to the input terminal of a switched capacitor circuit. The control switch network is used to connect the back gate of the MOS switch to different operating nodes according to the operating phase of the control circuit, ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit. The operating phases of the control circuit include a pre-charge phase and a sampling phase; The pre-charge phase and the sampling phase are out of phase with each other; The gate of the MOS switch is controlled by the sampling phase and / or the inverting phase of the sampling phase; When the MOS switch is an NMOS switch, the source of the NMOS switch is electrically connected to the input terminal of the precharge buffer, the drain is electrically connected to the output terminal of the precharge buffer, and the gate is controlled by the sampling phase. The plurality of control switches include a first control switch, a second control switch, and a third control switch; The first control switch is controlled by the pre-charge phase, and one end of the first control switch is electrically connected to the input terminal of the switched capacitor circuit, the drain of the NMOS switch, and one end of the second control switch, while the other end is electrically connected to the output terminal of the pre-charge buffer. The second control switch is controlled by the first back gate phase, which leads the sampling phase, and its period and duty cycle are the same as those of the sampling phase. The other end of the second control switch is electrically connected to the back gate of the NMOS switch and one end of the third control switch. The third control switch is controlled by the inverse phase of the first back grid phase, and its other end is connected to ground. or, The plurality of control switches include a first control switch, a second control switch, a third control switch, a fourth control switch, and a fifth control switch; The first control switch is controlled by the pre-charge phase, and one end of it is electrically connected to the input terminal of the switched capacitor circuit and the drain of the NMOS switch, while the other end is electrically connected to the output terminal of the pre-charge buffer. The second control switch is controlled by a second back-gate phase, the period of which is the same as the period of the sampling phase, and its duty cycle is less than the duty cycle of the sampling phase. One end of the second control switch is electrically connected to one end of the first control switch, and the other end is simultaneously electrically connected to one end of the third control switch and one end of the fourth control switch. The third control switch is controlled by the inverted phase of the second back gate phase, and its other end is electrically connected to the source of the NMOS switch. The fourth control switch is controlled by the sampling phase, and its other end is simultaneously electrically connected to the back gate of the NMOS switch and one end of the fifth control switch. The fifth control switch is controlled by the pre-charge phase, and its other end is connected to ground.
2. The control circuit according to claim 1, characterized in that, When the MOS switch is a PMOS switch, the source of the PMOS switch is electrically connected to the input terminal of the precharge buffer, the drain is electrically connected to the output terminal of the precharge buffer, and the gate is controlled by the inverted phase of the sampling phase. The plurality of control switches include a first control switch, a second control switch, and a third control switch; The first control switch is controlled by the pre-charge phase, and one end of the first control switch is electrically connected to the input terminal of the switched capacitor circuit, the drain of the PMOS switch, and one end of the second control switch, while the other end is electrically connected to the output terminal of the pre-charge buffer. The second control switch is controlled by the first back gate phase, which leads the sampling phase, and its period and duty cycle are the same as those of the sampling phase. The other end of the second control switch is electrically connected to the back gate of the PMOS switch and one end of the third control switch. The third control switch is controlled by the inverted phase of the first back gate phase, and its other end is electrically connected to the power supply. or, The plurality of control switches include a first control switch, a second control switch, a third control switch, a fourth control switch, and a fifth control switch; The first control switch is controlled by the pre-charge phase, and one end of it is electrically connected to the input terminal of the switched capacitor circuit and the drain of the PMOS switch, while the other end is electrically connected to the output terminal of the pre-charge buffer. The second control switch is controlled by a second back-gate phase, the period of which is the same as the period of the sampling phase, and its duty cycle is less than the duty cycle of the sampling phase. One end of the second control switch is electrically connected to one end of the first control switch, and the other end is simultaneously electrically connected to one end of the third control switch and one end of the fourth control switch. The third control switch is controlled by the inverted phase of the second back gate phase, and its other end is electrically connected to the source of the PMOS switch. The fourth control switch is controlled by the sampling phase, and its other end is simultaneously electrically connected to the back gate of the PMOS switch and one end of the fifth control switch. The fifth control switch is controlled by the pre-charge phase, and its other end is connected to ground.
3. The control circuit according to claim 1, characterized in that, When the MOS switch is a CMOS switch, the CMOS switch includes an NMOS sub-switch and a PMOS sub-switch. The sources of the NMOS sub-switch and the PMOS sub-switch are electrically connected to each other and electrically connected to the input terminal of the precharge buffer, and their drains are electrically connected to each other and electrically connected to the output terminal of the precharge buffer. The gate of the NMOS sub-switch is controlled by the sampling phase, and the gate of the PMOS sub-switch is controlled by the inverted phase of the sampling phase. The plurality of control switches include a first control switch, a second control switch, a third control switch, a fourth control switch, and a fifth control switch; The first control switch is controlled by the pre-charge phase, and one end of it is simultaneously electrically connected to the input terminal of the switched capacitor circuit, the drain of the NMOS sub-switch, the drain of the PMOS sub-switch, one end of the second control switch, and one end of the fourth control switch, while the other end is electrically connected to the output terminal of the pre-charge buffer. The second control switch and the fourth control switch are both controlled by the first back gate phase, which leads the sampling phase, and its period and duty cycle are the same as the sampling phase. The other end of the second control switch is electrically connected to the back gate of the NMOS switch and one end of the third control switch. The other end of the fourth control switch is electrically connected to the back gate of the PMOS switch and one end of the fifth control switch. The third control switch and the fifth control switch are both controlled by the inverted phase of the first back grid phase. The other end of the third control switch is connected to ground, and the other end of the fifth control switch is connected to the power supply. or, The plurality of control switches include a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, and a seventh control switch; The first control switch is controlled by the pre-charge phase, and one end of it is simultaneously electrically connected to the input terminal of the switched capacitor circuit, the drain of the NMOS sub-switch, and the drain of the PMOS sub-switch, while the other end is simultaneously electrically connected to the output terminal of the pre-charge buffer, one end of the second control switch, and one end of the fourth control switch. The second control switch is controlled by a second back-gate phase, the period of which is the same as the period of the sampling phase, and its duty cycle is less than the duty cycle of the sampling phase. One end of the second control switch is electrically connected to one end of the first control switch, and the other end is simultaneously electrically connected to one end of the third control switch, one end of the fourth control switch, and one end of the sixth control switch. The third control switch is controlled by the inverted phase of the second back gate phase, and its other end is simultaneously electrically connected to the source of the NMOS sub-switch and the source of the PMOS sub-switch. The fourth control switch and the sixth control switch are both controlled by the sampling phase. The other end of the fourth control switch is simultaneously electrically connected to the back gate of the NMOS sub-switch and one end of the fifth control switch. The other end of the sixth control switch is simultaneously electrically connected to the back gate of the PMOS sub-switch and one end of the seventh control switch. Both the fifth control switch and the seventh control switch are controlled by the pre-charge phase. The other end of the fifth control switch is connected to ground, and the other end of the seventh control switch is connected to the power supply. or, The plurality of control switches include a first control switch, a second control switch, a third control switch, a fourth control switch, and a fifth control switch; The first control switch is controlled by the pre-charge phase, and one end of it is simultaneously electrically connected to the input terminal of the switched capacitor circuit, the drain of the NMOS sub-switch, and the drain of the PMOS sub-switch, while the other end is simultaneously electrically connected to the output terminal of the pre-charge buffer, one end of the second control switch, and one end of the fourth control switch. The second control switch and the fourth control switch are both controlled by sampling phase. One end of the second control switch is electrically connected to one end of the first control switch, and the other end is simultaneously electrically connected to the back gate of the NMOS switch and one end of the third control switch. One end of the fourth control switch is electrically connected to one end of the first control switch, and the other end is simultaneously electrically connected to the back gate of the PMOS switch and one end of the fifth control switch. Both the third control switch and the fifth control switch are controlled by the pre-charge phase. The other end of the third control switch is connected to ground, and the other end of the fifth control switch is connected to the power supply.
4. A pre-charge low leakage control method performed in the control circuit according to any one of claims 1-3, characterized in that, include: The source of the MOS switch is electrically connected to the input terminal of the precharge buffer as the first port, and the drain is electrically connected to the output terminal of the precharge buffer as the second port. The MOS switch is an NMOS switch, a PMOS switch, or a CMOS switch. One end of one of the multiple control switches is electrically connected to the input terminal of the switched capacitor circuit. The back gate of the MOS switch is connected to different working nodes according to the working phase of the control circuit. This ensures that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit. Also includes: The gate of the MOS switch is controlled by sampling phase control and / or the inverted phase of the sampling phase, wherein the inverted phase of the sampling phase is the pre-charge phase; When the MOS switch is an NMOS switch, the source of the NMOS switch is electrically connected to the input terminal of the precharge buffer, the drain is electrically connected to the output terminal of the precharge buffer, and the gate is controlled by the sampling phase. Connecting one end of one of the multiple control switches to the input terminal of the switched capacitor circuit, and connecting the back gate of the MOS switch to different operating nodes according to the operating phase of the control circuit, to ensure that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer includes: The pre-charge phase controls the first control switch, and one end of the first control switch is simultaneously electrically connected to the input terminal of the switched capacitor circuit, the drain of the NMOS switch, and one end of the second control switch, while the other end is electrically connected to the output terminal of the pre-charge buffer. The second control switch is controlled by the first back gate phase, which leads the sampling phase, and its period and duty cycle are the same as those of the sampling phase. The other end of the second control switch is electrically connected to the back gate of the NMOS switch and one end of the third control switch. The third control switch is controlled by the inverted phase of the first back gate phase, and the other end of the third control switch is connected to ground, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer. Or, including: The pre-charge phase controls the first control switch, and one end of the first control switch is simultaneously connected to the input terminal of the switched capacitor circuit and the drain of the NMOS switch, while the other end is connected to the output terminal of the pre-charge buffer. The second control switch is controlled by the second back gate phase. The period of the back gate phase is the same as the period of the sampling phase, and its duty cycle is less than the duty cycle of the sampling phase. One end of the second control switch is electrically connected to one end of the first control switch, and the other end is simultaneously electrically connected to one end of the third control switch and one end of the fourth control switch. The third control switch is controlled by the inverted phase of the second back gate phase, and the other end of the third control switch is electrically connected to the source of the NMOS switch; The sampling phase controls the fourth control switch, and the other end of the fourth control switch is simultaneously electrically connected to the back gate of the NMOS switch and one end of the fifth control switch. The fifth control switch is controlled by the pre-charge phase, and the other end of the fifth control switch is connected to ground, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the pre-charge buffer.
5. The method according to claim 4, characterized in that, When the MOS switch is a PMOS switch, the source of the PMOS switch is electrically connected to the input terminal of the precharge buffer, the drain is electrically connected to the output terminal of the precharge buffer, and the gate is controlled by the inverted phase of the sampling phase. Connecting one end of one of the multiple control switches to the input terminal of the switched capacitor circuit, and connecting the back gate of the MOS switch to different operating nodes according to the operating phase of the control circuit, to ensure that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer includes: The pre-charge phase controls the first control switch, and one end of the first control switch is simultaneously electrically connected to the input terminal of the switched capacitor circuit, the drain of the PMOS switch, and one end of the second control switch, while the other end is electrically connected to the output terminal of the pre-charge buffer. The second control switch is controlled by the first back gate phase, which leads the sampling phase, and its period and duty cycle are the same as those of the sampling phase. The other end of the second control switch is simultaneously electrically connected to the back gate of the PMOS switch and one end of the third control switch. The third control switch is controlled by the inverted phase of the first back gate phase, and the other end of the third control switch is electrically connected to the power supply, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer. Or, including: The pre-charge phase controls the first control switch, and one end of the first control switch is simultaneously connected to the input terminal of the switched capacitor circuit and the drain of the PMOS switch, while the other end is connected to the output terminal of the pre-charge buffer. The second control switch is controlled by the second back gate phase. The period of the back gate phase is the same as the period of the sampling phase, and its duty cycle is less than the duty cycle of the sampling phase. One end of the second control switch is electrically connected to one end of the first control switch, and the other end is simultaneously electrically connected to one end of the third control switch and one end of the fourth control switch. The third control switch is controlled by the inverted phase of the second back gate phase, and the other end of the third control switch is electrically connected to the source of the PMOS switch. The sampling phase controls the fourth control switch, and the other end of the fourth control switch is simultaneously electrically connected to the back gate of the PMOS switch and one end of the fifth control switch. The fifth control switch is controlled by the pre-charge phase, and the other end of the fifth control switch is connected to ground, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the pre-charge buffer.
6. The method according to claim 4, characterized in that, When the MOS switch is a CMOS switch, the CMOS switch includes an NMOS sub-switch and a PMOS sub-switch. The sources of the NMOS sub-switch and the PMOS sub-switch are electrically connected to each other and electrically connected to the input terminal of the precharge buffer. The drains are electrically connected to each other and electrically connected to the output terminal of the precharge buffer. The gate of the NMOS sub-switch is controlled by the sampling phase, and the gate of the PMOS sub-switch is controlled by the inverted phase of the sampling phase. Connecting one end of one of the multiple control switches to the input terminal of the switched capacitor circuit, and connecting the back gate of the MOS switch to different operating nodes according to the operating phase of the control circuit, to ensure that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer includes: The pre-charge phase controls the first control switch, and one end of the first control switch is simultaneously electrically connected to the input terminal of the switched capacitor circuit, the drain of the NMOS sub-switch, the drain of the PMOS sub-switch, one end of the second control switch, and one end of the fourth control switch, while the other end is electrically connected to the output terminal of the pre-charge buffer. The second control switch and the fourth control switch are controlled by the first back gate phase. The back gate phase leads the sampling phase, and its period and duty cycle are the same as those of the sampling phase. The other end of the second control switch is simultaneously electrically connected to the back gate of the NMOS switch and one end of the third control switch. The other end of the fourth control switch is simultaneously electrically connected to the back gate of the PMOS switch and one end of the fifth control switch. The third control switch and the fifth control switch are controlled by the inverted phase of the first back gate phase. The other end of the third control switch is connected to ground, and the other end of the fifth control switch is connected to the power supply, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer. Or, including: The pre-charge phase controls the first control switch, and one end of the first control switch is simultaneously connected to the input terminal of the switched capacitor circuit, the drain of the NMOS sub-switch, and the drain of the PMOS sub-switch, while the other end is simultaneously connected to the output terminal of the pre-charge buffer, one end of the second control switch, and one end of the fourth control switch. The second control switch is controlled by the second back gate phase. The period of the back gate phase is the same as the period of the sampling phase, and its duty cycle is less than the duty cycle of the sampling phase. One end of the second control switch is electrically connected to one end of the first control switch, and the other end is simultaneously electrically connected to one end of the third control switch, one end of the fourth control switch, and one end of the sixth control switch. The third control switch is controlled by the inverted phase of the second back gate phase, and the other end of the third control switch is simultaneously electrically connected to the source of the NMOS sub-switch and the source of the PMOS sub-switch. The sampling phase controls the fourth control switch and the sixth control switch, and the other end of the fourth control switch is simultaneously electrically connected to the back gate of the NMOS sub-switch and one end of the fifth control switch, and the other end of the sixth control switch is simultaneously electrically connected to the back gate of the PMOS sub-switch and one end of the seventh control switch. The pre-charge phase controls the fifth control switch and the seventh control switch, and connects the other end of the fifth control switch to ground and the other end of the seventh control switch to the power supply, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the pre-charge buffer. Or, including: The pre-charge phase controls the first control switch, and one end of the first control switch is simultaneously connected to the input terminal of the switched capacitor circuit, the drain of the NMOS sub-switch, and the drain of the PMOS sub-switch, while the other end is simultaneously connected to the output terminal of the pre-charge buffer, one end of the second control switch, and one end of the fourth control switch. The sampling phase controls the second control switch and the fourth control switch, and one end of the second control switch is electrically connected to one end of the first control switch, while the other end is simultaneously electrically connected to the back gate of the NMOS switch and one end of the third control switch. One end of the fourth control switch is electrically connected to one end of the first control switch, while the other end is simultaneously electrically connected to the back gate of the PMOS switch and one end of the fifth control switch. The precharge phase controls the third control switch and the fifth control switch, and connects the other end of the third control switch to ground and the other end of the fifth control switch to the power supply, thereby ensuring that when the MOS switch is turned on, its back gate always maintains the same potential as the input terminal of the precharge buffer.