Hard macro component and method for cross-voltage domain signal interconnection and semiconductor chip

Abstract

The embodiment of the invention discloses a cross-voltage-domain signal interconnection hard macro component, a method and a semiconductor chip, relates to the technical field of integrated circuits, and can reduce the complexity of cross-voltage-domain signal interconnection. The hard macro component comprises at least one level conversion unit, the level conversion unit is integrated with a first signal port and a second signal port, and the first signal port is used for being electrically connected with a silicon through hole to receive an electric signal of a first voltage domain; the logic circuit units of the second voltage domain are arranged around the at least one level conversion unit, and the second signal port is electrically connected with the logic circuit units of the second voltage domain through metal wires; wherein the first voltage domain and the second voltage domain are working voltage domains of circuits, belonging to different power supply areas, at the two ends of the silicon through hole. The method and the device are suitable for a scene of signal interconnection between chips.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a hard macro component, method, and semiconductor chip for cross-voltage domain signal interconnection. Background Technology

[0002] With the ever-increasing demands for memory access performance from large-scale integrated chips for Artificial Intelligence (AI) applications, the architecture employing 3D stacked Dynamic Random Access Memory (DRAM) chips and integrated buffer dies has become a significant development trend. In such chip stacking designs, two chips typically require thousands or even tens of thousands of through-silicon vias (TSVs) for signal interconnection. Since the two chips often operate in different voltage domains, in addition to physical connection via TSVs, level shifters are also necessary to ensure correct signal transmission between different voltages.

[0003] Existing technologies typically employ the Unified Power Format (UPF) method to insert, place, and route level conversion units. This requires creating an independent power domain for the TSV region, cutting the standard unit region, and providing special power supply and connection for the newly added level conversion units. Furthermore, the diversity, quantity, and location uncertainty of TSV signals further exacerbate the complexity of the physical design. Summary of the Invention

[0004] In view of this, embodiments of this application provide a hard macro component, method, and semiconductor chip for cross-voltage domain signal interconnection, which can reduce the complexity of cross-voltage domain signal interconnection.

[0005] In a first aspect, embodiments of this application provide a hard macro component for cross-voltage domain signal interconnection, comprising: at least one level conversion unit, the level conversion unit integrating a first signal port and a second signal port, the first signal port being used for electrical connection with a through-silicon via (TSV) to receive an electrical signal from a first voltage domain; and logic circuit units of a second voltage domain arranged around the at least one level conversion unit, the second signal port being electrically connected to the logic circuit units of the second voltage domain via metal wiring; wherein the first voltage domain and the second voltage domain are the operating voltage domains of circuits belonging to different power supply regions at both ends of the TSV.

[0006] According to a specific implementation of an embodiment of this application, the hard macro component is a pre-packaged circuit module. The hard macro component includes a pre-packaged housing, and the interior of the pre-packaged housing includes at least: an upper edge layer unit row, a first auxiliary layer unit row, a center layer unit row, a second auxiliary layer unit row, and a lower edge layer unit row distributed sequentially from top to bottom; wherein, the at least one level conversion unit is located in the center layer unit row and is centrally arranged along the horizontal direction of the center layer unit row; the logic circuit unit includes: an edge isolation unit, at least one decoupling capacitor unit, and a custom power network; the edge isolation unit is disposed in the upper edge layer unit row and the lower edge layer unit row of the pre-packaged housing for physical isolation; the at least one decoupling capacitor unit is disposed in the first auxiliary layer unit row and the second auxiliary layer unit row of the pre-packaged housing; the custom power network is disposed within the pre-packaged housing for providing corresponding power connections for the first voltage domain pin and the second voltage domain pin of the level conversion unit, respectively.

[0007] According to a specific implementation of an embodiment of this application, the customized power network includes multiple parallel power lines, which are arranged in the order of power line in the first voltage domain, ground line, power line in the second voltage domain, and ground line; wherein, the power line adjacent to the first voltage domain pin of the level conversion unit is connected to the first voltage domain, and the power line adjacent to the second voltage domain pin is connected to the second voltage domain.

[0008] According to a specific implementation of this application, the first signal port is located on the top layer of a metal stack, and the through-silicon via is electrically connected to the first signal port by overlapping a horizontally extending metal contact on the top layer of the metal stack.

[0009] According to one specific implementation of the embodiments of this application, the height of the pre-packaged shell is an integer multiple of the standard cell row height, and the width is an integer multiple of the standard cell bit width.

[0010] According to one specific implementation of an embodiment of this application, the hard macro component is located in the adjacent region of the corresponding through-silicon via.

[0011] Secondly, embodiments of this application provide a cross-voltage domain signal interconnection method, comprising: calling at least one preset hard macro component according to the number and location of through-silicon vias (TSVs), and placing each hard macro component in the vicinity of the corresponding TSV; electrically connecting a first signal port of the preset hard macro component to the TSV to receive an electrical signal from a first voltage domain; and electrically connecting a second signal port of the preset hard macro component to a logic circuit unit of a second voltage domain via a metal wiring, thereby forming a complete signal interconnection path from the first voltage domain through the hard macro component and the TSV to the second voltage domain; wherein the first voltage domain and the second voltage domain are the operating voltage domains of circuits whose two ends of the TSV belong to different power supply regions.

[0012] According to a specific implementation of an embodiment of this application, before calling at least one preset hard macro component, the process includes: determining a pre-packaged housing of the hard macro component based on the design rules of the target process and the through-silicon via (TSV) size; planning an upper edge layer cell row, a first auxiliary layer cell row, a center layer cell row, a second auxiliary layer cell row, and a lower edge layer cell row distributed sequentially from top to bottom within the pre-packaged housing; placing at least one level conversion unit in the center layer cell row and centered along the horizontal direction of the center layer cell row; placing edge isolation units in the upper edge layer cell row and the lower edge layer cell row of the pre-packaged housing for physical isolation; placing at least one decoupling capacitor unit in the first auxiliary layer cell row and the second auxiliary layer cell row of the pre-packaged housing; and placing a custom power network within the pre-packaged housing to provide corresponding power connections for the first signal port and the second signal port of the level conversion unit, respectively; wherein, the logic circuit unit includes: an edge isolation unit, at least one decoupling capacitor unit, and a custom power network.

[0013] According to a specific implementation of an embodiment of this application, after constructing a custom power network, the process includes: generating a physical library file for the preset hard macro component based on the layout results of the pre-packaged housing, edge isolation unit, level conversion unit, and decoupling capacitor unit and the routing results of the custom power network; wherein, the physical library file includes a layout exchange file, a design exchange file, and a layout file describing the hard macro component, and the physical library file is used to call the preset hard macro component.

[0014] According to a specific implementation of an embodiment of this application, the customized power network includes multiple parallel power lines, which are arranged in the order of power line in the first voltage domain, ground line, power line in the second voltage domain, and ground line; wherein, the power line adjacent to the first voltage domain pin of the level conversion unit is connected to the first voltage domain, and the power line adjacent to the second voltage domain pin is connected to the second voltage domain.

[0015] According to a specific implementation of an embodiment of this application, the step of electrically connecting the first signal port of the preset hard macro component to a through-silicon via (TSV) includes: the first signal port being disposed on the top layer of a metal stack, and the TSV being electrically connected to the first signal port by overlapping a horizontally extending metal contact on the top layer of the metal stack.

[0016] Thirdly, embodiments of this application provide a semiconductor chip, the chip comprising: a first die; a second die stacked above the first die; a through-silicon via (TSV) disposed between the first die and the second die, extending upward from the first die into the interior of the second die; and a trans-voltage hard macro module disposed within the second die, and horizontally adjacent to the TSV extending into the interior of the second die; wherein the trans-voltage hard macro module comprises: at least one level conversion unit and logic circuit units of a second voltage domain arranged around the at least one level conversion unit; the level conversion unit integrates a first signal port and a second signal port, the first signal port being electrically connected to the upper end of the TSV extending into the interior of the second die, the first signal port being configured to receive an electrical signal from a first voltage domain of the first die, and the second signal port being electrically connected to the logic circuit units of the second voltage domain of the second die.

[0017] Fourthly, embodiments of this application provide an electronic device, the electronic device comprising: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the cross-voltage domain signal interconnection method provided in any embodiment of this application.

[0018] This application provides a hard macro component, method, and semiconductor chip for cross-voltage domain signal interconnection. It utilizes at least one level-shifting unit, integrating a first signal port and a second signal port. The first signal port is electrically connected to a through-silicon via (TSV) to receive electrical signals from a first voltage domain. Logic circuit units of a second voltage domain are arranged around the at least one level-shifting unit, and the second signal port is electrically connected to these logic circuit units via metal wiring. The first and second voltage domains are the operating voltage domains of circuits at the two ends of the TSV, which belong to different power supply regions. This eliminates the need to handle the power supply and connection of individual level-shifting units in the physical implementation. Instead, it addresses the overall power supply and signal connection of the hard macro component. Regardless of the number or location of TSV signals, the hard macro component can be repeatedly called and placed, effectively eliminating the physical design uncertainty caused by the diversity of TSV signals, improving implementation efficiency and reliability. Furthermore, it eliminates the complex UPF process, requiring no additional power domain creation or standard cell area cutting, thus reducing the complexity of cross-voltage domain signal interconnection. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a hard macro component for cross-voltage domain signal interconnection provided in an embodiment of this application; Figure 2 A schematic diagram of the interconnection path provided in the embodiments of this application; Figure 3 A schematic diagram of the cell layout in a hard macro component provided in an embodiment of this application; Figure 4 This is a schematic diagram of the internal wiring of the pre-packaged housing provided in the embodiments of this application; Figure 5 A schematic diagram of a custom power network provided for an embodiment of this application; Figure 6 A schematic flowchart illustrating the cross-voltage domain signal interconnection method provided in an embodiment of this application; Figure 7 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0022] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0023] In a first aspect, embodiments of this application provide a hard macro component for cross-voltage domain signal interconnection, which can reduce the complexity of cross-voltage domain signal interconnection.

[0024] like Figure 1 As shown, the hard macro component 101 for cross-voltage domain signal interconnection provided in the embodiments of this application includes: at least one level conversion unit 1, the level conversion unit 1 integrating a first signal port 11 and a second signal port 12, the first signal port 11 being electrically connected to a through-silicon via 102 to receive an electrical signal from a first voltage domain 103; and a logic circuit unit 2 of a second voltage domain 104 arranged around the at least one level conversion unit 1, the second signal port 12 being electrically connected to the logic circuit unit 2 of the second voltage domain via metal wiring; wherein, the first voltage domain 103 and the second voltage domain 104 are the operating voltage domains of circuits belonging to different power supply regions at both ends of the through-silicon via.

[0025] This application discloses a hard macro component specifically for cross-voltage domain signal interconnection. The hard macro component, also known as a hard macro module, is a pre-designed, reusable physical unit that can efficiently solve the signal level conversion and integration problems in 3D integrated circuits.

[0026] The cross-voltage domain signal interconnection hardware macro component provided in this application embodiment has a core structure including one or more level conversion units 1, and the level conversion unit 1 integrates a first signal port 11 and a second signal port 12 belonging to different voltage domains respectively.

[0027] Specifically, the first signal port 11 is configured to receive electrical signals from the first voltage domain 103 and is directly responsible for establishing an electrical connection with the through-silicon via (TSV) 102, thereby forming a vertical interconnect channel across the chip stack structure; at the same time, the second signal port 12 is electrically connected to the logic circuit unit 2 of the second voltage domain 104, which is also integrated inside the hard macro and arranged around the level conversion unit 1, through a preset metal wiring. Figure 2 This application provides a schematic diagram of interconnection paths for embodiments of the present application (this application uses a planar schematic diagram to represent a three-dimensional interconnection structure; to clearly show the overall layout, all vertical connections in the diagram are drawn in projection form), as follows: Figure 2The through-silicon via 102 is a neutral vertical interconnect structure, connecting two different voltage domains, so it does not belong to any one voltage domain. Similarly, via 105 itself does not belong to any voltage domain, but the network it connects to determines its voltage domain. Specifically, the signal first starts at the input terminal In of the power line VDD1 in the first voltage domain 103, with a standard VDD1 voltage level. It is guided through the internal via 105 and the metal interconnect layer to the core level conversion unit 1, which is responsible for boosting or converting the signal's voltage standard from VDD1 to VDD2. After level conversion, the signal is routed again through the internal via 105 and the top metal 1031 to the through-silicon via 102 for vertical transmission. After passing through the through-silicon via 102, the signal continues to be conducted through the internal via 105 and the metal interconnect layer in the second voltage domain 104, finally reaching the output terminal Out of the power line VDD2 in the second voltage domain 104. At this point, the signal has stabilized at the VDD2 level and can be correctly identified and processed by the target logic circuit within the second voltage domain 104. The first voltage domain 103 and the second voltage domain 104 are located on opposite sides of a through-silicon via (TSV) and are powered by their respective independent power networks. In 3D stacking, different dies or different modules within the same die may use different operating voltages. For example, the chip processing core of the same die might use a low-voltage domain VDD1 of 0.8V, while the interface unit might use a high-voltage domain VDD2 of 1.2V. The hard macro component simultaneously accesses both voltages through its internally integrated power network, ensuring correct and reliable level conversion and transmission of the signal between these two different voltage domains.

[0028] This highly integrated component design combines level shifting, local logic driving, and a standardized interface for TSVs into a single plug-and-play functional module, effectively avoiding the complex power domain segmentation and cross-level routing challenges of traditional designs.

[0029] The hard macro component for cross-voltage domain signal interconnection provided in this application includes at least one level conversion unit, which integrates a first signal port and a second signal port. The first signal port is used to electrically connect to a through-silicon via (TSV) to receive electrical signals from a first voltage domain. A second voltage domain logic circuit unit is arranged around the at least one level conversion unit, and the second signal port is electrically connected to the logic circuit unit of the second voltage domain via metal wiring. The first and second voltage domains are the operating voltage domains of circuits belonging to different power supply regions at both ends of the TSV. This eliminates the need to handle the power supply and connection of individual level conversion units in the physical implementation. Instead, it addresses the overall power supply and signal connection of the hard macro component. Regardless of the number or location of TSV signals, the hard macro component can be repeatedly called and placed, effectively eliminating the physical design uncertainty caused by the diversity of TSV signals, improving implementation efficiency and reliability. Simultaneously, it eliminates the complex UPF process, requiring no additional power domain creation or cutting of standard cell areas, thus reducing the complexity of cross-voltage domain signal interconnection.

[0030] In some embodiments, the hard macro component is a pre-packaged circuit module, the hard macro component includes a pre-packaged housing 3, the interior of the pre-packaged housing 3 includes at least: an upper edge layer unit row 31, a first auxiliary layer unit row 32, a center layer unit row 33, a second auxiliary layer unit row 34, and a lower edge layer unit row 35 distributed from top to bottom; wherein, the at least one level conversion unit 1 is located in the center layer unit row 33 and is centrally arranged along the horizontal direction of the center layer unit row; the logic circuit unit 2 includes: an edge isolation unit, at least one decoupling capacitor unit, and a custom power network, the edge isolation unit is disposed in the upper edge layer unit row 31 and the lower edge layer unit row 35 of the pre-packaged housing 3 for physical isolation; the at least one decoupling capacitor unit is disposed in the first auxiliary layer unit row 32 and the second auxiliary layer unit row 34 of the pre-packaged housing; the custom power network is disposed in the pre-packaged housing for providing corresponding power connections for the first voltage domain pin and the second voltage domain pin of the level conversion unit 1, respectively.

[0031] The embodiments of this application further disclose the specific internal structure and physical implementation details of the hard macro component. As a pre-packaged circuit module, the physical boundary and internal functional division of the hard macro component are defined by the pre-packaged shell.

[0032] Inside the pre-packaged housing 3, the functional units are precisely planned as five horizontal layers distributed from top to bottom: the upper edge layer unit row 31, the first auxiliary layer unit row 32, the center layer unit row 33, the second auxiliary layer unit row 34, and the lower edge layer unit row 35. This layered layout lays the foundation for achieving a compact and compliant modular design.

[0033] Specifically, Figure 3 This is a schematic diagram of the cell layout in the hard macro component provided in the embodiments of this application, such as... Figure 3 At least one level-shifting unit 1, which performs the core conversion function, is precisely arranged in the central layer unit row 33 and centered horizontally to ensure its optimal physical position. The components of the logic circuit unit 2, which constitutes the local environment, are placed in other specific layers. In some examples, the logic circuit unit 2 includes edge isolation units, at least one decoupling capacitor unit, and a custom power network. The edge isolation units are located in the outermost upper edge layer unit row 31 and lower edge layer unit row 35, and their core function is to form physical isolation. At least one decoupling capacitor unit is built into the first auxiliary layer unit row 32 and the second auxiliary layer unit row 34, respectively, acting as a local energy storage pool for the hard macro component, specifically for optimizing the local power quality around the level-shifting unit and suppressing noise. Furthermore, the custom power network is integrated within a pre-packaged housing 3. Figure 4 This is a schematic diagram of the internal wiring of the pre-packaged housing 3 provided in the embodiments of this application, as shown below. Figure 4 The level conversion unit 1 connects two power domains with different operating voltages, and the two power domains can reliably communicate bidirectionally. This provides independent, stable and efficient power connections for the first voltage domain pin 103 and the second voltage domain pin 104 of the level conversion unit 1, ensuring reliable operation of the hard macro component in cross-voltage domain scenarios.

[0034] In some embodiments, the customized power network includes multiple parallel power lines arranged in a repeating order of first voltage domain power line, ground line, second voltage domain power line, and ground line; wherein, the power line adjacent to the first voltage domain pin of the level conversion unit 1 is connected to the first voltage domain, and the power line adjacent to the second voltage domain pin is connected to the second voltage domain.

[0035] Figure 5 A schematic diagram of a customized power network provided for an embodiment of this application, such as... Figure 5The custom power network consists of multiple parallel power lines. These lines are not randomly arranged but follow an optimized, periodically repeating sequence: power line VDD1 (first voltage domain), ground line VSS, power line VDD2 (second voltage domain), and ground line VSS again. This VDD1-VSS-VDD2-VSS repeating pattern establishes a regular and balanced power delivery framework within the module. More importantly, this layout achieves precise spatial matching with the pin positions of level conversion unit 1. Specifically, power lines adjacent to the first voltage domain pins of level conversion unit 1 are connected to the first voltage domain, while power lines adjacent to the second voltage domain pins are connected to the second voltage domain. This proximity principle significantly shortens the distance from the power pins to the power lines, reduces parasitic effects, and ensures the stability and efficiency of the power supply. This is a key design feature ensuring the high-performance operation of the level conversion function.

[0036] In some embodiments, the first signal port 11 is disposed on the top layer of a metal stack, and the through-silicon via is electrically connected to the first signal port 11 by overlapping a horizontally extending metal contact on the top layer of the metal stack.

[0037] This application optimizes the interface design between the through-silicon via (TSV) and the preset hard macro component to achieve a direct connection without additional wiring. Specifically, the first signal port 11 of the hard macro component is not a simple contact point on the top layer of the chip metal stack, but is designed as a horizontally extending metal contact. When the hard macro component is placed in the vicinity of the TSV, the contact structure of the TSV and the horizontally extending metal contact overlap in the vertical projection. This physical overlap naturally forms a low-resistance contact hole or a direct metal connection during the manufacturing process, thereby automatically and reliably forming an electrical connection. This avoids the difficulties faced by traditional automatic routing tools when dealing with wide metal connections on the top layer, fundamentally eliminating missed connections or design rule violations, and greatly simplifying the physical implementation process.

[0038] In some examples, the height of the pre-packaged housing is an integer multiple of the standard cell row height, and the width is an integer multiple of the standard cell bit width.

[0039] This application's embodiments meticulously plan the physical dimensions of the hard macro components to ensure seamless integration into standard cell-based chip design flows and layouts. Specifically, the pre-packaged housing's dimensions are strictly designed to be highly compatible with manufacturing process design rules. Its height can be configured as an integer multiple of the target process standard cell row height, and its width can also be configured as an integer multiple of the standard cell bit width. This process-based basic design grid-based size definition method allows the hard macro components to perfectly align with surrounding standard cell rows and power supply networks in the chip layout, avoiding physical design rule violations caused by size mismatches and ensuring the efficiency and correctness of module retrieval, placement, and interconnection with surrounding logic circuits.

[0040] In some examples, the hard macro component is located in the vicinity of the corresponding through-silicon via.

[0041] This application's embodiments have made key optimizations to the layout of hard macro components to achieve the shortest signal path across voltage domains and optimal performance. In some examples, the hard macro component can be placed in the vicinity of the corresponding through-silicon via (TSV). Based on this, in terms of electrical performance, the high-frequency signal path from the second signal port of the hard macro component to the TSV can be greatly shortened, effectively reducing parasitic effects, signal reflection, and transmission delay, thereby improving signal integrity. In terms of physical implementation, the second signal port of the top layer of the hard macro component can be directly overlapped and connected to the TSV in the same top layer through a simple metal extension, thus avoiding the complexity and compliance risks faced by traditional automated routing processes when handling wide metal connections on the top layer, and achieving efficient integration with immediate placement and connection.

[0042] Secondly, embodiments of this application provide a signal interconnection method across voltage domains, which can reduce the complexity of signal interconnection across voltage domains.

[0043] like Figure 6 As shown, embodiments of this application provide a method for signal interconnection across voltage domains, including: S11. Based on the number and location of through-silicon vias, call at least one preset hard macro component and place each hard macro component in the adjacent area of ​​the corresponding through-silicon via; When completing the physical design of 3D stacked chips, it is necessary to call pre-designed hard macro components according to the actual layout of through-silicon vias (TSVs). Specifically, one or more hard macro components can be instantiated in the layout based on the number and specific coordinates of TSVs, and each hard macro component can be precisely placed in the adjacent area next to its corresponding TSV.

[0044] S12. Connect the first signal port of the preset hard macro component to the through-silicon via (TSV) to receive electrical signals from the first voltage domain; and connect the second signal port of the preset hard macro component to the logic circuit unit of the second voltage domain via metal wiring to form a complete signal interconnection path from the first voltage domain through the hard macro component and the TSV to the second voltage domain; wherein the first voltage domain and the second voltage domain are the operating voltage domains of circuits belonging to different power supply regions at both ends of the TSV.

[0045] In some examples, a hard macro component is a complete circuit structure integrating level conversion and input / output ports. Its core feature is the integration of two critical signal ports: a first signal port and a second signal port. The core function is to achieve signal conversion between a first voltage domain and a second voltage domain. The first and second voltage domains refer to the operating voltages used by different dies or different modules within the same die in a 3D stack. For example, the chip processing core of the same die might use a low voltage domain of 0.8V, while the interface unit might use a high voltage domain of 1.2V. The hard macro component simultaneously connects to both voltages through an internally integrated power network, ensuring correct and reliable level conversion and transmission of signals between these two different voltage domains.

[0046] After placing the hard macro component, the next step is to establish a complete cross-voltage domain signal path. Specifically, a first signal port, with a standardized shape and size, located on the top metal layer, is directly aligned and electrically connected to a through-silicon via (TSV), thus reliably receiving electrical signals from the first voltage domain. Simultaneously, a second signal port located on the middle metal layer is seamlessly connected to the logic circuit unit in the second voltage domain through a conventional metal wiring process. This constructs a complete signal interconnection path from the first voltage domain through the TSV, through the hard macro component for level conversion and signal driving, and finally to the logic unit in the second voltage domain.

[0047] The cross-voltage domain signal interconnection method provided in this application involves calling at least one preset hard macro component based on the number and location of through-silicon vias (TSVs), and placing each hard macro component in the vicinity of the corresponding TSV; electrically connecting the first signal port of the preset hard macro component to the TSV to receive electrical signals from the first voltage domain; and electrically connecting the second signal port of the preset hard macro component to a logic circuit unit in the second voltage domain via metal wiring, thereby forming a complete signal interconnection path from the first voltage domain through the hard macro component and the TSV to the second voltage domain; wherein the first voltage domain and the second voltage domain are the operating voltage domains of circuits belonging to different power supply regions at both ends of the TSV. In this way, the physical implementation no longer needs to handle the power supply and connection of individual level conversion units, but rather the overall power supply and signal connection of the hard macro component. Regardless of the changes in the number and location of the TSV signals, only the hard macro component needs to be repeatedly called and placed, effectively eliminating the physical design uncertainty caused by the diversity of TSV signals, improving implementation efficiency and reliability. At the same time, it eliminates the complex UPF process, requiring no additional power domain creation and no cutting of standard cell areas, reducing the complexity of cross-voltage domain signal interconnection.

[0048] In some embodiments, before invoking at least one preset hard macro component, the process includes: determining a pre-packaged housing of the hard macro component according to the design rules of the target process and the through-silicon via (TSV) size; planning an upper edge layer cell row, a first auxiliary layer cell row, a center layer cell row, a second auxiliary layer cell row, and a lower edge layer cell row distributed sequentially from top to bottom within the pre-packaged housing; placing at least one level-shifting unit in the center layer cell row and centered along the horizontal direction of the center layer cell row; placing the edge isolation unit in the upper edge layer cell row and the lower edge layer cell row of the pre-packaged housing for physical isolation; placing the at least one decoupling capacitor unit in the first auxiliary layer cell row and the second auxiliary layer cell row of the pre-packaged housing; and placing the custom power network within the pre-packaged housing to provide corresponding power connections for the first signal port and the second signal port of the level-shifting unit, respectively; wherein the logic circuit unit includes: an edge isolation unit, at least one decoupling capacitor unit, and a custom power network.

[0049] The pre-defined hard macro components in this application are constructed through a standardized design process. First, based on the design rules of the target process and the through-silicon via (TSV) size, such as a TSV size of 5μm × 5μm, the physical outline of the pre-packaged housing of the hard macro component is determined. The physical outline size must meet process compatibility requirements. For example, the height is 5 times the standard cell row height of 0.42μm, i.e., 2.1μm, and the width is 60 times the standard cell width of 0.06μm, i.e., 3.6μm. Then, five layers of cell rows are planned from top to bottom within the pre-packaged housing: upper edge layer cell row, first auxiliary layer cell row, center layer cell row, second auxiliary layer cell row, and lower edge layer cell row. Cells are laid out within the cell rows. In some examples, at least one level conversion unit can be placed in the center layer cell row and horizontally centered. The gaps on the left and right sides of the center layer cell row are filled with filler cells to ensure physical integrity. Edge isolation units are placed in the upper and lower edge layer cell rows to achieve physical isolation. Multiple decoupling capacitor units are placed in the first and second auxiliary layer cell rows to optimize local power quality by maximizing the capacitance value.

[0050] Next, routing is performed to construct a custom power network. In some examples, the power lines are arranged in the order of first voltage domain power line VDD1, ground line VSS, second voltage domain power line VDD2, and ground line VSS, using a repeating VDD1-VSS-VDD2-VSS pattern. The corresponding voltage domains are connected to the power pins adjacent to the level shifting unit. Simultaneously, the custom power network starts from the bottom metal layer and transitions to the middle metal layer through a crisscrossing routing method. The first signal port extends to the same top metal layer as the TSV, and the direction of the metal layer is orthogonal to the default power supply network. It is worth noting that the internal logic circuitry of the chip includes second voltage domain logic circuit units arranged around the level shifting unit. The functionality of these logic circuit units is achieved through the coordinated layout and integration of edge isolation units, decoupling capacitor units, and the custom power network at the physical level.

[0051] In some embodiments, after constructing the custom power network, the process includes: generating a physical library file for the preset hard macro component based on the layout results of the pre-packaged housing, edge isolation unit, level shifting unit, and decoupling capacitor unit and the routing results of the custom power network; wherein the physical library file includes a layout exchange file, a design exchange file, and a layout file describing the hard macro component, and the physical library file is used to call the preset hard macro component.

[0052] After successfully constructing the physical structure and interconnection network of the pre-defined hard macro components, they need to be converted into a standard format that can be directly called by the chip design process. This step is achieved by generating physical library files. Specifically, based on the final layout of the pre-packaged housing, edge isolation units, level shifting units, and decoupling capacitor units, as well as the detailed routing results of the custom power network, exchange files containing layout information, design exchange files, and the final layout file are comprehensively exported. These physical library files together constitute a complete physical description of the hard macro components, enabling the upper-level chip design system to accurately instantiate and place the hard macro components in the global layout, just like calling basic units in the standard cell library, and automatically complete the correct connection between them and through-silicon vias, global power networks, and core logic signals, thereby achieving standardized and reusable integration of hard macro components.

[0053] In some embodiments, the customized power network includes multiple parallel power lines arranged in a repeating order of first voltage domain power line, ground line, second voltage domain power line, and ground line; wherein, the power line adjacent to the first voltage domain pin of the level conversion unit is connected to the first voltage domain, and the power line adjacent to the second voltage domain pin is connected to the second voltage domain.

[0054] The custom power network in this application employs a highly regularized and repetitive parallel power line arrangement. Specifically, the custom power network consists of multiple parallel power lines arranged in a predetermined fixed order: power line of the first voltage domain, ground line, power line of the second voltage domain, and ground line in a cycle, forming a tight and uniform power distribution grid. This periodic arrangement of VDD1-VSS-VDD2-VSS provides both low-impedance power supply paths and adjacent current return paths for the two voltage domains simultaneously. More importantly, this layout strategy is co-optimized with the pin positions of the level shifting unit: ensuring that the physical pins on the level shifting unit connected to the first voltage domain are adjacent to and directly connected to the VDD1 power line in the network, while the pins connected to the second voltage domain are adjacent to and directly connected to the VDD2 power line, thus achieving the most direct and reliable power supply connection physically, minimizing power supply noise and voltage drop.

[0055] In some embodiments, electrically connecting the first signal port of the preset hard macro component to a through-silicon via (TSV) includes: the first signal port being disposed on the top layer of a metal stack, and the TSV being electrically connected to the first signal port by overlapping a horizontally extending metal contact on the top layer of the metal stack.

[0056] In this application, the connection between the through-silicon via (TSV) and the first signal port of the corresponding hard macro component is an automated physical docking achieved through a meticulous layout design. Specifically, the first signal port is designed to be located on the top layer of the chip metal stack, and a metal contact with horizontal extension characteristics is formed on this layer, for example, a rectangular metal layer extending outward from the hard macro component body by several micrometers. This extension design ensures that when the preset hard macro component is placed at a predetermined position near the TSV, the standardized, horizontally extending metal contact of the first signal port will automatically overlap with the metal contact point (Landing Pad) on top of the TSV. This overlap will naturally form a stable electrical connection point during the manufacturing process, thereby eliminating the need for any additional, customized manual wiring operations on the top layer, greatly simplifying the integration process and ensuring the consistency and reliability of the connection.

[0057] Thirdly, embodiments of this application also provide a semiconductor chip that can reduce the complexity of cross-voltage domain signal interconnection.

[0058] The semiconductor chip provided in the embodiments of this application includes: a first die; a second die stacked on top of the first die; a through-silicon via (TSV) disposed between the first die and the second die, extending upward from the first die into the interior of the second die; and a trans-voltage hard macro module disposed inside the second die, and horizontally adjacent to the TSV extending into the interior of the second die; wherein the trans-voltage hard macro module includes: at least one level conversion unit and logic circuit units of a second voltage domain arranged around the at least one level conversion unit; the level conversion unit integrates a first signal port and a second signal port, the first signal port being electrically connected to the upper end of the TSV extending into the interior of the second die, the first signal port being configured to receive an electrical signal from a first voltage domain of the first die, and the second signal port being electrically connected to the logic circuit units of the second voltage domain of the second die.

[0059] Fourthly, embodiments of this application also provide an electronic device capable of reducing the complexity of cross-voltage domain signal interconnection.

[0060] like Figure 7As shown, the electronic device provided in the embodiments of this application may include: a housing 51, a processor 52, a memory 53, a circuit board 54, and a power supply circuit 55, wherein the circuit board 54 is disposed inside the space enclosed by the housing 51, and the processor 52 and the memory 53 are disposed on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program code; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, for executing the cross-voltage domain signal interconnection method provided in any of the foregoing embodiments.

[0061] For details on the specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running executable program code, please refer to the description of the foregoing embodiments, which will not be repeated here.

[0062] This application significantly simplifies the physical implementation process of cross-die signals via through-silicon vias (TSVs) in integrated circuits, making it particularly suitable for complex scenarios with uncertain signal numbers or diverse signal distributions. Through customized peripheral circuit design of the level-shifting unit, i.e., the logic circuit unit, this application effectively meets various constraints of physical design rules and significantly improves local power quality through targeted power network and decoupling capacitor unit design. Furthermore, the signal ports of the hard macro components and the outgoing metal layers of the power network can be flexibly adjusted and adapted according to the actual usage environment. In actual project execution, this application helps reduce designer input, mitigates risks such as weak or unreasonable connections due to design diversity, thereby accelerating project timing and physical convergence and enhancing the overall robustness of the chip.

[0063] The core of this application lies in the independent peripheral circuit design of the level conversion unit, and the simultaneous integration of multiple dimensions such as decoupling capacitor unit, physical design rule compliance, power network optimization and outgoing wiring method, forming an integrated hard macro component. It abandons the default implementation path that relies on the unified power format (UPF) process and multi-power domain division in the traditional way, and simplifies the implementation process through modularization and standardization. It can flexibly cover a variety of application scenarios and greatly improve the design implementation efficiency.

[0064] It should be further noted that the specific dimensions of the hard macro component structure can be adjusted according to actual usage requirements. It can be reduced in size to save upper-layer design area, or enlarged to accommodate more decoupling capacitor units or enhance the power network. The placement order and position of each unit within the hard macro component are flexible. For example, when the overall height is six standard unit rows, the top and bottom layers remain edge-isolated units to meet design rules, the level conversion unit can be placed in the middle area, and the remaining positions are arranged with decoupling capacitor units as much as possible, with the remaining space filled by filler units. This layout can be adaptively adjusted while adhering to design rules.

[0065] Finally, the signal ports in the hard macro component structure are not fixed and can be set in the intermediate metal layer of a non-dual patterned process; the power network can also be laid in the intermediate metal layer of a non-dual patterned process, and the second signal port that directly interfaces with the through silicon via is set in the contact metal layer corresponding to the through silicon via and extends outward. The extension direction can be any direction, so that the second signal port can automatically connect with the through silicon via after the hard macro component is placed.

[0066] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0067] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0068] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0069] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0070] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0071] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A hard macro component for cross-voltage domain signal interconnection, characterized in that, include: At least one level conversion unit, the level conversion unit integrating a first signal port and a second signal port, the first signal port being used for electrical connection with a through-silicon via to receive an electrical signal in a first voltage domain; And, a logic circuit unit of a second voltage domain arranged around the at least one level conversion unit, wherein the second signal port is electrically connected to the logic circuit unit of the second voltage domain through metal wiring; The first voltage domain and the second voltage domain are the operating voltage domains of the circuits at both ends of the through-silicon via that belong to different power supply regions.

2. The hard macro component for cross-voltage domain signal interconnection according to claim 1, characterized in that, The hard macro component is a pre-packaged circuit module. The hard macro component includes a pre-packaged housing. The interior of the pre-packaged housing includes at least: an upper edge layer cell row, a first auxiliary layer cell row, a center layer cell row, a second auxiliary layer cell row, and a lower edge layer cell row, which are distributed from top to bottom. The at least one level conversion unit is located in the central layer unit row and is centered along the horizontal direction of the central layer unit row; The logic circuit unit includes: an edge isolation unit, at least one decoupling capacitor unit, and a custom power network. The edge isolation unit is disposed in the upper edge layer unit row and the lower edge layer unit row of the pre-packaged housing for physical isolation. The at least one decoupling capacitor unit is disposed in the first auxiliary layer unit row and the second auxiliary layer unit row of the pre-packaged housing. The custom power network is disposed within the pre-packaged housing for providing corresponding power connections to the first voltage domain pin and the second voltage domain pin of the level conversion unit, respectively.

3. The hard macro component for cross-voltage domain signal interconnection according to claim 2, characterized in that, The customized power network includes multiple parallel power lines, which are arranged in the order of power line in the first voltage domain, ground line, power line in the second voltage domain, and ground line. The power line adjacent to the first voltage domain pin of the level conversion unit is connected to the first voltage domain, and the power line adjacent to the second voltage domain pin is connected to the second voltage domain.

4. The hard macro component for cross-voltage domain signal interconnection according to claim 1, characterized in that, The first signal port is located on the top layer of the metal stack, and the through-silicon via is electrically connected to the first signal port by overlapping with a horizontally extending metal contact on the top layer of the metal stack.

5. The hard macro component for cross-voltage domain signal interconnection according to claim 2, characterized in that, The height of the pre-packaged housing is an integer multiple of the standard cell row height, and the width is an integer multiple of the standard cell bit width.

6. The hard macro component for cross-voltage domain signal interconnection according to claim 1, characterized in that, The hard macro component is located in the vicinity of the corresponding through-silicon via.

7. A method for signal interconnection across voltage domains, characterized in that, include: Based on the number and location of through-silicon vias, at least one preset hard macro component is invoked, and each hard macro component is placed in the adjacent area of ​​the corresponding through-silicon via; The first signal port of the preset hard macro component is electrically connected to a through-silicon via to receive an electrical signal in the first voltage domain; Furthermore, the second signal port of the preset hard macro component is electrically connected to the logic circuit unit of the second voltage domain through metal wiring to form a complete signal interconnection path from the first voltage domain through the hard macro component and the through silicon via to the second voltage domain; wherein the first voltage domain and the second voltage domain are the operating voltage domains of the circuits that belong to different power supply areas at both ends of the through silicon via.

8. The cross-voltage domain signal interconnection method according to claim 7, characterized in that, Before invoking at least one preset hard macro component, the following is included: The pre-packaged housing of the hard macro component is determined based on the design rules of the target process and the through-silicon via size; Within the pre-packaged housing, the upper edge layer unit row, the first auxiliary layer unit row, the center layer unit row, the second auxiliary layer unit row, and the lower edge layer unit row are arranged sequentially from top to bottom; At least one level conversion unit is disposed in the central layer unit row and is centered along the horizontal direction of the central layer unit row; Edge isolation units are disposed in the upper edge layer unit row and the lower edge layer unit row of the pre-encapsulated housing for physical isolation; At least one decoupling capacitor unit is disposed in the first auxiliary layer unit row and the second auxiliary layer unit row of the pre-encapsulated housing; A custom power network is disposed within the pre-packaged housing to provide corresponding power connections for the first and second signal ports of the level conversion unit, respectively; wherein, the logic circuit unit includes: an edge isolation unit, at least one decoupling capacitor unit, and the custom power network.

9. The cross-voltage domain signal interconnection method according to claim 8, characterized in that, After building a custom power network, the following is included: Based on the layout results of the pre-packaged housing, edge isolation unit, level conversion unit, and decoupling capacitor unit, and the routing results of the custom power network, a physical library file for the preset hard macro component is generated; wherein, the physical library file includes a layout exchange file, a design exchange file, and a layout file describing the hard macro component, and the physical library file is used to call the preset hard macro component.

10. The cross-voltage domain signal interconnection method according to claim 8, characterized in that, The customized power network includes multiple parallel power lines, which are arranged in the order of power line in the first voltage domain, ground line, power line in the second voltage domain, and ground line. The power line adjacent to the first voltage domain pin of the level conversion unit is connected to the first voltage domain, and the power line adjacent to the second voltage domain pin is connected to the second voltage domain.

11. The cross-voltage domain signal interconnection method according to claim 7, characterized in that, The step of electrically connecting the first signal port of the preset hard macro component to the through-silicon via includes: The first signal port is located on the top layer of the metal stack, and the through-silicon via is electrically connected to the first signal port by overlapping with a horizontally extending metal contact on the top layer of the metal stack.

12. A semiconductor chip, characterized in that, include: The first nude film; The second die is stacked on top of the first die; A through-silicon via is disposed between the first die and the second die, and extends upward from the first die to the interior of the second die; A cross-voltage hard macro module is disposed inside the second die and is horizontally adjacent to a through-silicon via extending into the interior of the second die; wherein, the cross-voltage hard macro module includes: at least one level conversion unit and logic circuit units of a second voltage domain arranged around the at least one level conversion unit; The level conversion unit integrates a first signal port and a second signal port. The first signal port is electrically connected to the upper end of the through-silicon via that extends into the interior of the second die. The first signal port is configured to receive an electrical signal from a first voltage domain of the first die. The second signal port is electrically connected to a logic circuit unit in a second voltage domain of the second die.

13. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the cross-voltage domain signal interconnection method according to any one of claims 7 to 11.

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