High-precision clock taming and signal shaping method and device for satellite time service system

Abstract

The application discloses a high-precision clock taming and signal shaping method and device of a satellite time service system. The method comprises the following steps: using a local high-frequency clock signal output by a local voltage-controlled crystal oscillator to count and measure a reference second pulse received in real time, and obtaining a phase count deviation sequence of the local high-frequency clock signal relative to the reference second pulse; inputting the phase count deviation sequence into a frequency control closed loop model, analyzing historical state characteristics of the phase count deviation sequence, and calculating a frequency adjustment instruction for the local voltage-controlled crystal oscillator; converting the frequency adjustment instruction into an analog voltage signal, driving the local voltage-controlled crystal oscillator to adjust the output frequency, and obtaining a tamed local high-frequency clock signal; and using the tamed local high-frequency clock signal to drive a phase regulation logic, and generating a local second pulse which is kept synchronous with the reference second pulse. Through adaptive closed loop control and phase regulation, the application realizes accurate taming of the crystal oscillator frequency and high-precision shaping of the output signal.

Description

High-precision clock discipline and signal shaping method and device for satellite timing systems Technical Field

[0001] This invention belongs to the field of satellite time synchronization technology, and in particular to a high-precision clock discipline and signal shaping method and apparatus for satellite time synchronization systems. Background Technology

[0002] High-precision time synchronization is the cornerstone of distributed communication networks, power systems, and industrial automation control. In satellite timing systems, the local clock relies on a voltage-controlled crystal oscillator (VCXO) as its core oscillation source. It tracks the reference pulses per second (1PPS, i.e., 1 pulse per second) output by the Global Navigation Satellite System (GNSS) to calibrate its own frequency and phase, maintaining the system's timekeeping capability when satellite signals are blocked or lost. The accuracy and convergence speed of the local crystal oscillator's discipline directly determine the synchronization performance and reliability of the timing system in complex environments.

[0003] Currently, mainstream low-cost clock discipline solutions employ a counter-based feedback regulation mechanism. This type of technology uses a local high-frequency clock to count and measure the GNSS reference second pulse, obtaining the phase deviation between the two. In terms of control strategy, a fixed threshold judgment method is often used. That is, when the accumulated phase error exceeds a preset fixed count value (such as 10 or 30 clock cycles), the digital-to-analog converter (DAC) is controlled to adjust the voltage-controlled voltage in fixed steps to correct the crystal oscillator frequency. For signal shaping, a hard alignment strategy is often used. That is, after determining frequency lock, the local counter is forcibly reset to align the edge of the output local second pulse with the reference signal.

[0004] However, existing technologies suffer from limitations in addressing the nonlinear characteristics caused by device aging and the physical constraints of hardware clock accuracy. These limitations include voltage-controlled gain parameter mismatch leading to decreased control performance, and clock frequency quantization limitations resulting in restricted phase accuracy. Therefore, further research and innovation are needed to resolve these issues in existing technologies. Summary of the Invention

[0005] Purpose of the invention: In view of the above-mentioned problems in the prior art, this application provides a high-precision clock discipline and signal shaping method and apparatus for satellite timing systems.

[0006] Technical solution: Firstly, a high-precision clock discipline and signal shaping method for a satellite timing system, comprising:

[0007] Using the local high-frequency clock signal output by the local voltage-controlled crystal oscillator, the real-time received reference second pulse is counted and measured to obtain the phase count deviation sequence of the local high-frequency clock signal relative to the reference second pulse;

[0008] Input the phase count deviation sequence into the frequency control closed-loop model, analyze the historical state characteristics of the phase count deviation sequence, and calculate the frequency adjustment command for the local voltage-controlled crystal oscillator.

[0009] The frequency adjustment command is converted into an analog voltage signal, which drives the local voltage-controlled crystal oscillator to adjust the output frequency, thereby obtaining a disciplined local high-frequency clock signal.

[0010] Based on this (the tamed local high-frequency clock signal), the phase warping logic is driven to generate a local second pulse that is synchronized with the reference second pulse.

[0011] Secondly, a satellite timing device, characterized in that it comprises:

[0012] A satellite navigation receiver is used to receive satellite signals and output a reference second pulse.

[0013] A local voltage-controlled crystal oscillator is used to output a local high-frequency clock signal. Its output frequency is controlled by the input voltage control signal.

[0014] The digital-to-analog converter circuit is connected to the control terminal of the local voltage-controlled crystal oscillator and is used to generate voltage control signals;

[0015] The logic processing unit and the memory, the memory storing computer-executable instructions, the logic processing unit executing the computer-executable instructions to implement the method as described in any of the first aspects.

[0016] Beneficial effects: This invention employs online gain identification and adaptive step size control to compensate for the nonlinear characteristics caused by device aging; combined with Σ-Δ (Sigma-Delta modulation algorithm) phase micro-shift shaping, it overcomes the physical limitations of hardware clock precision, achieving the taming of the crystal oscillator frequency and the shaping of the output signal. The related technical effects will be described in detail below with reference to specific embodiments. Attached Figure Description

[0017] Figure 1 is a flowchart of a high-precision clock discipline and signal shaping method for a satellite timing system provided in an embodiment of this application.

[0018] Figure 2 is a flowchart of an embodiment of this application, which uses a local high-frequency clock signal output by a local voltage-controlled crystal oscillator to count and measure a reference second pulse received in real time.

[0019] Figure 3 is a flowchart illustrating an example of calculating a frequency adjustment command for a local voltage-controlled crystal oscillator, provided in an embodiment of this application.

[0020] Figure 4 is a flowchart illustrating another example of calculating a frequency adjustment command for a local voltage-controlled crystal oscillator, provided in an embodiment of this application.

[0021] Figure 5 is a flowchart of the phase normalization logic using the Σ-Δ phase micro-shift mechanism provided in the embodiment of this application.

[0022] Figure 6 is a timing diagram of 1PPS and TOD provided in an embodiment of this application.

[0023] Figure 7 shows an example of the experimental measurement results of the difference between real-time time and local count provided in an embodiment of this application.

[0024] Figure 8 shows another example of experimental measurement results of the difference between real-time time and local count provided in an embodiment of this application. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] To address the aforementioned issues, the applicant conducted in-depth searches and analyses, and discovered:

[0028] Correspondingly, the voltage control sensitivity (gain) of VCXO is not a constant value, but drifts with temperature changes and device aging. Existing control algorithms with fixed step size or fixed parameters cannot sense real-time changes, which can easily lead to slow convergence of the discipline process or oscillations in steady state.

[0029] Furthermore, limited by the system clock frequency of the FPGA or processor, such as 20MHz corresponding to a 50ns period, the counting and hard alignment methods cannot eliminate quantization errors and it is difficult to achieve sub-clock cycle phase synchronization accuracy, resulting in inherent phase jitter noise in the output signal.

[0030] To address these issues, the present invention will be specifically described through the following embodiments, in conjunction with Figures 1 to 5.

[0031] On the one hand, an exemplary scheme for a high-precision clock discipline and signal shaping method and apparatus for a satellite timing system is provided, covering a closed-loop process from physical layer measurement to logic layer control and then to physical layer shaping. Specifically:

[0032] Step 101: Use the local high-frequency clock signal output by the local voltage-controlled crystal oscillator to count and measure the real-time received reference second pulse, and obtain the phase count deviation sequence of the local high-frequency clock signal relative to the reference second pulse.

[0033] In this embodiment, a local voltage-controlled crystal oscillator (VCO) refers to a crystal oscillator whose output frequency can be controlled by voltage, serving as the system's local time base. Its nominal frequency is typically 20MHz or other high-frequency values. The local high-frequency clock signal is the periodic signal output by this crystal oscillator. The reference second pulse refers to a pulse signal with high time accuracy output by the satellite navigation receiver, such as GNSS 1PPS. The phase count deviation sequence reflects the real-time phase difference between the local clock and the reference clock, typically measured in clock cycles.

[0034] Specifically, the system uses a high-speed counter driven by a local high-frequency clock signal to capture the count values ​​at the arrival time of the reference second pulse and the generation time of the local second pulse, respectively. The phase difference between the two values ​​at the clock cycle level is then obtained through differential calculation. This step is fundamental to the entire closed-loop control, and its measurement accuracy is limited by the frequency of the local clock. For example, at a 20MHz clock, the counting quantization error is approximately 50ns. By acquiring this sequence in real time, the system can sense the speed of the local clock relative to standard time.

[0035] Step 102: Input the phase count deviation sequence into the frequency control closed-loop model, analyze the historical state characteristics of the phase count deviation sequence, and calculate the frequency adjustment command for the local voltage-controlled crystal oscillator.

[0036] In this step, the frequency control closed-loop model is an abstract algorithmic processing unit that can be configured with different control strategies, such as accumulation-based control, statistical optimization-based integral control, or state estimation-based robust control. This model is used to establish the mapping relationship between input error and output control quantity.

[0037] Among these, historical state characteristics are statistical or trend information extracted from error sequences over a past period, such as cumulative error, error rate of change, or the dispersion of the error distribution. Frequency adjustment commands are digital control quantities used to adjust the crystal oscillator frequency. In practice, this model runs on an FPGA or microprocessor, filtering, integrating, or estimating the state of the input phase count deviation sequence to remove measurement noise and extract the crystal oscillator's frequency drift component. This process converts instantaneous phase error into frequency correction, solving the system instability problem caused by directly adjusting using instantaneous error.

[0038] Step 103 involves converting the frequency adjustment command into an analog voltage signal to drive the local voltage-controlled crystal oscillator to adjust the output frequency, thereby obtaining a disciplined local high-frequency clock signal. This process involves a conversion from the digital domain to the analog domain.

[0039] Furthermore, the analog voltage signal is the physical voltage applied to the voltage-controlled terminal of the voltage-controlled crystal oscillator (VCO), and its magnitude determines the output frequency of the crystal oscillator. The system can use a digital-to-analog converter (DAC) to convert the digital frequency adjustment command into an analog voltage. The disciplined local high-frequency clock signal refers to the local clock signal whose frequency accuracy is locked near the reference clock under closed-loop control.

[0040] Specifically, when the frequency adjustment command changes, the DAC output voltage changes accordingly, altering the internal capacitor of the VCXO and causing its oscillation frequency to shift, thus compensating for the crystal oscillator's frequency error. Through a negative feedback mechanism, the long-term average frequency of the local clock is locked to the reference clock frequency.

[0041] Step 104: Based on this (the tamed local high-frequency clock signal), drive the phase warping logic to generate a local second pulse that is synchronized with the reference second pulse.

[0042] In this step, phase-normalization logic is used to generate the final timing signal. It can employ a simple hard-aligned counter or a more complex error-spreading modulation method. It utilizes a local clock with accurate frequency to synthesize a 1PPS signal with accurate phase.

[0043] The local second pulse is a high-precision time synchronization signal output by the system. In its implementation, this logic dynamically adjusts the overflow or toggle time of the local counter based on the output of the control model or real-time phase measurement results, ensuring that the rising edge of the generated pulse is aligned with the rising edge of the reference second pulse. This step ensures that the system is not only frequency accurate but also phase-synchronized with the standard time, achieving high-precision time synchronization.

[0044] Building upon this, traditional phase-locked loop (PLL) technology operates in the phase domain, using instantaneous phase differences to drive voltage-controlled oscillators (VCOs) for adjustment. While offering fast response, it cannot eliminate steady-state frequency deviations. This proposed solution's control strategy operates in the frequency-time integral domain, using the accumulated count deviation (i.e., the time integral of the frequency error) as the control variable. This eliminates long-term frequency deviations and helps maintain the accuracy of the long-term average frequency.

[0045] On the other hand, the optional implementations of the hardware environment and basic measurement mechanism are described, especially the hardware device architecture required to implement the method of the present invention and the specific implementation of phase measurement, which provide a data foundation for subsequent control algorithms.

[0046] In some embodiments, a satellite timing device is provided, comprising:

[0047] A satellite navigation receiver is used to receive satellite signals and output a reference second pulse.

[0048] A local voltage-controlled crystal oscillator is used to output a local high-frequency clock signal. Its output frequency is controlled by the input voltage control signal.

[0049] The digital-to-analog converter circuit is connected to the control terminal of the local voltage-controlled crystal oscillator and is used to generate voltage control signals;

[0050] The logic processing unit and the memory, the memory storing computer execution instructions, the logic processing unit executing the computer execution instructions to implement the method as described in any one of the present invention.

[0051] In this embodiment, the local high-frequency clock signal output by the local voltage-controlled crystal oscillator is used to count and measure the real-time received reference second pulses, including:

[0052] Step 201: Maintain the free-running counter driven by the local high-frequency clock signal.

[0053] In this embodiment, the system hardware includes a satellite navigation receiver, a local voltage-controlled crystal oscillator (VCXO), a digital-to-analog converter (DAC), and a logic processing unit. The satellite navigation receiver provides a reference second pulse. The local VCXO, such as a 20MHz VCXO, provides the system clock. The DAC, such as an AD5141 digital potentiometer or a dedicated DAC chip, is connected to the voltage-controlled terminal of the VCXO.

[0054] The logic processing unit can be implemented using an FPGA. The free-running counter is a continuously accumulating register within the FPGA, with a bit width sufficient to cover time intervals in the second range, such as 26 bits, and a counting range from 0 to 19,999,999. It automatically wraps around after overflowing. This counter is driven by a 20MHz local clock and serves as the system's internal time scale. Maintaining a continuously running counter avoids measurement dead zones or logic complexity caused by frequent counter resets.

[0055] Step 202: When the rising edge of the reference second pulse is detected, the current value of the free-running counter is latched to obtain the reference time latch value.

[0056] Specifically, the FPGA incorporates an edge detection circuit to monitor the externally input reference second pulse in real time. When the rising edge of the reference second pulse is detected, a capture register is triggered, instantly copying and saving the current free-running counter value. This saved value serves as the reference time latch value. This process maps external physical events onto the internal digital timeline, providing a reference point for subsequent phase comparison.

[0057] Step 203: When the rising edge of the local second pulse generated by the phase normalization logic is detected, the current value of the free-running counter is latched to obtain the local time latch value.

[0058] In other words, the local second pulse is for the current period or the previous period.

[0059] Similar to the capture of the reference time, the system simultaneously monitors the internally generated local second pulse. When the rising edge of the local second pulse is output by the phase warping logic, another capture register is triggered, latching the current free-running counter value to obtain the local time latch value. Since the local second pulse is generated by the same free-running counter or logic synchronized with it, this latch value accurately reflects the moment the local time was generated.

[0060] Step 204: Calculate the difference between the reference time latch value and the local time latch value, and perform a modulo operation on the difference based on a preset counting period to obtain the phase counting deviation sequence.

[0061] In this step, the system calculates the difference between the two latched values ​​using the following formula:

[0062] e _k =(t _g_k -t _l_k +C _0 / 2) MOD C _0 -C _0 / 2;

[0063] Among them, e _kt represents the phase count deviation at time k, in clock cycles; _g_k t represents the reference time latch value at time k; _l_k C represents the local time latch value at time k; _0 This indicates the preset counting period, which is the local clock count value corresponding to one second, such as 20,000,000; MOD represents the modulo operator.

[0064] By introducing offset C _0 The modulo operation of / 2 can solve the numerical jump problem caused by the periodic wrapping of a free-running counter, such as jumping back to 0 from 19,999,999, making the obtained e... _k This indicates the amount (positive or negative) that the local second pulse leads or lags the reference second pulse in the current second, serving as the raw input data for subsequent control algorithms.

[0065] In other words, the modulo operation can be used to handle the periodic wraparound problem of a free-running counter. Since the counter reaches C... _0 It will automatically reset to zero. If no modulus correction is performed, when the reference second pulse falls exactly near the counter's rewind time, directly calculating the difference will produce a result close to ±C. _0 The spurious large error value is eliminated by introducing an offset C. _0 The modulo operation of / 2 can map the spurious transition into a real phase error with a small absolute value, so that the subsequent control algorithm can obtain continuous and meaningful error input.

[0066] On the other hand, this embodiment describes the specific implementation process of robust adaptive discipline control. It introduces robust statistical gating, a state estimator, and an online gain identification mechanism to solve the control problem under scenarios with large input signal jitter and nonlinear device gain. Specifically, it includes:

[0067] Step 301: Construct a sliding window containing a sequence of phase count deviations at historical moments; calculate the robust statistical center and discrete scale based on the sample data within the sliding window.

[0068] Alternatively, a sliding window is invoked; based on the sample data within the sliding window, the robust statistical center and discrete scale are calculated; wherein, the sliding window contains a sequence of phase count deviations at historical moments.

[0069] In this embodiment, the system performs statistical preprocessing on the input phase count deviation sequence to resist random jitter and abnormal jumps in the reference second pulse. The sliding window is a first-in-first-out buffer that stores deviation samples W from the most recent M moments. _k ={e _k -M+1, ...,e _kThis can also be called a sliding window dataset, where the window length M can be set from 30 to 300. The system calculates the median of the data within this window as the robust statistical center m. _k =median(W _k Simultaneously, the discrete scale σ is calculated using the median absolute deviation algorithm. _k =1.4826×median(|e _i -m _k |);

[0070] Above, σ _k The discrete scale is represented by 1.4826, which is the normality coefficient used to correct the median absolute deviation (MAD) estimate to the standard deviation estimate under a normal distribution; median(...) indicates the median operation; e _i Represents the sliding window W _k The i-th phase count deviation sample within; m _k The median and MAD represent robust statistical centers. Compared to traditional mean and standard deviation, the median and MAD are less sensitive to outliers and can more accurately reflect the central tendency of the signal and the level of background noise.

[0071] Step 302: Based on the robust statistical center and discrete scale, a dynamic confidence interval is set, and outlier determination is performed on the sample data within the sliding window; the sample data determined to be outliers are removed, a reliable measurement sequence is generated, and only the reliable measurement sequence is used for subsequent frequency adjustment calculations.

[0072] Among them, the reliable measurement sequence is data that carries valid historical state characteristics after filtering out noise.

[0073] In other words, the effective historical state features, that is, the sample data after removing those judged as outliers (filtering noise), are also called reliable measurement sequences.

[0074] Specifically, the system is based on the calculated σ _k Set dynamic confidence interval [m] _k -γ×σ _k m _k +γ×σ _k ], where γ is a preset threshold coefficient, for example, ranging from 3 to 6. For the measured value e at the current time... _k If it falls outside the interval, it is determined to be an outlier and the valid flag is set to 0; otherwise, it is determined to be a reliable measurement and the valid flag is set to 1.

[0075] Alternatively, a sliding window dataset is constructed based on the raw phase count deviation values ​​at multiple consecutive time points, and a dynamic confidence interval [m] is set according to the calculated discrete scale. _k -γ×σ _k m _k+γ×σ _k ], where γ is a preset threshold coefficient, for example, 3 to 6; for the phase count deviation at the current moment in the sliding window dataset, if it falls outside the interval, it is determined to be an outlier and the valid flag is set to 0; otherwise, it is determined to be a reliable measurement and is set to 1.

[0076] Based on this, the removed data does not participate in subsequent state updates, preventing single large-scale abnormal changes from misleading the control loop and achieving robustness against interference.

[0077] Step 303: The frequency control closed-loop model has a built-in state vector containing phase error state and frequency deviation state. Subsequent frequency adjustment calculations are performed using only reliable measurement sequences, including:

[0078] The prior state estimate for the current time is predicted based on the state vector of the previous time step; the measurement noise covariance matrix is ​​dynamically adjusted using a discrete scale; the state vector is updated based on the residual between the reliable measurement sequence and the prior state estimate, combined with the measurement noise covariance matrix, to obtain the posterior phase error estimate and the posterior frequency deviation estimate for the current time step.

[0079] Accordingly, the system defines a state vector x. _k =[θ _k ω _k ] T , where θ _k For phase error, ω _k For frequency deviation, [...] T This indicates a transpose operation. State prediction is then performed using the following formula:

[0080] x # _k - =F×x # _k-1 ;

[0081] Where, x # _k - x represents the prior state estimate at the current moment; # _k-1 This represents the posterior state estimate from the previous time step. # The symbol _hat represents the state transition matrix; F represents the state transition matrix, with the first row containing 1s and T, and the second row containing 0s and 1s, where T is the sampling period, typically 1 second. Next, the measurement noise covariance matrix is ​​dynamically adjusted using discrete scaling, with the following formula:

[0082] R _k =max((σ _k ) 2 R _min );

[0083] Among them, R _k σ represents the measurement noise covariance at the current moment. _k For discrete scales; R _min This represents the preset minimum noise covariance limit, and max(...) corresponds to the function that takes the maximum value. This step achieves noise adaptation, that is, when the input signal jitter increases, σ... _k Increase, leading to R _k If the value is increased, the filter will automatically reduce the trust weight of the current measurement value, maintaining the stability of the output.

[0084] Based on this, the optimal estimate is obtained by updating the state vector using the standard Kalman filter formula or the equivalent recursive least squares formula, combined with reliable measurements. In other words, the phase count bias is a core component of the reliable measurements.

[0085] The specific form of the state transition matrix F is as follows:

[0086] ;

[0087] Where T is the sampling period, and in this scheme, T = 1 second. This matrix reflects the physical relationship between phase error and frequency deviation. Within one sampling period, the increment of phase error is equal to the product of frequency deviation and sampling period, while the frequency deviation itself remains approximately constant.

[0088] Furthermore, the state estimator also needs to configure the process noise covariance matrix Q to describe the random walk characteristics of the crystal oscillator frequency. A typical form of the Q matrix is:

[0089] ;

[0090] Where, q θ The process noise variance corresponding to the phase can be set to a small value, such as 10. -18 s 2 ;q ω The process noise variance corresponding to the frequency deviation reflects the short-term stability index of the crystal oscillator; a typical value can be taken as 10. -16 Up to 10 -14 (Dimensionless). The specific value of the Q matrix can be determined based on the Allan variance index of the crystal oscillator used. The Allan variance (AVAR) is a statistical index used to analyze the stability of stochastic processes.

[0091] Step 304, the frequency control closed-loop model also includes an online gain identification unit, whose processing steps include:

[0092] The locking state of the frequency control closed-loop model is monitored. When it is in a stable locking state, a micro-perturbation signal is generated and superimposed on the frequency adjustment command.

[0093] Real-time estimation of the frequency deviation of the local voltage-controlled crystal oscillator under the action of micro-perturbation signals, and calculation of the change in the frequency deviation estimate;

[0094] Based on the ratio between the change in the micro-perturbation signal and the frequency deviation estimate, the control gain coefficient is updated. The control gain coefficient characterizes the degree of influence of the change in the frequency adjustment command on the output frequency.

[0095] Furthermore, the system introduces an online gain identification mechanism. When the system determines that both the phase error and frequency deviation are less than the locking threshold, it enters the identification mode. The system generates a small perturbation signal Δu, such as an alternating square wave or pseudo-random sequence with an amplitude of 1, and superimposes it onto the current control word.

[0096] Next, the state estimator detects the frequency deviation change caused by the disturbance. The system calculates the instantaneous gain g. _inst =Δω / Δu. Where, g _inst Δω represents the instantaneous control gain; Δω represents the detected frequency deviation change; Δu represents the amplitude of the applied micro-perturbation signal. The control gain coefficient is the smoothed value of this instantaneous gain, describing how many hertz (or relative frequency offset) the crystal oscillator frequency will change by 1 unit of DAC control word under the current conditions.

[0097] Furthermore, the design of micro-perturbation signals must meet the following principles:

[0098] The disturbance amplitude should be small enough not to affect the system's lockout state, but large enough so that the resulting frequency change can be reliably identified in the measurement noise. In this scheme, the typical disturbance amplitude is ±1 DAC code value, and the disturbance form is an alternating square wave with a period of 2 to 4 seconds, that is, the disturbance direction is switched every 1 to 2 seconds.

[0099] Based on this, the conditions for initiating the identification process include:

[0100] The lock flag lock_k=1 has been in place for at least L seconds, for example, L=10s;

[0101] Phase error estimate |θ # _k | Less than the identification allowable threshold θ _th For example, θ _th =200ns;

[0102] Frequency deviation estimate |ω # _k | Less than the identification allowable threshold ω _th For example, ω _th =5×10 -8If the above conditions are not met, freeze the gain update and keep g. _k =g _k-1 .

[0103] Step 305: Calculate the instantaneous ratio of the change in the micro-disturbance signal to the frequency deviation estimate; use the exponentially weighted moving average algorithm to smooth the instantaneous ratio, update the control gain coefficient, and suppress the influence of single identification error on the control parameters.

[0104] To obtain a stable gain estimate and avoid instantaneous noise interference, the system uses an exponentially weighted moving average (EWMA) algorithm to smooth the instantaneous gain. The update formula is as follows:

[0105] g _k =(1-β)×g _k-1 +β×(Δω / Δu);

[0106] Among them, g _k This represents the updated control gain coefficient at the current time; β represents the smoothing factor, typically a small value such as 0.01 to 0.1; g _k-1 Δω represents the control gain coefficient at the previous moment; Δω represents the change in the estimated frequency deviation; and Δu represents the amplitude of the micro-perturbation signal. Through smoothing, the system can slowly track the long-term drift of device characteristics while filtering out high-frequency noise during the measurement process, which helps maintain the stability of control parameters. For example, if the initial gain estimate is 10 ns / code and the measured instantaneous gain is 12 ns / code, after smoothing, it is updated to 10.02 ns / code, gradually approaching the true value.

[0107] Step 306, calculate the frequency adjustment command for the local voltage-controlled crystal oscillator, including:

[0108] Based on a reliable measurement sequence, the target frequency correction required to eliminate the current frequency error is calculated using a servo loop filter.

[0109] By using the control gain coefficient, the target frequency correction is mapped to an adaptive step size in the voltage control domain;

[0110] Based on this (adaptive step size), update the current frequency adjustment command and perform amplitude limiting processing on the updated frequency adjustment command.

[0111] In other words, the adaptive step size is adapted to the local voltage-controlled crystal oscillator input characteristics.

[0112] Based on the frequency deviation and phase error output by the state estimator, the servo controller, such as a PI controller (proportional-integral controller), calculates the target frequency correction ω5 required to bring the error to zero. _cmd Then, using the identified gain coefficient g_k The frequency correction is converted into the adjustment step size of the DAC control word, and the calculation formula is as follows:

[0113] Δu _k =ω _cmd / g _k ;

[0114] Where, Δu _k Indicates the adaptive step size; ω _cmd Indicates the target frequency correction amount; g _k This represents the control gain coefficient at the current moment. For example, if a 1Hz frequency offset needs to be corrected and the current gain is 0.5Hz / code, then two code values ​​need to be adjusted; if the gain becomes 1Hz / code, then only one code value needs to be adjusted.

[0115] Based on this, the step size is applied to the current control word. _k =u _k-1 +Δu _k ; where u _k-1 The DAC control word from the previous moment is used for amplitude limiting to prevent overflow. Adaptive step-size control based on true gain ensures consistent loop bandwidth and convergence speed under different operating conditions, avoiding overshoot or slow response issues caused by fixed step sizes.

[0116] According to one aspect of this application, based on the state estimation results and measurement validity, a system lockout state flag, also referred to as a lockout flag, is determined and output, including:

[0117] The conditions for setting the lock status flag include the simultaneous fulfillment of the following three conditions:

[0118] The valid flags output by the robust statistical gating unit have been continuously L _lock The second is a valid value of 1, where L _lock To lock the confirmation duration, a value of 10 seconds can be set, where the valid flag corresponds to the valid flag bit;

[0119] The absolute value of the phase error estimate output by the state estimator is less than the locked phase threshold θ. _lock , where θ _lock The value can be 500ns;

[0120] The absolute value of the frequency deviation estimate output by the state estimator is less than the locked frequency threshold ω. _lock , where ω _lock It can take the value 1×10 -7 That is, 0.1 ppm.

[0121] Furthermore, the condition for clearing the lock status flag is that any of the following conditions are met:

[0122] Lock status flag consecutive M _unlock The second value is invalid (0), M _unlock The value can be 3s;

[0123] The absolute value of the phase error estimate |θ # _k |Exceeding the unlock phase threshold θ _unlock The value can be 2μs;

[0124] The absolute value of the frequency deviation estimate |ω # _k |Exceeding the unlocking frequency threshold ω _unlock It can take the value 5×10 -7 .

[0125] The lockout status flag can be used as a system status output for monitoring by the host computer, and can also be used as a start condition for the subsequent online gain identification module.

[0126] This solution employs online gain identification and adaptive step-size control to address the nonlinearity of voltage-controlled gain caused by device aging and temperature drift. A small disturbance signal is injected into the system in a locked state, and the ratio of frequency deviation to control word change (i.e., instantaneous gain) is measured and calculated in real time. This real-time gain is then used to dynamically adjust the step size of the servo loop. This mechanism allows the system to sense real-time changes in hardware sensitivity, ensuring that the control loop maintains optimal response speed and stability under different temperatures and aging levels. It also solves the problems of slow convergence or steady-state oscillations that are easily caused by fixed-step-size algorithms.

[0127] As an example, an alternative implementation of the Σ-Δ (Sigma-Delta modulation technique) high-precision shaping and signal holding mechanism is described. This embodiment breaks through the physical quantization limitation of the system clock cycle, such as the 50ns resolution corresponding to a 20MHz clock, and achieves long-term average phase alignment accuracy of the sub-clock cycle through jitter modulation on the time axis.

[0128] Step 401: Obtain the phase error estimate of the current moment output by the frequency control closed-loop model, and convert it (phase error estimate) into a target phase correction amount in clock cycles.

[0129] Alternatively, it can be described as obtaining the phase error estimate of the current moment generated by the frequency control closed-loop model when analyzing the phase count deviation sequence, and converting it into a target phase correction amount in clock cycles.

[0130] In this embodiment, the phase error estimate is the optimal posterior phase estimate output by the state estimator, typically in seconds. Since the FPGA's internal logic operates on a clock cycle basis, unit conversion is necessary. The target phase correction amount δ _k This represents the amount of correction that needs to be applied within this second to eliminate the current phase error, and its calculation formula is as follows:

[0131] δ _k =-θ _k ×f _clk ;

[0132] Among them, f _clk For the local clock frequency, δ _k It is typically a real number with a decimal part. For example, if the current phase error estimate is +12.5ns and the local clock is 20MHz (period 50ns), then the target phase correction δ _k =-12.5 / 50=-0.25 tick. This means that theoretically, the local second pulse needs to be advanced by 0.25 clock cycles, which cannot be physically achieved through a single counter operation, thus requiring subsequent Σ-Δ modulation processing.

[0133] Step 402: The target phase correction amount is processed by error diffusion using the Σ-Δ modulation algorithm, which converts the non-integer phase correction requirement into a discrete micro-shift decision amount of integer clock cycles.

[0134] Among them, the Σ-Δ modulation algorithm is also known as the Sigma-Delta modulation algorithm.

[0135] In this step, the Σ-Δ modulation algorithm is a signal processing technique that converts high-precision low-frequency signals into low-precision wideband signals. In this scheme, it is used to convert non-integer tick correction quantities that cannot be directly executed into a series of executable integer tick operations (+1, 0, -1). Error diffusion processing refers to retaining the residual error that was not executed in this quantization and adding it to the next operation to ensure that the long-term accumulated error is zero. Discrete micro-shift decision quantity q _k This is the integer instruction output per second by the algorithm, with a value set of {+1, 0, -1}. Here, +1 indicates a delay of one clock cycle, -1 indicates an advance of one clock cycle, and 0 indicates normal counting.

[0136] Step 403: Maintain the phase residual accumulator. In each second pulse generation cycle, accumulate the target phase correction amount to the phase residual accumulator.

[0137] Specifically, the system defines a floating-point or fixed-point register, denoted as `acc`, as a phase residual accumulator in the FPGA logic. This accumulator stores the phase error residuals that have not yet been physically executed. During the k-th second pulse generation cycle, the system performs an update operation: `acc`. _new =acc _old +δ _k Among them, acc _new The corresponding value of the accumulator after the update, acc _old The corresponding accumulator value before the update, δ _k This is the target phase correction value input at the current moment. For example, if the target phase correction value is -0.25 ticks for four consecutive seconds, the accumulator value will change to -0.25, -0.50, -0.75, and -1.00 respectively. This process reflects the integral effect of the error.

[0138] Accordingly, the phase residual accumulator (acc) is implemented in the FPGA using a fixed-point fractional format. It can be configured as a 32-bit signed fixed-point number, where 16 bits represent the integer part and 16 bits represent the fractional part, i.e., the Q16.16 format. The minimum resolution that this format can represent is 1 / 65536 of a clock cycle, which corresponds to approximately 0.76 picoseconds for a 20MHz clock, far less than the system's target accuracy.

[0139] To prevent the accumulator from overflowing under abnormal conditions, the system sets an upper limit on the absolute value of the accumulator, for example, ±16 clock cycles. When the accumulator value exceeds this range, saturation limiting is performed, which can trigger an abnormal alarm. Next, when the system enters hold mode, the accumulator can be slowly brought to zero in an exponential decay manner, for example, at 10% per second, to avoid sudden output phase changes due to accumulated historical residuals after signal recovery.

[0140] Step 404: Detect whether the value of the phase residual accumulator exceeds the preset unit clock cycle threshold; when the value of the phase residual accumulator exceeds the unit clock cycle threshold, control the generation time of the local second pulse to be advanced or delayed by one clock cycle relative to the preset planned time, and subtract the value corresponding to the unit clock cycle threshold from the phase residual accumulator to achieve smooth release of phase error across cycles.

[0141] In this step, the unit clock cycle threshold is typically set to 1.0 or 0.5, depending on the specific quantization strategy. The system monitors the accumulator value in real time; if the accumulator value... _new If ≥1.0, then generate q. _k =+1 (delay 1 tick), update accumulator acc _new =acc _new -1.0; if acc _new If ≤-1.0, then generate q. _k=-1 (1 tick early) to update accumulator. _new =acc _new +1.0; otherwise, generate q. _k =0, the accumulator value remains unchanged.

[0142] Furthermore, when the accumulator reaches -1.00, the system triggers an advance operation by 1 tick, and the accumulator is simultaneously reset to zero. Externally, this manifests as follows: the local 1PPS phase remains unchanged for the first 3 seconds (with an error), while the local 1PPS suddenly advances by 50ns in the 4th second. Although the instantaneous jitter is 50ns, the average phase correction over 4 seconds is precisely equal to -12.5ns, achieving sub-clock precision average alignment.

[0143] Step 405: Dynamically adjust the generation time of the local second pulse using discrete micro-shift decision quantities, so that the average phase of the local second pulse over multiple cycles is aligned with the reference second pulse, and the average phase error is less than one clock cycle.

[0144] In practice, the local second pulse is generated by a counter, and the default overflow threshold of this counter is C. _0 -1. For example, 19,999,999. When the discrete micro-shift decision quantity q is received. _k At that time, the system dynamically adjusts the overflow threshold for the current second to C. _target =(C _0 -1)+q _k If q _k =+1, the threshold becomes 20,000,000, the counter increments by one number, and the pulse is delayed before output; if q _k =-1, the threshold becomes 19,999,998, the counter counts down by one, and the pulse is output earlier. Through dynamic adjustment, the output 1PPS signal exhibits a slight jitter on the time axis. This jitter is a high-frequency shift of quantization noise. After low-pass filtering in downstream application systems, such as phase-locked loops or smoothing algorithms, high synchronization accuracy can be obtained.

[0145] Based on this, the system determines whether the satellite signal has been lost by monitoring the count value of the reference second pulse. Accordingly, a BD (BeiDou Navigation Satellite System) 1PPS counter is maintained. This counter is reset to its initial value, for example, 2, each time a rising edge of a BD 1PPS is detected, and then continuously incremented by the local clock. If the value of this counter exceeds a preset loss determination threshold, for example, 40,000,000, corresponding to 2 seconds without receiving a BD 1PPS, the satellite signal is determined to be lost, and the loss flag is set to 1. During the period when the loss flag is 1, the coarse adjustment logic pauses the adjustment operation, keeping the current RDAC (resistance digital-to-analog converter) value unchanged; the shaping logic, depending on the configuration, can choose to directly output the BD 1PPS (even if it is unstable) or output the local 1PPS and mark it as hold mode.

[0146] Step 406: When the robust statistical gating unit fails to output a reliable measurement sequence for a preset duration, it enters the hold mode. In the hold mode, the current control gain coefficient and frequency adjustment command are frozen, and the error accumulation of the phase residual accumulator is stopped. Only the current residual value of the phase residual accumulator is used to continue to perform Σ-Δ phase micro-shift until a reliable measurement sequence is reacquired.

[0147] This step describes the soft hold strategy when satellite signals are lost or of poor quality. The preset duration can be set, for example, from 10 seconds to 60 seconds. When the system determines that it has entered hold mode, it considers the external reference unreliable and therefore stops updating the frequency control word and gain coefficient, maintaining the state of the last stable lock and relying on the crystal oscillator's own stability to maintain the frequency output.

[0148] Next, the input target phase correction is forcibly set to zero to prevent noise from being introduced into the accumulator. However, if a non-zero value, such as 0.8 ticks, is still present in the phase residual accumulator at the moment of entering hold mode, it indicates that the system is still awaiting the upcoming phase adjustment. Based on this, the system allows the accumulator to continue operating according to its original logic; that is, although no new errors are accumulated, threshold judgment is still performed. If a mechanism allows the residual value to be released, such as using a decay release strategy, the corresponding micro-shift operation is executed.

[0149] Optionally, in hold mode, the accumulator can be frozen directly or smoothly reset to zero to avoid phase abrupt changes when there is no reference source. Compared to direct hard switching or reset, this approach ensures the continuity and smoothness of the output signal, avoiding phase shocks to downstream systems.

[0150] According to one aspect of this application, the system outputs a lock flag, the determination condition of which is: consecutive L... _lock Within seconds, for example, 30 seconds, all valid flag bits are 1, and the estimated phase error value |θ # _k |<θ _lock (e.g., 100 ns), and the frequency deviation estimate |ω # _k |<ω _lock (e.g., 1×10) -8 The lock flag is used to trigger subsequent online gain identification and to indicate the system status to downstream modules.

[0151] This solution employs a Σ-Δ phase micro-shifting and shaping technique to address the phase quantization accuracy issue caused by hardware clock frequency limitations. This mechanism utilizes the error diffusion principle, recording sub-clock errors that cannot be executed within a single clock cycle using a phase residual accumulator. These errors are then transformed into probabilistic integer clock cycle fine-tuning decisions, dynamically advancing or delaying the process by one clock cycle. This cross-cycle averaging strategy overcomes the resolution limitations of FPGA physical clock cycles (e.g., 50ns), achieving a high-precision synchronization effect with a long-term average phase error far less than one clock cycle.

[0152] As another example, an optional implementation of dual-timescale statistical disciplined control is provided. This is suitable for resource-constrained FPGA platforms or those with slightly lower robustness requirements, utilizing a fast and slow dual-channel integrator to resolve the trade-off between response speed and stability. Specifically, it includes:

[0153] Step 501: Based on the short-term forgetting factor, perform an exponentially weighted moving average calculation on the phase count deviation sequence to obtain the short-term weighted integral value. The short-term weighted integral value is used to characterize the transient frequency fluctuation of the local voltage-controlled crystal oscillator.

[0154] In this embodiment, the system constructs a short-term integrator. The short-term forgetting factor λ _s It is a small constant close to 1, for example, it can be preset to 0.9 or 0.95, which corresponds to a short effective memory time window of about 10 to 20 seconds. Short-term weighted integral value S _short The iterative calculation formula is:

[0155] S _short (n)=λ _s ×S _short (n-1)+e(n);

[0156] Where e(n) is the phase count deviation for the current second, S _short (n) is the short-term weighted integral value calculated at the nth second, λ _s For a pre-configured short-term forgetting factor, such as 0.9, S _short (n-1) is the short-term weighted integral value of the previous second. Since λ _s Smaller, S _short It can quickly follow changes in e(n) and is very sensitive to sudden frequency disturbances, making it suitable for capturing transient fluctuations.

[0157] Step 502: Based on the long-term forgetting factor, perform exponential weighted moving average calculation on the phase count deviation sequence to obtain the long-term weighted integral value. The long-term weighted integral value is used to characterize the steady-state frequency drift of the local voltage-controlled crystal oscillator.

[0158] In parallel, the system constructs a long-term integrator. The long-term forgetting factor λ... _lIt is a constant close to 1, for example, it can be pre-configured to 0.99 or 0.995, which corresponds to a longer effective memory time window, approximately 100 to 200 seconds. Long-term weighted integral value S _long The iterative calculation formula is:

[0159] S _long (n)=λ _l ×S _long (n-1)+e(n);

[0160] Among them, S _long (n) is the long-term weighted integral value calculated at the nth second, λ _l For a pre-configured long-term forgetting factor, such as 0.99, S _long (n-1) is the long-term weighted integral value of the previous second, and e(n) is the phase count deviation of the nth second.

[0161] Due to λ _l Larger, S _long It possesses strong low-pass filtering characteristics, effectively filtering out high-frequency jitter and primarily reflecting the long-term average drift trend of the crystal oscillator frequency. The long-term forgetting factor is greater than the short-term forgetting factor, resulting in a longer memory length for historical errors in the long-term weighted integral value compared to the short-term weighted integral value. In other words, the short-term and long-term weighted integral values ​​can be used to determine the direction of frequency drift and calculate frequency adjustment commands.

[0162] Step 503: Calculate the error standard deviation of the phase counting deviation sequence in real time, and set a dynamic adjustment threshold based on the error standard deviation.

[0163] To distinguish between normal noise and anomalous drift, the system estimates the statistical characteristics of the error in real time. The standard deviation of the error σ(n) can be calculated using a recursive formula:

[0164] σ 2 (n)=λ _σ ×σ 2 (n-1)+(1-λ _σ )×e 2 (n),

[0165] Where, σ 2 (n) represents the variance of the error estimated at the nth second, and the square root of this variance is the standard deviation σ(n). _σ σ is the smoothing coefficient for variance estimation. 2 (n-1) represents the error variance of the previous second, and e(n) represents the phase count deviation of the nth second.

[0166] Furthermore, the dynamic adjustment threshold Th(n) is set to a multiple of the standard deviation, for example, Th(n) = k × σ(n), where k is typically 3 to 5. That is, when the ambient noise increases, the adjustment threshold automatically increases to avoid frequent system malfunctions; when the environment is quiet, the threshold automatically decreases to improve control accuracy.

[0167] Step 504: Calculate the ratio of the short-term weighted integral value to the long-term weighted integral value. When the ratio is in a stable range and the absolute value of the long-term weighted integral value is greater than the dynamic adjustment threshold, it is determined that there is an effective frequency drift.

[0168] In this step, the system defines the ratio R = |S _short | / |S _long If R is too large, for example, greater than 2.0, it indicates that the short-term error is much larger than the long-term error, which may be due to sudden interference, and adjustment is not advisable in this case. If R is too small, for example, less than 0.5, it indicates that the error is mainly contributed by the long-term term but has a recent reversal trend, and adjustment is also not advisable. Adjustment should only be made when R is in a stable range, for example, preset to 0.5 to 2.0, and |S _long Only when |>Th(n) is a definite frequency drift that needs correction confirmed. It should be understood that this dual criterion avoids the phenomenon of chasing jitter.

[0169] Step 505: Based on the difference between the long-term weighted integral value and the dynamic adjustment threshold, a variable step size frequency adjustment command is calculated using a piecewise or linear mapping method to eliminate effective frequency drift and suppress over-adjustment oscillation.

[0170] Once adjustment is determined, the system decides the adjustment level based on the severity of the drift. The segmented mapping method can be set as follows: if |S _long Within the range [Th, 2Th] (Th corresponds to the dynamic adjustment threshold), the adjustment step size Δu = 1; if it's within the range [2Th, 3Th], Δu = 2; and so on, setting a maximum step size limit. Alternatively, a linear mapping method can be used to solve Δu = round((|S _long |-Th)×K _gain ); K _gain This represents the linear mapping gain coefficient. Through this variable step-size mechanism, the system can quickly pull back to the frequency when the error is large, and fine-tune the approximation when the error is small. This ensures convergence speed while suppressing overshoot oscillations, thus optimizing control performance.

[0171] According to one aspect of this application, the above floating-point operations are converted to fixed-point format to facilitate FPGA hardware implementation. Specifically, the forgetting factor λ... _s =0.9 can be approximated as 230 / 256, which can be achieved using 8-bit shift operations: S _short =(S _short ×230)>>8+e(n).

[0172] Similarly, λ _l =0.99 can be approximated as 253 / 256. Square root calculations can be performed using a lookup table or a single Newton-Raphson iteration approximation. Specifically, for calculating the standard deviation of the error, a 256-point square root lookup table can be pre-stored, and σ... 2 The high 8 bits of (n) are used as an index to look up a table and obtain an approximate value of the error standard deviation. Division operations can be converted to multiplication comparisons to avoid consuming divider resources. For example, the condition for judging the error ratio, error ratio > 2, can be equivalently converted to |S _short (n)|>2×|S _long (n)| requires only multiplication and comparison operations.

[0173] As another example, a specific implementation method for cumulative counting discipline and hard alignment shaping is described, particularly based on a fundamental control strategy of fixed-step cumulative adjustment and state-locked hard alignment. This embodiment has a simple structure and is easy to implement on low-cost hardware.

[0174] During the system power-on initialization phase, the logic processing unit writes a preset empirical initial value, such as 0x8a, to the digital-to-analog converter circuit, so that the local voltage-controlled crystal oscillator outputs a signal close to the nominal frequency in an undisciplined state.

[0175] In this embodiment, the frequency control closed-loop model is configured to perform fixed-step cumulative adjustment, specifically including:

[0176] Step 601: Directly accumulate the phase count deviation sequence and maintain the accumulated count deviation value.

[0177] In this embodiment, the system does not perform weighted processing, but directly counts the phase deviation e per second. _k Perform arithmetic summation to obtain the cumulative count deviation value ∑ _clkDif The calculation formula can be expressed as:

[0178] ∑ _clkDif (n)=∑ _clkDif (n-1)+e _k ;

[0179] Where, ∑ _clkDif (n) represents the cumulative count deviation value updated in the nth second, reflecting the cumulative time slippage of the local clock relative to the reference clock; ∑ _clkDif (n-1) is the cumulative count deviation value of the previous second, e _k This represents the phase count deviation measured in the current second.

[0180] Step 602: Compare the absolute value of the accumulated count deviation with a fixed threshold; when the absolute value of the accumulated count deviation exceeds the fixed threshold, generate a frequency adjustment command according to a fixed adjustment step size to correct the output frequency of the local voltage-controlled crystal oscillator in a single direction until the absolute value of the accumulated count deviation falls back to within the fixed threshold.

[0181] In this step, the fixed threshold can be set to 10 or 30 clock cycles, or in other words, it can be preset to 10 or 30 clock cycles. When ∑ _clkDif When the value is ≥30, the system determines that the local frequency is too high and reduces the DAC control word by a preset fixed adjustment step, usually 1; when ∑ _clkDif When the value is ≤-30, the frequency is considered too low, and the DAC control word is incremented by 1. When the value is below the threshold, the control word remains unchanged.

[0182] Optionally, to address the response delay of the crystal oscillator, this adjustment process can be combined with a timer, for example, allowing an adjustment action to be performed only once every 20 seconds. Although this coarse adjustment strategy has a slower response, it offers good stability and is suitable for applications where extreme precision requirements are not necessary.

[0183] Furthermore, the specific implementation of the coarse-tuning logic is as follows:

[0184] The system uses a 20-second adjustment cycle, and at the end of each cycle, it counts the local 20MHz clock within a BD 1PPS interval. The nominal count value is 20,000,000. The coarse adjustment is determined using the following rules: if the count value is greater than 20,000,000 for 20 consecutive seconds (i.e., the local frequency is too high), the DAC control word is decremented by 1; if the count value is less than 20,000,000 for 20 consecutive seconds (i.e., the local frequency is too low), the DAC control word is incremented by 1; if the count value equals 20,000,000 or fluctuates within 20 seconds, the DAC value remains unchanged.

[0185] Based on this, the determination of 20 consecutive seconds is achieved through a 4-bit counter cnt_20s: the relationship between the count value and the nominal value is checked once per second. If the direction is consistent with the previous second, cnt_20s is incremented by 1; otherwise, it is cleared to zero. When cnt_20s reaches 20, a DAC adjustment is triggered to clear cnt_20s to zero.

[0186] Furthermore, the phase warping logic is configured to perform state-locked hard alignment, specifically including:

[0187] Step 603: Real-time statistical analysis of the phase count deviation sequence. When the value of the phase count deviation sequence is detected to remain within a stable range for a preset number of consecutive times, a lock validity flag is generated.

[0188] Based on this, the system statistics e _kThe state of e can be used to determine whether the system has been successfully tamed. _k For N consecutive times, for example, N=10, the value remains 0, meaning the counter value is 20,000,000, or ∑ _clkDif If no adjustment is triggered within a prolonged period, the lockout flag is activated, indicating that the local crystal oscillator frequency is very close to the nominal value.

[0189] Step 604: In response to the lock valid flag, at the arrival time of the reference second pulse, the local counter used to generate the local second pulse is forcibly reset to the alignment initial value.

[0190] In locked state, the system performs a hard alignment operation to achieve phase alignment. When the rising edge of the reference second pulse is detected and the lock flag is valid, the system forcibly modifies the value of the local counter to a preset initial alignment value on the next clock edge. This initial value is typically calibrated based on hardware latency, for example, set to 9 or 2 to compensate for processing delay. Through this forced reset, the phase of the local second pulse is pulled to the same position as the reference second pulse in one go.

[0191] Step 605: During the period before a lock validity flag is generated, keep the local counter running freely and directly output the reference second pulse as a backup output to achieve forced synchronization and maintenance between the local second pulse and the reference second pulse.

[0192] When the system is not locked, it indicates that the local clock is unreliable. Next, the phase-normalizing logic selects a directly transmitted reference second pulse, such as BeiDou 1PPS, as the system output, or outputs a locally generated pulse but marks it as unavailable. This backoff mechanism ensures that downstream devices can still obtain a usable (although potentially jittery) second signal during the initial training phase or in a lost-lock state.

[0193] Specifically, the system maintains a tracking counter cnt_9 to record the counting position corresponding to BD 1PPS at the 9th stable counting moment. When the 10th consecutive count value of 20,000,000 is detected, the local counter is assigned the value cnt_9+1, thereby aligning with the historical stable moment rather than the current moment and avoiding introducing residual jitter from the current moment into the output signal.

[0194] According to one aspect of this application, during the coarse adjustment stage, if cnt _1pps If the value is ≤19,999,998, the frequency is considered too low, and the RDAC value is incremented by 1; if cnt... _1pps If the value is ≥20,000,000, the frequency is considered too high, and the RDAC value is decreased by 1. Where cnt... _1ppsThis corresponds to the hardware count value within a 1-second pulse period. To avoid misjudgments caused by BD 1PPS jitter and to provide sufficient response time for the voltage-controlled crystal oscillator, a strategy of adjusting every 20 seconds is adopted. When the count value is 20,000,000 for 10 consecutive times, the system enters a locked state and switches to fine-tuning mode.

[0195] During the fine-tuning phase, an offset encoding method is used to maintain the cumulative count deviation ∑. _clkDif Its zero point corresponds to the value 20. When ∑ _clkDif When the actual deviation is ≥30, i.e., ≥+10 clock cycles, the RDAC value is decreased by 1; when ∑ _clkDif When the actual deviation is ≤10, i.e., ≤-10 clock cycles, the RDAC value is incremented by 1. The fine-tuning logic uses a cumulative count deviation driving method. The cumulative count deviation ∑ is defined as follows: _clkDif This is the sum of the differences between each second's count value (count(n)) and the nominal value of 20,000,000, i.e.:

[0196] ∑ _clkDif (n)=∑ _clkDif (n-1)+[count(n)-20,000,000];

[0197] Furthermore, the fine-tuning decision adopts a dual-threshold rule, as follows:

[0198] When ∑ _clkDif When the value is greater than +30, decrement the DAC control word by 1 and set the ∑ value to 1. _clkDif Subtract 10; when ∑ _clkDif When <-30, increment the DAC control word by 1, and set ∑ _clkDif Add 10. The threshold of 30 corresponds to a cumulative phase deviation of approximately 1.5 μs, which is 30 clock cycles × 50 ns / cycle. The offset of 10 is used to introduce adjustment hysteresis to avoid frequent oscillations near the threshold.

[0199] Optionally, the DAC control word uses an offset binary encoding format, where 0x00 corresponds to the lowest output voltage (lowest crystal frequency), 0xFF corresponds to the highest output voltage (highest crystal frequency), and 0x80 corresponds to the intermediate voltage. When the system is powered on, the DAC is initialized to an empirical value of 0x8A, which corresponds to the typical operating point of the crystal oscillator at room temperature close to its nominal frequency.

[0200] Optionally, the system maintains a modulo-10 counter cnt_9, which increments by 1 at the rising edge of each local 1PPS. When cnt_9 = 9, an alignment operation is performed and cnt_9 is cleared. The alignment operation involves adjusting the generation time of the local 1PPS to align with the most recent BD 1PPS. The adjustment amount is determined by the integer part of the Σ-Δ phase accumulator.

[0201] While maintaining the short-term stability of the local 1PPS, a phase correction is performed every 10 seconds to ensure that the long-term average phase of the local 1PPS tracks the BD 1PPS. From the 1st to the 9th second, the generation time of the local 1PPS is only adjusted by ±1 clock cycle of the Σ-Δ micro-shift logic; at the 10th second (cnt_9=9), a larger phase jump is allowed to eliminate accumulated errors.

[0202] When the system is in hold mode (BD signal is lost), the cnt_9 counter stops counting, the alignment operation is not performed, and the local 1PPS is generated freely by the local clock.

[0203] In some embodiments, exemplary schemes for system-level integration and time recovery are described, illustrating the system-level functions of a satellite timing device, particularly the recovery and output of absolute time. The specific steps are as follows:

[0204] Step 701: Receive a time message (TOD) containing Coordinated Universal Time (UTC) information through the serial communication interface; parse the time message to obtain the UTC time value of the current second, and establish a timing association between the time message and the reference second pulse.

[0205] In this embodiment, the device receives TOD messages sent by the satellite receiver via a Universal Asynchronous Receiver / Transmitter (UART) serial port, typically configured with a baud rate of 9600. TOD messages follow a specific protocol, such as no parity check, one start bit, one stop bit, and eight data bits. The message contains the current year, month, day, hour, minute, and second information. According to the interface specification, TOD messages are typically sent within a specific time window after the rising edge of the reference second pulse (e.g., 1 ms to 500 ms). The system parses the message, extracts the UTC time value, and marks it as the time corresponding to the current reference second pulse.

[0206] Furthermore, the system establishes a pairing record for each valid GNSS 1PPS, which includes the following fields: reference time latch value, local time latch value, phase error, validity flag, UTC second value of the TOD identifier, k, and counter latch value for the TOD message arrival time. By statistically analyzing the counter latch value versus the reference time latch value, the typical value and fluctuation range of the serial communication delay can be estimated. When the delay exceeds the statistical range, the system can generate a consistency alarm, indicating that the association between TOD and 1PPS may be abnormal. In other words, GNSS 1PPS refers to the reference second pulse 1PPS output by the Global Navigation Satellite System (GNSS), i.e., 1 pulse per second; its validity can be determined by:

[0207] The GNSS receiver's lock flag is set to 1;

[0208] The 1PPS signal enables the system hardware to accurately identify rising / falling edges;

[0209] The rising edge of the GNSS 1PPS pulse must be strictly aligned with the UTC (Coordinated Universal Time) second boundary, and the time deviation must be controlled within the range required by the system (such as nanoseconds or microseconds, depending on the application scenario). If the deviation exceeds the threshold, it is considered an invalid signal.

[0210] Within several consecutive cycles (e.g., 3 to 5 1PPS cycles), the period of the 1PPS pulse remains stable at 1 second, without any abnormalities such as pulse loss or multiple pulses.

[0211] Building upon this, the fusion processing of multi-source time information also includes the parsing and pairing of TOD messages output by the BD module. The BD module outputs a TOD message via serial port at every full second, containing information such as the UTC timestamp, positioning status, and the number of visible satellites. The system processes the TOD messages using the following procedure:

[0212] Upon detecting the rising edge of BD 1PPS, record the current local timestamp T. _local Set the TOD (Transit-Oriented Development) sign to wait;

[0213] Upon receiving the complete TOD message, parse the UTC seconds value within it and compare it with the previously recorded T... _local Perform pairing and calculate message transmission delay Δt _TOD =T _current -T _local , among which, T _current The local time at which the message was received; for Δt _TOD Perform statistical analysis.

[0214] Under normal circumstances, the TOD message should arrive within approximately 100 to 500 ms after BD 1PPS. If Δt _TOD If a message exceeds a preset range, such as greater than 1 second or less than 50 ms, it is considered an abnormal message and discarded. If multiple consecutive TOD messages are abnormal, a communication failure alarm can be triggered in the BD module. Successfully paired TOD information can be used to initialize the local RTC (Real-Time Clock) and to quickly obtain the current UTC time when the system powers on, avoiding reliance on external time sources such as the Network Time Protocol (NTP).

[0215] Step 702: Align and bind the UTC time value with the rising edge of the local second pulse, and perform cumulative counting under the drive of the local second pulse to recover the real-time absolute time with nanosecond-level accuracy.

[0216] Once the UTC time is obtained, the system loads it into a local second counter. The second counter increments by 1 when the rising edge of the local second pulse arrives. Simultaneously, the system maintains a nanosecond-level counter driven by a 20MHz clock. By combining the integer second portion (UTC time) with the nanosecond portion (local phase), the system can output the complete real-time absolute time. For example, the output format is 2025-01-01 12:00:00.000000050. Because the local second pulse has undergone high-precision discipline and shaping, the long-term stability of this absolute time remains within 50ns, and in optional scenarios, it can be better than 10ns. Next, the system can also output a time uncertainty index, which increases linearly with time when in hold mode, informing the user that the reliability of the current time is decreasing.

[0217] When the system recovers from the hold state to the normal tracking state, a gradual reacquisition strategy is adopted to avoid abrupt changes in the output signal. The specific process is as follows:

[0218] Accordingly, upon detecting BD 1PPS recovery (i.e., the loss flag being cleared), the system does not immediately switch to normal mode but instead enters a recapture observation period. During this period, the system begins collecting and statistically analyzing BD 1PPS count data, but the DAC value and shaping logic remain frozen.

[0219] Furthermore, when N consecutive _rec seconds (e.g., N) _rec If the count values ​​(=5 seconds) all fall within the normal range, for example, from 19,999,998 to 20,000,002, and the valid flag of the robust statistical gating unit is continuously 1, it is determined that the signal quality has been restored and the system exits the hold state.

[0220] Based on this, after exiting the hold state, the system determines subsequent actions according to the currently estimated phase error, if |θ # _k If the value is small, for example, less than 1 μs, it can directly enter the fine-tuning / locking state; if |θ # _k If the value is too large, the system will revert to the coarse-tuning state for re-training. The Σ-Δ phase accumulator is cleared when exiting the hold state to prevent historical residuals from affecting the new tracking process.

[0221] In other embodiments, the workflow can be abstracted as a finite state machine containing the following states:

[0222] After the system powers on, it enters this state, writes a preset empirical initial value, such as 0x8a, to the DAC, and clears all accumulators, state estimators, and counters. After initialization, it unconditionally transitions to the coarse adjustment state.

[0223] The system adjusts the DAC every 20 seconds based on a comparison between the second pulse count and the nominal value. When 10 consecutive counts are both the nominal value (20,000,000), it enters a locked state. If a BD signal loss is detected, the current DAC value is maintained and the system continues to wait.

[0224] The system uses accumulated count deviation to drive fine-tuning logic, initiating a 1PPS shaping output. If the accumulated deviation exceeds a set threshold, requiring a larger adjustment, or if the count value deviates from the nominal value multiple times consecutively, it reverts to coarse-tuning mode. If the BD signal is lost for more than a preset duration, it enters hold mode.

[0225] Furthermore, the DAC value and control parameters are frozen, relying solely on the crystal oscillator's inherent stability to maintain the output. Local 1PPS continues to output but is marked as hold mode. Once the BD signal recovers and the count values ​​are normal multiple times consecutively, it transitions to coarse adjustment mode to re-capture.

[0226] In summary, the state transition logic helps to make the system's behavior predictable and verifiable under various operating conditions.

[0227] Building upon this, traditional PLLs operate in the phase domain, using the instantaneous phase difference as an error signal to drive the voltage-controlled oscillator (VCO) adjustment. Their advantage lies in their fast response speed, but due to the lack of an integral component, they cannot fundamentally eliminate steady-state frequency deviation. This scheme operates in the frequency-time integral domain, using the cumulative counting deviation (i.e., the integral of the frequency error over time) as the control variable. Let the instantaneous frequency error of the local crystal oscillator be Δf(t), then the cumulative counting deviation D(t) = ∫0 t Δf(τ)dτ; where τ is the integral variable, representing the instantaneous time point, and t is the interval boundary. Driving the control loop with D(t) is equivalent to applying integral control over the frequency error, which helps to achieve accuracy in the long-term average frequency. This mechanism complements the proportional control of traditional PLLs and can be used to achieve accurate long-term average frequency and limited short-term jitter.

[0228] On the other hand, some methods of the present invention can also be:

[0229] Accordingly, the BeiDou 1PPS is used to achieve local crystal oscillator discipline, 1PPS shaping, and real-time time recovery, providing accurate clock references and time information for other modules.

[0230] To achieve the desired crystal oscillator training, the training method employed is based on the unshaped BD 1PPS. Even with significant jitter in the BD 1PPS, the frequency accuracy of the trained crystal oscillator can still be controlled within 50ns per second, with a long-term average frequency maintained at 20MHz. After training, the crystal oscillator frequency accuracy is within an acceptable range, allowing for BD 1PPS shaping. Due to the BD 1PPS tracking processing, the long-term cumulative jitter error of the 1PPS is also within 50ns, a relatively stable value. Since both the trained crystal oscillator frequency and the shaped 1PPS maintain long-term stability, combined with the TOD time information output by the BD receiver and according to the China Mobile high-precision time synchronization 1PPS+TOD interface specification, the recovered real-time time also maintains a long-term stability within 50ns.

[0231] Optionally, an implementation environment includes: a baseband board containing a BD receiver module and an FPGA chip; the BD receiver is used to acquire GPS or BeiDou navigation and positioning information and output pulse-per-second (PPS) and time-of-death (TOD) information; the FPGA is used to implement crystal oscillator discipline, PPS shaping, time recovery, etc., providing clock reference and time basis for other modules.

[0232] The output frequency of a voltage-controlled crystal oscillator (VCO) is highly sensitive to the voltage value at its control pin. Appropriate voltage excitation can be applied to calibrate the output frequency. An AD5141 digital-to-analog converter (DAC) chip is used to convert the frequency calibration value to an analog voltage value. The frequency calibration value is the phase difference between the 1PPS BD value calculated by the FPGA and the 1PPS value generated by the local 20MHz clock. The AD5141 performs a direct-to-analog conversion on the frequency calibration value and outputs it to the VCO pin of the crystal oscillator to adjust its frequency.

[0233] Optionally, crystal oscillator training consists of two parts: coarse adjustment and fine adjustment. Coarse adjustment ensures the crystal oscillator error is within one clock cycle per second. After coarse adjustment, with the crystal oscillator error within one clock cycle per second, the module outputs a crystal oscillator lock signal. During the crystal oscillator lock period, the coarse adjustment module considers the crystal oscillator locked and stops adjusting it. After the crystal oscillator is locked, the fine adjustment module further adjusts the error within one clock cycle, ensuring that the crystal oscillator frequency does not remain consistently slightly below or slightly above 20MHz, but fluctuates around 20MHz within a range not exceeding one clock cycle. This prevents the local count accumulation value from becoming too large or too small in one direction, but only oscillates around the precise value, guaranteeing the long-term accuracy of the crystal oscillator frequency value and enabling applications sensitive to local count accumulation value offsets.

[0234] During coarse adjustment, the BD second pulse count is reset to 0 every second. Even if there is a deviation between the local crystal oscillator and the accurate 20MHz crystal oscillator, as long as the difference does not exceed one clock cycle, the count value per second will still be 20M. This count value cannot reflect the crystal oscillator error within one clock cycle.

[0235] Based on this, fine-tuning logic is needed to calibrate this error. Specifically, the long-term accumulated count value of the crystal oscillator reflects the small error of the crystal oscillator due to the cumulative error characteristic of the crystal frequency. Fine-tuning the crystal oscillator using the deviation of the long-term count value compensates for the accumulated error of the long-term count, causing the long-term count value to fluctuate around the accurate count value. Although the instantaneous frequency of the output clock may jitter, the long-term average frequency is accurate.

[0236] Alternatively, the crystal oscillator discipline process is as follows:

[0237] Initially, writing the test experience value of 0x8a at room temperature to the AD5141 can quickly tame the crystal oscillator to the accurate frequency.

[0238] Determine if the crystal oscillator is locked. If not locked, proceed to the coarse adjustment process; if locked, proceed to the fine adjustment process.

[0239] During coarse adjustment, it is determined whether there is a BD 1PPS signal. If not, the crystal oscillator cannot be tamed, and the process ends.

[0240] If a BD 1PPS signal is present, the local voltage-controlled crystal oscillator (VCO) is tamed based on the second pulse signal provided by the BD receiver. The second pulses are counted using a 20MHz local crystal oscillator. If the count value is greater than 20MHz, the local crystal oscillator frequency is too fast; the value written to AD5141 is reduced to lower the crystal oscillator frequency. Conversely, if the count value is less than 20MHz, the local crystal oscillator frequency is too low; the value written to AD5141 is increased to raise the crystal oscillator frequency. When the voltage output from AD5141 is applied to the VCO pin, the crystal oscillator frequency response has a certain delay. To allow sufficient response time for the VCO and improve taming accuracy, a taming method of adjusting the VCO pin voltage every 20 seconds is adopted. Simultaneously, adjusting the VCO pin voltage every 20 seconds avoids misjudgment of the crystal oscillator frequency caused by BD1PPS jitter.

[0241] If there is a BD 1PPS signal, and the second pulse count is 20M for 10 consecutive times, then the crystal oscillator is locked.

[0242] After coarse adjustment and the crystal oscillator is locked, further fine-tuning and taming are needed to improve the accuracy of the crystal oscillator frequency.

[0243] Fine-tuning: The BD 1PPS signal is a signal that pulls up one pulse per second. By comparing the difference between the local counter and the second pulse counter, when the difference accumulates to 10 clock cycles, the voltage of the crystal oscillator voltage control pin is adjusted once.

[0244] Optionally, the BD 1PPS output by the BD receiver may exhibit occasional phenomena such as jitter and loss, making it unsuitable for direct real-time time recovery. It requires shaping to obtain a stable and reliable second pulse. The BD 1PPS is counted using a trained local crystal oscillator. When the count value reaches 20MHz (20,000,000) for 10 consecutive times, the BD 1PPS is considered stable and reliable, without significant jitter. At this point, the local 1PPS count is kept consistent with the ninth BD 1PPS count. At other times, the local 1PPS count is used instead of tracking the BD 1PPS count. This ensures that the local 1PPS is consistently tracked and maintained against the BD 1PPS, using the BD 1PPS as a baseline.

[0245] If the BD 1PPS count value is 20M for 10 consecutive times, the subsequent local count value is considered valid, and the output 1PPS is consistent with the local count. If the BD 1PPS count value is not 20M for 10 consecutive times, it is considered that the crystal oscillator is not disciplined or there is jitter in the BD 1PPS. The second pulse generated by the local PPS count is not used, and the BD 1PPS is directly output.

[0246] Optionally, after crystal oscillator discipline and 1PPS shaping are achieved, the shaped 1PPS and the TOD time information output by the BeiDou receiver can be used to recover real-time local time information with an accuracy of 50ns.

[0247] For 1PPS and TOD timing, the default baud rate for TOD information is 9600, with no parity check, one start bit (represented by a low level), one stop bit (represented by a high level), and an idle frame with a high level. It consists of 8 data bits and should begin transmitting TOD information 1ms after the rising edge of 1PPS, completing the transmission within 500ms. This TOD message indicates the current 1PPS trigger rising edge time. The TOD protocol message is sent once per second.

[0248] Optionally, the time synchronization of the present invention is implemented by a time recovery module, which outputs year, month, day, hour, minute, and second time information with an accuracy of 50 ns for use by other modules.

[0249] Optionally, the satellite can be selected to receive GPS satellite signals or BeiDou navigation and positioning satellite signals to adapt to certain application scenarios with special requirements.

[0250] Optionally, the difference between the real-time time and the local count can also be taken from data at 980 seconds and 1 hour and 10 minutes of counting, respectively. The real-time time refers to the accurate UTC time obtained from the BeiDou navigation and positioning module. The positioning module outputs a timestamp every second, indicating the accurate real-time time. The local count is continuously accumulated using the local crystal oscillator as the clock. The difference between the real-time time and the local count is zero when the local crystal oscillator has no deviation; when the local crystal oscillator has a fixed deviation, the difference will increase in one direction; when the local crystal oscillator fluctuates around its accurate frequency value, the difference will sometimes increase and sometimes decrease. Repeating this process continuously stabilizes the deviation between the locally accumulated count and the real-time time within a certain range, allowing the local count to also be used as a time reference.

[0251] The optional embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solution of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A high-precision clock discipline and signal shaping method for a satellite timing system, characterized in that, include: Using the local high-frequency clock signal output from a local voltage-controlled crystal oscillator (VCO), the real-time received reference second pulse is counted to obtain the phase count deviation sequence of the local high-frequency clock signal relative to the reference second pulse. This sequence is then input into a frequency control closed-loop model to analyze the historical state characteristics of the phase count deviation sequence and calculate the frequency adjustment command for the local VCO. The frequency adjustment command is converted into an analog voltage signal to drive the local VCO to adjust its output frequency, resulting in a docile local high-frequency clock signal. Based on this, phase warping logic is driven to generate a local second pulse synchronized with the reference second pulse. The frequency control closed-loop model includes a robust statistical gating unit. Analyzing the historical state characteristics of the phase count deviation sequence involves: calling a sliding window containing the historical phase count deviation sequence; calculating the robust statistical center and discrete scale based on the sample data within the sliding window; and calculating the robust statistical center and discrete scale based on the robust statistical center and discrete scale. A dynamic confidence interval is set, and outlier detection is performed on the sample data within the sliding window. Sample data identified as outliers are removed, generating a reliable measurement sequence. Only this reliable measurement sequence is used for subsequent frequency adjustment calculations. The reliable measurement sequence is data that has been filtered of noise and carries valid historical state characteristics. The phase normalization logic employs a Σ-Δ phase micro-shift mechanism, specifically including: obtaining the phase error estimate of the current moment from the frequency control closed-loop model output and converting it into a target phase correction amount in clock cycles; using a Σ-Δ modulation algorithm to perform error diffusion processing on the target phase correction amount, converting the non-integer phase correction requirement into a discrete micro-shift decision amount in integer clock cycles; and dynamically adjusting the generation time of the local second pulse using the discrete micro-shift decision amount, ensuring that the average phase of the local second pulse over multiple cycles is aligned with the reference second pulse, and that the average phase error is less than one clock cycle.

2. The method according to claim 1, characterized in that, Using the local high-frequency clock signal output by the local voltage-controlled crystal oscillator, the real-time received reference second pulse is counted and measured, including: maintaining a free-running counter driven by the local high-frequency clock signal; latching the current value of the free-running counter when the rising edge of the reference second pulse is detected to obtain the reference time latch value; latching the current value of the free-running counter when the rising edge of the local second pulse generated by the phase normalization logic is detected to obtain the local time latch value; calculating the difference between the reference time latch value and the local time latch value, and performing a modulo operation based on a preset counting period on the difference to obtain the phase counting deviation sequence.

3. The method according to claim 1, characterized in that, The frequency control closed-loop model also includes an online gain identification unit, whose processing steps include: monitoring the locking state of the frequency control closed-loop model; when it is in a stable locked state, generating a micro-perturbation signal and superimposing it on the frequency adjustment command; estimating the frequency deviation estimate of the local voltage-controlled crystal oscillator under the action of the micro-perturbation signal in real time, and calculating the change in the frequency deviation estimate; updating the control gain coefficient based on the ratio between the micro-perturbation signal and the change in the frequency deviation estimate, whereby the control gain coefficient characterizes the degree of influence of the change unit of the frequency adjustment command on the output frequency.

4. The method according to claim 3, characterized in that, The calculation of the frequency adjustment command for the local voltage-controlled crystal oscillator includes: calculating the target frequency correction amount required to eliminate the current frequency error based on a reliable measurement sequence and using a servo loop filter; mapping the target frequency correction amount to an adaptive step size of the voltage control domain using a control gain coefficient; updating the current frequency adjustment command accordingly; and performing amplitude limiting processing on the updated frequency adjustment command.

5. The method according to claim 1, characterized in that, The frequency control closed-loop model is configured to perform parallel dual-time-scale integral processing, specifically including: based on a short-term forgetting factor, performing an exponentially weighted moving average calculation on the phase count deviation sequence to obtain a short-term weighted integral value, which is used to characterize the transient frequency fluctuation of the local voltage-controlled crystal oscillator; based on a long-term forgetting factor, performing an exponentially weighted moving average calculation on the phase count deviation sequence to obtain a long-term weighted integral value, which is used to characterize the steady-state frequency drift of the local voltage-controlled crystal oscillator; wherein, the value of the long-term forgetting factor is greater than the value of the short-term forgetting factor, so that the memory length of the long-term weighted integral value for historical errors is greater than that of the short-term weighted integral value.

6. The method according to claim 5, characterized in that, The calculation of frequency adjustment commands for the local voltage-controlled crystal oscillator includes: real-time calculation of the error standard deviation of the phase count deviation sequence, setting a dynamic adjustment threshold based on the error standard deviation; calculating the ratio of the short-term weighted integral value to the long-term weighted integral value, and determining that there is an effective frequency drift when the ratio is in a stable range and the absolute value of the long-term weighted integral value is greater than the dynamic adjustment threshold; and calculating a variable-step frequency adjustment command using a piecewise or linear mapping method based on the difference between the long-term weighted integral value and the dynamic adjustment threshold.

7. The method according to claim 1, characterized in that, The frequency control closed-loop model is configured to perform fixed-step cumulative adjustment, which specifically includes: directly accumulating the phase count deviation sequence and maintaining the cumulative count deviation value; comparing the absolute value of the cumulative count deviation value with a fixed threshold; when the absolute value of the cumulative count deviation value exceeds the fixed threshold, generating a frequency adjustment command according to a fixed adjustment step size to correct the output frequency of the local voltage-controlled crystal oscillator in a single direction until the absolute value of the cumulative count deviation value falls back to within the fixed threshold.

8. A satellite timing device, characterized in that, include: A satellite navigation receiver is used to receive satellite signals and output a reference second pulse. A local voltage-controlled crystal oscillator is used to output a local high-frequency clock signal, and its output frequency is controlled by the input voltage control signal. A digital-to-analog converter circuit is connected to the control terminal of a local voltage-controlled crystal oscillator to generate a voltage control signal; a logic processing unit and a memory, the memory storing computer-executed instructions, the logic processing unit executing the computer-executed instructions to implement the method as described in any one of claims 1 to 7.

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