Channel estimation and equalization device and method
By using a channel estimation and equalization device with a parallel processing architecture, the real-time performance and efficiency issues of signal processing in ultra-wideband wireless communication are solved, achieving efficient signal processing on the FPGA platform and improving the system's reliability and data throughput.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-13
AI Technical Summary
In ultra-wideband wireless communication systems, signals in complex wireless channels generate severe inter-symbol interference and frequency-selective fading, making it impossible for FPGAs with traditional serial processing architectures to efficiently and in real-time process ultra-wideband signals.
The channel estimation and equalization device, which adopts a parallel processing architecture, converts the synchronized baseband digital signal into a parallel data stream through a parallel conversion module, performs parallel demodulation, channel estimation and frequency domain equalization, and reduces the system processing clock frequency to within the range that can be achieved by FPGA.
It enables real-time, high-throughput processing of ultra-wideband signals on an FPGA platform, improving the reliability and effectiveness of the communication system.
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Figure CN121664589A_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of wireless communication technology, specifically relating to a channel estimation and equalization device and method. Background Technology
[0002] To meet the extreme demands of future society for wireless data transmission capabilities, 5G-Advanced (5G-A) and 6G communication technologies are evolving towards ultra-wideband, requiring systems to stably process signals with bandwidths exceeding 500MHz or even higher to achieve peak rates at the Tbps level. This marks the beginning of the ultra-wideband era for wireless communication.
[0003] In ultra-wideband wireless communication systems, signals experience severe inter-symbol interference and frequency-selective fading when transmitted through complex wireless channels. To accurately recover the original transmitted information at the receiver, channel estimation and equalization are indispensable key components of the digital receiver's baseband processing, and their performance directly determines the reliability and effectiveness of the entire communication system. Summary of the Invention
[0004] This disclosure provides a channel estimation and equalization apparatus, comprising:
[0005] The data parallel conversion module is configured to perform data parallel conversion on the synchronized baseband digital signal to obtain M parallel data streams, where M is an integer greater than 1, and each data stream includes multiple time-domain OFDM symbol data.
[0006] The orthogonal frequency division multiplexing demodulation module is configured to perform parallel demodulation on the M data streams to obtain M parallel frequency domain OFDM symbol data;
[0007] The data flow control module is configured to separate reference symbol data for channel estimation and effective symbol data to be equalized from the M frequency domain OFDM symbol data;
[0008] The channel estimation module is configured to perform channel estimation based on the reference symbol data, and generate and output channel estimation parameters.
[0009] The equalization module is configured to perform parallel frequency domain equalization on the effective symbol data based on the channel estimation parameters to obtain equalized data.
[0010] In some embodiments, the time-domain OFDM symbol data includes a cyclic prefix portion and an OFDM data portion;
[0011] The orthogonal frequency division multiplexing demodulation module includes:
[0012] The parallel deprecation submodule is configured to remove the cyclic prefix portion from each of the M data streams in parallel.
[0013] The parallel demodulation submodule is configured to perform parallel Fourier transform processing on the M data streams after removing the cyclic prefix portion, to obtain parallel M frequency domain OFDM symbol data.
[0014] In some embodiments, the channel estimation module includes:
[0015] The channel estimation submodule is configured to perform a complex multiplication operation on the received reference symbol data and the complex conjugate of the corresponding points of the local reference sequence to obtain the initial estimation parameters;
[0016] The noise reduction submodule is configured to perform an inverse discrete Fourier transform on the initial estimated parameters to obtain time-domain variation data, and then perform noise reduction processing on the denoised data. After performing a discrete Fourier transform on the denoised data, the channel estimated parameters are obtained.
[0017] In some embodiments, the channel estimation module further includes a buffer submodule, which includes a first buffer unit and a second buffer unit. The first buffer unit and the second buffer unit are configured to use a ping-pong buffering mechanism to buffer the initial channel frequency response data output by the channel estimation submodule and output it to the noise reduction submodule.
[0018] In some embodiments, the channel estimation and equalization apparatus further includes:
[0019] R first cache modules are configured to cache and output the valid symbolic data separated by the data flow control module in parallel.
[0020] The second caching module is configured to cache and output the channel estimation parameters output by the channel estimation module;
[0021] The equalization module is configured to perform frequency domain equalization processing on the R valid symbol data output by the R first buffer modules in parallel, based on the channel estimation parameters output by the second buffer module, where R is a positive integer and 1 < R < M.
[0022] In some embodiments, the second caching module includes a third caching unit and a fourth caching unit, wherein the third caching unit and the fourth caching unit are configured to use a ping-pong caching mechanism to cache and output the channel estimation parameters output by the channel estimation module;
[0023] The equalization module is configured to,
[0024] In the i-th time period, based on the channel estimation parameters of the third buffer unit, frequency domain equalization is performed on the R effective symbol data currently output by the R first buffer modules;
[0025] In the (i+1)th time period, based on the channel estimation parameters of the third buffer unit, frequency domain equalization is performed on a portion of the R valid symbol data currently output by the R first buffer modules; based on the channel estimation parameters of the fourth buffer unit, frequency domain equalization is performed on another portion of the currently output R valid symbol data.
[0026] In the (i+2)th time period, based on the channel estimation parameters of the fourth buffer unit, frequency domain equalization is performed on the R valid symbol data currently output by the first buffer module;
[0027] Where i is a positive integer, and frequency domain equalization of the R effective symbol data is performed in parallel during any given time period.
[0028] In some embodiments, the equalization module is configured to perform frequency domain equalization using a zero-forcing equalization algorithm.
[0029] In some embodiments, the parallel conversion module, the orthogonal frequency division multiplexing demodulation module, the data flow control module, the channel estimation module, and the equalization module are all integrated in FGPA.
[0030] This disclosure also provides a channel estimation and equalization method, including:
[0031] The synchronized baseband digital signal is converted into parallel data to obtain M parallel data streams, where M is an integer greater than 1, and each data stream includes multiple time-domain OFDM symbol data.
[0032] The M data streams are demodulated in parallel to obtain M parallel frequency domain OFDM symbol data;
[0033] From the M-channel frequency domain OFDM symbol data, the reference symbol data for channel estimation and the effective symbol data to be equalized are separated.
[0034] Channel estimation is performed based on the reference symbol data, and channel estimation parameters are generated and output.
[0035] Based on the channel estimation parameters, the effective symbol data is subjected to parallel frequency domain equalization to obtain the equalized data.
[0036] In some embodiments, the time-domain OFDM symbol data includes a cyclic prefix portion and an OFDM data portion;
[0037] The steps for parallel demodulating the M data streams include:
[0038] In parallel, remove the cyclic prefix portion from each of the M data streams;
[0039] The M data streams after removing the cyclic prefix are subjected to parallel Fourier transform processing to obtain parallel M frequency domain OFDM symbol data.
[0040] In some embodiments, the step of performing channel estimation based on the reference symbol data and generating and outputting channel estimation parameters includes:
[0041] The reference symbol data is multiplied by the complex conjugate of the corresponding points in the local reference sequence to obtain the initial channel frequency response data.
[0042] The initial channel frequency response value is subjected to inverse discrete Fourier transform to obtain time-domain variation data, which is then denoised. The denoised data is then subjected to discrete Fourier transform to obtain the channel estimation parameters.
[0043] In some embodiments, before performing the discrete inverse Fourier transform on the initial channel frequency response value, the method further includes: caching the initial estimated parameters using a ping-pong caching mechanism. Attached Figure Description
[0044] Figure 1A This is a schematic diagram of the channel estimation and equalization device provided in the embodiments of this disclosure.
[0045] Figure 1B This is another schematic diagram of the channel estimation and equalization device provided in the embodiments of this disclosure.
[0046] Figure 2 A schematic diagram of the frame structure in the embodiments of this disclosure.
[0047] Figure 3 This is a schematic diagram of parallel data conversion provided in an embodiment of this disclosure.
[0048] Figure 4 This is a schematic diagram of data splitting after demodulation in an embodiment of this disclosure.
[0049] Figure 5 This is a schematic diagram of the channel estimation module provided in an embodiment of this disclosure.
[0050] Figure 6 This is a flowchart of channel estimation provided in an embodiment of this disclosure.
[0051] Figure 7 This is a flowchart of the parallel equalization process provided in the embodiments of this disclosure. Detailed Implementation
[0052] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0053] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this disclosure do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this disclosure are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to such processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” in this disclosure refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can indicate: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," "third," etc., used in this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. "Above," "below," "left," "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.
[0054] In ultra-wideband wireless communication systems, signals experience severe inter-symbol interference and frequency-selective fading when transmitted through complex wireless channels. To accurately recover the original transmitted information at the receiver, channel estimation and equalization are indispensable key components of the digital receiver's baseband processing, and their performance directly determines the reliability and effectiveness of the entire communication system.
[0055] However, real-time processing of ultra-wideband signals faces severe hardware implementation challenges. As the mainstream baseband processing platform, the field-programmable gate array (FPGA) has a reliable operating synchronous timing clock frequency (typically around 200MHz) that is far lower than the sampling rate required for ultra-wideband signals (which can be as high as 1GSPS). This means that FPGAs using traditional serial processing architectures cannot directly achieve efficient, real-time processing of ultra-wideband signals.
[0056] This disclosure provides a channel estimation and equalization device, which is deployed in the signal receiving equipment of a communication system. In addition to the channel estimation and equalization device, the signal receiving equipment may also include a radio frequency processing device, which is configured to receive downlink signals transmitted by a base station and process them to obtain baseband digital signals.
[0057] For example, the radio frequency (RF) processing device may include a receiving antenna, an RF link processing module, and an analog-to-digital (ADC) converter module. The receiving antenna is configured to receive downlink signals transmitted by a base station, which are high-frequency RF signals. The RF link processing module is configured to process the downlink signal, and the processing may include low-noise amplification, filtering, down-mixing, etc., thereby converting the high-frequency RF signal into a lower-frequency, easier-to-process analog signal. The ADC module is configured to perform analog-to-digital conversion on the analog signal to obtain a baseband digital signal.
[0058] Figure 1A This is a schematic diagram of the channel estimation and equalization device provided in the embodiments of this disclosure. Figure 1B This is another schematic diagram of the channel estimation and equalization device provided in the embodiments of this disclosure, as shown below. Figure 1A and Figure 1B As shown, the channel estimation and equalization device includes: a parallel conversion module 10, an orthogonal frequency division multiplexing demodulation module 20, a data flow control module 30, a channel estimation module 40, and an equalization module 50.
[0059] The parallel conversion module 10 is configured to perform parallel data conversion on the synchronized baseband digital signal to obtain M parallel data streams, where M is an integer greater than 1, such as M > 2, M > 3, or M > 4. Each data stream includes multiple time-domain OFDM (Orthogonal Frequency Division Multiplexing) symbol data, and each time-domain OFDM symbol data includes a cyclic prefix (CP) part and an OFDM data part.
[0060] For example, the channel estimation and equalization apparatus may further include a synchronization module configured to receive the digital baseband signal output by the analog-to-digital conversion module, perform synchronization processing on the received digital baseband signal, and output M parallel data streams to the parallel conversion module 10, each data stream being sample data. The parallel conversion module 10 performs parallel conversion on the received signal, that is, converts the synchronized sample parallel data into parallel data in units of OFDM symbols.
[0061] The orthogonal frequency division multiplexing demodulation module 20 is configured to perform parallel demodulation on M data streams to obtain M parallel frequency domain OFDM symbol data.
[0062] The data flow control module 30 is configured to separate reference symbol data for channel estimation and effective symbol data to be equalized from M channels of frequency-domain OFDM symbol data. Specifically, a portion of the M channels of frequency-domain OFDM symbol data serves as reference symbol data, while the remaining portion serves as effective symbol data. The data flow control module 30 can determine the reference symbol data and effective symbol data from the M channels of frequency-domain OFDM symbol data according to a preset communication protocol.
[0063] The channel estimation module 40 is configured to perform channel estimation based on reference symbol data, generate and output channel estimation parameters, which are the channel frequency response.
[0064] The equalization module 50 is configured to perform parallel frequency domain equalization on the effective symbol data based on channel estimation parameters to obtain equalized data. The equalized data can be used for subsequent demodulation and decoding.
[0065] In this embodiment of the disclosure, the parallel conversion module 10, the orthogonal frequency division multiplexing demodulation module 20, the data flow control module 30, the channel estimation module 40, and the equalization module 50 can be integrated into an FPGA.
[0066] In this embodiment of the disclosure, the channel estimation and equalization device converts the synchronized digital baseband signal into M parallel data streams in units of OFDM symbols through the parallel conversion module 10. The subsequent orthogonal frequency division multiplexing demodulation module 20, equalization module 50, etc. are all processed based on the M parallel data streams. Through this parallel processing architecture, the actual processing clock frequency inside the system can be reduced to 1 / M of the original sampling rate (for example, by using a 5-channel parallel approach, the sampling rate of 983.04 MSPS can be reduced to a clock frequency of 196.608 MHz). This adapts the processing requirements of ultra-wideband signals to the clock frequency range of the FPGA, so as to realize real-time, high data throughput processing of ultra-wideband signals on the FPGA platform.
[0067] The channel estimation and equalization apparatus of this disclosure will now be described in conjunction with specific embodiments.
[0068] This embodiment of the disclosure uses a 5G protocol with 240kHz subcarriers and 4096 OFDM points as an example. Its single sampling rate is 983.04MSPS, supporting a theoretical maximum bandwidth of 983.04MHz. However, in actual use, not all 4096 subcarriers are used. This embodiment selects to use 3336 subcarriers, with an effective bandwidth of 3336 * 240kHz = 800.64MHz. The corresponding reference sequence length is also 3336 points. To ensure stable FPGA operation, this embodiment uses a 5x parallelism approach, meaning the FPGA's system processing clock is 196.608MHz. The frame structure in this embodiment is as follows: Figure 2 As shown, each frame is 10ms long; one frame contains 10 time slots, each time slot being 1ms long; each time slot includes 16 sets of time-domain OFDM symbol data, each set of time-domain OFDM symbol data contains 14 time-domain OFDM symbol data, and each time-domain symbol data includes a CP part and an OFDM data part. The length of each set of time-domain OFDM symbol data is 62.5µs, where the 3rd and 10th time-domain OFDM symbol data are reference data, and the remaining OFDM symbol data are valid symbol data. Each OFDM data part contains 4096 points.
[0069] Figure 3 This is a schematic diagram of the parallel data conversion provided in this embodiment of the disclosure. J is the sum of the lengths of the OFDM data portion and the CP portion. In this embodiment, the length of the OFDM data portion is 4096, and the length of the CP portion is 292, so J is 4096 + 292 = 4388 points. The parallel data conversion converts 5 channels of single-point parallel data into 5 channels of 4388-point parallel data. After conversion, each channel of 4388 points is continuous sample data. The input data of the synchronization module is a serial sample input, including sample 1, sample 2, sample 3, and so on. The output data of the synchronization module is parallel multi-channel data. For example, the first channel includes sample 1, sample 6, ..., sample j+1, etc.; the second channel includes sample 2, sample 7, ..., sample j+2, etc.; the third channel includes sample 3, sample 8, ..., sample j+3, etc.; the fourth channel includes sample 4, sample 9, ..., sample j+4, etc.; and the fifth channel includes sample 5, sample 10, ..., sample j+5, etc. After parallel data conversion by the parallel conversion module 10, five data streams are output, each consisting of OFDM symbol data, with each OFDM symbol data including 4388 samples.
[0070] like Figure 1BAs shown, in some embodiments, the orthogonal frequency division multiplexing demodulation module 20 includes a parallel deprecation submodule 21 and a parallel demodulation submodule 22. The parallel deprecation submodule 21 is configured to remove the cyclic prefix portion from each of the M data streams. Taking M=5 as an example, the parallel deprecation submodule 21 removes the cyclic prefix portion from the 5 data streams in parallel.
[0071] The parallel demodulation submodule 22 is configured to perform Fourier transform (FFT) processing on the M data streams in parallel to obtain M parallel frequency domain OFDM symbol data.
[0072] In some embodiments, such as Figure 1B As shown, the channel estimation and equalization device further includes: R first buffer modules 70 and a second buffer module 60. The R first buffer modules 70 are configured to perform parallel buffering and parallel output of the valid symbol data separated by the data flow control module 30. The first buffer modules 70 can be RAM (random access memory). The second buffer module 60 is configured to buffer the channel estimation parameters output by the channel estimation module 40. R is a positive integer, 1 < R < M.
[0073] Specifically, the data flow control module 30 splits the demodulated M-channel frequency domain OFDM symbol data, transmitting the reference symbol data to the channel estimation module 40 and the valid symbol data to R parallel first buffer modules 70. After determining the channel estimation parameters, the channel estimation module 40 transmits these parameters to the second buffer module 60 for buffering. For example, M is 5 and R is 4.
[0074] Figure 4 This is a schematic diagram of data splitting after demodulation in an embodiment of this disclosure, as shown below. Figure 4 As shown, taking the above frame structure as an example, the 16 time-domain OFDM symbols in the same group are transmitted in 5 channels. After demodulation, the resulting 16 frequency-domain OFDM symbols are also transmitted in 5 channels. In one group, the 1st, 6th, and 11th frequency-domain OFDM symbols are located in channel 1; the 2nd, 7th, and 12th frequency-domain OFDM symbols are located in channel 2; the 3rd, 8th, and 12th frequency-domain OFDM symbols are located in channel 3; the 4th, 9th, and 14th frequency-domain OFDM symbols are located in channel 4; and the 5th, 10th, and the 1st frequency-domain OFDM symbols of the next group are located in channel 4. Among them, the 3rd and 10th frequency-domain OFDM symbols in the same group are reference symbols and are transmitted to the channel estimation module 40; the remaining frequency-domain OFDM symbols are transmitted to the four first buffer modules 70 respectively.
[0075] Figure 5This is a schematic diagram of the channel estimation module 40 provided in an embodiment of this disclosure. Figure 6 This is a flowchart of channel estimation provided in an embodiment of the present disclosure. The channel estimation module 40 in this embodiment employs an improved channel estimation algorithm based on LS (Least Squares) and DFT (Fourier Transform), thereby achieving lower complexity and better estimation performance. Figure 5 and Figure 6 As shown, the channel estimation module 40 includes: a channel estimation submodule 41, a buffering submodule 42, and a noise reduction submodule 43.
[0076] The channel estimation submodule 41 is configured to perform LS channel estimation. Specifically, the channel estimation submodule 41 is configured to perform complex multiplication on the complex conjugate of the corresponding points of the received reference symbol data and the local reference sequence to obtain LS estimation parameters, which are denoted as initial estimation parameters, i.e., initial channel frequency response.
[0077]
[0078] Where X is the local reference sequence, Y is the corresponding received reference symbol data, and k represents the subcarrier sequence number. The initial estimation parameters are a vector containing the channel responses of all subcarriers. The local reference sequence uses the ZC sequence as the reference sequence for channel estimation. Its sequence... The generation method is as follows:
[0079]
[0080] Where n is the sequence element index, taking the value from 0 to Mzc-1. Mzc is the actual length of the generated local reference sequence, and m is the index variable of the ZC sequence, taking the value from 0 to N. ZC -1. It is to satisfy The largest prime number, in practical implementation, is... To calculate the sequence, that is, when generating local sequences in real time, The value of is the length of the sequence, which is 3336 in this embodiment. According to the characteristics of the ZC sequence, the inverse of X is the complex conjugate of X. Therefore, in the actual implementation of LS channel estimation, it is obtained by performing complex multiplication between the received reference symbol data and the complex conjugate of the corresponding point in the local reference sequence.
[0081] The caching submodule 42 is configured to cache the initial estimation parameters output by the channel estimation submodule 41.
[0082] As illustrated in the example above, the Orthogonal Frequency Division Multiplexing (OFDM) demodulation module 20 outputs five parallel data streams. The 3rd and 10th OFDM symbol data (i.e., reference symbol data) in the same group are serially input to the channel estimation module 40. This results in a situation where, when a new LS estimation parameter arrives, the previous LS estimation parameter has not yet been input to the noise reduction submodule 43. Therefore, to avoid data conflicts, in this embodiment, the buffer submodule 42 uses a ping-pong method to buffer the LS estimation parameters. That is, the buffer submodule 42 includes a first buffer unit and a second buffer unit, both configured to alternately buffer the initial channel frequency response data output by the channel estimation submodule 41 using a ping-pong buffering mechanism. For example, both the first and second buffer units are 4096-bit RAM blocks. The ping-pong buffering mechanism means that the two buffer units work alternately; while one buffer unit receives and buffers data, the other buffer unit outputs data.
[0083] The noise reduction submodule 43 is configured to perform an inverse discrete Fourier transform (IDFT) on the initial estimated parameters output by the buffer submodule 42 to obtain time-domain variation data, and then perform noise reduction on the data. After performing an inverse discrete Fourier transform on the noise-reduced data, the channel estimation parameters are obtained.
[0084] The denoising submodule 43 is an estimation algorithm based on Discrete Fourier Transform (IDFT). Building upon the LS estimation algorithm, it modifies the LS estimation parameters. This technique improves estimation accuracy by reducing noise beyond the maximum multipath delay. The principle involves first performing an Inverse Discrete Fourier Transform (IDFT) on the LS estimation parameters obtained from the LS channel estimation, then performing appropriate linear or nonlinear processing in the time domain to denoise the channel's impulse response, and finally restoring the denoised impulse response to the frequency domain using another IFT to obtain the denoised channel estimation parameters. The specific implementation process of the denoising submodule 43 is as follows:
[0085] The first step is to perform an inverse discrete Fourier transform on the sequence obtained after LS channel estimation to obtain the time-domain reference sequence. :
[0086] ;
[0087] Where Hls1 represents the initial estimated parameters, k is the subcarrier index, and Hls1(k) is the channel response value in Hls1 corresponding to the k-th subcarrier. N is the number of points in the inverse discrete Fourier transform, which is the length of the local reference sequence. In this embodiment, N is 3336.
[0088] The second step is noise reduction. Points with higher energy at both ends of the time axis of the time-domain reference sequence are retained, while the rest are treated as noise and filtered out. It can be expressed as follows:
[0089]
[0090] After noise filtering:
[0091]
[0092] in, The length of the cyclic prefix is 292 in this embodiment. In specific implementation, the length of CP is used as the standard. Points 1 to CP / 4 and 3336-CP / 4+1 to 3336 in the time-domain reference sequence are selected as useful data, and all other points are assigned a value of 0, resulting in the denoised data. That is, in this embodiment, points 1 to 73 and 3274 to 3336 are retained, and the values at other positions are assigned a value of 0.
[0093] The third step is to perform a Distributed Fourier Transform (DFT) on the denoised data to obtain the channel frequency response. :
[0094]
[0095] The 3336 points corresponding to the DFT transformation in this embodiment are the frequency domain channel estimation parameters after the LS-DFT channel estimation algorithm.
[0096] In some embodiments, the second buffer module 60 is configured to buffer the channel estimation parameters output by the channel estimation module 40. As in the example given above, the orthogonal frequency division multiplexing demodulation module 20 outputs five parallel data streams. The third and tenth frequency domain OFDM symbol data (i.e., reference symbol data) in the same group are serially input to the channel estimation module 40. Correspondingly, the channel estimation parameters obtained after channel estimation are also continuously output. To avoid data conflicts, in this embodiment, the second buffer module 60 includes a third buffer unit and a fourth buffer unit. The third and fourth buffer units are configured to use a ping-pong buffering mechanism to buffer and output the channel estimation parameters output by the channel estimation module 40.
[0097] In some embodiments, the equalization module 50 is configured to perform R-path parallel frequency domain equalization processing on the effective symbol data in the first buffer module 70 based on the channel estimation parameters in the second buffer module 60. The equalization module 50 is used to compensate for the linear distortion caused by channel frequency selectivity and to reduce multipath interference in the system. The equalization method is divided into two processing modes: time-domain equalization and frequency-domain equalization. In this embodiment, the data demodulated by the orthogonal frequency division multiplexing demodulation module 20 is frequency-domain data, therefore frequency-domain equalization is more suitable.
[0098] Figure 7The flowchart of the parallel equalization process provided in the embodiments of this disclosure is as follows: Figure 7 As shown, in each time period, R first buffer modules 70 output R valid symbol data in parallel. The equalization module 50 is configured to: in the i-th time period, perform frequency domain equalization on the R valid symbol data currently output by the R first buffer modules 70 based on the channel estimation parameters of the third buffer unit; in the (i+1)-th time period, perform frequency domain equalization on a portion of the R valid symbol data currently output by the R first buffer modules 70 based on the channel estimation parameters of the third buffer unit; and perform frequency domain equalization on another portion of the currently output R valid symbol data based on the channel estimation parameters of the fourth buffer unit; in the (i+2)-th time period, perform frequency domain equalization on the R valid symbol data currently output by the first buffer module 70 based on the channel estimation parameters of the fourth buffer unit. Here, i is a positive integer, and the frequency domain equalization of the R valid symbol data is performed in parallel within any given time period.
[0099] The system completes multi-channel data equalization over three consecutive time periods, and processes four data streams in parallel within each time period. The four parallel output data streams are the data obtained after channel estimation and equalization, which can be used for subsequent demodulation and decoding operations.
[0100] One time period refers to the stage of balancing the R valid symbol data in parallel.
[0101] In some embodiments, the equalization module 50 is configured to perform frequency domain equalization using a zero-forcing (ZF) equalization algorithm. Zero-forcing equalization is derived from the peak distortion criterion. According to the peak distortion criterion, the overall response of the equalization module 50 and the channel is 1, i.e., the transfer function of the equalization module 50... It is the channel filter transfer function The reciprocal of . This theory applies to each subcarrier when processing OFDM signals in the digital domain. For the k-th subcarrier, the equalization coefficient W k Channel estimation parameters The reciprocal of, that is, N is the sequence length; in the example disclosed herein, N is 3336. The channel estimation module 40 described above provides the result. The equalization operation is performed in the frequency domain, i.e., the received valid symbol data S... k With the equilibrium coefficient W k Perform complex number multiplication:
[0102]
[0103] Among them, Y k This is the balanced data.
[0104] Based on the same inventive concept, this disclosure also provides a channel estimation and equalization method, which is executed by the aforementioned channel estimation and equalization device, and includes:
[0105] S1. Perform parallel data conversion on the synchronized baseband digital signal to obtain M parallel data streams, where M is an integer greater than 1, and each data stream includes multiple time-domain OFDM symbol data.
[0106] S2. Perform parallel demodulation on the M data streams to obtain parallel M frequency domain OFDM symbol data.
[0107] S3. From the M-channel frequency domain OFDM symbol data, separate the reference symbol data for channel estimation and the effective symbol data to be equalized.
[0108] S4. Based on the reference symbol data, perform channel estimation, generate and output channel estimation parameters.
[0109] S5. Based on the channel estimation parameters, perform parallel frequency domain equalization on the effective symbol data to obtain the equalized data.
[0110] In some embodiments, the time-domain OFDM symbol data includes a cyclic prefix portion and an OFDM data portion; step S2 includes:
[0111] S21. Remove the cyclic prefix portion from each of the M data streams in parallel.
[0112] S22. Perform parallel Fourier transform processing on the M data streams after removing the cyclic prefix to obtain parallel M frequency domain OFDM symbol data.
[0113] In some embodiments, step S4 includes:
[0114] S41. Perform complex multiplication on the reference symbol data and the complex conjugate of corresponding points in the local reference sequence to obtain the initial estimated parameters.
[0115] S42. The initial estimated parameters are cached using a ping-pong caching mechanism.
[0116] S43. Perform an inverse discrete Fourier transform on the initial estimated parameters to obtain time-domain variation data, and then perform noise reduction processing on the data. After performing a discrete Fourier transform on the noise-reduced data, the channel estimation parameters are obtained. For the specific execution process of step S4, please refer to the description of the channel estimation and equalization device above.
[0117] In some embodiments, the signal estimation and equalization method further includes: after separating the reference symbol data for channel estimation and the effective symbol data to be equalized, transmitting the effective symbol data in parallel to R first buffer modules for buffering. After obtaining the channel estimation parameters, transmitting the channel estimation parameters to a second buffer module for buffering. During frequency domain equalization, based on the channel estimation parameters output by the second buffer module, performing frequency domain equalization processing in parallel on the R effective symbol data output by the R first buffer modules, where R is a positive integer, 1 < R < M. The second buffer module includes a third buffer unit and a fourth buffer unit, which employ a ping-pong buffering mechanism to buffer and output the channel estimation parameters. The specific execution process of step S5 can be found in the above description of the channel estimation and equalization device, and will not be repeated here.
[0118] This disclosure also provides a signal receiving device, which includes a radio frequency (RF) processing unit and the aforementioned channel estimation and equalization unit. The RF processing unit is configured to receive downlink signals transmitted by a base station and process them to obtain baseband digital signals. The RF processing unit may include a receiving antenna, an RF link processing module, and an analog-to-digital conversion module, as described above, and will not be repeated here.
[0119] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.
Claims
1. A channel estimation and equalization device, characterized in that, include: The data parallel conversion module is configured to perform data parallel conversion on the synchronized baseband digital signal to obtain M parallel data streams, where M is an integer greater than 1, and each data stream includes multiple time-domain OFDM symbol data. The orthogonal frequency division multiplexing demodulation module is configured to perform parallel demodulation on the M data streams to obtain M parallel frequency domain OFDM symbol data; The data flow control module is configured to separate reference symbol data for channel estimation and effective symbol data to be equalized from the M frequency domain OFDM symbol data; The channel estimation module is configured to perform channel estimation based on the reference symbol data, and generate and output channel estimation parameters. The equalization module is configured to perform parallel frequency domain equalization on the effective symbol data based on the channel estimation parameters to obtain equalized data.
2. The channel estimation and equalization apparatus according to claim 1, characterized in that, The time-domain OFDM symbol data includes a cyclic prefix portion and an OFDM data portion; The orthogonal frequency division multiplexing demodulation module includes: The parallel deprecation submodule is configured to remove the cyclic prefix portion from each of the M data streams in parallel. The parallel demodulation submodule is configured to perform parallel Fourier transform processing on the M data streams after removing the cyclic prefix portion, to obtain parallel M frequency domain OFDM symbol data.
3. The channel estimation and equalization apparatus according to claim 1, characterized in that, The channel estimation module includes: The channel estimation submodule is configured to perform a complex multiplication operation on the received reference symbol data and the complex conjugate of the corresponding points of the local reference sequence to obtain the initial estimation parameters; The noise reduction submodule is configured to perform an inverse discrete Fourier transform on the initial estimated parameters to obtain time-domain variation data, and then perform noise reduction processing on the denoised data. After performing a discrete Fourier transform on the denoised data, the channel estimated parameters are obtained.
4. The channel estimation and equalization apparatus according to claim 3, characterized in that, The channel estimation module further includes a caching submodule, which includes a first caching unit and a second caching unit. The first caching unit and the second caching unit are configured to use a ping-pong caching mechanism to cache the initial channel frequency response data output by the channel estimation submodule and output it to the noise reduction submodule.
5. The channel estimation and equalization apparatus according to claim 1, characterized in that, The channel estimation and equalization device further includes: R first cache modules are configured to cache and output the valid symbolic data separated by the data flow control module in parallel. The second caching module is configured to cache and output the channel estimation parameters output by the channel estimation module; The equalization module is configured to perform frequency domain equalization processing on the R valid symbol data output by the R first buffer modules in parallel, based on the channel estimation parameters output by the second buffer module, where R is a positive integer and 1 < R < M.
6. The channel estimation and equalization apparatus according to claim 5, characterized in that, The second caching module includes a third caching unit and a fourth caching unit, wherein the third caching unit and the fourth caching unit are configured to use a ping-pong caching mechanism to cache and output the channel estimation parameters output by the channel estimation module; The equalization module is configured to, In the i-th time period, based on the channel estimation parameters of the third buffer unit, frequency domain equalization is performed on the R effective symbol data currently output by the R first buffer modules; In the (i+1)th time period, based on the channel estimation parameters of the third buffer unit, frequency domain equalization is performed on a portion of the R valid symbol data currently output by the R first buffer modules; based on the channel estimation parameters of the fourth buffer unit, frequency domain equalization is performed on another portion of the currently output R valid symbol data. In the (i+2)th time period, based on the channel estimation parameters of the fourth buffer unit, frequency domain equalization is performed on the R valid symbol data currently output by the first buffer module; Where i is a positive integer, and frequency domain equalization of the R effective symbol data is performed in parallel during any given time period.
7. The channel estimation and equalization apparatus according to claim 5 or 6, characterized in that, The equalization module is configured to perform frequency domain equalization using a zero-forcing equalization algorithm.
8. The channel estimation and equalization apparatus according to any one of claims 1 to 6, characterized in that, The parallel conversion module, the orthogonal frequency division multiplexing demodulation module, the data flow control module, the channel estimation module, and the equalization module are all integrated in FGPA.
9. A channel estimation and equalization method, characterized in that, include: The synchronized baseband digital signal is converted into parallel data to obtain M parallel data streams, where M is an integer greater than 1, and each data stream includes multiple time-domain OFDM symbol data. The M data streams are demodulated in parallel to obtain M parallel frequency domain OFDM symbol data; From the M-channel frequency domain OFDM symbol data, the reference symbol data for channel estimation and the effective symbol data to be equalized are separated. Channel estimation is performed based on the reference symbol data, and channel estimation parameters are generated and output. Based on the channel estimation parameters, the effective symbol data is subjected to parallel frequency domain equalization to obtain the equalized data.
10. The channel estimation and equalization method according to claim 9, characterized in that, The time-domain OFDM symbol data includes a cyclic prefix portion and an OFDM data portion; The steps for parallel demodulating the M data streams include: In parallel, remove the cyclic prefix portion from each of the M data streams; The M data streams after removing the cyclic prefix are subjected to parallel Fourier transform processing to obtain parallel M frequency domain OFDM symbol data.
11. The channel estimation and equalization method according to claim 9, characterized in that, The steps of performing channel estimation based on the reference symbol data and generating and outputting channel estimation parameters include: The reference symbol data is multiplied by the complex conjugate of the corresponding points in the local reference sequence to obtain the initial channel frequency response data. The initial channel frequency response value is subjected to inverse discrete Fourier transform to obtain time-domain variation data, which is then denoised. The denoised data is then subjected to discrete Fourier transform to obtain the channel estimation parameters.
12. The channel estimation and equalization method according to claim 11, characterized in that, Before the step of performing an inverse discrete Fourier transform on the initial channel frequency response value, the method further includes: The initial estimated parameters are cached using a ping-pong caching mechanism.