PAM4 signal equalizer based on automatic gain control

Abstract

The invention provides a PAM4 signal equalizer based on automatic gain control, which comprises a continuous time linear equalizer CTLE, a variable gain amplifier VGA, a negative capacitor I, a negative capacitor II, a power detector, an encoder, an eye diagram parameter calculation module, a digital time converter, a pipelined analog-to-digital converter and a counter, the first input end of the continuous time linear equalizer CTLE is connected to an input signal DIN, the second input end VCTLE1 of the continuous time linear equalizer CTLE is connected to the first output end of the encoder, the third input end VCTLE2 of the continuous time linear equalizer CTLE is connected to the second output end of the encoder, and the output end N1 of the continuous time linear equalizer CTLE is connected to the input end of the first negative capacitor and the first input end of the VGA. According to the invention, optimization and real-time adaptive adjustment for PAM4 characteristics can be realized, the adaptability and the anti-noise capability can be improved, and the signal recovery capability and the signal integrity can be improved.

Description

Technical Field

[0001] This invention relates to a PAM4 signal equalizer based on automatic gain control, belonging to the field of signal equalizers. Background Technology

[0002] The equalizer is a crucial module in the high-speed serializer / deserializer (SerDes) link, used to compensate for inter-symbol interference (ISI) during channel transmission and improve signal integrity at the receiver. With the continuous increase in data rates, modulation schemes have evolved from traditional non-return-to-zero (NRZ) codes to four-level pulse amplitude modulation (PAM4). In this context, the receiver equalizer not only needs to compensate for signal attenuation caused by high-speed transmission but also needs to address crosstalk and noise accumulation between multi-level signals.

[0003] In existing technologies, common equalizer structures include continuous-time linear equalizers (CTLE), decision feedback equalizers (DFE), and feedforward equalizers (FFE), often combined with adaptive methods to adjust equalization parameters. Traditional adaptive methods are primarily designed for NRZ signals. For example, they judge the equalization effect by monitoring the power of the equalized signal, use the slope at the zero-crossing point as an adjustment basis, or correct the equalization parameters by comparing the decision result with the original signal. In NRZ scenarios, these methods can improve the received signal quality to some extent, but they all have significant shortcomings in PAM4 signals. On the one hand, the level spacing in PAM4 is small, and power detection methods are easily affected by noise amplification, leading to unstable convergence. On the other hand, PAM4 signals contain multiple decision boundaries, and slope detection and decision guidance methods lack accuracy under multi-level conditions, easily causing a decrease in equalization effect or even erroneous convergence.

[0004] Therefore, as high-speed interconnects place higher demands on bandwidth, power consumption, and reliability, existing equalization technologies have revealed problems such as insufficient dynamic range, poor adaptability, and weak noise immunity when processing PAM4 signals, making it difficult to meet the needs of next-generation multi-level high-speed links. Summary of the Invention

[0005] The purpose of this invention is to provide a PAM4 signal equalizer based on automatic gain control to solve the problems of poor adaptability, weak noise immunity, and the need to improve signal recovery and signal integrity in the prior art.

[0006] The technical solution of this invention is: A PAM4 signal equalizer based on automatic gain control includes a continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), a negative capacitor (first), a negative capacitor (second), a power detector, an encoder, an eye diagram parameter calculation module, a digital-to-time converter, a pipelined analog-to-digital converter, and a counter. The first input of the continuous-time linear equalizer CTLE is connected to the input signal, namely the PAM4 pseudo-random code D. IN Its second input terminal V CTLE1 Connected to the first output terminal of the encoder, its third input terminal V CTLE2 The second output terminal of the encoder is connected to the input terminal of the negative capacitor and the first input terminal of the variable gain amplifier VGA. The second input terminal V of the variable gain amplifier VGA VGA The output of the variable gain amplifier VGA, connected to the third output terminal of the encoder, is connected to the input terminal of the negative capacitor II and the output signal D, respectively. OUT ; Output terminal C of the power detector W Connect to the first input terminal of the encoder; The encoder's second input terminal EH is connected to the first output terminal of the eye diagram parameter calculation module, and the encoder's third input terminal ET is connected to the second output terminal of the eye diagram parameter calculation module. The encoder's third output terminal V... VGA Connect to the second input terminal of the variable gain amplifier VGA; The first input terminal V of the eye diagram parameter calculation module SAMP Connected to the first output of the pipelined analog-to-digital converter, and the second input C of the eye diagram parameter calculation module. N <0:2> is connected to the second output terminal of the pipelined analog-to-digital converter, the third input terminal CNT of the eye diagram parameter calculation module is connected to the output terminal of the counter, and the third output terminal RST of the eye diagram parameter calculation module is connected to the second input terminal of the counter. The output of the digital time converter is connected to the first input of the pipelined analog-to-digital converter (SAMP) to provide the low-frequency clock required for sampling by the pipelined analog-to-digital converter. The second input terminal of the pipelined analog-to-digital converter is connected to the output signal D. OUT The second output of the pipelined analog-to-digital converter is connected to the first input of the counter.

[0007] Furthermore, the eye diagram parameter calculation module includes an analog multiplier, a bubble sorting module, an eye thickness averaging module, a subtractor, and a digital control module. The bubble sorting module receives the sampled voltage from the first input terminal of the eye diagram parameter calculation module and the control code from the second input terminal CN<0:2> of the eye diagram parameter calculation module. After performing bubble sorting on the sampled voltage at each eye diagram level, the bubble sorting module obtains the eight characteristic levels V corresponding to the eye diagram. 11max V 11min V 10max V 10min V 01max V01min V 00max and V 00min The bubble sorting module outputs the characteristic level V respectively. 01min and V 00max The characteristic level V of the output of the subtractor is given. 10min and V 01max The characteristic level V of the output of the subtractor is given. 11min and V 10max The characteristic level V of the output of the subtractor is given. 11max and V 11min The characteristic level V of the output of the subtractor is given below. 10max and V 10min The characteristic level V of the output of the subtractor is given below. 01max and V 01min The characteristic level V of the output of the subtractor is given. 00max and V 00min Subtractors 7, 1, 2, and 3 calculate three eye height values ​​EH1, EH2, and EH3 respectively and output them to the analog multiplier. The analog multiplier multiplies the three eye height values ​​EH1, EH2, and EH3 and outputs the result as the first output terminal EH of the eye diagram parameter calculation module. Subtractors 4, 5, 6, and 7 output four eye thickness values ​​ET1, ET2, ET3, and ET4 respectively and output them to the eye thickness averaging module. The eye thickness averaging module averages the four eye thickness values ​​ET1, ET2, ET3, and ET4 and outputs the result as the second output terminal ET of the eye diagram parameter calculation module. The digital control module receives the counting signal input from the third input terminal CNT of the eye diagram parameter calculation module. When the counting signal equals the set value, it outputs a reset signal as the third output terminal RST of the eye diagram parameter calculation module.

[0008] Furthermore, the bubble sort module includes a demultiplexer DEMUX and four bubble sort units. The first input of the demultiplexer DEMUX is connected to the first input V of the eye diagram parameter calculation module. SAMP The second input of the demultiplexer DEMUX is connected to the second input C of the eye diagram parameter calculation module. N <0:2>, the first output terminal V11, the second output terminal V10, the third output terminal V01, and the fourth output terminal V00 of the demultiplexer DEMUX are respectively connected to the input terminals of the four bubble sorting units. The first bubble sorting unit outputs the characteristic level V. 11max V 11min The second bubble sorting unit outputs the characteristic level V. 10max V 10min The third bubble sorting unit outputs the characteristic level V. 01max V 01min The fourth bubble sorting unit outputs the characteristic level V. 00max and V00min .

[0009] Furthermore, the bubble sorting unit includes operational amplifiers A1, A2, A3, and A4, switches S1 and S2, capacitor C1, and capacitor C2. The input terminals of the bubble sorting unit are connected to the non-inverting input terminal of operational amplifier A1 and one end of switch S1, respectively. The other end of switch S1 is grounded through capacitor C1, and the other end of switch S1 is connected to the inverting input terminal of operational amplifier A1 and the non-inverting input terminal of operational amplifier A3, respectively. The output terminal of operational amplifier A1 is connected to the control terminal of switch S1, and the inverting input terminal of operational amplifier A3 is connected to the output terminal of operational amplifier A3. The output terminal of operational amplifier A3 serves as the first output terminal of the bubble sorting unit. The input terminals of the bubble sorting unit are connected to the inverting input terminal of operational amplifier A2 and one end of switch S2, respectively. The other end of switch S2 is grounded through capacitor C2, and the other end of switch S2 is connected to the non-inverting input terminal of operational amplifier A2 and the non-inverting input terminal of operational amplifier A4, respectively. The output terminal of operational amplifier A2 is connected to the control terminal of switch S2, and the inverting input terminal of operational amplifier A4 is connected to the output terminal of operational amplifier A4. The output terminal of operational amplifier A4 serves as the second output terminal of the bubble sorting unit.

[0010] Furthermore, in the bubble sorting module, the demultiplexer DEMUX receives the sampled voltage and allocates it to the corresponding bubble sorting unit according to the control code. The two capacitors C1 and C2 in the bubble sorting unit are used to store the maximum and minimum values ​​of the sampled voltage, respectively. If the sampled voltage is greater than the value stored in capacitor C1, the operational amplifier A1 controls the switch S1 to turn on, and the value stored in capacitor C1 is updated to the current maximum value. If the sampled voltage is not greater than the value stored in capacitor C1, the switch S1 is turned off, and capacitor C1 retains the currently stored value. Similarly, if the sampled voltage is less than the value stored in capacitor C2, the operational amplifier A2 controls the switch S2 to turn on, and the value stored in capacitor C2 is updated to the current minimum value. If the sampled voltage is not less than the value stored in capacitor C2, the switch S2 is turned off, and capacitor C2 retains the currently stored value.

[0011] Furthermore, the continuous-time linear equalizer CTLE includes NMOS transistors M1, M2, and M3, and resistor R. D1 Resistance R D2 Resistance R S Resistance R F1 Resistance R F2 Inductor L D1 Inductor L D2 Inductor L F1 Inductor L F2 Variable capacitor CS Switch S1, switch S2, current source I1, current source I2, and first transimpedance amplifier TIA1, Differential input voltage V in The gates of NMOS transistors M1 and M2 are connected to each other, serving as the first input terminal of the continuous-time linear equalizer CTLE. The drain of NMOS transistor M1 is connected to a resistor R. D1 and inductor L D1 Connect to power supply V DD And the drain of NMOS transistor M1 is connected to inductor L F2 and resistance R F2 Connected to the second output terminal of the first transimpedance amplifier TIA1, switch S2 and inductor L F2 In parallel connection, the drain of NMOS transistor M1 is connected to the second input terminal of the first transimpedance amplifier TIA1; The drain of NMOS transistor M2 is connected to resistor R. D2 and inductor L D2 Connect to power supply V DD And the drain of NMOS transistor M2 is connected to inductor L F1 and resistance R F1 The switch S1 and inductor L are connected to the first output terminal of the first transimpedance amplifier TIA1. F1 The NMOS transistor M2 is connected in parallel, and its drain is connected to the first input terminal of the first transimpedance amplifier TIA1. The first and second output terminals of the first transimpedance amplifier TIA1 are connected to the differential output voltage V. OUT And serve as the output terminal N1 of CTLE; The source of NMOS transistor M1 is grounded through current source I1 and through resistor R. S Connect the source of NMOS transistor M2, connect the drain of MOS transistor M3, and connect through a variable capacitor C. S The source of NMOS transistor M2 is connected, the source of MOS transistor M3 is connected to the source of NMOS transistor M2, and the gate of MOS transistor M3 is connected to the second input terminal V of the continuous-time linear equalizer CTLE. CTLE1 The source of NMOS transistor M2 is grounded through current source I2, and the variable capacitor C... S The control terminal is connected to the third input terminal V of the continuous-time linear equalizer CTLE. CTLE2 .

[0012] Furthermore, the variable gain amplifier VGA includes an NMOS transistor M. 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14Resistors R1, R2, R3, R4, and R5; inductors L1 and L2; capacitor C3; current source I3; current source I4; and the second transimpedance amplifier TIA2. The differential input voltage Vin` is connected to the NMOS transistor M. 11 The gate of the NMOS transistor M 12 The gate of the NMOS transistor M serves as the first input terminal of the variable gain amplifier VGA. 11 The drain of the circuit is connected to the power supply V through resistor R1 and inductor L1. DD And NMOS transistor M 11 The drain of the transistor is connected to the second input terminal of the second transimpedance amplifier TIA2, and through resistor R4 to the second output terminal of the second transimpedance amplifier TIA2, and connected to the NMOS transistor M. 14 The drain of the NMOS transistor M 14 The source of the transistor is connected to the second output terminal of the second transimpedance amplifier TIA2, and the NMOS transistor M... 14 The gate is connected to the second input terminal V of the variable gain amplifier VGA. VGA ; NMOS transistor M 12 The drain of the circuit is connected to the power supply V through resistor R2 and inductor L2. DD And NMOS transistor M 12 The drain of the first terminal is connected to the first input terminal of the second transimpedance amplifier TIA2, and is connected to the first output terminal of the second transimpedance amplifier TIA2 through resistor R3, and is connected to the NMOS transistor M. 13 The drain of the NMOS transistor M 13 The source of the transistor is connected to the first output terminal of the second transimpedance amplifier TIA2, and the NMOS transistor M... 13 The gate is connected to the second input terminal V of the variable gain amplifier VGA. VGA ; Differential output voltage V OUT `Connect to the first output terminal and the second output terminal of the second transimpedance amplifier TIA2, as the output terminal of the variable gain amplifier VGA; NMOS transistor M 11 The source terminals are connected to the NMOS transistor M through resistor R5. 12 The source of the NMOS transistor is connected to capacitor C3. 12 The source of the NMOS transistor is grounded through current source I3. 12 The source of is grounded through current source I4.

[0013] Furthermore, the encoder uses a performance maximization function to sequentially determine and optimize power consumption, eye height, and eye thickness, specifically as follows: 1) Set the initial control code EQ coef(1) Assign the equalizer control code EQ coef EQ coef =EQ coef (1); 2) Receive the output power P sent by the power detector, where the output power P is the sum of the output power Pc of the continuous-time linear equalizer CTLE and the output power Pv of the variable gain amplifier VGA. If the output power P exceeds the preset threshold Pset, then the current iteration number i = i + 1, proceed to the next iteration, and return to repeat step 2); otherwise, calculate the eye height index FOM1 = (EH1 − EH) set )(EH2−EH set )(EH3−EH set ), where EHset is the target eye height; 3) When the eye height index FOM1 < 0, the current iteration number i = i + 1, continue to the next iteration, and return to step 2); when the eye height index FOM1 ≥ 0, further calculate the eye thickness deviation FOM2 = −(ET − ET). set ), where ETset is used to set the target eye thickness, and then proceed to step 4); 4) Calculate the final comprehensive index FOM = FOM1 × FOM2, and the control code EQ under the current iteration number i is greater than 1 and the current iteration order i. coef If the quality factor FOM(i) corresponding to (i) is greater than the quality factor FOM(i-1) of the previous iteration, then the equalizer control code EQ will be changed. coef Update, i.e., EQ coef =EQ coef (i), and proceed to step 5); 5) Determine if the current iteration order is greater than the set maximum iteration order i. max If the maximum iteration order is not reached, repeat step 2; otherwise, terminate.

[0014] Furthermore, the implementation process of this PAM4 signal equalizer based on automatic gain control is as follows: The continuous-time linear equalizer CTLE receives an externally input PAM4 pseudo-random code D. IN The signal is then equalized and output to the variable gain amplifier (VGA); the VGA adjusts the low-frequency gain and scales the swing; the pipelined analog-to-digital converter subsamples the output signal of the VGA and outputs the sampled voltage and control code to the eye diagram parameter calculation module, and outputs the control code counter. The digital time converter provides the low-frequency clock required for sampling by the pipelined analog-to-digital converter; the counter counts the number of current sampling cycles and sends the count result to the digital control module inside the eye diagram parameter calculation module; if the current sampling set cycle has been counted, the counter is reset; the eye diagram parameter counting module performs bubble sorting operation on different sampling voltages according to the control code and analyzes and extracts eye height data and eye thickness data. The power detector acquires the output power Pc of the continuous-time linear equalizer (CTLE) and the output power Pv of the variable gain amplifier (VGA), sums them to obtain the output power P, and sends it to the encoder. The encoder generates a feedback control voltage V for adjusting the gain of the CTLE based on eye height data, eye thickness data (ET), and the current system power. CTLE1 Feedback control voltage V CTLE2 It generates a feedback control voltage V for adjusting the gain of the variable gain amplifier VGA. VGA .

[0015] The beneficial effects of this invention are: I. This PAM4 signal equalizer based on automatic gain control can achieve optimization and real-time adaptive adjustment for PAM4 characteristics, improving adaptability and noise immunity, and enhancing signal recovery and integrity. This invention combines a CTLE, a cascaded variable gain amplifier (VGA) structure, and a negative capacitor compensation design, which not only offsets the influence of load capacitance to a certain extent but also enhances the transmission capability of high-frequency components, significantly improves eye diagram opening, and reduces inter-symbol interference. The introduction of a power detector enables the system to have self-monitoring and protection functions, automatically adjusting the equalizer gain to avoid overload risks when power exceeds limits. This invention has good scalability and portability, and can be widely applied to various high-speed interface scenarios such as serializers (SerDes), optical interconnects, and on-chip interconnects, possessing outstanding engineering application value and promising industrial application prospects.

[0016] II. This PAM4 signal equalizer based on automatic gain control improves the system's adaptability and signal integrity by extracting eye height and eye thickness parameters in real time and dynamically adjusting CTLE and the variable gain amplifier VGA. Through cascaded structure and negative capacitance compensation, it effectively suppresses parasitic effects, improves eye diagram quality, and reduces inter-symbol interference. This invention reduces circuit complexity and power consumption while ensuring equalization accuracy, and has good scalability and application prospects.

[0017] Third, this PAM4 signal equalizer based on automatic gain control introduces an adaptive control mechanism based on eye diagram opening detection, which can extract key indicators such as eye height and eye thickness in real time during high-speed PAM4 multi-level signal transmission and dynamically adjust the gain of CTLE and VGA, thereby overcoming the limitation of traditional NRZ adaptive equalizers in handling multi-level signals and effectively improving signal integrity and system stability. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating the PAM4 signal equalizer based on automatic gain control according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the eye diagram parameter calculation module in the embodiment; Figure 3 This is a schematic diagram illustrating the bubble sorting module in the embodiment; Figure 4 This is a circuit diagram of the continuous-time linear equalizer (CTLE) in the embodiment. Figure 5 This is a circuit diagram of the variable gain amplifier VGA in the embodiment; Figure 6 This is a flowchart illustrating the encoder in the embodiment; Figure 7 This is a schematic diagram of the gain simulation waveform of the continuous-time linear equalizer CTLE in the embodiment; Figure 8 This is a simulation waveform of the gain of the variable gain amplifier VGA in the embodiment; Figure 9 This is the total output eye diagram of the PAM4 signal equalizer based on automatic gain control in the embodiment. Detailed Implementation

[0019] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0020] The embodiment provides a PAM4 signal equalizer based on automatic gain control, such as Figure 1 It includes a continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), negative capacitor one, negative capacitor two, a power detector, an encoder, an eye diagram parameter calculation module, a digital-to-time converter, a pipelined analog-to-digital converter, and a counter. The first input of the continuous-time linear equalizer CTLE is connected to the input signal, namely the PAM4 pseudo-random code D. IN Its second input terminal V CTLE1 Connected to the first output terminal of the encoder, its third input terminal V CTLE2 The second output terminal of the encoder is connected to the input terminal of the negative capacitor and the first input terminal of the variable gain amplifier VGA. The second input terminal V of the variable gain amplifier VGA VGA The output of the variable gain amplifier VGA, connected to the third output terminal of the encoder, is connected to the input terminal of the negative capacitor II and the output signal D, respectively. OUT ; Output terminal C of the power detector W Connect to the first input terminal of the encoder; The encoder's second input terminal EH is connected to the first output terminal of the eye diagram parameter calculation module, and the encoder's third input terminal ET is connected to the second output terminal of the eye diagram parameter calculation module. The encoder's third output terminal V... VGA Connect to the second input terminal of the variable gain amplifier VGA; The first input terminal V of the eye diagram parameter calculation module SAMP Connected to the first output of the pipelined analog-to-digital converter, and the second input C of the eye diagram parameter calculation module. N <0:2> is connected to the second output terminal of the pipelined analog-to-digital converter, the third input terminal CNT of the eye diagram parameter calculation module is connected to the output terminal of the counter, and the third output terminal RST of the eye diagram parameter calculation module is connected to the second input terminal of the counter. The output of the digital time converter is connected to the first input of the pipelined analog-to-digital converter (SAMP) to provide the low-frequency clock required for sampling by the pipelined analog-to-digital converter. The second input terminal of the pipelined analog-to-digital converter is connected to the output signal D. OUT The second output of the pipelined analog-to-digital converter is connected to the first input of the counter.

[0021] This PAM4 signal equalizer based on automatic gain control can optimize and adaptively adjust for PAM4 characteristics in real time, improving adaptability and noise immunity, as well as signal recovery and integrity. This invention combines a continuous-time linear equalizer (CTLE), a cascaded variable gain amplifier (VGA), and a negative capacitor compensation design. This not only offsets the influence of load capacitance to a certain extent but also enhances the transmission capability of high-frequency components, significantly improves eye diagram opening, and reduces inter-symbol interference. The introduction of a power detector enables the system to have self-monitoring and protection functions, automatically adjusting the equalizer gain to avoid overload risks when power exceeds limits. This invention has good scalability and portability, and can be widely applied to various high-speed interface scenarios such as serializers (SerDes), optical interconnects, and on-chip interconnects, demonstrating outstanding engineering application value and promising industrial application prospects.

[0022] like Figure 2 The eye diagram parameter calculation module includes an analog multiplier, a bubble sorting module, an eye thickness averaging module, a subtractor, and a digital control module.

[0023] The bubble sorting module receives the sampled voltage from the first input terminal of the eye diagram parameter calculation module and the control code from the second input terminal CN<0:2> of the eye diagram parameter calculation module. After performing bubble sorting on the sampled voltage at each eye diagram level, the bubble sorting module obtains the eight characteristic levels V corresponding to the eye diagram. 11max V 11min V 10max V 10min V 01max V 01min V 00max and V 00min The bubble sorting module outputs the characteristic level V respectively. 01min and V 00max The characteristic level V of the output of the subtractor is given. 10min and V 01max The characteristic level V of the output of the subtractor is given. 11min and V 10max The characteristic level V of the output of the subtractor is given. 11max and V 11min The characteristic level V of the output of the subtractor is given below. 10max and V 10min The characteristic level V of the output of the subtractor is given below. 01max and V 01min The characteristic level V of the output of the subtractor is given. 00max and V 00min Subtractors 7, 1, 2, and 3 calculate three eye height values ​​EH1, EH2, and EH3 respectively and output them to the analog multiplier. The analog multiplier multiplies the three eye height values ​​EH1, EH2, and EH3 and outputs the result as the first output terminal EH of the eye diagram parameter calculation module. Subtractors 4, 5, 6, and 7 output four eye thickness values ​​ET1, ET2, ET3, and ET4 respectively and output them to the eye thickness averaging module. The eye thickness averaging module averages the four eye thickness values ​​ET1, ET2, ET3, and ET4 and outputs the result as the second output terminal ET of the eye diagram parameter calculation module. The digital control module receives the counting signal input from the third input terminal CNT of the eye diagram parameter calculation module. When the counting signal equals the set value, it outputs a reset signal as the third output terminal RST of the eye diagram parameter calculation module.

[0024] like Figure 3 The bubble sort module includes a demultiplexer DEMUX and four bubble sort units. The first input of the demultiplexer DEMUX is connected to the first input V of the eye diagram parameter calculation module. SAMP The second input of the demultiplexer DEMUX is connected to the second input C of the eye diagram parameter calculation module. N<0:2>, the first output terminal V11, the second output terminal V10, the third output terminal V01, and the fourth output terminal V00 of the demultiplexer DEMUX are respectively connected to the input terminals of the four bubble sorting units. The first bubble sorting unit outputs the characteristic level V. 11max V 11min The second bubble sorting unit outputs the characteristic level V. 10max V 10min The third bubble sorting unit outputs the characteristic level V. 01max V 01min The fourth bubble sorting unit outputs the characteristic level V. 00max and V 00min .

[0025] The bubble sorting unit includes operational amplifiers A1, A2, A3, and A4, switch S1, switch S2, capacitor C1, and capacitor C2. The input terminals of the bubble sorting unit are connected to the non-inverting input terminal of operational amplifier A1 and one end of switch S1, respectively. The other end of switch S1 is grounded through capacitor C1, and the other end of switch S1 is connected to the inverting input terminal of operational amplifier A1 and the non-inverting input terminal of operational amplifier A3, respectively. The output terminal of operational amplifier A1 is connected to the control terminal of switch S1, and the inverting input terminal of operational amplifier A3 is connected to the output terminal of operational amplifier A3. The output terminal of operational amplifier A3 serves as the first output terminal of the bubble sorting unit. The input terminals of the bubble sorting unit are connected to the inverting input terminal of operational amplifier A2 and one end of switch S2, respectively. The other end of switch S2 is grounded through capacitor C2, and the other end of switch S2 is connected to the non-inverting input terminal of operational amplifier A2 and the non-inverting input terminal of operational amplifier A4, respectively. The output terminal of operational amplifier A2 is connected to the control terminal of switch S2, and the inverting input terminal of operational amplifier A4 is connected to the output terminal of operational amplifier A4. The output terminal of operational amplifier A4 serves as the second output terminal of the bubble sorting unit.

[0026] In the bubble sorting module, the demultiplexer DEMUX receives the sampled voltage and distributes it to the corresponding bubble sorting unit according to the control code. The two capacitors C1 and C2 in the bubble sorting unit are used to store the maximum and minimum values ​​of the sampled voltage, respectively. If the sampled voltage is greater than the value stored in capacitor C1, operational amplifier A1 controls switch S1 to turn on, and the value stored in capacitor C1 is updated to the current maximum value. If the sampled voltage is not greater than the value stored in capacitor C1, switch S1 is turned off, and capacitor C1 retains its current stored value. Similarly, if the sampled voltage is less than the value stored in capacitor C2, operational amplifier A2 controls switch S2 to turn on, and the value stored in capacitor C2 is updated to the current minimum value. If the sampled voltage is not less than the value stored in capacitor C2, switch S2 is turned off, and capacitor C2 retains its current stored value.

[0027] The eye diagram parameter calculation module is used for sampling level processing and eye height and thickness calculation. The sampling level processing function is used to perform bubble sorting on the sampled voltage and extract eight key level values ​​that characterize the eye diagram opening. The eye height and thickness calculation function calculates the corresponding eye height and thickness values ​​based on the extracted level values, and then multiplies the eye height and averages the eye thickness.

[0028] like Figure 4 The continuous-time linear equalizer (CTLE) includes NMOS transistors M1, M2, and M3, and resistor R. D1 Resistance R D2 Resistance R S Resistance R F1 Resistance R F2 Inductor L D1 Inductor L D2 Inductor L F1 Inductor L F2 Variable capacitor C S Switch S1, switch S2, current source I1, current source I2, and first transimpedance amplifier TIA1, Differential input voltage V in The gates of NMOS transistors M1 and M2 are connected to each other, serving as the first input terminal of the continuous-time linear equalizer CTLE. The drain of NMOS transistor M1 is connected to a resistor R. D1 and inductor L D1 Connect to power supply V DD And the drain of NMOS transistor M1 is connected to inductor L F2 and resistance R F2 Connected to the second output terminal of the first transimpedance amplifier TIA1, switch S2 and inductor L F2 In parallel connection, the drain of NMOS transistor M1 is connected to the second input terminal of the first transimpedance amplifier TIA1; The drain of NMOS transistor M2 is connected to resistor R. D2 and inductor L D2 Connect to power supply V DD And the drain of NMOS transistor M2 is connected to inductor L F1 and resistance R F1 The switch S1 and inductor L are connected to the first output terminal of the first transimpedance amplifier TIA1. F1 The NMOS transistor M2 is connected in parallel, and its drain is connected to the first input terminal of the first transimpedance amplifier TIA1. The first and second output terminals of the first transimpedance amplifier TIA1 are connected to the differential output voltage V. OUT And serve as the output terminal N1 of CTLE; The source of NMOS transistor M1 is grounded through current source I1 and through resistor R.S Connect the source of NMOS transistor M2, connect the drain of MOS transistor M3, and connect through a variable capacitor C. S The source of NMOS transistor M2 is connected, the source of MOS transistor M3 is connected to the source of NMOS transistor M2, and the gate of MOS transistor M3 is connected to the second input terminal V of the continuous-time linear equalizer CTLE. CTLE1 The source of NMOS transistor M2 is grounded through current source I2, and the variable capacitor C... S The control terminal is connected to the third input terminal V of the continuous-time linear equalizer CTLE. CTLE2 .

[0029] like Figure 5 The variable gain amplifier VGA includes an NMOS transistor M 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 Resistors R1, R2, R3, R4, and R5; inductors L1 and L2; capacitor C3; current source I3; current source I4; and the second transimpedance amplifier TIA2. The differential input voltage Vin` is connected to the NMOS transistor M. 11 The gate of the NMOS transistor M 12 The gate of the NMOS transistor M serves as the first input terminal of the variable gain amplifier VGA. 11 The drain of the circuit is connected to the power supply V through resistor R1 and inductor L1. DD And NMOS transistor M 11 The drain of the transistor is connected to the second input terminal of the second transimpedance amplifier TIA2, and through resistor R4 to the second output terminal of the second transimpedance amplifier TIA2, and connected to the NMOS transistor M. 14 The drain of the NMOS transistor M 14 The source of the transistor is connected to the second output terminal of the second transimpedance amplifier TIA2, and the NMOS transistor M... 14 The gate is connected to the second input terminal V of the variable gain amplifier VGA. VGA ; NMOS transistor M 12 The drain of the circuit is connected to the power supply V through resistor R2 and inductor L2. DD And NMOS transistor M 12 The drain of the first terminal is connected to the first input terminal of the second transimpedance amplifier TIA2, and is connected to the first output terminal of the second transimpedance amplifier TIA2 through resistor R3, and is connected to the NMOS transistor M. 13 The drain of the NMOS transistor M 13 The source of the transistor is connected to the first output terminal of the second transimpedance amplifier TIA2, and the NMOS transistor M... 13 The gate is connected to the second input terminal V of the variable gain amplifier VGA.VGA ; Differential output voltage V OUT `Connect to the first output terminal and the second output terminal of the second transimpedance amplifier TIA2, as the output terminal of the variable gain amplifier VGA; NMOS transistor M 11 The source terminals are connected to the NMOS transistor M through resistor R5. 12 The source of the NMOS transistor is connected to capacitor C3. 12 The source of the NMOS transistor is grounded through current source I3. 12 The source of is grounded through current source I4.

[0030] like Figure 6 The encoder uses a performance maximization function to sequentially determine and optimize power consumption, eye height, and eye thickness, specifically as follows: 1) Set the initial control code EQ coef (1) Assign the equalizer control code EQ coef EQ coef =EQ coef (1); 2) Receive the output power P sent by the power detector, where the output power P is the sum of the output power Pc of the continuous-time linear equalizer CTLE and the output power Pv of the variable gain amplifier VGA. If the output power P exceeds the preset threshold Pset, then the current iteration number i = i + 1, proceed to the next iteration, and return to repeat step 2); otherwise, calculate the eye height index FOM1 = (EH1 − EH) set )(EH2−EH set )(EH3−EH set ), where EHset is the target eye height; 3) When the eye height index FOM1 < 0, the current iteration number i = i + 1, continue to the next iteration, and return to step 2); when the eye height index FOM1 ≥ 0, further calculate the eye thickness deviation FOM2 = −(ET − ET). set ), where ETset is used to set the target eye thickness, and then proceed to step 4); 4) Calculate the final comprehensive index FOM = FOM1 × FOM2, and the control code EQ under the current iteration number i is greater than 1 and the current iteration order i. coef If the quality factor FOM(i) corresponding to (i) is greater than the quality factor FOM(i-1) of the previous iteration, then the equalizer control code EQ will be changed. coef Update, i.e., EQ coef =EQ coef (i), and proceed to step 5); In step 4), FOM1 is used to determine the three eye height information so that the eye diagram can open better, while FOM2 is used to determine the eye thickness information so that the eye thickness is as small as possible. However, it is often difficult to take both eye height and eye thickness into account at the same time. Therefore, the embodiment sets an index FOM to make the eye height increase while taking into account that the eye thickness is not too large, so as a comprehensive evaluation standard.

[0031] 5) Determine if the current iteration order is greater than the set maximum iteration order i. max If the maximum iteration order is not reached, repeat step 2; otherwise, terminate.

[0032] The implementation process of this PAM4 signal equalizer based on automatic gain control is as follows: The continuous-time linear equalizer CTLE receives an externally input PAM4 pseudo-random code D. IN The signal is then equalized and output to the variable gain amplifier (VGA); the VGA adjusts the low-frequency gain and scales the swing; the pipelined analog-to-digital converter subsamples the output signal of the VGA and outputs the sampled voltage and control code to the eye diagram parameter calculation module, and outputs the control code counter. The digital time converter provides the low-frequency clock required for sampling by the pipelined analog-to-digital converter, ensuring that the sampling point falls at the center of the eye diagram. The counter counts the number of current sampling cycles and sends the count result to the digital control module inside the eye diagram parameter calculation module. If the current set number of sampling cycles has been counted, the counter is reset. The eye diagram parameter counting module performs bubble sorting on different sampling voltages according to the control code and analyzes and extracts eye height and eye thickness data. The power detector acquires the output power Pc of the continuous-time linear equalizer (CTLE) and the output power Pv of the variable gain amplifier (VGA), sums them to obtain the output power P, and sends it to the encoder. The encoder generates a feedback control voltage V for adjusting the gain of the CTLE based on eye height data, eye thickness data, and the current system power. CTLE1 Feedback control voltage V CTLE2 It generates a feedback control voltage V for adjusting the gain of the variable gain amplifier VGA. VGA Meanwhile, negative capacitors one and two are used at the outputs of the continuous-time linear equalizer CTLE and the variable gain amplifier VGA, respectively, to cancel parasitic capacitance and expand the system bandwidth.

[0033] This PAM4 signal equalizer based on automatic gain control improves system adaptability and signal integrity by extracting eye height and eye thickness parameters in real time and dynamically adjusting the CTLE and variable gain amplifier VGA. Through cascaded structure and negative capacitance compensation, it effectively suppresses parasitic effects, improves eye diagram quality, and reduces inter-symbol interference. This invention reduces circuit complexity and power consumption while maintaining equalization accuracy, exhibiting good scalability and application prospects. The invention uses a low-frequency clock, such as 14MHz, for subsampling of the output data, effectively reducing the design difficulty of the automatic gain control section.

[0034] This PAM4 signal equalizer based on automatic gain control introduces an adaptive control mechanism based on eye diagram opening detection. It can extract key indicators such as eye height and eye thickness in real time during high-speed PAM4 multi-level signal transmission and dynamically adjust the gain of CTLE and VGA. This overcomes the limitation of traditional NRZ adaptive equalizers in handling multi-level signals and effectively improves signal integrity and system stability.

[0035] This PAM4 signal equalizer based on automatic gain control (AGC) utilizes a continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), a power detector, a pipelined analog-to-digital converter (ADC), an eye diagram parameter calculation module, and an encoder to achieve signal equalization and amplification, power detection, eye diagram sampling, eye diagram parameter calculation, and encoding feedback functions. The signal equalization and amplification function enhances the amplitude of high-frequency components, thereby mitigating the low-pass characteristics of the channel to some extent and compensating for losses incurred during high-speed signal transmission. The power detection function monitors system power consumption in real time and triggers protection when power consumption exceeds limits. The eye diagram sampling function quantizes and analyzes the eye diagram of the output signal, generating corresponding sampling voltages and control codes for subsequent eye diagram parameter calculations. The eye diagram parameter calculation function calculates the eye thickness and eye height parameters based on the sampling results. The encoding feedback function calculates the optimal feedback control parameters based on the eye diagram parameters and system power consumption using a built-in algorithm, thereby adjusting the gain of the pre-stage equalizer to optimize the system output eye diagram.

[0036] This PAM4 signal equalizer based on automatic gain control was designed for an external data rate of 56Gbps. The CTLE, VGA, negative capacitor one, and negative capacitor two operated at a Nyquist frequency of 14GHz. The power detector, encoder, eye diagram parameter calculation module, digital-to-time converter, pipelined analog-to-digital converter, and counter operated at a clock frequency of 14MHz. The simulated gain waveforms of the continuous-time linear equalizer CTLE are shown below. Figure 7 The gain simulation waveform of the variable gain amplifier VGA is shown below. Figure 8 The total output eye diagram of the equalizer is as follows: Figure 9 .

[0037] like Figure 7 The gain simulation waveform of the continuous-time linear equalizer CTLE shows that its gain response curve can be changed by adjusting the control voltage; the low-frequency gain changes with the control voltage V. CTLE1 The gain increases with the increase of the frequency, while the high-frequency (Nyquist frequency) gain remains basically stable; when the control voltage is scanned from 0.85V to 1.1V, the low-frequency gain increases from -4.4dB to 3.8dB, and the Peaking value of the gain curve increases from 0.5dB to 8.4dB, thus enabling flexible compensation for channels with different loss levels.

[0038] like Figure 8 The gain simulation waveform of the variable gain amplifier VGA shows that its gain response curve can be changed by adjusting the control voltage; the gain of VGA increases monotonically with the increase of control voltage, and the gain adjustment range covers -1.5dB to 2.4dB; at the same time, the bandwidth of VGA is about 14GHz, which meets the system requirements.

[0039] like Figure 9 The total output eye diagram of this PAM signal equalizer based on automatic gain control has good opening under channel conditions of 56Gbps data rate and 10dB loss, with an eye height of about 12mV and an eye width of about 0.36UI.

[0040] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. A PAM4 signal equalizer based on automatic gain control, characterized in that: This includes a continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), negative capacitor one, negative capacitor two, a power detector, an encoder, an eye diagram parameter calculation module, a digital-to-time converter, a pipelined analog-to-digital converter, and a counter. The first input of the continuous-time linear equalizer CTLE is connected to the input signal, namely the PAM4 pseudo-random code D. IN Its second input terminal V CTLE1 Connected to the first output terminal of the encoder, its third input terminal V CTLE2 The second output terminal of the encoder is connected to the input terminal of the negative capacitor and the first input terminal of the variable gain amplifier VGA. The second input terminal V of the variable gain amplifier VGA VGA The output of the variable gain amplifier VGA, connected to the third output terminal of the encoder, is connected to the input terminal of the negative capacitor II and the output signal D, respectively. OUT ; Output terminal C of the power detector W Connect to the first input terminal of the encoder; The encoder's second input terminal EH is connected to the first output terminal of the eye diagram parameter calculation module, and the encoder's third input terminal ET is connected to the second output terminal of the eye diagram parameter calculation module. The encoder's third output terminal V... VGA Connect to the second input terminal of the variable gain amplifier VGA; The first input terminal V of the eye diagram parameter calculation module SAMP Connected to the first output of the pipelined analog-to-digital converter, and the second input C of the eye diagram parameter calculation module. N <0:2> is connected to the second output terminal of the pipelined analog-to-digital converter, the third input terminal CNT of the eye diagram parameter calculation module is connected to the output terminal of the counter, and the third output terminal RST of the eye diagram parameter calculation module is connected to the second input terminal of the counter. The output of the digital time converter is connected to the first input of the pipelined analog-to-digital converter (SAMP) to provide the low-frequency clock required for sampling by the pipelined analog-to-digital converter. The second input terminal of the pipelined analog-to-digital converter is connected to the output signal D. OUT The second output of the pipelined analog-to-digital converter is connected to the first input of the counter.

2. The PAM4 signal equalizer based on automatic gain control as described in claim 1, characterized in that: The eye diagram parameter calculation module includes an analog multiplier, a bubble sorting module, an eye thickness averaging module, a subtractor, and a digital control module. The bubble sorting module receives the sampled voltage from the first input terminal of the eye diagram parameter calculation module and the control code from the second input terminal CN<0:2> of the eye diagram parameter calculation module. After performing bubble sorting on the sampled voltage at each eye diagram level, the bubble sorting module obtains the eight characteristic levels V corresponding to the eye diagram. 11max V 11min V 10max V 10min V 01max V 01min V 00max and V 00min The bubble sorting module outputs the characteristic level V respectively. 01min and V 00max The characteristic level V of the output of the subtractor is given. 10min and V 01max The characteristic level V of the output of the subtractor is given. 11min and V 10max The characteristic level V of the output of the subtractor is given. 11max and V 11min The characteristic level V of the output of the subtractor is given below. 10max and V 10min The characteristic level V of the output of the subtractor is given below. 01max and V 01min The characteristic level V of the output of the subtractor is given. 00max and V 00min Subtractor 7, Subtractor 1, Subtractor 2, and Subtractor 3 calculate three eye height values ​​EH1, EH2, and EH3 respectively and output them to the analog multiplier. The analog multiplier multiplies the three eye height values ​​EH1, EH2, and EH3 and outputs the result as the first output of the eye diagram parameter calculation module, EH. Subtractors 4, 5, 6, and 7 output four eye thickness values ​​ET1, ET2, ET3, and ET4 respectively and output them to the eye thickness averaging module. The eye thickness averaging module averages the four eye thickness values ​​ET1, ET2, ET3, and ET4 and outputs the result as the second output of the eye diagram parameter calculation module, ET. The digital control module receives the counting signal from the third input terminal CNT of the eye diagram parameter calculation module. When the counting signal equals the set value, it outputs a reset signal as the output of the third output terminal RST of the eye diagram parameter calculation module.

3. The PAM4 signal equalizer based on automatic gain control as described in claim 2, characterized in that: The bubble sort module includes a demultiplexer DEMUX and four bubble sort units. The first input of the demultiplexer DEMUX is connected to the first input V of the eye diagram parameter calculation module. SAMP The second input of the demultiplexer DEMUX is connected to the second input C of the eye diagram parameter calculation module. N <0:2>, the first output terminal V11, the second output terminal V10, the third output terminal V01, and the fourth output terminal V00 of the demultiplexer DEMUX are respectively connected to the input terminals of the four bubble sorting units. The first bubble sorting unit outputs the characteristic level V. 11max V 11min The second bubble sorting unit outputs the characteristic level V. 10max V 10min The third bubble sorting unit outputs the characteristic level V. 01max V 01min The fourth bubble sorting unit outputs the characteristic level V. 00max and V 00min .

4. The PAM4 signal equalizer based on automatic gain control as described in claim 3, characterized in that: The bubble sorting unit includes operational amplifiers A1, A2, A3, and A4, switch S1, switch S2, capacitor C1, and capacitor C2. The input terminals of the bubble sorting unit are connected to the non-inverting input terminal of operational amplifier A1 and one end of switch S1, respectively. The other end of switch S1 is grounded through capacitor C1, and the other end of switch S1 is connected to the inverting input terminal of operational amplifier A1 and the non-inverting input terminal of operational amplifier A3, respectively. The output terminal of operational amplifier A1 is connected to the control terminal of switch S1, and the inverting input terminal of operational amplifier A3 is connected to the output terminal of operational amplifier A3. The output terminal of operational amplifier A3 serves as the first output terminal of the bubble sorting unit. The input terminals of the bubble sorting unit are connected to the inverting input terminal of operational amplifier A2 and one end of switch S2, respectively. The other end of switch S2 is grounded through capacitor C2, and the other end of switch S2 is connected to the non-inverting input terminal of operational amplifier A2 and the non-inverting input terminal of operational amplifier A4, respectively. The output terminal of operational amplifier A2 is connected to the control terminal of switch S2, and the inverting input terminal of operational amplifier A4 is connected to the output terminal of operational amplifier A4. The output terminal of operational amplifier A4 serves as the second output terminal of the bubble sorting unit.

5. The PAM4 signal equalizer based on automatic gain control as described in claim 4, characterized in that: In the bubble sorting module, the demultiplexer DEMUX receives the sampled voltage and distributes it to the corresponding bubble sorting unit according to the control code. The two capacitors C1 and C2 in the bubble sorting unit are used to store the maximum and minimum values ​​of the sampled voltage, respectively. If the sampled voltage is greater than the value stored in capacitor C1, operational amplifier A1 controls switch S1 to turn on, and the value stored in capacitor C1 is updated to the current maximum value. If the sampled voltage is not greater than the value stored in capacitor C1, switch S1 is turned off, and capacitor C1 retains its current stored value. Similarly, if the sampled voltage is less than the value stored in capacitor C2, operational amplifier A2 controls switch S2 to turn on, and the value stored in capacitor C2 is updated to the current minimum value. If the sampled voltage is not less than the value stored in capacitor C2, switch S2 is turned off, and capacitor C2 retains its current stored value.

6. The PAM4 signal equalizer based on automatic gain control as described in any one of claims 1-5, characterized in that: The continuous-time linear equalizer (CTLE) includes NMOS transistors M1, M2, and M3, and resistor R. D1 Resistance R D2 Resistance R S Resistance R F1 Resistance R F2 Inductor L D1 Inductor L D2 Inductor L F1 Inductor L F2 Variable capacitor C S Switch S1, switch S2, current source I1, current source I2, and first transimpedance amplifier TIA1, Differential input voltage V in The gates of NMOS transistors M1 and M2 are connected to each other, serving as the first input terminal of the continuous-time linear equalizer CTLE. The drain of NMOS transistor M1 is connected to a resistor R. D1 and inductor L D1 Connect to power supply V DD And the drain of NMOS transistor M1 is connected to inductor L F2 and resistance R F2 Connected to the second output terminal of the first transimpedance amplifier TIA1, switch S2 and inductor L F2 In parallel connection, the drain of NMOS transistor M1 is connected to the second input terminal of the first transimpedance amplifier TIA1; The drain of NMOS transistor M2 is connected to resistor R. D2 and inductor L D2 Connect to power supply V DD And the drain of NMOS transistor M2 is connected to inductor L F1 and resistance R F1 The switch S1 and inductor L are connected to the first output terminal of the first transimpedance amplifier TIA1. F1 The NMOS transistor M2 is connected in parallel, and its drain is connected to the first input terminal of the first transimpedance amplifier TIA1. The first and second output terminals of the first transimpedance amplifier TIA1 are connected to the differential output voltage V. OUT And serve as the output terminal N1 of CTLE; The source of NMOS transistor M1 is grounded through current source I1 and through resistor R. S Connect the source of NMOS transistor M2, connect the drain of MOS transistor M3, and connect through a variable capacitor C. S The source of NMOS transistor M2 is connected, the source of MOS transistor M3 is connected to the source of NMOS transistor M2, and the gate of MOS transistor M3 is connected to the second input terminal V of the continuous-time linear equalizer CTLE. CTLE1 The source of NMOS transistor M2 is grounded through current source I2, and the variable capacitor C... S The control terminal is connected to the third input terminal V of the continuous-time linear equalizer CTLE. CTLE2 .

7. The PAM4 signal equalizer based on automatic gain control as described in any one of claims 1-5, characterized in that: Variable gain amplifier VGA includes NMOS transistor M 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 Resistors R1, R2, R3, R4, and R5; inductors L1 and L2; capacitor C3; current source I3; current source I4; and the second transimpedance amplifier TIA2. The differential input voltage Vin` is connected to the NMOS transistor M. 11 The gate of the NMOS transistor M 12 The gate of the NMOS transistor M serves as the first input terminal of the variable gain amplifier VGA. 11 The drain of the circuit is connected to the power supply V through resistor R1 and inductor L1. DD And NMOS transistor M 11 The drain of the transistor is connected to the second input terminal of the second transimpedance amplifier TIA2, and through resistor R4 to the second output terminal of the second transimpedance amplifier TIA2, and connected to the NMOS transistor M. 14 The drain of the NMOS transistor M 14 The source of the transistor is connected to the second output terminal of the second transimpedance amplifier TIA2, and the NMOS transistor M... 14 The gate is connected to the second input terminal V of the variable gain amplifier VGA. VGA ; NMOS transistor M 12 The drain of the circuit is connected to the power supply V through resistor R2 and inductor L2. DD And NMOS transistor M 12 The drain of the first terminal is connected to the first input terminal of the second transimpedance amplifier TIA2, and is connected to the first output terminal of the second transimpedance amplifier TIA2 through resistor R3, and is connected to the NMOS transistor M. 13 The drain of the NMOS transistor M 13 The source of the transistor is connected to the first output terminal of the second transimpedance amplifier TIA2, and the NMOS transistor M... 13 The gate is connected to the second input terminal V of the variable gain amplifier VGA. VGA ; Differential output voltage V OUT `Connect to the first output terminal and the second output terminal of the second transimpedance amplifier TIA2, as the output terminal of the variable gain amplifier VGA; NMOS transistor M 11 The source terminals are connected to the NMOS transistor M through resistor R5. 12 The source of the NMOS transistor is connected to capacitor C3. 12 The source of the NMOS transistor is grounded through current source I3. 12 The source of is grounded through current source I4.

8. The PAM4 signal equalizer based on automatic gain control as described in any one of claims 2-5, characterized in that: The encoder uses a performance maximization function to sequentially determine and optimize power consumption, eye height, and eye thickness, specifically as follows: 1) Set the initial control code EQ coef (1) Assign the equalizer control code EQ coef EQ coef =EQ coef (1); 2) Receive the output power P sent by the power detector, where the output power P is the sum of the output power Pc of the continuous-time linear equalizer CTLE and the output power Pv of the variable gain amplifier VGA. If the output power P exceeds the preset threshold Pset, then the current iteration number i = i + 1, proceed to the next iteration, and return to repeat step 2); otherwise, calculate the eye height index FOM1 = (EH1 − EH) set )(EH2−EH set )(EH3−EH set ), where EHset is the target eye height; 3) When the eye height index FOM1 < 0, the current iteration number i = i + 1, continue to the next iteration, and return to step 2); when the eye height index FOM1 ≥ 0, further calculate the eye thickness deviation FOM2 = −(ET − ET). set ), where ETset is used to set the target eye thickness, and then proceed to step 4); 4) Calculate the final comprehensive index FOM = FOM1 × FOM2, and the control code EQ under the current iteration number i is greater than 1 and the current iteration order i. coef If the quality factor FOM(i) corresponding to (i) is greater than the quality factor FOM(i-1) of the previous iteration, then the equalizer control code EQ will be changed. coef Update, i.e., EQ coef =EQ coef (i), and proceed to step 5); 5) Determine if the current iteration order is greater than the set maximum iteration order i. max If the maximum iteration order is not reached, repeat step 2; otherwise, terminate.

9. The PAM4 signal equalizer based on automatic gain control as described in any one of claims 1-5, characterized in that: The implementation process of this PAM4 signal equalizer based on automatic gain control is as follows: The continuous-time linear equalizer CTLE receives an externally input PAM4 pseudo-random code D. IN The signal is then equalized and output to the variable gain amplifier (VGA); the VGA adjusts the low-frequency gain and scales the swing; the pipelined analog-to-digital converter subsamples the output signal of the VGA and outputs the sampled voltage and control code to the eye diagram parameter calculation module, and outputs the control code counter. The digital time converter provides the low-frequency clock required for sampling by the pipelined analog-to-digital converter; the counter counts the number of current sampling cycles and sends the count result to the digital control module inside the eye diagram parameter calculation module; if the current sampling set cycle has been counted, the counter is reset; the eye diagram parameter counting module performs bubble sorting operation on different sampling voltages according to the control code and analyzes and extracts eye height data and eye thickness data. The power detector acquires the output power Pc of the continuous-time linear equalizer (CTLE) and the output power Pv of the variable gain amplifier (VGA), sums them to obtain the output power P, and sends it to the encoder. The encoder generates a feedback control voltage V for adjusting the gain of the CTLE based on eye height data, eye thickness data (ET), and the current system power. CTLE1 Feedback control voltage V CTLE2 It generates a feedback control voltage V for adjusting the gain of the variable gain amplifier VGA. VGA .

Images