Semiconductor structure, manufacturing method thereof and memory

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure comprises an active column array; each active column comprises a first source / drain electrode, a channel and a second source / drain electrode which are arranged in the vertical direction; a plurality of word lines; each word line fully surrounds a channel of each active column of a row of active columns of the active column array; a plurality of memory cells; each storage unit is connected with a first source / drain electrode; the plurality of bit lines comprise a plurality of first type bit lines and a plurality of second type bit lines; each bit line is connected with a second source / drain electrode of each active column of a column of active columns of the active column array; at least one bit line lead; each bit line lead is connected with two paired bit lines in the plurality of first type bit lines; and the number of the active columns in the column active columns corresponding to the two pairing bit lines is the same as the number of the active columns in the column active columns corresponding to each second type bit line.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, including but not limited to a semiconductor structure and its manufacturing method, and a memory. Background Technology

[0002] As the integration density of semiconductor devices increases and their size continues to shrink, the transistor feature size in semiconductor devices, such as Dynamic Random Access Memory (DRAM), shrinks to the nanoscale. This limits the power consumption, density, and mobility of transistors, posing greater challenges to improving transistor performance. For example, while increasing the number of memory cells per unit density, reducing parasitic capacitance and mitigating row hammer effects remains a challenge. Summary of the Invention

[0003] In view of this, embodiments of this application provide a semiconductor structure, a method for manufacturing the same, and a memory.

[0004] In a first aspect, embodiments of this application provide a semiconductor structure comprising: an active pillar array; each active pillar including a first source / drain, a channel, and a second source / drain disposed vertically; multiple word lines; each word line completely surrounding the channel of each active pillar in a row of active pillars of the active pillar array; multiple memory cells; each memory cell being connected to a first source / drain; multiple bit lines, including multiple first-type bit lines and multiple second-type bit lines; each bit line being connected to the second source / drain of each active pillar in a column of active pillars of the active pillar array; the row active pillar arrangement direction intersects with the column active pillar arrangement direction but is not orthogonal; at least one bit line lead; each bit line lead connecting two of the multiple first-type bit lines to form a paired bit line; the number of active pillars in the column active pillars corresponding to each paired bit line is the same as the number of active pillars in the column active pillars corresponding to each second-type bit line.

[0005] In some embodiments, each word line includes a plurality of first portions and a plurality of second portions; each first portion fully surrounds the channel of an active post in a corresponding row of active posts, and each second portion connects two adjacent first portions; wherein the vertical dimension of the first portion is greater than the vertical dimension of the second portion.

[0006] In some embodiments, the dimension of the first portion along the direction of the arrangement of the active columns is greater than the dimension of the second portion along the direction of the arrangement of the active columns.

[0007] In some embodiments, the thickness of the first portion along the direction of the active column arrangement is less than or equal to the thickness of the second portion along the vertical direction.

[0008] In some embodiments, an active column is provided at the intersection of the row active column arrangement direction and the column active column arrangement direction; the row active column arrangement direction and the column active column arrangement direction have an angle; the angle range is greater than 0 degrees and less than 90 degrees.

[0009] In some embodiments, the included angle is 60 degrees, and the active column array arrangement includes a close-packed hexagonal arrangement; or, the included angle is 45 degrees, and the active column array arrangement includes a square arrangement; or, the included angle is 75 degrees, and the active column array arrangement includes a rhombus arrangement.

[0010] In some embodiments, a plurality of second-type bit lines are located in a first region; a plurality of first-type bit lines are located in a second region and a third region; the second region and the third region are located on opposite sides of the first region along the row active column arrangement direction; one bit line of all paired bit lines originates from the second region and the other bit line originates from the third region; or, some paired bit lines all originate from the second region and the remaining paired bit lines all originate from the third region; or, some paired bit lines all originate from the second region, another portion of paired bit lines all originate from the third region, and one bit line of the remaining paired bit lines originates from the second region and the other bit line originates from the third region.

[0011] In some embodiments, the semiconductor structure further includes: a first word line contact corresponding to odd-numbered row word lines and a second word line contact corresponding to even-numbered row word lines, and a first bit line contact corresponding to odd-numbered column bit lines and a second bit line contact corresponding to even-numbered column bit lines; wherein the first word line contact and the second word line contact are located on both sides of the active pillar array along the row active pillar arrangement direction; the first bit line contact and the second bit line contact are located on both sides of the active pillar array along a direction perpendicular to the row active pillar arrangement direction.

[0012] In some embodiments, the semiconductor structure further includes an active pillar connection portion; the active pillar connection portion is integrally formed with each column of active pillars and extends along the arrangement direction of the column of active pillars; the column of active pillars is located on the active pillar connection portion; wherein, the bit line covers the end of the active pillar connection portion away from the active pillar.

[0013] In some embodiments, the plurality of storage cells are arranged in a square or in a hexagonal arrangement.

[0014] In a second aspect, embodiments of this application provide a memory comprising: any of the semiconductor structures provided in the embodiments of the first aspect; word lines of the semiconductor structure are configured to receive word line voltage and control the channel of an active pillar to be turned on or off via the word line voltage, for connecting / disconnecting the first source / drain and the second source / drain of the semiconductor structure; bit lines of the semiconductor structure are configured to perform read or write operations on memory cells of the semiconductor structure when the channel of the active pillar is turned on.

[0015] In some embodiments, even-numbered bit lines are configured to receive word line voltage to control the channel conduction of the corresponding active pillar, and even-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the active pillar's channel is conduction; odd-numbered bit lines are configured to receive a default voltage to shield the even-numbered bit lines; or, odd-numbered bit lines are configured to receive word line voltage to control the channel conduction of the corresponding active pillar, and odd-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the active pillar's channel is conduction; even-numbered bit lines are configured to receive a default voltage to shield the odd-numbered bit lines.

[0016] Thirdly, embodiments of this application provide a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; forming an active pillar array along a first surface of the substrate; wherein the row active pillar arrangement direction of the active pillar array is not orthogonal to the column active pillar arrangement direction of the active pillar array; each active pillar is used to form a first source / drain, a channel, and a second source / drain, all disposed in a vertical direction; forming multiple word lines; each word line completely surrounds the channel of each active pillar in a row of active pillars of the active pillar array; forming multiple memory cells; each memory cell is respectively connected to a first source / drain. / Drain connection; Multiple bit lines are formed along the second surface of the substrate; The multiple bit lines include multiple first-type bit lines and multiple second-type bit lines; Each bit line is connected to the second source / drain of each active pillar in a column of active pillars of the active pillar array; The second surface is the opposite surface of the substrate with the first surface perpendicular to it; At least one bit line lead is formed; Each bit line lead connects two of the multiple first-type bit lines to form a paired bit line; The number of active pillars in the column of active pillars corresponding to each paired bit line is the same as the number of active pillars in the column of active pillars corresponding to each second-type bit line.

[0017] In some embodiments, forming an active pillar array along a first surface of a substrate includes: forming a plurality of spaced-apart first trenches and active strips along the first surface of the substrate, wherein the first trenches and active strips extend along a first direction; filling the first trenches with insulating material to form a first isolation structure; forming a plurality of spaced-apart second trenches along the first surface of the substrate in the first isolation structure and active strips, wherein the second trenches extend along a second direction; filling the second trenches with insulating material to form a second isolation structure; the plurality of second isolation structures divide each active strip into a plurality of active pillars extending along a third direction; wherein the dimension of the second trench along the third direction is smaller than the dimension of the first trench along the third direction; the third direction is perpendicular to the plane formed by the first direction and the second direction; there is an angle between the first direction and the second direction; the angle range is greater than 0 degrees and less than 90 degrees.

[0018] In some embodiments, forming multiple word lines includes: removing a portion of a first isolation structure and a portion of a second isolation structure along a first surface of a substrate to form a third trench; the third trench completely surrounds and exposes at least a portion of the sidewalls of each active pillar; in the third trench, a gate dielectric layer, a first conductive structure, and a third isolation structure are formed sequentially covering the third trench; removing at least a portion of the third isolation structure and a portion of the first conductive structure along the first surface of the substrate to form a word line isolation trench; the word line isolation trench extends along a second direction and is located between adjacent row active pillars; multiple word line isolation trenches divide the first conductive structure into multiple word lines extending along the second direction; filling the word line isolation trenches with insulating material to form a word line isolation structure; wherein the dimension of the word line isolation trench along a third direction is larger than the dimension of the third trench along a third direction; the dimension of the third trench along a third direction is smaller than the dimension of the second trench along a third direction; each word line includes multiple first portions and multiple second portions; each first portion completely surrounds the channel of one active pillar in a corresponding row of active pillars, and each second portion connects two adjacent first portions; wherein the dimension of the first portion along a third direction is larger than the dimension of the second portion along a third direction.

[0019] In some embodiments, forming a plurality of memory cells includes: forming a plurality of memory cell contacts on a first source / drain; each memory cell contact being connected to a first source / drain; forming a plurality of memory cells on the memory cell contacts; and each memory cell being connected to a memory cell contact.

[0020] In some embodiments, forming a plurality of bit lines along the second surface of a substrate includes: thinning the substrate along the second surface to expose a first isolation structure and an active strip at one end away from the first surface of the substrate; forming a second conductive structure along the second surface of the substrate covering the first isolation structure and the active strip at one end away from the first surface of the substrate; wherein a portion of the second conductive structure covering the active strip at one end away from the first surface of the substrate reacts with the active strip; a portion of the second conductive structure covering the first isolation structure at one end away from the first surface of the substrate does not react with the first isolation structure; at least removing the portion of the second conductive structure that does not react with the first isolation structure to form a plurality of bit lines; filling the bit lines with insulating material to form a bit line isolation structure; the plurality of bit lines and the plurality of bit line isolation structures are spaced apart and extend along a first direction.

[0021] In some embodiments, a plurality of second-type bit lines are located in a first region; a plurality of first-type bit lines are located in a second region and a third region; the second region and the third region are located on opposite sides of the first region along the active pillar arrangement direction; forming at least one bit line lead includes: forming at least one bit line lead outside the active pillar array region; each bit line lead connects to a paired bit line; one bit line of all paired bit lines comes from the second region and the other bit line comes from the third region; or, some paired bit lines all come from the second region and the remaining paired bit lines all come from the third region; or, some paired bit lines all come from the second region, another portion of paired bit lines all come from the third region, and one bit line of the remaining paired bit lines comes from the second region and the other bit line comes from the third region.

[0022] In some embodiments, the manufacturing method further includes: forming a first word line contact corresponding to an odd-numbered row word line and a second word line contact corresponding to an even-numbered row word line outside the active column array region; and forming a first bit line contact corresponding to an odd-numbered column bit line and a second bit line contact corresponding to an even-numbered column bit line outside the active column array region; wherein the first word line contact and the second word line contact are located on both sides of the active column array along the row active column arrangement direction; and the first bit line contact and the second bit line contact are located on both sides of the active column array along a direction perpendicular to the row active column arrangement direction.

[0023] In various embodiments of this application, by setting the row active column arrangement direction and the column active column arrangement direction to an intersecting but non-orthogonal angle (e.g., an angle of 60 degrees), and by specially leading out at least some bit lines (e.g., at least some bit lines are connected by bit line leads to form paired bit lines), the logical address addressing of the data lines is ensured to be normal. This can achieve the increase of storage cells per unit density while reducing parasitic capacitance and reducing row hammer effect. Attached Figure Description

[0024] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0025] Figure 1 This is a top-view schematic diagram of the structure of a DRAM transistor in related technologies;

[0026] Figure 2 A top plan view of a semiconductor structure including an active pillar array, provided for an embodiment of this application;

[0027] Figure 3 A three-dimensional perspective schematic diagram of a semiconductor structure including an active pillar array, provided for embodiments of this application;

[0028] Figure 4 for Figure 3 A three-dimensional structural diagram of an array element in an active column array;

[0029] Figure 5 This is a schematic diagram illustrating the implementation process of a semiconductor structure manufacturing method according to an embodiment of this application;

[0030] Figures 6A to 6M A top view schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of this application;

[0031] Figure 6N , Figure 6O and Figure 6P Top plan view of the manufacturing process of some other semiconductor structures provided in the embodiments of this application;

[0032] Figure 7A and Figure 7B A schematic diagram illustrating several different arrangements of storage capacitors provided in the embodiments of this application;

[0033] Figure 8A , Figure 8B and Figure 8C These are schematic diagrams illustrating several different structural forms of storage capacitors provided in embodiments of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of the application will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0035] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0036] In the various embodiments of this application, the first direction is a direction that intersects with but is not orthogonal to the second direction, and is parallel to the surface of the substrate. The third direction is a direction perpendicular to the surface of the substrate (or a perpendicular direction). The first direction can be understood as the direction in which the active pillars in the active pillar array are arranged in columns, or the direction in which the bit lines in the active pillar array extend. The second direction can be understood as the direction in which the active pillars in the active pillar array are arranged in rows, or the direction in which the word lines in the active pillar array extend. The third direction can be understood as the direction in which each element, component, region, layer, or part is stacked, or the direction in which each active pillar in the active pillar array extends. For example, the first direction is represented by the D1 direction in the figure; the second direction is represented by the D2 direction or the X direction in the figure; the third direction is represented by the Z direction in the figure, and the Y direction in the figure is parallel to the surface of the substrate and orthogonal to the X direction.

[0037] Because transistors can be fabricated on silicon substrates, they can be used in various types of memory, such as DRAM. Typically, DRAM consists of multiple memory cell structures, each of which mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, DRAM includes an architecture of 1T1C (Transistor T and Capacitor C).

[0038] refer to Figure 1 In one type of DRAM memory array architecture, word line isolation can mitigate the row hammer effect. Due to the existence of word line isolation, the pitch of back-to-back (B2B) word lines is relatively large, which is not conducive to increasing the unit storage density. The row active columns are arranged orthogonally to the column active columns, and the active columns of adjacent rows are aligned with each other, which is not conducive to improving the row hammer effect.

[0039] refer to Figure 2 This application provides a memory by setting the row active column arrangement direction and the column active column arrangement direction to an intersecting but non-orthogonal angle θ (e.g., the angle θ = 60 degrees), and by specially leading out at least some bit lines (e.g., in conjunction with reference to...). Figure 6M (At least some bit lines are connected by bit line leads to form paired bit lines) to ensure that the logical address addressing of the data lines is normal. This can increase the number of storage cells per unit density while reducing parasitic capacitance and reducing row hammer effect.

[0040] refer to Figure 3 and Figure 4 In a first aspect, embodiments of this application provide a semiconductor structure comprising: an active pillar array; each active pillar including a first source / drain, a channel, and a second source / drain disposed in a vertical direction; multiple word lines; each word line completely surrounding the channel of each active pillar in a row of active pillars in the active pillar array; multiple memory cells; each memory cell being connected to a first source / drain; multiple bit lines, including multiple first-type bit lines and multiple second-type bit lines; each bit line being connected to the second source / drain of each active pillar in a column of active pillars in the active pillar array; the row active pillar arrangement direction intersects with the column active pillar arrangement direction but is not orthogonal; at least one bit line lead; each bit line lead connecting two of the multiple first-type bit lines to form a paired bit line; the number of active pillars in the column active pillars corresponding to each paired bit line is the same as the number of active pillars in the column active pillars corresponding to each second-type bit line.

[0041] It should be noted that the reference Figure 3The diagram does not show the case where each bit line lead connects to two of the multiple Type 1 bit lines to form a paired bit line. For details on how at least some bit lines are connected to form paired bit lines via bit line leads, please refer to [link to relevant documentation]. Figure 6M , Figure 6N , Figure 6O , Figure 6P Detailed explanation of the relevant parts.

[0042] It should be noted that, in order to clearly show the positional relationships between word lines, bit lines, array cells, etc., as... Figure 3 and Figure 4 Isolation structures are not shown, for example, word line isolation structures between adjacent word lines are not shown, bit line isolation structures between adjacent bit lines are not shown, and isolation structures between adjacent memory cells (e.g., capacitors) are not shown.

[0043] refer to Figure 3 and Figure 4 In some embodiments, each word line includes a plurality of first portions 1161 and a plurality of second portions 1162; each first portion 1161 fully surrounds the channel of an active post in a corresponding row of active posts, and each second portion 1162 connects two adjacent first portions 1161; wherein the dimension H1 of the first portion 1161 in the vertical direction is greater than the dimension H2 of the second portion 1162 in the vertical direction.

[0044] The first part 1161 can also be understood as the gate of the transistor, which completely surrounds the channel of the corresponding active pillar. The second part 1162 can also be understood as the gate connection line used to connect the gates of adjacent transistors. The transistor gate uses a gate-around architecture, and the dimension H2 of the gate connection line in the vertical direction is smaller than the dimension H1 of the transistor gate in the vertical direction, which can reduce the hammer effect.

[0045] refer to Figure 3 and Figure 4 In some embodiments, the dimension W1 of the first portion 1161 along the column active column arrangement direction is larger than the dimension W2 of the second portion 1162 along the column active column arrangement direction. This allows for an increase in memory cells per unit density while reducing parasitic capacitance and mitigating row hammer effect.

[0046] refer to Figure 3 and Figure 4 In some embodiments, the thickness dimension W3 of the first portion 1161 along the direction of the active column arrangement is less than or equal to the thickness dimension H2 of the second portion along the vertical direction.

[0047] In some embodiments, an active column is provided at the intersection of the row active column arrangement direction and the column active column arrangement direction; the row active column arrangement direction and the column active column arrangement direction have an angle θ; the angle θ ranges from greater than 0 degrees to less than 90 degrees.

[0048] In some embodiments, the angle θ between the row active column arrangement direction and the column active column arrangement direction can be any angle within the range of greater than 0 degrees and less than 90 degrees. Preferably, the angle θ ranges from 45 degrees to 75 degrees. For example, the angle θ can be 50 degrees, 60 degrees, or 70 degrees.

[0049] refer to Figure 3 In some embodiments, the included angle θ is 60 degrees, and the active column array arrangement includes a close-packed hexagonal arrangement; or, the included angle θ is 45 degrees, and the active column array arrangement includes a square arrangement; or, the included angle θ is 75 degrees, and the active column array arrangement includes a rhombus arrangement.

[0050] When the row active column arrangement direction and the column active column arrangement direction form an angle θ of 60 degrees, the active column array presents a close-packed hexagonal arrangement; or, when the row active column arrangement direction and the column active column arrangement direction form an angle θ of 45 degrees, the active column array presents a square arrangement. Figure 3 Not shown, please refer to Figure 6O (For understanding); or, if the row active column arrangement direction and the column active column arrangement direction have an angle θ of 75 degrees, the active column array can be arranged in a diamond shape. Figure 3 Not shown, please refer to Figure 6N (To understand).

[0051] refer to Figure 3 and Figure 6M In some embodiments, multiple second-type bit lines are located in a first region; multiple first-type bit lines are located in a second region and a third region; the second region and the third region are located on opposite sides of the first region along the row active post arrangement direction; one bit line of all paired bit lines comes from the second region and the other bit line comes from the third region; or, some paired bit lines all come from the second region and the remaining paired bit lines all come from the third region; or, some paired bit lines all come from the second region, the other paired bit lines all come from the third region, and one bit line of the remaining paired bit lines comes from the second region and the other bit line comes from the third region.

[0052] The number of active columns in the column active column corresponding to each type 1 bit line is less than the number of active columns in the column active column corresponding to each type 2 bit line. Bit line leads are used to pair two bit lines (or two type 1 bit lines) from non-first region bit lines to obtain paired bit lines. The number of active columns in the column active column corresponding to each paired bit line is the same as the number of active columns in the column active column corresponding to each type 2 bit line. Each paired bit line and each type 2 bit line can ensure that the logical address addressing of the data line is normal.

[0053] refer to Figure 6MFor example, the number of at least one bit line lead includes an even number, such as two bit line leads CL1 and CL2, wherein bit line lead CL1 pairs and connects two bit lines 1282a and 1282b from the second region to form a paired bit line PBL, and bit line lead CL2 pairs and connects two bit lines 1283a and 1283b from the third region to form a paired bit line PBL.

[0054] refer to Figure 3 In some embodiments, the semiconductor structure further includes: a first word line contact corresponding to an odd-numbered row of word lines (see reference). Figure 2 ) and the second word line of the corresponding even-numbered word line (refer to) Figure 2 ), and the first line contact of the corresponding odd-numbered column line ( Figure 2 and Figure 3 (not shown) and the second bit line contacting the corresponding even-numbered column bit line ( Figure 2 and Figure 3 (Not shown); wherein, the first word line contact and the second word line contact are located on both sides of the active column array along the row active column arrangement direction; the first bit line contact and the second bit line contact are located on both sides of the active column array along the direction perpendicular to the row active column arrangement direction.

[0055] refer to Figure 3 In some embodiments, the semiconductor structure further includes an active pillar connection portion; the active pillar connection portion is integrally formed with each column of active pillars and extends along the arrangement direction of the column of active pillars; the column of active pillars is located on the active pillar connection portion; wherein, the bit line covers the end of the active pillar connection portion away from the active pillars.

[0056] refer to Figure 3 In some embodiments, multiple storage cells are arranged in a square (see reference). Figure 7A Or arranged in a hexagonal pattern (see reference) Figure 7B ).

[0057] refer to Figure 3 and Figure 4 In some embodiments, the storage unit includes a storage capacitor; one end of the storage capacitor is connected to the first source / drain of an active pillar in the active pillar array, and the other end of the storage capacitor is grounded. The storage capacitor is used to store the written data.

[0058] In some embodiments, the storage capacitor includes a cup-shaped, cylindrical, or pillar-shaped capacitor.

[0059] For example, such as Figure 8A As shown, the storage capacitor 302 may include a cup-shaped capacitor CUP; for example, as Figure 8B As shown, the storage capacitor 302 may include a cylindrical capacitor CYL; exemplarily, as... Figure 8CAs shown, the storage capacitor 302 may include a pillar-shaped capacitor PIL. The cup-shaped capacitor CUP, the cylindrical capacitor CYL, and the pillar-shaped capacitor PIL all include a bottom electrode 3021, a top electrode 3023, and a dielectric layer 3022 located between the bottom electrode 3021 and the top electrode 3023. It should be noted that the bottom electrode 3021 is connected to the first source / drain of an active pillar in the active pillar array, the top electrode 3023 of the cup-shaped capacitor CUP is grounded, and the cup-shaped capacitor CUP is used to store the written data.

[0060] It should be noted that, when the areas of the bottom electrode 3021 in the cup-shaped capacitor (CUP), cylindrical capacitor (CYL), and pillar-shaped PIL are equal, the top electrode 3023 of the cylindrical capacitor (CYL) has the largest area, followed by the top electrode 3023 of both the cylindrical capacitor (CYL) and the pillar-shaped PIL. Therefore, in practical applications, the cylindrical capacitor (CYL) can be used as the storage unit of a memory, which is beneficial for achieving extremely high memory integration.

[0061] The semiconductor structure provided in the various embodiments of this application, by setting the row active pillar arrangement direction and the column active pillar arrangement direction to an intersecting but non-orthogonal angle (e.g., an angle of 60 degrees), and by specially leading out at least some bit lines (e.g., at least some bit lines are connected by bit line leads to form paired bit lines), ensures that the logical address addressing of the data lines is normal. This can achieve the increase of memory cells per unit density while reducing parasitic capacitance and reducing row hammer effect.

[0062] In a second aspect, embodiments of this application provide a memory, the memory comprising: any of the semiconductor structures provided in the embodiments of the first aspect; the memory includes a dynamic random access memory, and the memory cell includes a storage capacitor; the word lines of the semiconductor structure are configured to receive a word line voltage and control the channel of the active pillar to be turned on or off via the word line voltage, for connecting / disconnecting the first source / drain and the second source / drain of the semiconductor structure; the bit lines of the semiconductor structure are configured to perform read or write operations on the memory cell of the semiconductor structure when the channel of the active pillar is turned on.

[0063] In some embodiments, even-numbered bit lines are configured to receive word line voltage to control the channel conduction of the corresponding active pillar, and even-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the active pillar's channel is conduction; odd-numbered bit lines are configured to receive a default voltage to shield the even-numbered bit lines; or, odd-numbered bit lines are configured to receive word line voltage to control the channel conduction of the corresponding active pillar, and odd-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the active pillar's channel is conduction; even-numbered bit lines are configured to receive a default voltage to shield the odd-numbered bit lines.

[0064] When even-numbered bit lines are enabled, only even-numbered bit lines are active. Odd-numbered bit lines between adjacent active even-numbered bit lines are given a default voltage (e.g., pre-charge voltage VCC / 2), which acts as a metallic shield, reducing the parasitic capacitance between adjacent active even-numbered bit lines. The same principle applies when odd-numbered bit lines are enabled. For example, when word line WL_2n (even-numbered bit lines) is enabled, bit lines BL_2n and BL_2n+2 (adjacent even-numbered bit lines) are active, and bit line BL_2n+1 (odd-numbered bit lines between adjacent even-numbered bit lines) acts as a shield, where n represents a natural number.

[0065] The memory provided in the various embodiments of this application, by setting the row active column arrangement direction and the column active column arrangement direction to an intersecting but non-orthogonal angle (e.g., an angle of 60 degrees), and by specially leading out at least some bit lines (e.g., at least some bit lines are connected by bit line leads to form paired bit lines), ensures that the logical address addressing of the data lines is normal. This can achieve the increase of storage cells per unit density while reducing parasitic capacitance and reducing row hammer effect.

[0066] Figure 5 This is a schematic diagram illustrating the implementation process of a semiconductor structure manufacturing method provided in this application.

[0067] Thirdly, embodiments of this application provide a method for manufacturing a semiconductor structure, such as... Figure 5 As shown, the manufacturing method includes the following steps:

[0068] Step S501, provide a substrate;

[0069] Step S502: An active pillar array is formed along the first surface of the substrate; the row active pillar arrangement direction of the active pillar array intersects with the column active pillar arrangement direction of the active pillar array but is not orthogonal; each active pillar is used to form a first source / drain, a channel, and a second source / drain, which are arranged in a vertical direction.

[0070] Step S503: Form multiple word lines; each word line completely surrounds the channel of each active column in a row of active columns of the active column array;

[0071] Step S504: Multiple memory cells are formed; each memory cell is connected to a first source / drain.

[0072] Step S505: Multiple bit lines are formed along the second surface of the substrate; the multiple bit lines include multiple first-type bit lines and multiple second-type bit lines; each bit line is connected to the second source / drain of each active pillar in a column of active pillars of the active pillar array; the second surface is the opposite surface to the first surface in the thickness direction of the substrate;

[0073] Step S506: Form at least one bit line lead; each bit line lead connects two of the multiple first-type bit lines to form a paired bit line; the number of active columns in the column active columns corresponding to each paired bit line is the same as the number of active columns in the column active columns corresponding to each second-type bit line.

[0074] Figures 6A to 6M This is a top plan view illustrating the manufacturing process of a semiconductor structure provided in an embodiment of this application. It should be understood that... Figure 5 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 5 The steps shown can be rearranged in order according to actual needs. The following section combines... Figure 5 , Figures 6A to 6M The manufacturing method of the semiconductor structure provided in the embodiments of this application will be described in detail.

[0075] In various embodiments of this application, the second surface (or back side) of the substrate is the opposite surface to the first surface (or front side) of the substrate along a third direction (or perpendicular direction). Some elements, components, regions, layers, or portions of the semiconductor structure can be fabricated on the first surface of the substrate, and other elements, components, regions, layers, or portions of the semiconductor structure can be fabricated on the second surface of the substrate. For example, a first source / drain of the semiconductor structure can be fabricated on the first surface of the substrate, and a second source / drain of the semiconductor structure can be fabricated on the second surface of the substrate. As another example, word lines of the semiconductor structure can be fabricated on the first surface of the substrate, and bit lines of the semiconductor structure can be fabricated on the second surface of the substrate.

[0076] refer to Figure 6A Step S501 is executed to provide a substrate.

[0077] In some embodiments, the material of substrate 102 may include silicon (Si) substrate, germanium (Ge) substrate, silicon germanide (SiGe) substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc.

[0078] In some embodiments, the substrate 102 can be selected according to the actual needs of the semiconductor device. The substrate 102 has a composite stack structure, which includes a bottom substrate layer (not shown), a pad oxide layer (not shown), and a top substrate layer (not shown) stacked sequentially. The material of the top substrate layer may include silicon, germanium, or germanium-silicon; the material of the bottom substrate layer may include silicon, the material of the pad oxide layer may include silicon oxide, and the material of the top substrate layer may include polycrystalline silicon. In some specific embodiments, the pad oxide layer on the bottom substrate layer and the top substrate layer can both be formed using processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0079] In some embodiments, the substrate 102 is doped with certain impurity ions as needed. The impurity ions can be N-type or P-type impurity ions. In one embodiment, the doping includes well region doping and source / drain region doping to form an active layer (not shown) in the substrate 102. The active region is used to include the formation of active pillars.

[0080] In this way, the resulting substrate structure is a composite stacked structure, which is suitable for subsequent processes to be carried out on the front and back sides of the substrate. For example, transistors (including word lines) are manufactured on the front side of the substrate, and bit lines are manufactured on the back side of the substrate.

[0081] In various embodiments of this application, the etching (or removal) processes employed may include wet etching processes, dry etching processes, etc. For example, plasma etching processes. The deposition (or filling) processes employed may include PVD processes, CVD processes, or ALD processes, etc. For example, plasma enhanced chemical vapor deposition (PECVD) processes.

[0082] refer to Figure 6B , Figure 6C Then, execute step S502 to form an active column array.

[0083] In some embodiments, forming an active pillar array along a first surface of a substrate includes: forming a plurality of spaced-apart first trenches and active strips along the first surface of the substrate, wherein the first trenches and active strips extend along a first direction; filling the first trenches with insulating material to form a first isolation structure; forming a plurality of spaced-apart second trenches along the first surface of the substrate in the first isolation structure and active strips, wherein the second trenches extend along a second direction; filling the second trenches with insulating material to form a second isolation structure; the plurality of second isolation structures divide each active strip into a plurality of active pillars extending along a third direction; wherein the dimension of the second trench along the third direction is smaller than the dimension of the first trench along the third direction; the third direction is perpendicular to the plane formed by the first direction and the second direction; there is an angle between the first direction and the second direction; the angle range is greater than 0 degrees and less than 90 degrees.

[0084] refer to Figure 6B The first shallow trench isolation (STI) process can be used to etch a first trench T1 extending along the first direction D1 in the substrate 102 along the first surface of the substrate, forming multiple spaced first trenches T1 and active strips 104 in the substrate; an insulating material is deposited in the first trench T1 and chemical mechanical polishing (CMP) is performed so that the surface of the insulating material is flush with the surface of the substrate 102, forming a first isolation structure 106 filling the first trench T1, resulting in multiple spaced first isolation structures 106 and active strips 104 formed in the substrate 102.

[0085] In various embodiments of this application, the insulating material may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials.

[0086] refer to Figure 6C A second shallow trench isolation process can be used to etch a second trench T2 extending along the second direction D2 in the first isolation structure 106 and the active strip 104 along the first surface of the substrate. Multiple second trenches T2 divide each active strip into several active pillars 110 extending along the third direction. Insulating material is deposited in the second trenches T2 and CMP treatment is performed so that the surface of the insulating material is flush with the surface of the substrate 102, forming a second isolation structure 108 that fills the second trenches T2, resulting in multiple active pillars arranged in an array in the substrate 102.

[0087] In some embodiments, the first trench T1 and the second trench T2 may be formed by one or more patterning processes. These patterning processes include, but are not limited to, double-patterning technology (DPT), quadruple-patterning technology (QPT), or any combination thereof.

[0088] By employing a first shallow trench isolation process and a second shallow trench isolation process, the extension direction of the first trench T1 and the extension direction of the second trench T2 intersect but are not orthogonal at an angle θ, i.e. the angle θ is greater than 0 degrees and less than 90 degrees, which can achieve the intersecting but non-orthogonal arrangement direction of the row active column array and the column active column array.

[0089] In some embodiments, the angle θ between the extending direction of the first groove T1 and the extending direction of the second groove T2 can be any angle within the range of greater than 0 degrees and less than 90 degrees. Preferably, the angle θ ranges from 45 degrees to 75 degrees. For example, the angle θ can be 50 degrees, 60 degrees, or 70 degrees.

[0090] In some embodiments, the angle θ between the extension direction of the first trench T1 and the extension direction of the second trench T2 is 60 degrees, which can result in a close-packed hexagonal arrangement of the active pillar array; or, the angle θ between the extension direction of the first trench T1 and the extension direction of the second trench T2 is 45 degrees, which can result in a square arrangement of the active pillar array; or, the angle θ between the extension direction of the first trench T1 and the extension direction of the second trench T2 is 75 degrees, which can result in a rhomboid arrangement of the active pillar array.

[0091] In the following examples, the angle θ between the row active column arrangement direction and the column active column arrangement direction is 60 degrees, but this is not intended to limit the embodiments of this application.

[0092] The dimension of the second trench T2 along the third direction is smaller than the dimension of the first trench T1 along the third direction. In subsequent processes, word lines can be formed in the second trench T2 along the first surface of the substrate; bit lines are formed along the second surface of the substrate using the end of the second trench T2 away from the first surface of the substrate. The bit lines and word lines can be staggered from each other in the third direction (for example, see the section on self-aligned bit lines below for the specific bit line formation process).

[0093] The extension direction of the first trench T1 and the extension direction of the second trench T2 intersect at a non-orthogonal angle θ. In subsequent processes, word lines can be formed in the second trench T2 along the first surface of the substrate; bit lines are formed along the second surface of the substrate using the end of the second trench T2 away from the first surface of the substrate. The bit line extension direction and the word line extension direction intersect at a non-orthogonal angle θ, and at least some bit lines are connected by bit line leads to form paired bit lines, ensuring normal logical addressing of data lines. This allows for an increase in memory cells per unit density while reducing parasitic capacitance and mitigating row hammer effect.

[0094] refer to Figures 6D to 6G Step S503 forms multiple character lines.

[0095] In some embodiments, forming multiple word lines includes: removing a portion of a first isolation structure and a portion of a second isolation structure along a first surface of a substrate to form a third trench; the third trench completely surrounds and exposes at least a portion of the sidewalls of each active pillar; in the third trench, a gate dielectric layer, a first conductive structure, and a third isolation structure are formed sequentially covering the third trench; removing at least a portion of the third isolation structure and a portion of the first conductive structure along the first surface of the substrate to form a word line isolation trench; the word line isolation trench extends along a second direction and is located between adjacent row active pillars; multiple word line isolation trenches divide the first conductive structure into multiple word lines extending along the second direction; filling the word line isolation trenches with insulating material to form a word line isolation structure; wherein the dimension of the word line isolation trench along a third direction is larger than the dimension of the third trench along a third direction; the dimension of the third trench along a third direction is smaller than the dimension of the second trench along a third direction; each word line includes multiple first portions and multiple second portions; each first portion completely surrounds the channel of one active pillar in a corresponding row of active pillars, and each second portion connects two adjacent first portions; wherein the dimension of the first portion along a third direction is larger than the dimension of the second portion along a third direction.

[0096] refer to Figure 6DAn etching process, such as wet etching, can be used to remove a portion of the first isolation structure 106 and a portion of the second isolation structure 108 to form a third trench T3. The dimension of the third trench T3 along the third direction is smaller than the dimension of the second trench T2 along the third direction. It is understood that removing a portion of the first isolation structure 106 and a portion of the second isolation structure 108 along the third direction at the gap between adjacent active pillars 110 yields the third trench T3 located at the gap between adjacent active pillars 110. The third trench T3 completely surrounds and exposes at least a portion of the sidewall of each active pillar 110, while another portion of the sidewall of each active pillar 110 is covered by the remaining first isolation structure 106 and the remaining second isolation structure 108. It should be noted that the interface between the remaining first isolation structure 106 and the remaining second isolation structure 108 is not shown, but is used to clearly illustrate the relationships between other components / layers / structures, etc. Figure 6D The first isolation structure 106 and the second isolation structure 108 that have not been removed are shown as a whole.

[0097] In some embodiments, the cross-sectional shape of the active column 110 can be changed from a quadrilateral (see reference) through an oxidation process. Figure 6C (Refer to) It changes to an oval or circle (see reference) Figure 6D The elliptical or cylindrical active pillar 110 also provides a stable structure for the subsequent formation of transistor channels, which helps to reduce transistor defects, leakage current, etc., and improve transistor performance.

[0098] refer to Figure 6E In some embodiments, a gate dielectric layer conformally covering the third trench T3 can be formed by a deposition process. In some embodiments, an in-situ oxidation process can also be used to oxidize at least a portion of the sidewalls of each active pillar 110 exposed in the third trench T3 by heating or pressurizing, forming a gate dielectric layer 112 that completely surrounds at least a portion of the sidewalls of each active pillar 110. The material of the gate oxide layer 112 includes, but is not limited to, silicon oxide.

[0099] refer to Figure 6E and Figure 6F In some embodiments, a first conductive structure 114 conformally covering the third trench T3 can be formed by a deposition process to obtain a fourth trench T4. The dimension of the fourth trench T4 along the third direction is smaller than the dimension of the third trench T3 along the third direction. A gate dielectric layer 112 is included between the first conductive structure 114 and the active pillar 110. The material of the first conductive structure 114 includes, but is not limited to, tungsten (W). It should be noted that the shape of the fourth trench T4 can refer to the shape of the third trench T3, and the fourth trench T4 is located in the gap between adjacent active pillars 110.

[0100] In some embodiments, the first conductive structure 114 includes a first conductive layer, a second conductive layer and a third conductive layer stacked sequentially, wherein the material of the first conductive layer includes polysilicon, the material of the second conductive layer includes titanium nitride, and the material of the third conductive layer includes tungsten; a gate dielectric layer 112 is included between the first conductive layer and the original pillar 110.

[0101] In some embodiments, insulating material is deposited in the fourth trench T4 and CMP is performed to remove at least the first conductive structure and insulating material located on the top surface of the active pillar, such that the surface of the insulating material is flush with the top surface of the active pillar; by an etch-back process, a portion of the first conductive structure surrounding the active pillar is removed along the first surface of the substrate in a third direction to form a recess, and insulating material is filled in the recess to embed the first conductive structure into the substrate structure.

[0102] refer to Figure 6G In some embodiments, word line isolation trenches T5 can be formed by a lithography-etch (LE) process, wherein the dimension of word line isolation trench T5 along the third direction is greater than the dimension of the third trench T3 along the third direction.

[0103] The active strip 102 can be etched using a dry etching process, such as plasma etching or reactive ion etching. At least a portion of the third isolation structure and a portion of the first conductive structure are removed along the first surface of the substrate to form a word line isolation trench T5. The word line isolation trench T5 extends along the second direction and is located between adjacent row active pillars. The dimension of the word line isolation trench T5 along the third direction is larger than the dimension of the third trench T3 along the third direction. Multiple word line isolation trenches T5 divide the first conductive structure into multiple word lines extending along the second direction. An insulating material is filled in the third trench to form a word line isolation structure. Figure 6G (Not shown).

[0104] refer to Figure 6G In some embodiments, the opening pattern of the photomask can be set by a photolithography-etching process. The opening pattern can be a pattern complementary to the word line 161 pattern. Through the opening pattern, the etching process forms the word line isolation trench T5 to obtain the word line 116 of the corresponding size.

[0105] In some embodiments, each word line 161 includes a plurality of first portions 1161 and a plurality of second portions 1162; each first portion 1161 fully surrounds the channel of an active post in a corresponding row of active posts, and each second portion 1162 connects two adjacent first portions; wherein the dimension of the first portion 1161 along a third direction is greater than the dimension of the second portion 1162 along a third direction.

[0106] In some embodiments, the dimension of the first portion 1161 along the column active column arrangement direction is greater than the dimension of the second portion 1162 along the column active column arrangement direction.

[0107] In some embodiments, the thickness of the first portion 1161 along the direction of the active column arrangement is less than or equal to the thickness of the second portion 1162 along the vertical direction.

[0108] In some embodiments, after forming multiple word line isolation structures, the manufacturing method further includes: doping one end of the active pillar near the first surface of the substrate along the first surface of the substrate to form a first source / drain. In some embodiments, the active pillar is doped with a certain amount of impurity ions on the first surface of the substrate; the impurity ions can be N-type impurity ions or P-type impurity ions.

[0109] refer to Figure 6H and Figure 6I Step S504: Multiple storage units are formed.

[0110] In some embodiments, forming a plurality of memory cells includes: forming a plurality of memory cell contacts on a first source / drain; each memory cell contact being connected to a first source / drain; forming a plurality of memory cells on the memory cell contacts; and each memory cell being connected to a memory cell contact.

[0111] refer to Figure 6H In some embodiments, a deposition process can be used to form an insulating material covering the first surface of the substrate. A plurality of memory cell contact openings can be formed in this insulating material using a photolithography-etching process to obtain a first dielectric layer 120, where each memory cell contact opening exposes at least a portion of the top surface of an active pillar. A deposition process can be used to deposit conductive material in the plurality of memory cell contact openings to form memory cell contacts 122 covering at least a portion of the top surface of the active pillar. In some embodiments, the memory cell contacts 122 are connected to the first source / drain of the active pillar.

[0112] refer to Figure 6I In some embodiments, a deposition process can be used to form an insulating material covering the first surface of the substrate; a plurality of memory cell openings can be formed in the insulating material by a photolithography-etching process to obtain a second dielectric layer 124, each memory cell opening exposing at least a portion of the top surface of a memory cell contact; a deposition process can be used to form memory cells 126 covering at least a portion of the top surface of the memory cell contacts in the plurality of memory cell openings. In some embodiments, the memory cell 126 is connected to the first source / drain of the active pillar through the memory cell contact 122.

[0113] In some embodiments, the storage cell 126 includes a storage capacitor. One end of the storage capacitor 302 is connected to the first source / drain of a transistor in the transistor array, and the other end of the storage capacitor 302 is grounded. The storage capacitor 302 is used to store written data.

[0114] In practical applications, multiple storage capacitors can be arranged in various shapes.

[0115] In some embodiments, the plurality of storage capacitors are arranged in a square or in a hexagonal arrangement.

[0116] For example, such as Figure 7A In the XY top view plane, the array layout of the storage capacitors 302 can be arranged in a square. For example, as... Figure 7B In the XY top view plane, the array layout of the storage capacitors 302 can be arranged in a hexagonal shape.

[0117] In practical applications, storage capacitors can take on various structures.

[0118] refer to Figure 8A , Figure 8B , Figure 8C In some embodiments, the storage capacitor includes cup-shaped, cylindrical, or pillar-shaped capacitors.

[0119] refer to Figure 6J and Figure 6K Step S505: Multiple bit lines are formed.

[0120] In some embodiments, forming a plurality of bit lines along the second surface of a substrate includes: thinning the substrate along the second surface to expose a first isolation structure and an active strip at one end away from the first surface of the substrate; forming a second conductive structure along the second surface of the substrate covering the first isolation structure and the active strip at one end away from the first surface of the substrate; wherein a portion of the second conductive structure covering the active strip at one end away from the first surface of the substrate reacts with the active strip; a portion of the second conductive structure covering the first isolation structure at one end away from the first surface of the substrate does not react with the first isolation structure; at least removing the portion of the second conductive structure that does not react with the first isolation structure to form a plurality of bit lines; filling the bit lines with insulating material to form a bit line isolation structure; the plurality of bit lines and the plurality of bit line isolation structures are spaced apart and extend along a first direction.

[0121] In some embodiments, after thinning the substrate, the manufacturing method further includes: doping the active strip (also called the active pillar connection portion) and one end of the active pillar near the second surface of the substrate along the second surface of the substrate to form a second source / drain. The second source / drain and the first source / drain are located at opposite ends of the channel along a third direction. In some embodiments, the active pillar is doped with a certain amount of impurity ions on the second surface of the substrate; the impurity ions can be N-type impurity ions or P-type impurity ions. The second source / drain and the first source / drain have the same doping type.

[0122] refer to Figure 6J The substrate 102 containing the active pillar array is flipped, and the substrate 102 is thinned starting from the second surface of the substrate 102 using an etching process or a CMP process to expose the first isolation structure and the end of the active strip away from the first surface of the substrate. The first isolation structure 106 and the active strip 104 are arranged alternately at the first direction D1 at the end away from the first surface of the substrate.

[0123] refer to Figure 6K A second conductive structure, such as a material like NiPt, is deposited using a deposition process. Starting from the second surface of the substrate 102, and using the bit line isolation structure 106 as a mask, the deposited second conductive structure can diffuse in the active strip 104 and react with the active strip 104 along the third direction, for example, to form silicide, but does not react with the first isolation structure 106.

[0124] A wet etching process can be used to remove the unreacted second conductive structure in the region covering the first isolation structure away from the first surface of the substrate, leaving bit line 128.

[0125] A bit line isolation structure 130 is formed to fill the spaces between the bit lines; multiple bit lines 128 and multiple bit line isolation structures 130 are spaced apart and extend along a first direction. The material of the bit lines 128 includes, but is not limited to, tungsten (W). The material of the bit line isolation structure 130 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials. In some embodiments, the bit line isolation structure 130 includes an air gap.

[0126] In some embodiments, bit line 128 includes a fourth conductive layer, a fifth conductive layer and a sixth conductive layer stacked sequentially, wherein the material of the fourth conductive layer includes polysilicon, the material of the fifth conductive layer includes titanium nitride, and the material of the sixth conductive layer includes tungsten; the fourth conductive layer is in contact with the active strip 104.

[0127] In some embodiments, one end of the active strip of bit line 128 away from the first surface of substrate 102 is connected to the second source / drain of the active pillar in the column of active pillars.

[0128] refer to Figure 6L To clearly show the positional relationship between word line 116 and bit line 128, in Figure 6K Based on perspective, the character line 116 is obtained. Figure 6L The extension directions of word line 116 and bit line 128 are set at an angle θ that intersects but is not orthogonal. That is, the row active pillar arrangement direction and column active pillar arrangement direction are set at an angle θ that intersects but is not orthogonal. Adjacent rows of active pillars are staggered along directions perpendicular to the row active pillar arrangement direction, increasing the array cell density and reducing parasitic capacitance and row hammer effect. For example, if the extension directions of word line 116 and bit line 128 are set at an angle θ = 60 degrees, the active pillar array will present a close-packed hexagonal arrangement, increasing the array cell density and reducing parasitic capacitance and row hammer effect.

[0129] refer to Figure 6M Step S506: Form at least one bit line lead.

[0130] In some embodiments, a plurality of second-type bit lines are located in a first region; a plurality of first-type bit lines are located in a second region and a third region; the second region and the third region are located on opposite sides of the first region along the active pillar arrangement direction; forming at least one bit line lead includes: forming at least one bit line lead outside the active pillar array region; each bit line lead connects to a paired bit line; one bit line of all paired bit lines comes from the second region and the other bit line comes from the third region; or, some paired bit lines all come from the second region and the remaining paired bit lines all come from the third region; or, some paired bit lines all come from the second region, another portion of paired bit lines all come from the third region, and one bit line of the remaining paired bit lines comes from the second region and the other bit line comes from the third region.

[0131] In some embodiments, after the substrate is thinned, at least one bit line lead opening can be formed by photolithography-etching process. The bit line lead opening exposes the surface of the thinned substrate 102 and connects to the surface of the end of the active strip away from the first surface of the substrate 102. A deposition process and a wet etching process (refer to the bit line 128 formation process) can be used to deposit a second conductive structure on the surface of the end of the active strip away from the first surface of the substrate 102 and to deposit a second conductive structure in at least one bit line lead opening, so that the integrally formed bit line 128 and bit line lead (e.g., bit line lead CL1, bit line lead CL2) are obtained simultaneously.

[0132] The number of active columns in the column active column corresponding to each type 1 bit line is less than the number of active columns in the column active column corresponding to each type 2 bit line. Bit line leads are used to pair two bit lines (or two type 1 bit lines) from non-first region bit lines to obtain paired bit lines. The number of active columns in the column active column corresponding to each paired bit line is the same as the number of active columns in the column active column corresponding to each type 2 bit line. Each paired bit line and each type 2 bit line can ensure that the logical address addressing of the data line is normal.

[0133] Multiple second-class bit lines located in the first region, such as bit line 1281; multiple first-class bit lines located in the second region, such as bit line 1282a and bit line 1282b; multiple first-class bit lines located in the third region, such as bit line 1283a and bit line 1283b.

[0134] refer to Figure 6M For example, the number of at least one bit line lead includes an even number, such as two bit line leads CL1 and CL2, wherein bit line lead CL1 pairs and connects two bit lines 1282a and 1282b from the second region to form a paired bit line PBL, and bit line lead CL2 pairs and connects two bit lines 1283a and 1283b from the third region to form a paired bit line PBL.

[0135] refer to Figure 6O For example, the number of at least one bit line lead includes an even number, such as ten bit line leads, wherein bit line lead CL1 pairs and connects two bit lines 1282a and 1282b from the second region to form a paired bit line PBL, and bit line lead CL2 pairs and connects two bit lines 1283a and 1283b from the third region to form a paired bit line PBL.

[0136] refer to Figure 6N For example, the number of at least one bit line lead may be odd, such as three bit line leads, wherein each bit line lead, such as bit line lead CL1, pairs a bit line 1282a from the second region and a bit line 1283b from the third region to form a paired bit line PBL.

[0137] refer to Figure 6PFor example, the number of at least one bit line lead may be an odd number, such as three bit line leads, wherein bit line lead CL1 pairs and connects two bit lines 1282a and 1282b from the second region to form a paired bit line PBL, bit line lead CL2 pairs and connects two bit lines 1283a and 1283b from the third region to form a paired bit line PBL, and bit line lead CL3 pairs and connects one bit line 1282c from the second region and one bit line 1283c from the third region to form a paired bit line PBL.

[0138] In some embodiments, the manufacturing method further includes: forming first word line contacts corresponding to odd-numbered row word lines outside the active column array region (see reference). Figure 2 ) and the second word line of the corresponding even-numbered word line (refer to) Figure 2 ), and, forming the first line contact of the corresponding odd-numbered column lines outside the active column array region ( Figure 2 (not shown) and the second bit line contacting the corresponding even-numbered column bit line ( Figure 2 (Not shown); wherein, the first word line contact and the second word line contact are located on both sides of the active column array along the row active column arrangement direction; the first bit line contact and the second bit line contact are located on both sides of the active column array along the direction perpendicular to the row active column arrangement direction.

[0139] The semiconductor structure manufactured by the semiconductor structure manufacturing method provided in this application is similar to the semiconductor structure in the embodiments of the first aspect above. For technical features not disclosed in detail in this application, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0140] This application provides a semiconductor structure manufacturing method that produces a semiconductor structure by setting the row active pillar arrangement direction and the column active pillar arrangement direction to an intersecting but non-orthogonal angle (e.g., an angle of 60 degrees), and by specially leading out at least some bit lines (e.g., at least some bit lines are connected by bit line leads to form paired bit lines), ensuring that the logical address addressing of the data lines is normal. This can achieve an increase in the number of memory cells per unit density while reducing parasitic capacitance and reducing the row hammer effect.

[0141] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0142] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0143] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0144] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, include: Active column array; Each of the active pillars includes a first source / drain, a channel, and a second source / drain arranged in a vertical direction; Multiple letter lines; Each of the word lines completely surrounds the channel of each of the active pillars in a row of active pillars of the active pillar array; Multiple storage cells; each of the storage cells is connected to one of the first source / drain terminals; Multiple bit lines, including multiple first-type bit lines and multiple second-type bit lines; each bit line is connected to the second source / drain of each active pillar in a column of the active pillar array; the row active pillar arrangement direction intersects the column active pillar arrangement direction but is not orthogonal; At least one bit line lead; each bit line lead connects two of the plurality of first-type bit lines to form a paired bit line; the number of active columns in the column active columns corresponding to each paired bit line is the same as the number of active columns in the column active columns corresponding to each second-type bit line.

2. The semiconductor structure according to claim 1, characterized in that, Each of the word lines includes a plurality of first portions and a plurality of second portions; each first portion fully surrounds the channel of one of the active columns in a corresponding row, and each second portion connects two adjacent first portions; wherein the dimension of the first portion along the vertical direction is greater than the dimension of the second portion along the vertical direction.

3. The semiconductor structure according to claim 2, characterized in that, The dimension of the first part along the direction of the arrangement of the active columns is greater than the dimension of the second part along the direction of the arrangement of the active columns.

4. The semiconductor structure according to claim 3, characterized in that, The thickness of the first part along the direction of the row of active columns is less than or equal to the thickness of the second part along the vertical direction.

5. The semiconductor structure according to claim 1, characterized in that, An active column is provided at the intersection of the row active column arrangement direction and the column active column arrangement direction; the row active column arrangement direction and the column active column arrangement direction have an angle; the angle range is greater than 0 degrees and less than 90 degrees.

6. The semiconductor structure according to claim 5, characterized in that, The included angle is 60 degrees, and the active column array arrangement includes a closely packed hexagonal arrangement; or, the included angle is 45 degrees, and the active column array arrangement includes a square arrangement; or, the included angle is 75 degrees, and the active column array arrangement includes a rhombus arrangement.

7. The semiconductor structure according to claim 6, characterized in that, The plurality of second-type bit lines are located in the first region; the plurality of first-type bit lines are located in the second region and the third region; the second region and the third region are located on both sides of the first region along the arrangement direction of the row active columns; Of all the paired bit lines, one bit line comes from the second region and the other bit line comes from the third region; or, Some of the paired bit lines all originate from the second region, and the remaining paired bit lines all originate from the third region; or, Some of the paired bit lines all come from the second region, another portion of the paired bit lines all come from the third region, and the remaining portion of the paired bit lines have one bit line from the second region and another bit line from the third region.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a first word line contact corresponding to odd-numbered row word lines and a second word line contact corresponding to even-numbered row word lines, as well as a first bit line contact corresponding to odd-numbered column bit lines and a second bit line contact corresponding to even-numbered column bit lines; The first word line contact and the second word line contact are located on both sides of the active column array along the row active column arrangement direction; the first bit line contact and the second bit line contact are located on both sides of the active column array along a direction perpendicular to the row active column arrangement direction.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes an active pillar connection portion; the active pillar connection portion is integrally formed with each of the column of active pillars and extends along the arrangement direction of the column of active pillars; the column of active pillars is located on the active pillar connection portion; The bit line covers the end of the active post connection portion that is away from the active post.

10. The semiconductor structure according to claim 1, characterized in that, The multiple storage cells are arranged in a square or a hexagonal pattern.

11. A memory, characterized in that, include: The semiconductor structure provided in any one of claims 1 to 10; The word line of the semiconductor structure is configured to receive a word line voltage and control the channel of the active pillar to be turned on or off via the word line voltage, for connecting / disconnecting the first source / drain and the second source / drain of the semiconductor structure. The bit lines of the semiconductor structure are configured to perform read or write operations on the memory cells of the semiconductor structure when the channel of the active pillar is turned on.

12. The memory according to claim 11, characterized in that, Even-numbered digital lines are configured to receive the word line voltage to control the channel conduction of the corresponding active post. The even-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the channel of the active pillar is turned on. The odd-numbered bit lines are configured to receive a default voltage, thus shielding the even-numbered bit lines. or, The odd-number lines are configured to receive the word line voltage to control the channel conduction of the corresponding active pillar. The odd-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the channel of the active pillar is turned on; The even-numbered bit lines are configured to receive the default voltage, thus shielding the odd-numbered bit lines.

13. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; An active pillar array is formed along the first surface of the substrate; the row active pillar arrangement direction of the active pillar array is not orthogonal to the column active pillar arrangement direction of the active pillar array; each active pillar is used to form a first source / drain, a channel, and a second source / drain, which are arranged in a vertical direction. Multiple word lines are formed; each word line completely surrounds the channel of each active column in a row of active columns of the active column array; Multiple memory cells are formed; each memory cell is connected to a first source / drain. Multiple bit lines are formed along the second surface of the substrate; the multiple bit lines include multiple first-type bit lines and multiple second-type bit lines; each bit line is connected to the second source / drain of each active pillar in a column of active pillars of the active pillar array; the second surface is the opposite surface of the substrate to the first surface along the vertical direction. At least one bit line lead is formed; each bit line lead connects two of the plurality of first-type bit lines to form a paired bit line; the number of active columns in the column active columns corresponding to each paired bit line is the same as the number of active columns in the column active columns corresponding to each second-type bit line.

14. The manufacturing method according to claim 13, characterized in that, The array of source pillars formed along the first surface of the substrate includes: Along the first surface of the substrate, a plurality of first trenches and active stripes are formed in the substrate at intervals, wherein the first trenches and the active stripes extend along a first direction; A first isolation structure is formed by filling the first trench with insulating material; Along the first surface of the substrate, a plurality of spaced second trenches are formed in the first isolation structure and the active strip, the second trenches extending along a second direction; The second trench is filled with insulating material to form the second isolation structure; a plurality of the second isolation structures divide each of the active strips into a plurality of active pillars extending in a third direction; Wherein, the dimension of the second groove along the third direction is smaller than the dimension of the first groove along the third direction; the third direction is perpendicular to the plane formed by the first direction and the second direction; there is an angle between the first direction and the second direction; the angle range is greater than 0 degrees and less than 90 degrees.

15. The manufacturing method according to claim 14, characterized in that, The formation of multiple character lines includes: Along the first surface of the substrate, a portion of the first isolation structure and a portion of the second isolation structure are removed to form a third trench; the third trench fully surrounds and exposes at least a portion of the sidewalls of each of the active pillars; In the third trench, a gate dielectric layer, a first conductive structure, and a third isolation structure are formed sequentially covering the third trench; Along the first surface of the substrate, at least a portion of the third isolation structure and a portion of the first conductive structure are removed to form word line isolation trenches; the word line isolation trenches extend along the second direction and are located between adjacent row active pillars; a plurality of word line isolation trenches divide the first conductive structure into a plurality of word lines extending along the second direction; An insulating material is filled into the word line isolation trench to form a word line isolation structure; Wherein, the dimension of the word line isolation groove along the third direction is greater than the dimension of the third groove along the third direction; the dimension of the third groove along the third direction is less than the dimension of the second groove along the third direction; each word line includes a plurality of first parts and a plurality of second parts; each first part completely surrounds the channel of one of the active columns in the corresponding row, and each second part connects two adjacent first parts; wherein, the dimension of the first part along the third direction is greater than the dimension of the second part along the third direction.

16. The manufacturing method according to claim 14, characterized in that, The formation of multiple storage units includes: Multiple memory cell contacts are formed on the first source / drain; each memory cell contact is connected to a first source / drain. Multiple storage cells are formed on the storage cell contact; each storage cell is connected to a storage cell contact.

17. The manufacturing method according to claim 14, characterized in that, The formation of multiple bit lines along the second surface of the substrate includes: The substrate is thinned along its second surface to expose the first isolation structure and one end of the active strip away from the first surface of the substrate; A second conductive structure is formed along the second surface of the substrate, covering the first isolation structure and one end of the active strip away from the first surface of the substrate; wherein, the portion of the second conductive structure covering the end of the active strip away from the first surface of the substrate reacts with the active strip; the portion of the second conductive structure covering the end of the first isolation structure away from the first surface of the substrate does not react with the first isolation structure; The portion of the second conductive structure that does not react with the first isolation structure is removed to form the plurality of bit lines; insulating material is filled between the plurality of bit lines to form a plurality of bit line isolation structures; the plurality of bit lines and the plurality of bit line isolation structures are arranged at intervals and extend along a first direction.

18. The manufacturing method according to claim 17, characterized in that, The plurality of second-type bit lines are located in the first region; the plurality of first-type bit lines are located in the second region and the third region; the second region and the third region are located on both sides of the first region along the arrangement direction of the row active columns; The formation of at least one bit line lead includes: At least one bit line lead is formed outside the active pillar array region; each bit line lead is connected to a paired bit line. Of all the paired bit lines, one bit line comes from the second region and the other bit line comes from the third region; or, Some of the paired bit lines all originate from the second region, and the remaining paired bit lines all originate from the third region; or, Some of the paired bit lines all come from the second region, another portion of the paired bit lines all come from the third region, and the remaining portion of the paired bit lines have one bit line from the second region and another bit line from the third region.

19. The manufacturing method according to claim 18, characterized in that, The manufacturing method further includes: A first word line contact corresponding to an odd-numbered row word line and a second word line contact corresponding to an even-numbered row word line are formed outside the active column array region; and a first bit line contact corresponding to an odd-numbered column bit line and a second bit line contact corresponding to an even-numbered column bit line are formed outside the active column array region. The first word line contact and the second word line contact are located on both sides of the active column array along the row active column arrangement direction; the first bit line contact and the second bit line contact are located on both sides of the active column array along a direction perpendicular to the row active column arrangement direction.

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