Semiconductor structure and preparation method thereof, memory and memory system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method of the semiconductor structure, a memory and a storage system.The semiconductor structure comprises a substrate and a first isolation structure, the first isolation structure is located in the substrate, extends in the first direction and comprises a capacitor structure and a first insulating layer, the capacitor structure extends in the first direction, and the first insulating layer is located in the substrate. The first insulating layer is located between the capacitor structure and the substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for fabricating semiconductor structures, memories, and memory systems. Background Technology

[0002] Memory is one of the most important components in electronic systems. Taking memory as an example, it can include Random Access Memory (RAM), Read Only Memory (ROM), and cache. Random Access Memory can include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Memory also includes flash memory. Summary of the Invention

[0003] This application provides semiconductor structures, methods for fabricating semiconductor structures, memories, and storage systems that can at least partially solve the problems described above or other problems in the art.

[0004] This application provides a semiconductor structure, including: a substrate and a first isolation structure, the first isolation structure being located in the substrate and extending along a first direction and including a capacitor structure and a first insulating layer, the capacitor structure extending along the first direction, and the first insulating layer being located between the capacitor structure and the substrate.

[0005] In some embodiments, the capacitor structure includes a first electrode layer, a second electrode layer, and a second insulating layer extending along a first direction, wherein the second insulating layer is located between the first electrode layer and the second electrode layer along a direction intersecting the first direction.

[0006] In some embodiments, the first electrode layer and the second electrode layer have an annular structure, with the second electrode layer surrounding the sidewall of the first electrode layer.

[0007] In some embodiments, the semiconductor structure further includes a transistor, which includes a gate structure, a source region, and a drain region. The gate structure is located on one side of the substrate along a first direction; the source region is located in the substrate and on one side of the gate structure along a second direction; the drain region is located in the substrate and on the other side of the gate structure along the second direction; wherein the second direction intersects the first direction; and wherein a first isolation structure is located on the side of the transistor along a direction intersecting the first direction.

[0008] In some embodiments, the semiconductor structure further includes a first dielectric layer, a first interconnect structure, and a second interconnect structure; the first dielectric layer is located on one side of the substrate along a first direction and covers the gate structure; the first interconnect structure is located in the first dielectric layer and on one side of the transistor along a direction intersecting the first direction; the second interconnect structure extends through the substrate along the first direction and through the portion of the first dielectric layer located between the first interconnect structure and the substrate, and the second interconnect structure is connected to the first interconnect structure.

[0009] In some embodiments, the semiconductor structure further includes a conductive layer and a third insulating layer; the conductive layer is located in the first dielectric layer and spaced from the substrate; the third insulating layer is located in the first dielectric layer and on the side of the conductive layer opposite to the substrate; wherein a portion of the first connection structure penetrates the third insulating layer along a first direction; and a portion of the second connection structure penetrates the conductive layer along the first direction.

[0010] In some embodiments, the semiconductor structure further includes a resistor structure, a fourth insulating layer, and a third connection structure; the resistor structure is located in the first dielectric layer and on the side of the transistor intersecting the first direction; the fourth insulating layer is located in the first dielectric layer and on the side of the resistor structure facing away from the substrate; the third connection structure is located in the first dielectric layer on the side of the resistor structure facing away from the substrate, and a portion of the third connection structure penetrates the fourth insulating layer along the first direction; wherein the material of the third insulating layer is the same as the material of the fourth insulating layer, and the material of the conductive layer is the same as the material of the resistor structure; wherein the third insulating layer and the fourth insulating layer have the same height relative to the substrate along the first direction, and the conductive layer and the resistor structure have the same height relative to the substrate along the first direction.

[0011] In some embodiments, the first connection structure includes a first connection layer and a first adhesive layer located on the sidewall of the first connection layer, with a portion of the first connection layer and a portion of the first adhesive layer penetrating a third insulating layer along a first direction.

[0012] In some embodiments, the second connection structure includes a second connection layer and an insulating isolation layer; the second connection layer extends along a first direction through the substrate, the portion of the first dielectric layer located between the conductive layer and the substrate, and the conductive layer; the insulating isolation layer is located between the second connection layer and the substrate.

[0013] In some embodiments, the semiconductor structure further includes a first lead-out structure and a second lead-out structure; the first lead-out structure is located on one side of the substrate in the opposite direction to the first direction and is connected to the first electrode layer; the second lead-out structure is located on one side of the substrate in the opposite direction to the first direction and is connected to the second electrode layer.

[0014] In some embodiments, the semiconductor structure further includes a second dielectric layer located on one side of the substrate opposite to the first direction; wherein the first lead-out structure and the second lead-out structure are located in the second dielectric layer.

[0015] In some embodiments, the first electrode layer and the second electrode layer also extend into a portion of the second dielectric layer.

[0016] This application also provides a method for fabricating a semiconductor structure, comprising: forming a first isolation structure extending along a first direction in a substrate; wherein the first isolation structure includes: a capacitor structure extending along the first direction; and a first insulating layer located between the capacitor structure and the substrate.

[0017] In some embodiments, forming a first isolation structure extending in a first direction in a substrate includes forming the first isolation structure in the substrate from one side of the substrate along the first direction.

[0018] In some embodiments, forming the first isolation structure includes: forming a first isolation trench in a substrate; forming a first insulating layer on the sidewall of the first isolation trench; and forming a capacitor structure in the first isolation trench, the capacitor structure including a first electrode layer, a second electrode layer, and a second insulating layer extending along a first direction, wherein the second insulating layer is located between the first electrode layer and the second electrode layer along a direction intersecting the first direction.

[0019] In some embodiments, forming the first isolation structure further includes: forming a sacrificial layer in a first isolation trench from one side of the substrate along a first direction; wherein a first insulating layer is located between the sacrificial layer and the substrate; and removing the sacrificial layer from the substrate along a direction opposite to the first direction before forming the capacitor structure in the first isolation trench; wherein forming the capacitor structure in the first isolation trench includes: forming a first electrode layer and a second electrode layer in the first isolation trench from the substrate along a direction opposite to the first direction; and forming a second insulating layer in the first isolation trench from the substrate along a direction opposite to the first direction.

[0020] In some embodiments, forming a first electrode layer and a second electrode layer in a first isolation trench from a side of the substrate opposite to the first direction includes: forming an initial electrode layer in the first isolation trench, the initial electrode layer being located on the sidewall of the first insulating layer away from the substrate and on the inner wall of the first isolation trench along the first direction; and removing a portion of the initial electrode layer located on the inner wall of the first isolation trench along the first direction, wherein the portion of the initial electrode layer located on the sidewall of the first insulating layer away from the substrate forms the first electrode layer and the second electrode layer.

[0021] In some embodiments, forming a first insulating layer on the sidewall of the first isolation trench includes: forming a first initial insulating layer on the sidewall of the first isolation trench and on the inner wall of the first isolation trench on the side opposite to the first direction before forming a sacrificial layer; and removing a portion of the first initial insulating layer located on the inner wall of the first isolation trench on the side opposite to the first direction, wherein the portion of the first initial insulating layer located on the sidewall of the first isolation trench forms the first insulating layer.

[0022] In some embodiments, removing the portion of the inner wall of the first initial insulating layer located on the side opposite to the first direction of the first isolation trench includes: removing the portion of the inner wall of the first initial insulating layer located on the side opposite to the first direction of the first isolation trench before removing the sacrificial layer.

[0023] In some embodiments, the fabrication method further includes: thinning the substrate from a side opposite to the first direction; wherein removing the portion of the inner wall of the first initial insulating layer located on the side opposite to the first direction of the first isolation trench includes: during the substrate thinning process, removing the portion of the inner wall of the first initial insulating layer located on the side opposite to the first direction of the first isolation trench and exposing the sacrificial layer.

[0024] In some embodiments, the fabrication method further includes: forming a transistor, comprising: forming a gate structure on one side of a substrate along a first direction; forming a source region in a substrate on one side of the gate structure along a second direction; and forming a drain region in a substrate on the other side of the gate structure along the second direction; wherein the second direction intersects the first direction; and wherein a first isolation structure is located on the side of the transistor along a direction intersecting the first direction.

[0025] In some embodiments, the fabrication method further includes: forming a first dielectric layer located on one side of the substrate along a first direction and covering the gate structure; forming a first connection structure located in the first dielectric layer and on one side of the transistor along a direction intersecting the first direction; and forming a second connection structure that penetrates the substrate along the first direction and the portion of the first dielectric layer located between the first connection structure and the substrate, wherein the second connection structure is connected to the first connection structure.

[0026] In some embodiments, the fabrication method further includes: forming a conductive layer located in a first dielectric layer and spaced apart from a substrate; forming a third insulating layer located in the first dielectric layer and on the side of the conductive layer opposite to the substrate; wherein a portion of the first connection structure penetrates the third insulating layer along a first direction; and a portion of the second connection structure penetrates the conductive layer along the first direction.

[0027] In some embodiments, forming a conductive layer includes: forming a conductive layer during the formation of a resistive structure, wherein the resistive structure is located in a first dielectric layer and on one side of the transistor along a direction intersecting a first direction; wherein forming a third insulating layer includes: forming a third insulating layer during the formation of a fourth insulating layer, wherein the fourth insulating layer is located in the first dielectric layer and on the side of the resistive structure away from the substrate; and wherein the fabrication method further includes: forming a third connection structure, the third connection structure being located in the first dielectric layer on the side of the resistive structure away from the substrate, a portion of the third connection structure penetrating the fourth insulating layer along a first direction.

[0028] In some embodiments, forming a conductive layer during the formation of a resistive structure includes: forming an initial resistive film on a side of a first dielectric layer away from the substrate; and etching the initial resistive film to form a resistive structure and a conductive layer; wherein forming a third insulating layer during the formation of a fourth insulating layer includes: forming an initial insulating layer on a side of the initial resistive film away from the substrate; and etching the initial insulating layer to form a fourth insulating layer and a third insulating layer.

[0029] In some embodiments, forming the first connection structure includes: forming a first opening located in a first dielectric layer and a third insulating layer on the side of the conductive layer away from the substrate, the first opening exposing the conductive layer; and forming the first connection structure in the first opening.

[0030] In some embodiments, forming the second connection structure includes: forming a second opening extending in the substrate along a first direction; forming an initial insulating isolation layer in the second opening; forming a third opening that extends along the first direction through the initial insulating isolation layer, a portion of the first dielectric layer between the conductive layer and the substrate, and the conductive layer, wherein the portion of the initial insulating isolation layer between the third opening and the substrate forms an insulating isolation layer; and forming a second connection layer in the third opening.

[0031] In some embodiments, the fabrication method further includes: forming a first lead-out structure located on one side of the substrate opposite to the first direction and connected to a first electrode layer; and forming a second lead-out structure located on one side of the substrate opposite to the first direction and connected to a second electrode layer.

[0032] In some embodiments, the fabrication method further includes: forming a second dielectric layer located on one side of the substrate opposite to the first direction; wherein the first lead-out structure and the second lead-out structure are located in the second dielectric layer.

[0033] This application also provides a memory, including a memory cell array and peripheral circuitry, the peripheral circuitry being coupled to the memory cell array and including semiconductor structures as described in any of the embodiments above.

[0034] In another aspect, this application provides a storage system, including a controller and a memory as mentioned in any of the embodiments above, wherein the controller is coupled to the memory and is used to control the memory to store data. Attached Figure Description

[0035] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0036] Figures 1 to 5 This is a structural diagram of the semiconductor structure fabrication process according to an embodiment of this application;

[0037] Figure 6 This is a structural diagram of a semiconductor structure according to another embodiment of this application;

[0038] Figure 7 for Figure 6 Top view of the transistor, the first isolation structure, and the substrate;

[0039] Figure 8 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application;

[0040] Figures 9 to 25 This is a structural diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this application;

[0041] Figure 26 This is a schematic diagram of the structure of a memory according to an exemplary embodiment of this application;

[0042] Figure 27 A block diagram of a system having a storage system according to an exemplary embodiment of this application; and

[0043] Figure 28 This is a schematic diagram of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0044] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0046] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0047] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0048] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0049] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0050] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0051] This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0052] This application provides a method for fabricating a semiconductor structure through some embodiments. Figures 1 to 5 This is a structural diagram of the semiconductor structure fabrication process according to an embodiment of this application.

[0053] refer to Figure 1A first isolation structure 12 and a second isolation structure 13 are formed in the substrate 10, wherein the dimension of the second isolation structure 13 along the first direction Z is smaller than the dimension of the first isolation structure 12 along the first direction Z; and an initial insulating isolation layer 11 is formed in the substrate 10.

[0054] refer to Figure 2 A transistor 20 is formed; a dielectric layer 50 is formed, which covers the transistor 20; a resistor structure 31 is formed, which is located in the dielectric layer 50; and a first connection structure 41 is formed, which is located in the dielectric layer 50.

[0055] Forming transistor 20 includes: forming a gate structure 21 on one side of substrate 10 along a first direction Z; forming a source region 22 in substrate 10 on one side of gate structure 21 along a second direction; and forming a drain region 23 in substrate 10 on the other side of gate structure 21 along the second direction. The second direction intersects the first direction, for example, the second direction is perpendicular to the first direction.

[0056] In this embodiment, the method for fabricating the semiconductor structure further includes: forming a capacitor structure (not shown), the capacitor structure being located in the dielectric layer 50, and the capacitor structure needing to occupy a certain space.

[0057] refer to Figure 3 The substrate 10 is bonded to one side of the support substrate 60, wherein the dielectric layer 50 is located between the substrate 10 and the support substrate 60; then the substrate 10 is thinned from the side of the substrate 10 away from the support substrate 60 until the initial insulating isolation layer 11 is exposed.

[0058] refer to Figure 4 An opening (not shown) is formed in the substrate 10 and in the dielectric layer 50 between the substrate 10 and the first connection structure 41. The opening penetrates the initial insulating isolation layer 11, and the opening and the initial insulating isolation layer 11 between the substrate 10 constitute the insulating isolation layer 11a.

[0059] refer to Figure 5 A connecting layer 42 is formed in the opening. The connecting layer 42 and the insulating isolation layer 11a constitute a second connecting structure (not shown). The second connecting structure is connected to the first connecting structure 41.

[0060] Other embodiments of this application provide a semiconductor structure. Figure 6 This is a structural diagram of a semiconductor structure 1000 according to another embodiment of this application. Figure 7 for Figure 6 Top view of transistor 200, first isolation structure 907 and substrate 100.

[0061] refer to Figure 6The semiconductor structure 1000 includes a substrate 100 and a first isolation structure 907, which is located in the substrate 100 and extends along a first direction Z. The first isolation structure 907 includes a capacitor structure 906 and a first insulating layer 110a. The capacitor structure 906 extends along the first direction Z. The first insulating layer 110a is located between the capacitor structure 906 and the substrate 100.

[0062] For example, the first insulating layer 110a is located between the capacitor structure 906 and the substrate 100 along a direction intersecting the first direction Z.

[0063] In at least one embodiment of this application, a capacitor structure 906 is integrated into the first isolation structure 907, which enables the first isolation structure 907 to simultaneously achieve the functions of isolation and capacitance, saving the area of ​​the semiconductor structure and improving the integration density of the semiconductor structure.

[0064] In some embodiments, the material of the substrate 100 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0065] In some embodiments, the material of the first insulating layer 110a is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0066] In some implementations, in conjunction with reference Figure 6 and Figure 7 The capacitor structure 906 includes a first electrode layer 903, a second electrode layer 904, and a second insulating layer 905 extending along a first direction Z, wherein the second insulating layer 905 is located between the first electrode layer 903 and the second electrode layer 904 along a direction intersecting the first direction Z.

[0067] In some implementations, reference Figure 7 The first electrode layer 903 has a ring structure, and the second electrode layer 904 has a ring structure, with the second electrode layer 904 surrounding the sidewall of the first electrode layer 903. The surface area of ​​the first electrode layer 903 facing the second electrode layer 904 is larger, and the surface area of ​​the second electrode layer 904 facing the first electrode layer 903 is also larger, which increases the capacitance value of the capacitor structure 906.

[0068] In some embodiments, the second insulating layer 905 is a capacitor dielectric material.

[0069] In some embodiments, the material of the first electrode layer 903 includes a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum, or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or a silicide; this application does not limit the specific materials used. For example, the material of the first electrode layer 903 is a combination of titanium nitride and tungsten.

[0070] In some embodiments, the material of the second electrode layer 904 includes a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum, or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or a silicide; this application does not limit the specific materials used. For example, the material of the second electrode layer 904 is a combination of titanium nitride and tungsten.

[0071] In some embodiments, the first isolation structure 907 penetrates the substrate 100 along a first direction Z.

[0072] In some implementations, reference Figure 6 The semiconductor structure 1000 further includes a transistor 200, which includes a gate structure 201, a source region 202, and a drain region 203. The gate structure 201 is located on one side of the substrate 100 along a first direction Z; the source region 202 is located in the substrate 100 and is located on one side of the gate structure 201 along a second direction X; the drain region 203 is located in the substrate 100 and is located on the other side of the gate structure 201 along the second direction X. The second direction X intersects the first direction Z, and exemplarily, the second direction X is perpendicular to the first direction Z.

[0073] In some embodiments, the gate structure 201 includes a gate electrode layer and a gate dielectric layer. The gate electrode layer is located on the side of the gate dielectric layer away from the substrate 100. The gate electrode layer includes one of a metal gate material and a semiconductor gate material. The material of the gate dielectric layer includes silicon oxide or a high-k dielectric material (dielectric constant K is greater than 3.9).

[0074] In some implementations, reference Figure 6 The first isolation structure 907 is located on the side of the transistor 200 along a direction intersecting the first direction Z.

[0075] In some implementations, reference Figure 6 The semiconductor structure 1000 further includes a second isolation structure 105, which is located in the substrate 100 and between the first isolation structure 907 and the transistor 200. The dimension of the second isolation structure 105 along the first direction Z is smaller than the dimension of the first isolation structure 907 along the first direction Z.

[0076] In some implementations, reference Figure 6 The semiconductor structure 1000 also includes a first dielectric layer 500, which is located on one side of the substrate 100 along the first direction Z and covers the gate structure 201.

[0077] In some embodiments, the material of the first dielectric layer 500 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0078] In some embodiments, the second isolation structure 105 extends from the side surface of the substrate 100 facing the first dielectric layer 500 into a portion of the substrate 100. The distance between the side surface of the second isolation structure 105 facing away from the first dielectric layer 500 and the side surface of the substrate 100 facing away from the first dielectric layer 500 is greater than zero.

[0079] In some implementations, reference Figure 6 The second isolation structure 105 includes a first isolation portion 103 and a second isolation portion 104. The first isolation portion 103 is located between the sidewall of the second isolation portion 104 and the substrate 100, and between the side surface of the second isolation portion 104 facing away from the first dielectric layer 500 and the substrate 100.

[0080] In some embodiments, the first isolation portion 103 is made of an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The second isolation portion 104 is made of an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The materials of the first isolation portion 103 and the second isolation portion 104 are the same, or the materials of the first isolation portion 103 and the second isolation portion 104 are different.

[0081] In some embodiments, the material of the first isolation portion 103 is the same as that of the second isolation portion 104, and the density of the first isolation portion 103 is greater than that of the second isolation portion 104.

[0082] In other embodiments, the second isolation structure is a single-layer structure. The material of the second isolation structure 105 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0083] In some implementations, reference Figure 6 The semiconductor structure 1000 further includes a first connection structure 704 and a second connection structure 913. The first connection structure 704 is located in the first dielectric layer 500 and on one side of the transistor 200 along the direction intersecting the first direction Z. The second connection structure 913 extends along the first direction Z through the substrate 100 and the portion of the first dielectric layer 500 located between the first connection structure 704 and the substrate 100, and the second connection structure 913 is connected to the first connection structure 704.

[0084] In some embodiments, the first connection structure 704 includes a first connection layer 704b and a first adhesive layer 704a located on the sidewall of the first connection layer 704b.

[0085] In some embodiments, the material of the first interconnect layer 704b includes a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum, or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or a silicide; this application does not limit the specific materials used. For example, the material of the first interconnect layer 704b is a combination of titanium nitride and tungsten. The material of the first adhesive layer 704a includes at least one of titanium (Ti) and titanium nitride (TiN).

[0086] In some embodiments, the second connection structure 913 includes a second connection layer 912 and an insulating isolation layer 108a. The second connection layer 912 extends along a first direction Z through the portion of the substrate 100 and the first dielectric layer 500 located between the first connection structure 704 and the substrate 100. The insulating isolation layer 108a is located between the second connection layer 912 and the substrate 100. The second connection layer 912 is connected to the first connection layer 704b, and the second connection layer 912 may also be connected to the first adhesive layer 704a.

[0087] In some embodiments, the material of the second interconnect layer 912 includes a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum, or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or a silicide; this application does not limit the specific materials used. For example, the material of the second interconnect layer 912 is a combination of titanium nitride and tungsten.

[0088] In some embodiments, the insulating layer 108a is made of an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0089] In some implementations, reference Figure 6 The insulating isolation layer 108a includes a third isolation portion 106 and a fourth isolation portion 107a. The third isolation portion 106 is located between the fourth isolation portion 107a and the substrate 100.

[0090] In some embodiments, the material of the third isolation portion 106 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the fourth isolation portion 107a is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the third isolation portion 106 is the same as the material of the fourth isolation portion 107a, or the material of the third isolation portion 106 is different from the material of the fourth isolation portion 107a.

[0091] In some embodiments, the material of the third isolation portion 106 is the same as that of the fourth isolation portion 107a, and the density of the third isolation portion 106 is greater than that of the fourth isolation portion 107a.

[0092] In other embodiments, the insulating layer 108a is a single-layer structure, and the material of the insulating layer 108a is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0093] In some implementations, reference Figure 6 The semiconductor structure 1000 further includes a conductive layer 401 and a third insulating layer 402. The conductive layer 401 is located in the first dielectric layer 500 and spaced from the substrate 100. The third insulating layer 402 is located in the first dielectric layer 500 and on the side of the conductive layer 401 facing away from the substrate 100. A portion of the first connection structure 704 penetrates the third insulating layer 402 along the first direction Z, and a portion of the second connection structure 913 penetrates the conductive layer 401 along the first direction Z.

[0094] In some embodiments, the conductive layer 401 is made of a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum, or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or a silicide. This application does not limit the specific materials used. For example, the conductive layer 401 is made of a combination of titanium nitride and tungsten.

[0095] In some embodiments, the third insulating layer 402 is made of an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the third insulating layer 402 is different from the material of the first dielectric layer 500.

[0096] In some embodiments, the dimension of the conductive layer 401 along the first direction Z is smaller than the dimension of the third insulating layer 402 along the first direction Z. In other embodiments, there are no limitations on the dimensions of the conductive layer 401 and the third insulating layer 402 along the first direction Z.

[0097] In some embodiments, a portion of the first connecting layer 704b and a portion of the first adhesive layer 704a penetrate the third insulating layer 402 along the first direction Z.

[0098] In some embodiments, the second interconnect layer 912 extends along the first direction Z through the substrate 100, the portion of the first dielectric layer 500 located between the conductive layer 401 and the substrate 100, and the conductive layer 401.

[0099] In some implementations, reference Figure 6The semiconductor structure also includes a resistor structure 301, a fourth insulating layer 302, and a third connection structure 701. The resistor structure 301 is located in the first dielectric layer 500 and on the side of the transistor 200 intersecting the first direction Z. The fourth insulating layer 302 is located in the first dielectric layer 500 and on the side of the resistor structure 301 facing away from the substrate 100. The third connection structure 701 is located in the first dielectric layer 500 on the side of the resistor structure 301 facing away from the substrate 100, and a portion of the third connection structure 701 penetrates the fourth insulating layer 302 along the first direction Z. The fourth insulating layer 302 serves as an etch stop layer for forming a first trench accommodating the third connection structure 701, reducing damage to the resistor structure 301.

[0100] In some embodiments, the material of the fourth insulating layer 302 is different from the material of the first dielectric layer 500.

[0101] In some embodiments, the material of the third insulating layer 402 is the same as that of the fourth insulating layer 302, and the material of the conductive layer 401 is the same as that of the resistive structure 301. The third insulating layer 402 and the fourth insulating layer 302 have the same height relative to the substrate 100 along the first direction Z, and the conductive layer 401 and the resistive structure 301 have the same height relative to the substrate 100 along the first direction Z.

[0102] In other embodiments, the semiconductor structure 1000 may not include the conductive layer 401 and the third insulating layer 402.

[0103] In some implementations, reference Figure 6 The semiconductor structure 1000 further includes a first lead-out structure 920 and a second lead-out structure 918. The first lead-out structure 920 is located on the side of the substrate 100 opposite to the first direction Z and is connected to the first electrode layer 903. Exemplarily, the first lead-out structure 920 is located on the side of the first electrode layer 903 opposite to the first dielectric layer 500. The second lead-out structure 918 is located on the side of the substrate 100 opposite to the first direction Z and is connected to the second electrode layer 904. Exemplarily, the second lead-out structure 918 is located on the side of the second electrode layer 904 opposite to the first dielectric layer 500.

[0104] In some implementations, reference Figure 6 The semiconductor structure 1000 further includes a second dielectric layer 915, which is located on the side of the substrate 100 opposite to the first direction Z. For example, the second dielectric layer 915 is located on the side of the substrate 100 away from the first dielectric layer 500. The first lead-out structure 920 and the second lead-out structure 918 are located in the second dielectric layer 915.

[0105] In some embodiments, the material of the second dielectric layer 915 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0106] In some embodiments, the first electrode layer 903 and the second electrode layer 904 further extend into a portion of the second dielectric layer 915, and the second insulating layer 905 further extends into a portion of the second dielectric layer 915.

[0107] In other embodiments, the first electrode layer and the second electrode layer may not extend into the second dielectric layer 915, and the second insulating layer may not extend into the second dielectric layer 915.

[0108] In some implementations, reference Figure 6 The first lead-out structure 920 includes a first lead-out member 914 and a first interconnect member 919. The first interconnect member 919 is located on the side of the first lead-out member 914 away from the substrate 100 and is connected to the first lead-out member 914. The first lead-out member 914 is connected to the first electrode layer 903. The size of the first lead-out member 914 is smaller than the size of the first interconnect member 919 along the direction intersecting the first direction Z.

[0109] In some embodiments, the material of the first lead-out 914 includes a conductive material, which may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or silicide. This application does not limit the specific materials used in this application.

[0110] In some embodiments, the material of the first interconnect 919 includes a conductive material, which may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or silicide. This application does not limit the specific materials used in this application.

[0111] In some implementations, reference Figure 6 The second lead structure 918 includes a second lead 913 and a second interconnect 917. The second interconnect 917 is located on the side of the second lead 913 away from the substrate 100 and is connected to the second lead 913. The second lead 913 is connected to the second electrode layer 904. The size of the second lead 913 is smaller than the size of the second interconnect 917 along the direction intersecting the first direction Z.

[0112] In some embodiments, the material of the second lead-out 913 includes a conductive material, which may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or silicide. This application does not limit the specific materials used in this application.

[0113] In some embodiments, the material of the second interconnect 917 includes a conductive material, which may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or silicide. This application does not limit the specific materials used in this application.

[0114] In some implementations, reference Figure 6 The semiconductor structure 1000 also includes a third interconnect 916 located in the second dielectric layer 915. The third interconnect 916 is located on the side of the second connection layer 912 opposite to the first connection structure 704 and is connected to the second connection layer 912.

[0115] In some embodiments, the material of the third interconnect 916 includes a conductive material, which may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or silicide. This application does not limit the specific materials used in this application.

[0116] In some implementations, reference Figure 6 The semiconductor structure 1000 also includes a fourth interconnect 804 located in the first dielectric layer 500. The fourth interconnect 804 is located on the side of the first connection structure 704 opposite to the second connection structure 913 and is connected to the first connection structure 704.

[0117] In some embodiments, the material of the fourth interconnect 804 includes a conductive material, which may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or silicide. This application does not limit the specific materials used in this application.

[0118] In some implementations, reference Figure 6The semiconductor structure 1000 also includes a fourth connection structure 702 and a fifth connection structure 703 located in the first dielectric layer 500. The fourth connection structure 702 is located on the side of the gate structure 201 away from the substrate 100 and is connected to the gate structure 201. The fifth connection structure 703 is located on both sides of the fourth connection structure 702 along the second direction X. The fifth connection structure 703 located on one side of the fourth connection structure 702 along the second direction X is connected to the source region 202, and the fifth connection structure 703 located on the other side of the fourth connection structure 702 along the second direction X is connected to the drain region 203.

[0119] In some implementations, reference Figure 6 The fourth connection structure 702 includes a fourth connection layer and a fourth adhesive layer located on the sidewall of the fourth connection layer.

[0120] In some embodiments, the material of the fourth interconnect layer includes a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum, or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or a silicide; this application is not limited in this regard. For example, the material of the fourth interconnect layer is a combination of titanium nitride and tungsten. The material of the fourth adhesive layer includes at least one of titanium (Ti) and titanium nitride (TiN).

[0121] In some embodiments, the fifth connection structure 703 includes a fifth connection layer and a fifth adhesive layer located on the sidewall of the fifth connection layer.

[0122] In some embodiments, the material of the fifth interconnect layer includes a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum, or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or a silicide; this application is not limited thereto. For example, the material of the fifth interconnect layer is a combination of titanium nitride and tungsten. The material of the fifth adhesive layer includes at least one of titanium (Ti) and titanium nitride (TiN).

[0123] In some implementations, reference Figure 6 The semiconductor structure 1000 also includes a fifth interconnect 802 and a sixth interconnect 803 located in the first dielectric layer 500. The fifth interconnect 802 is located on the side of the fourth connection structure 702 away from the gate structure 201 and is connected to the fourth connection structure 702. The sixth interconnect 803 is located on the side of the fifth connection structure 703 away from the substrate 100 and is connected to the fifth connection structure 703.

[0124] In some embodiments, the material of the fifth interconnect 802 includes a conductive material, which may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or silicide. This application does not limit the specific materials used in this application.

[0125] In some embodiments, the material of the sixth interconnect 803 includes a conductive material, which may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or silicide. This application does not limit the specific materials used in this application.

[0126] In some implementations, reference Figure 6 The semiconductor structure 1000 also includes a seventh interconnect 801 located in the first dielectric layer 500. The seventh interconnect 801 is located on the side of the third connection structure 701 away from the resistor structure 301 and is connected to the third connection structure 701.

[0127] In some embodiments, the material of the seventh interconnect 801 includes a conductive material, which may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or silicide. This application does not limit the specific materials used in this application.

[0128] In some implementations, reference Figure 6 The semiconductor structure 1000 also includes a support substrate 900, which can be a semiconductor substrate.

[0129] In some implementations, reference Figure 6 The semiconductor structure 1000 further includes a bonding dielectric layer 901, which is located between the first dielectric layer 500 and the support substrate 900, between the fourth interconnect 804 and the support substrate 900, between the fifth interconnect 802 and the support substrate 900, between the sixth interconnect 803 and the support substrate 900, and between the seventh interconnect 801 and the support substrate 900.

[0130] In some embodiments, the bonding dielectric layer 901 is made of an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0131] In some embodiments, the bonding dielectric layer 901 and the first dielectric layer 500 are made of the same material, and the bonding dielectric layer 901 and the first dielectric layer 500 are an integral structure.

[0132] In other embodiments, the bonding dielectric layer 901 and the first dielectric layer 500 are made of different materials.

[0133] In some embodiments, the first dielectric layer 500 includes a first dielectric portion 501, a second dielectric portion 502, a third dielectric portion 503, and a fourth dielectric portion 504. The first dielectric portion 501 is located on the side of the gate structure 201 intersecting the first direction Z and does not extend to the side of the gate structure 201 opposite to the substrate 100. The second dielectric portion 502 is located on the side of the first dielectric portion 501 opposite to the substrate 100. The conductive layer 401, the third insulating layer 402, the resistive structure 301, and the fourth insulating layer 302 are located on the side of the second dielectric portion 502 opposite to the substrate 100. The third dielectric portion 503 is located on the side of the second dielectric portion 502 opposite to the substrate 100 and covers the conductive layer 401, the third insulating layer 402, the resistive structure 301, and the fourth insulating layer 302. The first connection structure 704 and the third connection structure 701 are located in the third dielectric portion 503. The fourth connection structure 702 is located in the second dielectric section 502 and the third dielectric section 503, and the fifth connection structure 703 is located in the first dielectric section 501, the second dielectric section 502, and the third dielectric section 503. The fourth dielectric section 504 is located on the side of the third dielectric section 503 facing away from the substrate 100, and the fourth interconnect 804, the fifth interconnect 802, the sixth interconnect 803, and the seventh interconnect 801 are located in the fourth dielectric section 504.

[0134] In some embodiments, the material of the first dielectric portion 501 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the second dielectric portion 502 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the third dielectric portion 503 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the fourth dielectric portion 504 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0135] In some embodiments, the first medium portion 501, the second medium portion 502, the third medium portion 503, and the fourth medium portion 504 may be made of the same material, and the first medium portion 501, the second medium portion 502, the third medium portion 503, and the fourth medium portion 504 may be an integral structure.

[0136] In some embodiments, the materials of the first medium portion 501, the second medium portion 502, the third medium portion 503, and the fourth medium portion 504 may be partially or completely different.

[0137] Another embodiment of this application provides a method for fabricating a semiconductor structure, see reference. Figure 8 ,include:

[0138] Step S1: Form a first isolation structure extending along a first direction in the substrate; wherein the first isolation structure includes a capacitor structure extending along the first direction and a first insulating layer, the first insulating layer being located between the capacitor structure and the substrate.

[0139] In some embodiments, forming the first isolation structure includes: forming a first isolation trench in a substrate; forming a first insulating layer on the sidewall of the first isolation trench; and forming a capacitor structure in the first isolation trench.

[0140] In some embodiments, forming the first isolation structure further includes: forming a sacrificial layer in a first isolation trench from one side of the substrate along a first direction; wherein a first insulating layer is located between the sacrificial layer and the substrate; and removing the sacrificial layer from the substrate along a direction opposite to the first direction before forming the capacitor structure in the first isolation trench; wherein forming the capacitor structure in the first isolation trench includes: forming a first electrode layer and a second electrode layer in the first isolation trench from the substrate along a direction opposite to the first direction; and forming a second insulating layer in the first isolation trench from the substrate along a direction opposite to the first direction.

[0141] In some embodiments, forming a first electrode layer and a second electrode layer in a first isolation trench from a side of the substrate opposite to the first direction includes: forming an initial electrode layer in the first isolation trench, the initial electrode layer being located on the sidewall of the first insulating layer away from the substrate and on the inner wall of the first isolation trench along the first direction; and removing a portion of the initial electrode layer located on the inner wall of the first isolation trench along the first direction, wherein the portion of the initial electrode layer located on the sidewall of the first insulating layer away from the substrate forms the first electrode layer and the second electrode layer.

[0142] In some embodiments, forming a first insulating layer on the sidewall of the first isolation trench includes: forming a first initial insulating layer on the sidewall of the first isolation trench and on the inner wall of the first isolation trench on the side opposite to the first direction before forming a sacrificial layer; and removing a portion of the first initial insulating layer located on the inner wall of the first isolation trench on the side opposite to the first direction, wherein the portion of the first initial insulating layer located on the sidewall of the first isolation trench forms the first insulating layer.

[0143] In some embodiments, the method for fabricating a semiconductor structure further includes: forming a transistor; forming a first dielectric layer, the first dielectric layer being located on one side of the substrate along a first direction Z and covering the transistor.

[0144] In some embodiments, the method for fabricating a semiconductor structure further includes forming a first interconnect structure; forming the first interconnect structure includes: forming a first opening located in a first dielectric layer and a third insulating layer on the side of the conductive layer away from the substrate, the first opening exposing the conductive layer; and forming the first interconnect structure in the first opening.

[0145] In some embodiments, the method for fabricating a semiconductor structure further includes forming a second interconnect structure; forming the second interconnect structure includes: forming a second opening extending in a substrate along a first direction; forming an initial insulating isolation layer in the second opening; forming a third opening that extends along the first direction through the initial insulating isolation layer, a portion of a first dielectric layer located between a conductive layer and the substrate, and a conductive layer, wherein the portion of the initial insulating isolation layer located between the third opening and the substrate forms an insulating isolation layer; and forming a second interconnect layer in the third opening.

[0146] Reference Figures 9 to 22 A first isolation structure 907 extending along a first direction Z is formed in the substrate 100; wherein the first isolation structure 907 includes a capacitor structure 906 extending along the first direction Z and a first insulating layer 110a, the first insulating layer 110a being located between the capacitor structure 906 and the substrate 100. For example, the first insulating layer 110a is located between the capacitor structure 906 and the substrate 100 in a direction intersecting the first direction Z.

[0147] refer to Figure 9 A second isolation trench 102 extending along the first direction Z on the substrate 100 is formed; a second opening 101 extending along the first direction Z on the substrate 100 is formed.

[0148] In some embodiments, the process for forming the second isolation trench 102 is an etching process, which includes one or a combination of dry etching and wet etching. The process for forming the second opening 101 is an etching process, which includes one or a combination of dry etching and wet etching.

[0149] In some embodiments, the second opening 101 is formed after the second isolation groove 102 is formed, or the second isolation groove 102 is formed after the second opening 101 is formed.

[0150] In one embodiment, the second opening 101 is located on one side of the second isolation groove 102 along a direction intersecting the first direction Z. For example, the second opening 101 is located on one side of the second isolation groove 102 along a second direction. The second direction intersects the first direction Z; exemplarily, the second direction is perpendicular to the first direction Z.

[0151] In one embodiment, the second isolation groove 102 is an annular structure. The second opening 101 is located outside the second isolation groove 102; in other words, the second isolation groove 102 does not surround the second opening 101.

[0152] In one embodiment, the dimension of the second opening 101 along the first direction Z is greater than the dimension of the second isolation groove 102 along the first direction Z.

[0153] refer to Figure 10A second isolation structure 105 is formed in the second isolation groove 102; an initial insulating isolation layer 108 is formed in the second opening 101.

[0154] In one embodiment, forming a second isolation structure 105 in a second isolation groove 102 includes: forming a first isolation portion 103 on the inner wall surface of the second isolation groove 102; after forming the first isolation portion 103, forming a second isolation portion 104 in the second isolation groove 102, wherein the first isolation portion 103 is located between the side wall of the second isolation portion 104 and the substrate 100, and between the surface of the second isolation portion 104 on the side opposite to the first direction Z and the substrate 100.

[0155] In one embodiment, the process of forming the first isolation portion 103 on the inner wall surface of the second isolation tank 102 includes an oxidation process or a deposition process. The process of forming the second isolation portion 104 in the second isolation tank 102 includes a deposition process. Deposition processes include, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0156] In one embodiment, forming an initial insulating layer 108 in the second opening 101 includes: forming a third insulating portion 106 on the inner wall surface of the second opening 101; after forming the third insulating portion 106, forming a fourth initial insulating portion 107 in the second opening 101, wherein the third insulating portion 106 is located between the sidewall of the fourth initial insulating portion 107 and the substrate 100, and between the surface of the fourth initial insulating portion 107 on the side opposite to the first direction Z and the substrate 100.

[0157] In one embodiment, the process of forming a third isolation portion 106 on the inner wall surface of the second opening 101 includes an oxidation process or a deposition process. The process of forming a fourth initial isolation portion 107 in the second opening 101 includes a deposition process. Deposition processes include, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0158] In one embodiment, during the formation of the second isolation structure 105 in the second isolation groove 102, an initial insulating isolation layer 108 is formed in the second opening 101. A third isolation portion 106 is formed during the formation of the first isolation portion 103, and a fourth initial isolation portion 107 is formed during the formation of the second isolation portion 104, simplifying the process.

[0159] In other embodiments, after the second isolation structure 105 is formed in the second isolation groove 102, an initial insulating isolation layer 108 is formed in the second opening 101; or, after the initial insulating isolation layer 108 is formed in the second opening 101, the second isolation structure 105 is formed in the second isolation groove 102.

[0160] The material description of the first isolation section 103 and the second isolation section 104 is the same as that in the previous embodiment. The material description of the third isolation section 106 is the same as that in the previous embodiment.

[0161] In one embodiment, the material of the fourth initial isolation section 107 refers to the material of the fourth isolation section 107a in the aforementioned embodiment.

[0162] In other embodiments, the second isolation structure 105 may be a single-layer structure, and the initial insulating isolation layer 108 may be a single-layer structure.

[0163] refer to Figure 11 A first isolation trench 109 is formed in the substrate 100.

[0164] In one embodiment, the process of forming the first isolation trench 109 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0165] In one embodiment, the dimension of the first isolation groove 109 along the first direction Z is greater than the dimension of the second isolation structure 105 along the first direction Z.

[0166] In one embodiment, the first isolation groove 109 is an annular structure. The first isolation groove 109 surrounds the sidewall of the second isolation structure 105.

[0167] refer to Figure 12 A first initial insulating layer 110 is formed on the sidewall of the first isolation trench 109 and the inner wall of the first isolation trench 109 on the side opposite to the first direction Z; after the first initial insulating layer 110 is formed, a sacrificial layer 111 is formed in the first isolation trench 109 from the side of the substrate 100 along the first direction Z.

[0168] In one embodiment, the process for forming the first initial insulating layer 110 includes an oxidation process or a deposition process. The process for forming the sacrificial layer 111 includes a deposition process. Deposition processes include, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0169] The material of the first initial insulating layer 110 is described with reference to the material of the first insulating layer 110a in the aforementioned embodiment. The material of the sacrificial layer 111 is different from the material of the first initial insulating layer 110. The material of the sacrificial layer 111 is, for example, polycrystalline silicon or amorphous carbon.

[0170] refer to Figures 13 to 17 A transistor 200 is formed, which includes a gate structure 201, a source region 202 and a drain region 203; a first dielectric layer 500 is formed, which is located on one side of the substrate 100 along the first direction Z and covers the gate structure 201.

[0171] refer to Figure 13 This forms transistor 200.

[0172] In some implementations, reference Figure 13 The transistor 200 is formed by: forming a gate structure 201 on one side of the substrate 100 along a first direction Z; forming a source region 202 in the substrate on one side of the gate structure 201 along a second direction; and forming a drain region 203 in the substrate 100 on the other side of the gate structure 201 along the second direction; wherein the second direction intersects the first direction Z.

[0173] The materials and structure of the gate structure 201 are described in the foregoing embodiments and will not be detailed hereafter.

[0174] Continue to refer to Figure 13 A first dielectric portion 501 and a second dielectric portion 502 are formed on one side of the substrate 100 along the first direction Z.

[0175] In some embodiments, the first dielectric portion 501 is located on one side of the substrate 100 along the first direction Z and on the side of the gate structure 201 along the direction intersecting the first direction Z, and the first dielectric portion 501 does not extend to the side of the gate structure 201 away from the substrate 100. The second dielectric portion 502 is located on the side of the first dielectric portion 501 away from the substrate 100.

[0176] In some embodiments, a second dielectric portion 502 is formed after the first dielectric portion 501 is formed. The process for forming the first dielectric portion 501 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the second dielectric portion 502 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0177] In other embodiments, the first dielectric portion 501 and the second dielectric portion 502 are formed in the same process.

[0178] In some embodiments, the material of the first dielectric portion 501 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the second dielectric portion 502 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the first dielectric portion 501 may be the same as the material of the second dielectric portion 502, or the material of the first dielectric portion 501 may be different from the material of the second dielectric portion 502.

[0179] Reference Figure 13 and Figure 14 A conductive layer 401 is formed, which is located on the side of the second dielectric portion 502 away from the substrate 100; a third insulating layer 402 is formed, which is located on the side of the conductive layer 401 away from the substrate 100.

[0180] In some implementations, in conjunction with reference Figure 13 and Figure 14 The formation of conductive layer 401 includes: forming conductive layer 401 during the formation of resistive structure 301, wherein resistive structure 301 is located on the side of second dielectric portion 502 away from substrate 100 and on the side of transistor 200 along the direction intersecting with first direction Z.

[0181] In some implementations, in conjunction with reference Figure 13 and Figure 14 The formation of the third insulating layer 402 includes: forming the third insulating layer 402 during the formation of the fourth insulating layer 302, wherein the fourth insulating layer 302 is located on the side of the resistor structure 301 away from the substrate 100.

[0182] In some embodiments, a conductive layer 401 is formed during the formation of the resistive structure 301, including: a reference Figure 13 An initial resistive film 3010 is formed on a portion of the first dielectric layer on the side facing away from the substrate 100. Specifically, an initial resistive film 3010 is formed on the side of the second dielectric portion 502 facing away from the substrate 100. (Reference) Figure 14 The initial resistive film 3010 is etched to form the resistive structure 301 and the conductive layer 401.

[0183] In some embodiments, the process for forming the initial resistive film 3010 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for etching the initial resistive film 3010 includes one or a combination of dry etching and wet etching processes.

[0184] In some embodiments, the third insulating layer 402 is formed during the formation of the fourth insulating layer 302, including: reference Figure 13 An initial insulating layer 3020 is formed on the side of the initial resistive film 3010 facing away from the substrate 100; Reference Figure 14 The initial insulating layer 3020 is etched to form the fourth insulating layer 302 and the third insulating layer 402.

[0185] In some embodiments, the process for forming the initial insulating layer 3020 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for etching the initial insulating layer 3020 includes one or a combination of dry etching and wet etching processes.

[0186] In some embodiments, the initial insulating layer 3020 and the initial resistive film 3010 are etched in the same etching process, which simplifies the process.

[0187] refer to Figure 15A third dielectric portion 503 is formed on the side of the second dielectric portion 502 that is away from the substrate 100.

[0188] In some embodiments, the process of forming the third dielectric portion 503 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0189] In some embodiments, the material of the third dielectric portion 503 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0190] Reference Figures 15 to 17 A first connection structure 704 is formed, which is located in the first dielectric layer 500 and on the side of the transistor 200 along the direction intersecting the first direction Z; a third connection structure 701 is formed, which is located in the first dielectric layer 500 on the side of the resistor structure 301 away from the substrate 100, and a portion of the third connection structure 701 penetrates the fourth insulating layer 302 along the first direction Z.

[0191] In some embodiments, forming the first connection structure 704 includes: a reference Figure 15 A first opening 602 is formed, which is located in the first dielectric layer on the side of the conductive layer 401 away from the substrate 100 and in the third insulating layer 402. The first opening 602 exposes the conductive layer 401. For example, the first opening 602 is located in the third dielectric portion 503 on the side of the conductive layer 401 away from the substrate 100 and in the third insulating layer 402; Reference Figure 16 A first connecting structure 704 is formed in the first opening 602.

[0192] During the formation of the first opening 602, the third insulating layer 402 serves as an etching barrier layer.

[0193] In some implementations, reference Figure 16 Forming a first connecting structure 704 in the first opening 602 includes: forming a first adhesive layer 704a on the sidewall of the first opening 602; and forming a first connecting layer 704b in the first opening 602; wherein the first adhesive layer 704a is located on the sidewall of the first connecting layer 704b. The structure and materials of the first connecting structure 704 are described in the foregoing embodiments.

[0194] In some embodiments, the process for forming the first opening 602 is an etching process, including one or a combination of dry etching and wet etching. The process for forming the first adhesive layer 704a on the sidewall of the first opening 602 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the first connecting layer 704b in the first opening 602 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0195] In some embodiments, a portion of the first connection structure 704 penetrates the third insulating layer 402 along the first direction Z. For example, a portion of the first connection layer 704b and a portion of the first adhesive layer 704a penetrate the third insulating layer 402 along the first direction Z.

[0196] In some embodiments, forming the third connection structure 701 includes: a reference Figure 15 A first slot 601 is formed, which is located in the third dielectric portion 503 on the side of the resistor structure 301 away from the substrate 100 and in the fourth insulating layer 302; Reference Figure 16 A third connection structure 701 is formed in the first slot 601. During the formation of the first slot 601, the fourth insulating layer 302 acts as an etching barrier layer to reduce etching damage to the resistive structure 301.

[0197] In some embodiments, the process for forming the first groove 601 is an etching process, including one or a combination of dry etching and wet etching. The process for forming the third connection structure 701 in the first groove 601 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0198] The structure and materials of the third connecting structure 701 are as described in the foregoing embodiments and will not be detailed further.

[0199] In some embodiments, the first opening 602 is formed during the formation of the first slot 601, simplifying the process. During the formation of the third connecting structure 701 in the first slot 601, the first connecting structure 704 is formed in the first opening 602, further simplifying the process.

[0200] In other embodiments, the first opening 602 is formed after the first slot 601 is formed, or the first slot 601 is formed after the first opening 602 is formed. The formation of the third connecting structure 701 in the first slot 601 and the formation of the first connecting structure 704 in the first opening 602 are performed separately in different steps.

[0201] Reference Figures 15 to 16The method for fabricating the semiconductor structure further includes: forming a fourth connection structure 702 and a fifth connection structure 703. The fourth connection structure 702 is located on the side of the gate structure 201 away from the substrate 100 and is connected to the gate structure 201. The fifth connection structure 703 is located on both sides of the fourth connection structure 702 along the second direction. The fifth connection structure 703 located on one side of the fourth connection structure 702 along the second direction is connected to the source region 202, and the fifth connection structure 703 located on the other side of the fourth connection structure 702 along the second direction is connected to the drain region 203.

[0202] The structure and materials of the fourth connecting structure 702 and the fifth connecting structure 703 are described in the foregoing embodiments.

[0203] In some embodiments, forming the fourth connection structure 702 includes: a reference Figure 15 A second slot 603 is formed, which is located in the second dielectric portion 502 and the third dielectric portion 503 on the side of the gate structure 201 opposite to the substrate 100; Reference Figure 16 A fourth connecting structure 702 is formed in the second slot 603.

[0204] In some embodiments, the process for forming the second groove 603 is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the fourth connection structure 702 in the second groove 603 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0205] In some embodiments, forming the fifth connection structure 703 includes: a reference Figure 15 A third slot 604 is formed, which is located in the first medium section 501, the second medium section 502 and the third medium section 503. Part of the third slot 604 exposes the source region 202 and part of the third slot 604 exposes the drain region 203. A fifth connection structure 703 is formed in the third slot 604.

[0206] In some embodiments, the process for forming the third groove 604 is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the fifth connection structure 703 in the third groove 604 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0207] In some embodiments, a first slot 601, a second slot 603, and a third slot 604 are formed during the formation of the first opening 602, simplifying the process. During the formation of the first connecting structure 704 in the first opening 602, a third connecting structure 701 is formed in the first slot 601, a fourth connecting structure 702 is formed in the second slot 603, and a fifth connecting structure 703 is formed in the third slot 604, further simplifying the process.

[0208] In other embodiments, the first opening 602, the first slot 601, the second slot 603, and the third slot 604 are formed separately in different steps. The formation of the first connecting structure 704 in the first opening 602, the formation of the third connecting structure 701 in the first slot 601, the formation of the fourth connecting structure 702 in the second slot 603, and the formation of the fifth connecting structure 703 in the third slot 604 are performed separately in different steps.

[0209] refer to Figure 17 A fourth dielectric portion 504 is formed on the side of the third dielectric portion 503 facing away from the substrate 100. The first dielectric portion 501, the second dielectric portion 502, the third dielectric portion 503 and the fourth dielectric portion 504 constitute the first dielectric layer 500.

[0210] In some embodiments, the process for forming the fourth dielectric portion 504 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0211] In some embodiments, the material of the fourth dielectric portion 504 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0212] Continue to refer to Figure 17 A fourth interconnect 804, a fifth interconnect 802, a sixth interconnect 803, and a seventh interconnect 801 are formed in the fourth medium section 504.

[0213] In some embodiments, forming the fourth interconnect 804 includes: forming a fourth trench (not shown) in the fourth dielectric portion 504; and forming the fourth interconnect 804 in the fourth opening. The process for forming the fourth trench is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the fourth interconnect 804 in the fourth opening is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0214] In some embodiments, forming the fifth interconnect 802 includes: forming a fifth trench (not shown) in the fourth dielectric portion 504; and forming the fifth interconnect 802 in the fifth trench. The process for forming the fifth trench is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the fifth interconnect 802 in the fifth trench is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0215] In some embodiments, forming the sixth interconnect 803 includes: forming a sixth trench (not shown) in the fourth dielectric portion 504; and forming the sixth interconnect 803 in the sixth trench. The process for forming the sixth trench is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the sixth interconnect 803 in the sixth trench is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0216] In some embodiments, forming the seventh interconnect 801 includes: forming a seventh trench (not shown) in the fourth dielectric portion 504; and forming the seventh interconnect 801 in the seventh trench. The process for forming the seventh trench is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the seventh interconnect 801 in the seventh trench is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0217] In some embodiments, a fifth, sixth, and seventh slot are formed during the formation of the fourth slot; and a fifth interconnect 802 is formed in the fifth slot, a sixth interconnect 803 is formed in the sixth slot, and a seventh interconnect 801 is formed in the seventh slot during the formation of the fourth interconnect 804 in the fourth opening, thus simplifying the process.

[0218] In other embodiments, the fourth, fifth, sixth, and seventh slots are formed in different steps. The formation of the fourth interconnect 804 in the fourth opening, the formation of the fifth interconnect 802 in the fifth slot, the formation of the sixth interconnect 803 in the sixth slot, and the formation of the seventh interconnect 801 in the seventh slot are performed in different steps.

[0219] The materials of the fourth interconnecting component 804, the fifth interconnecting component 802, the sixth interconnecting component 803, and the seventh interconnecting component 801 are described with reference to the aforementioned embodiments and will not be described in detail again.

[0220] In some embodiments, a fourth insulating layer 302 is located in the first dielectric layer 500. A third insulating layer 402 is located in the first dielectric layer 500. A conductive layer 401 is located in the first dielectric layer 500 and spaced from the substrate 100. A resistive structure 301 is located in the first dielectric layer 500. A first connection structure 704, a third connection structure 701, a fourth connection structure 702, and a fifth connection structure 703 are located in the first dielectric layer 500. A fourth interconnect 804, a fifth interconnect 802, a sixth interconnect 803, and a seventh interconnect 801 are located in the first dielectric layer 500.

[0221] refer to Figure 18 The first dielectric layer 500 is bonded to the support substrate 900. For example, the first dielectric layer 500 is bonded to the support substrate 900 via a bonding dielectric layer 901. The bonding dielectric layer 901 is located between the first dielectric layer 500 and the support substrate 900, between the fourth interconnect 804 and the support substrate 900, between the fifth interconnect 802 and the support substrate 900, between the sixth interconnect 803 and the support substrate 900, and between the seventh interconnect 801 and the support substrate 900.

[0222] The support substrate 900 provides support for the execution of subsequent steps.

[0223] The material descriptions of the support substrate 900 and the bonding dielectric layer 901 are as described in the foregoing embodiments.

[0224] refer to Figure 19 The portion of the inner wall of the first initial insulating layer 110 located on the side opposite to the first direction Z of the first isolation trench is removed, wherein the portion of the first initial insulating layer 110 located on the side wall of the first isolation trench forms the first insulating layer 110a. The first insulating layer 110a is located between the sacrificial layer 111 and the substrate 100.

[0225] For example, a portion of the surface of the first initial insulating layer 110 located on the side opposite to the first direction Z of the sacrificial layer 111 is removed, wherein the portion of the first initial insulating layer 110 located on the sidewall of the sacrificial layer 111 forms the first insulating layer 110a.

[0226] refer to Figure 19 The method for fabricating the semiconductor structure further includes: thinning the substrate 100 from a side opposite to the first direction Z, for example, thinning the substrate 100 from the side of the substrate 100 away from the gate structure 201. The process for thinning the substrate 100 includes a chemical mechanical polishing process.

[0227] In some embodiments, removing the portion of the inner wall of the first initial insulating layer 110 located on the side opposite to the first direction Z of the first isolation trench includes: removing the portion of the inner wall of the first initial insulating layer 110 located on the side opposite to the first direction Z of the first isolation trench during the thinning of the substrate 100, and exposing the sacrificial layer 111.

[0228] In other embodiments, the process may involve: after forming a first insulating layer on the sidewall of the first isolation trench, forming a sacrificial layer in the first isolation trench from one side of the substrate along a first direction; forming the first insulating layer on the sidewall of the first isolation trench includes: forming a first initial insulating layer on the sidewall of the first isolation trench and on the inner wall of the first isolation trench on the side opposite to the first direction, and then removing the portion of the first initial insulating layer located on the inner wall of the first isolation trench on the side opposite to the first direction Z. The substrate is then thinned from the side opposite to the first direction until the sacrificial layer is exposed.

[0229] In some embodiments, the method for fabricating the semiconductor structure further includes: removing the portion of the third isolation portion 106 located in the fourth initial isolation portion 107 away from the first dielectric layer 500, and retaining the portion of the third isolation portion 106 located between the sidewall of the fourth initial isolation portion 107 and the substrate 100.

[0230] In some embodiments, during the thinning of the substrate 100, the portion of the third isolation portion 106 located on the fourth initial isolation portion 107 away from the first dielectric layer 500 is removed.

[0231] refer to Figure 20 After thinning the substrate 100, a fifth dielectric portion 902 is formed on the side of the substrate 100 away from the first dielectric layer 500. The fifth dielectric portion 902 is also located on the side of the first insulating layer 110a away from the first dielectric layer 500 and the side of the initial insulating isolation layer 108 away from the first dielectric layer 500. An eighth slot 9021 is formed in the fifth dielectric portion 902, and the eighth slot 9021 exposes the sacrificial layer 111.

[0232] In some embodiments, the process for forming the fifth dielectric portion 902 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the eighth trench 9021 is an etching process, including one or a combination of dry etching and wet etching processes.

[0233] In some embodiments, the material of the fifth dielectric section 902 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0234] In some embodiments, the material of the fifth dielectric section 902 is different from the material of the sacrificial layer 111.

[0235] refer to Figure 21 After the fifth medium section 902 is formed, the sacrificial layer 111 is removed.

[0236] Remove the sacrificial layer 111 to expose the first isolation slot 109.

[0237] In some embodiments, the sacrificial layer 111 is removed from the substrate 100 along a side opposite to the first direction Z.

[0238] In some embodiments, the process for removing the sacrificial layer 111 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0239] During the removal of the sacrificial layer 111, the fifth dielectric section 902 protects the substrate 100, the initial insulating isolation layer 108, and the first insulating layer 110a.

[0240] refer to Figure 22 A capacitor structure 906 is formed in the first isolation groove 109. The capacitor structure 906 includes a first electrode layer 903, a second electrode layer 904, and a second insulating layer 905 extending along the first direction Z. The second insulating layer 905 is located between the first electrode layer 903 and the second electrode layer 904 along a direction intersecting the first direction Z.

[0241] In some embodiments, after the sacrificial layer 111 is removed from the substrate 100 along the side opposite to the first direction Z, a capacitor structure 906 is formed in the first isolation trench 109.

[0242] In some embodiments, forming a capacitor structure 906 in the first isolation trench 109 includes: forming a first electrode layer 903 and a second electrode layer 904 in the first isolation trench 109 from the side of the substrate 100 opposite to the first direction Z; and forming a second insulating layer 905 in the first isolation trench 109 from the side of the substrate 100 opposite to the first direction Z.

[0243] In some embodiments, forming a first electrode layer 903 and a second electrode layer 904 in a first isolation trench 109 from the side of the substrate 100 opposite to the first direction Z includes: forming an initial electrode layer in the first isolation trench 109, the initial electrode layer being located on the sidewall of the first insulating layer 110a away from the substrate 100 and on the inner wall of the first isolation trench 109 along the first direction Z; and removing the portion of the initial electrode layer located on the inner wall of the first isolation trench 109 along the first direction Z, wherein the portion of the initial electrode layer located on the sidewall of the first insulating layer 110a away from the substrate 100 forms the first electrode layer 903 and the second electrode layer 904.

[0244] In some embodiments, the process for forming the initial electrode layer is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the second insulating layer 905 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0245] The materials of the first electrode layer 903 and the second electrode layer 904 are as described in the foregoing embodiment. The material of the second insulating layer 905 is as described in the foregoing embodiment.

[0246] In some embodiments, a capacitor structure 906 is formed in the first isolation groove 109 and the eighth slot 9021. In other embodiments, the capacitor structure is formed in the first isolation groove 109, and the capacitor structure does not extend into the eighth slot 9021.

[0247] In some embodiments, capacitor structure 906 and first insulating layer 110a constitute a first isolation structure 907. The first isolation structure 907 is located on the side of transistor 200 along a direction intersecting the first direction Z. A second isolation structure 105 is located between the first isolation structure 907 and transistor 200, and the dimension of the second isolation structure 105 along the first direction Z is smaller than the dimension of the first isolation structure 907 along the first direction.

[0248] Reference Figures 23 to 25 A first lead-out structure 920 is formed, which is located on the side of the substrate 100 opposite to the first direction Z and connected to the first electrode layer 903; a second lead-out structure 918 is formed, which is located on the side of the substrate 100 opposite to the first direction Z and connected to the second electrode layer 904.

[0249] In some embodiments, forming the first lead-out structure 920 includes: referencing Figure 24 This forms a first lead-out 914, which is connected to the first electrode layer 903; Reference Figure 25 A first interconnect 919 is formed, which is located on the side of the first lead-out 914 away from the substrate 100 and connected to the first lead-out 914. The size of the first lead-out 914 is smaller than the size of the first interconnect 919 along the direction intersecting the first direction Z.

[0250] In some embodiments, forming the second lead-out structure 918 includes: referencing Figure 24A second lead-out 913 is formed, which is connected to the second electrode layer 904; and a second interconnect 917 is formed, which is located on the side of the second lead-out 913 away from the substrate 100 and connected to the second lead-out 913, wherein the size of the second lead-out 913 is smaller than the size of the second interconnect 917 along the direction intersecting the first direction Z.

[0251] refer to Figure 23 A sixth dielectric portion 908 is formed on the side of the fifth dielectric portion 902 facing away from the substrate 100; a ninth groove 910 is formed in the sixth dielectric portion 908; a tenth groove 909 is formed in the sixth dielectric portion 908; a third opening 911 is formed, the third opening 911 penetrates along the first direction Z through the initial insulating isolation layer 108, the portion of the first dielectric layer 500 located between the conductive layer 401 and the substrate 100, and the conductive layer 401, wherein the portion of the initial insulating isolation layer 108 located between the third opening 911 and the substrate 100 forms an insulating isolation layer 108a.

[0252] The insulating layer 108a includes a third insulating portion 106 and a fourth insulating portion 107a. The materials and positions of the third insulating portion 106 and the fourth insulating portion 107a are as described in the previous embodiment.

[0253] In some embodiments, the tenth slot 909 is formed during the formation of the ninth slot 910. In other embodiments, the tenth slot 909 is formed after the formation of the ninth slot 910, or the ninth slot 910 is formed after the formation of the tenth slot 909.

[0254] In some embodiments, a third opening 911 is formed after the ninth slot 910 and the tenth slot 909 are formed. In other embodiments, the ninth slot 910 and the tenth slot 909 are formed after the third opening 911 is formed.

[0255] In some embodiments, the process for forming the sixth dielectric portion 908 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the ninth trench 910 is an etching process, including one or a combination of dry etching and wet etching. The process for forming the tenth trench 909 is an etching process, including one or a combination of dry etching and wet etching. The process for forming the third opening 911 is an etching process, including one or a combination of dry etching and wet etching.

[0256] In some embodiments, the third opening 911 extends through the fifth medium portion 902 and the sixth medium portion 908 along the first direction Z.

[0257] In some embodiments, the material of the sixth dielectric portion 908 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0258] refer to Figure 24 A second connecting layer 912 is formed in the third opening 911; a first lead-out 914 is formed in the ninth slot 910; and a second lead-out 913 is formed in the tenth slot 909.

[0259] In some implementations, the second lead 913 is formed during the formation of the first lead 914, simplifying the process.

[0260] In other embodiments, the second lead-out 913 is formed after the first lead-out 914 is formed, or the first lead-out 914 is formed after the second lead-out 913 is formed.

[0261] In some embodiments, the process of forming the second connecting layer 912 in the third opening 911 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process of forming the first lead 914 in the ninth slot 910 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process of forming the second lead 913 in the tenth slot 909 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0262] The materials of the first lead-out member 914 and the second lead-out member 913 are as described in the foregoing embodiments.

[0263] The second connection layer 912 and the insulating isolation layer 108a constitute a second connection structure 913. The second connection structure 913 penetrates the substrate 100 and the portion of the first dielectric layer 500 located between the first connection structure 704 and the substrate 100 along the first direction Z. The second connection structure 913 is connected to the first connection structure 704. A portion of the second connection structure 913 penetrates the conductive layer 401 along the first direction Z.

[0264] refer to Figure 25 A seventh dielectric portion 909 is formed on the side of the sixth dielectric portion 908 away from the substrate 100. The fifth dielectric portion 902, the sixth dielectric portion 908, and the seventh dielectric portion 909 constitute a second dielectric layer 915. A first interconnect 919 is formed in the seventh dielectric portion 909. A second interconnect 917 is formed in the seventh dielectric portion 909. A third interconnect 916 is formed in the seventh dielectric portion 909.

[0265] In some embodiments, the process for forming the seventh dielectric section 909 is a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0266] In some embodiments, the material of the seventh dielectric portion 909 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0267] In some embodiments, the fifth medium section 902, the sixth medium section 908, and the seventh medium section 909 are made of the same material, and the fifth medium section 902, the sixth medium section 908, and the seventh medium section 909 are an integral structure.

[0268] In other embodiments, the materials of the fifth medium section 902, the sixth medium section 908, and the seventh medium section 909 are different or completely different.

[0269] The materials of the first interconnect 919, the second interconnect 917, and the third interconnect 916 are as described in the foregoing embodiments.

[0270] In some embodiments, during the process of forming the first interconnect 919 in the seventh medium section 909, the second interconnect 917 is formed in the seventh medium section 909, and the third interconnect 916 is formed in the seventh medium section 909.

[0271] In other embodiments, the first interconnect 919, the second interconnect 917, and the third interconnect 916 are formed separately in different steps.

[0272] The second dielectric layer 915 is located on the side of the substrate 100 opposite to the first direction Z. For example, the second dielectric layer 915 is located on the side of the substrate 100 away from the first dielectric layer 500. The first lead-out structure 920 and the second lead-out structure 918 are located in the second dielectric layer 915.

[0273] In some embodiments, the first electrode layer 903 and the second electrode layer 904 further extend into a portion of the second dielectric layer 915. In other embodiments, the first electrode layer 903 and the second electrode layer 904 may extend into the second dielectric layer 915.

[0274] It should be noted that, in other embodiments, forming a first isolation structure extending along a first direction in the substrate includes: forming a first isolation structure in the substrate from one side of the substrate along the first direction.

[0275] Another embodiment of this application also provides a memory, referenced... Figure 26 It includes a memory cell array F1 and a peripheral circuit F2. The peripheral circuit F2 includes the semiconductor structure provided in the above embodiments of this application. The peripheral circuit F2 is coupled to the memory cell array F1.

[0276] The memory cell array F1 can be a 3D NAND flash memory cell array. The memory cell array F1 can also be a DRAM cell array.

[0277] The semiconductor structure may be the same as the semiconductor structure described in any of the embodiments above, and will not be described again in the embodiments of this application.

[0278] In some implementations, the peripheral circuitry F2 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory cell array F1. For example, the peripheral circuitry F2 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0279] Another embodiment of this application also provides a system 30000 having a storage system 32000. (See reference...) Figure 27 , Figure 27 This is a block diagram of a system 30000 having a storage system 32000 according to one embodiment of this application. Figure 28 This is a schematic diagram of a storage system according to one embodiment of this application.

[0280] like Figure 27 As shown, system 30000 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 32000 located therein). Figure 27 As shown, system 30000 may include host 31000 and storage system 32000, storage system 32000 having one or more memories 32100 and controller 32200. Host 31000 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 31000 may be configured to send or receive data to and from memory 32100.

[0281] Memory 32100 may include the memory described in any embodiment of this application. According to some embodiments, controller 32200 is coupled to memory 32100 and host 31000 and is configured to control memory 32100. Controller 32200 can manage data stored in memory 32100 and communicate with host 31000. In some embodiments, controller 32200 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 32200 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device such as a smartphone, tablet, laptop, etc. The controller 32200 can be configured to control the operation of the memory 32100, such as read, erase, and program operations. The controller 32200 can also be configured to manage various functions related to data stored in or to be stored in the memory 32100, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the controller 32200 is further configured to process error correction codes (ECCs) related to data read from or written to the memory 32100. The controller 32200 can also perform any other appropriate functions, such as formatting the memory 32100. The controller 32200 can communicate with external devices (e.g., host 31000) according to a specific communication protocol. For example, the controller 32200 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-express, PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0282] The controller 32200 and one or more memories 32100 can be integrated into various types of storage systems, such as Universal Flash Memory (UFS) packaged products or eMMC packaged products, where the controller 32200 and one or more memories 32100 can be included in the same packaged product (such as a Universal Flash Memory (UFS) packaged product or an eMMC packaged product). Figure 28 In one example shown in (a), the controller 32200 and a single memory 32100 may be integrated into a memory card 33100. The memory card 33100 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 33100 may further include a connection between the memory card 33100 and a host (e.g., Figure 27 The host 31000 in the memory card connector 32300 is coupled to the host 31000. In such a... Figure 28 In another example shown in (b), the controller 32200 and multiple memories 32100 may be integrated into the solid-state drive 33200. The solid-state drive 33200 may further include a connection between the solid-state drive 33200 and a host (e.g., Figure 27 The solid-state drive connector 32400 is coupled to the host 3100. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 33200 is higher than that of the memory card 33100.

[0283] Although exemplary fabrication methods and structures of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure. Furthermore, the materials of the exemplified layers are merely exemplary.

[0284] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, comprising: Substrate; as well as A first isolation structure, located in the substrate and extending along a first direction, includes: A capacitor structure extending along the first direction; as well as A first insulating layer is located between the capacitor structure and the substrate.

2. The semiconductor structure according to claim 1, wherein, The capacitor structure includes: A first electrode layer, a second electrode layer, and a second insulating layer extending along the first direction, wherein the second insulating layer is located between the first electrode layer and the second electrode layer along a direction intersecting the first direction.

3. The semiconductor structure according to claim 2, wherein, The first electrode layer and the second electrode layer have a ring structure, with the second electrode layer surrounding the sidewall of the first electrode layer.

4. The semiconductor structure according to claim 1, wherein, The semiconductor structure further includes a transistor, the transistor comprising: A gate structure is located on one side of the substrate along the first direction; The source region is located in the substrate and is situated on one side of the gate structure along the second direction; and The drain region is located in the substrate and on the other side of the gate structure along the second direction; Wherein, the second direction intersects with the first direction; The first isolation structure is located on the side of the transistor along a direction intersecting the first direction.

5. The semiconductor structure according to claim 4, wherein, The semiconductor structure also includes: A first dielectric layer is located on one side of the substrate along the first direction and covers the gate structure; A first connection structure is located in the first dielectric layer and on one side of the transistor along a direction intersecting the first direction; and The second connection structure extends along the first direction through the substrate and the portion of the first dielectric layer located between the first connection structure and the substrate, and the second connection structure is connected to the first connection structure.

6. The semiconductor structure according to claim 5, wherein, The semiconductor structure also includes: A conductive layer, located within the first dielectric layer and spaced from the substrate; and A third insulating layer is located in the first dielectric layer and on the side of the conductive layer opposite to the substrate; Wherein, a portion of the first connection structure penetrates the third insulating layer along the first direction; a portion of the second connection structure penetrates the conductive layer along the first direction.

7. The semiconductor structure according to claim 6, wherein, The semiconductor structure also includes: A resistor structure is located in the first dielectric layer and on one side of the transistor along the direction intersecting the first direction; A fourth insulating layer is located within the first dielectric layer and on the side of the resistive structure opposite to the substrate; and A third connection structure is located in the first dielectric layer on the side of the resistor structure facing away from the substrate, and a portion of the third connection structure penetrates the fourth insulating layer along the first direction; Wherein, the material of the third insulating layer is the same as that of the fourth insulating layer, and the material of the conductive layer is the same as that of the resistive structure; wherein, the third insulating layer and the fourth insulating layer have the same height relative to the substrate along the first direction, and the conductive layer and the resistive structure have the same height relative to the substrate along the first direction.

8. The semiconductor structure according to claim 6, wherein, The first connection structure includes: A first connecting layer and a first adhesive layer located on the sidewall of the first connecting layer, a portion of the first connecting layer and a portion of the first adhesive layer penetrating the third insulating layer along the first direction.

9. The semiconductor structure according to claim 6, wherein, The second connection structure includes: A second interconnecting layer extends along the first direction through the substrate, the portion of the first dielectric layer located between the conductive layer and the substrate, and the conductive layer; and An insulating layer is located between the second connecting layer and the substrate.

10. The semiconductor structure according to claim 2, wherein, The semiconductor structure also includes: A first lead-out structure is located on one side of the substrate in the opposite direction to the first direction and is connected to the first electrode layer; and The second lead-out structure is located on one side of the substrate in the opposite direction to the first direction and is connected to the second electrode layer.

11. The semiconductor structure according to claim 10, wherein, The semiconductor structure also includes: The second dielectric layer is located on the side of the substrate opposite to the first direction; The first lead-out structure and the second lead-out structure are located in the second dielectric layer.

12. The semiconductor structure according to claim 11, wherein, The first electrode layer and the second electrode layer also extend into a portion of the second dielectric layer.

13. A method for fabricating a semiconductor structure, comprising: A first isolation structure extending along a first direction is formed in the substrate; The first isolation structure includes: A capacitor structure extending along the first direction; and A first insulating layer is located between the capacitor structure and the substrate.

14. The preparation method according to claim 13, wherein, Forming the first isolation structure extending along the first direction in the substrate includes: The first isolation structure is formed in the substrate from one side of the substrate along the first direction.

15. The preparation method according to claim 13, wherein, Forming the first isolation structure includes: A first isolation trench is formed in the substrate; A first insulating layer is formed on the sidewall of the first isolation groove; and The capacitor structure is formed in the first isolation groove. The capacitor structure includes a first electrode layer, a second electrode layer and a second insulating layer extending along the first direction, wherein the second insulating layer is located between the first electrode layer and the second electrode layer along a direction intersecting the first direction.

16. The preparation method according to claim 15, wherein, The formation of the first isolation structure also includes: A sacrificial layer is formed in the first isolation trench from one side of the substrate along the first direction; wherein the first insulating layer is located between the sacrificial layer and the substrate; and Before forming the capacitor structure in the first isolation trench, the sacrificial layer is removed from the substrate along a side opposite to the first direction; The formation of the capacitor structure in the first isolation groove includes: The first electrode layer and the second electrode layer are formed in the first isolation trench from the substrate along a side opposite to the first direction; and The second insulating layer is formed in the first isolation trench from the side of the substrate in the opposite direction to the first direction.

17. The preparation method according to claim 16, wherein, Forming the first electrode layer and the second electrode layer in the first isolation trench from the substrate along a side opposite to the first direction includes: An initial electrode layer is formed in the first isolation trench, the initial electrode layer being located on the sidewall of the first insulating layer opposite to the substrate and on the inner wall of the first isolation trench along the first direction; and The portion of the initial electrode layer located on the inner wall of the first isolation trench along the first direction is removed, wherein the portion of the initial electrode layer located on the side wall of the first insulating layer opposite to the substrate forms the first electrode layer and the second electrode layer.

18. The preparation method according to claim 16, wherein, Forming the first insulating layer on the sidewall of the first isolation trench includes: Before forming the sacrificial layer, a first initial insulating layer is formed on the sidewall of the first isolation trench and the inner wall of the first isolation trench on the side opposite to the first direction; and Remove the portion of the first initial insulating layer located on the inner wall of the first isolation groove on the side opposite to the first direction, wherein the portion of the first initial insulating layer located on the side wall of the first isolation groove forms the first insulating layer.

19. The preparation method according to claim 18, wherein, Removing the portion of the inner wall of the first initial insulating layer located on the side opposite to the first direction of the first insulating groove includes: Before removing the sacrificial layer, remove the portion of the first initial insulating layer located on the inner wall of the first isolation trench on the side opposite to the first direction.

20. The preparation method according to claim 19, wherein, The preparation method further includes: The substrate is thinned from a side opposite to the first direction; The portion of the inner wall of the first isolation groove located on the side opposite to the first direction, where the first initial insulating layer is removed, includes: During the thinning of the substrate, a portion of the inner wall of the first initial insulating layer located on the side opposite to the first direction of the first isolation trench is removed, exposing the sacrificial layer.

21. The preparation method according to claim 13, wherein, The preparation method further includes: Forming a transistor includes: A gate structure is formed on one side of the substrate along the first direction; A source region is formed in the substrate on one side of the gate structure along the second direction; and A drain region is formed in the substrate on the other side of the gate structure along the second direction; Wherein, the second direction intersects with the first direction; The first isolation structure is located on the side of the transistor along a direction intersecting the first direction.

22. The preparation method according to claim 21, wherein, The preparation method further includes: A first dielectric layer is formed, the first dielectric layer being located on one side of the substrate along the first direction and covering the gate structure; A first connection structure is formed, the first connection structure being located in the first dielectric layer and on one side of the transistor along a direction intersecting the first direction; and A second connection structure is formed, which extends along the first direction through the substrate and the portion of the first dielectric layer located between the first connection structure and the substrate, and the second connection structure is connected to the first connection structure.

23. The preparation method according to claim 22, wherein, The preparation method further includes: A conductive layer is formed, the conductive layer being located in the first dielectric layer and spaced from the substrate; A third insulating layer is formed, the third insulating layer being located in the first dielectric layer and on the side of the conductive layer opposite to the substrate; Wherein, a portion of the first connection structure penetrates the third insulating layer along the first direction; a portion of the second connection structure penetrates the conductive layer along the first direction.

24. The preparation method according to claim 23, wherein, The formation of the conductive layer includes: The conductive layer is formed during the formation of the resistive structure, wherein the resistive structure is located in the first dielectric layer and on one side of the transistor along the direction intersecting the first direction; The formation of the third insulating layer includes: The third insulating layer is formed during the formation of the fourth insulating layer, wherein the fourth insulating layer is located within the first dielectric layer and on the side of the resistive structure opposite to the substrate; and The preparation method further includes: A third connection structure is formed, the third connection structure being located in the first dielectric layer on the side of the resistive structure opposite to the substrate, and a portion of the third connection structure penetrating the fourth insulating layer along the first direction.

25. The preparation method according to claim 24, wherein, The formation of the conductive layer during the formation of the resistive structure includes: An initial resistive film is formed on a portion of the first dielectric layer on the side facing away from the substrate; and The initial resistive film is etched to form the resistive structure and the conductive layer; The formation of the third insulating layer during the formation of the fourth insulating layer includes: An initial insulating layer is formed on the side of the initial resistive film opposite to the substrate; and The initial insulating layer is etched to form the fourth insulating layer and the third insulating layer.

26. The preparation method according to claim 23, wherein, Forming the first connection structure includes: A first opening is formed, the first opening being located in the first dielectric layer and the third insulating layer on the side of the conductive layer opposite to the substrate, the first opening exposing the conductive layer; and The first connection structure is formed in the first opening.

27. The preparation method according to claim 23, wherein, Forming the second connection structure includes: A second opening extending along the first direction is formed in the substrate; An initial insulating layer is formed in the second opening; A third opening is formed, the third opening penetrating along the first direction through the initial insulating layer, the portion of the first dielectric layer located between the conductive layer and the substrate, and the conductive layer, wherein the portion of the initial insulating layer located between the third opening and the substrate forms an insulating layer; and A second connecting layer is formed in the third opening.

28. The preparation method according to claim 15, wherein, The preparation method further includes: A first lead-out structure is formed, the first lead-out structure being located on one side of the substrate opposite to the first direction and connected to the first electrode layer; and A second lead-out structure is formed, which is located on one side of the substrate in the opposite direction to the first direction and is connected to the second electrode layer.

29. The preparation method according to claim 28, wherein, The preparation method further includes: A second dielectric layer is formed, the second dielectric layer being located on the side of the substrate opposite to the first direction; The first lead-out structure and the second lead-out structure are located in the second dielectric layer.

30. A memory comprising: Memory cell array; as well as Peripheral circuitry coupled to the memory cell array, the peripheral circuitry comprising a semiconductor structure as described in any one of claims 1 to 12.

31. A storage system, comprising: The memory as described in claim 30; as well as A controller, coupled to the memory, is used to control the memory to store data.

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