Semiconductor structure, manufacturing method thereof and memory

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure comprises an active column array; each active column comprises a first source / drain electrode, a channel and a second source / drain electrode which are vertically arranged; a plurality of word lines; each word line comprises a plurality of first parts and a plurality of second parts; each first part at least covers one side wall of a channel of one active column in one row of active columns of the corresponding active column array, and each second part is connected with two adjacent second parts; wherein the size of the first part in the vertical direction is larger than that of the second part in the vertical direction; a plurality of memory cells; each storage unit is connected with a first source / drain electrode; a plurality of bit lines; each bit line is connected with a second source / drain electrode of each active column of a column of active columns of the active column array.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, including but not limited to a semiconductor structure and its manufacturing method, and a memory. Background Technology

[0002] As the integration density of semiconductor devices increases and their size continues to shrink, the transistor feature size in semiconductor devices, such as Dynamic Random Access Memory (DRAM), shrinks to the nanoscale. This limits the power consumption, density, and mobility of transistors, posing greater challenges to improving transistor performance. For example, while increasing the number of memory cells per unit density, reducing parasitic capacitance and mitigating row hammer effects remains a challenge. Summary of the Invention

[0003] In view of this, embodiments of this application provide a semiconductor structure, a method for manufacturing the same, and a memory.

[0004] In a first aspect, embodiments of this application provide a semiconductor structure comprising: an active pillar array; each active pillar including a vertically disposed first source / drain, a channel, and a second source / drain; multiple word lines; each word line including multiple first portions and multiple second portions; each first portion at least covers one sidewall of the channel of one active pillar in a row of active pillars in the corresponding active pillar array, and each second portion connects two adjacent second portions; wherein the dimension of the first portion in the vertical direction is larger than the dimension of the second portion in the vertical direction; multiple memory cells; each memory cell is respectively connected to a first source / drain; and multiple bit lines; each bit line is connected to the second source / drain of each active pillar in a row of active pillars in the active pillar array.

[0005] In some embodiments, the ratio between the vertical dimension of the channel and the vertical dimension of the second portion is greater than or equal to 2.

[0006] In some embodiments, the plurality of second portions corresponding to each word line are disposed near the second source / drain; or, the plurality of second portions corresponding to each word line are disposed near the first source / drain; or, the plurality of second portions corresponding to each word line are disposed near the middle of the channel.

[0007] In some embodiments, the dimensions of the first portion along the column active column arrangement direction are substantially the same as the dimensions of the second portion along the column active column arrangement direction.

[0008] In some embodiments, at least two adjacent character lines correspond to a plurality of second portions which are staggered in the vertical direction.

[0009] In some embodiments, the plurality of word lines include: a plurality of first-type word lines; a first portion of each first-type word line covers a first sidewall of the channel of an odd-numbered active column in a row of active columns, and a second portion of each first-type word line connects two adjacent first portions and covers portions of the first sidewall of the channel of an even-numbered active column in a row of active columns; and a plurality of second-type word lines; a first portion of each second-type word line covers a second sidewall of the channel of an even-numbered active column in a row of active columns, and a second portion of each second-type word line connects two adjacent first portions and covers portions of the first sidewall of the channel of an odd-numbered active column in a row of active columns; the first sidewall and the second sidewall are opposite sidewalls along the extension direction of the column of active columns.

[0010] In some embodiments, each active column is located at the intersection of the row active column arrangement direction and the column active column arrangement direction; the number of active columns in the column active columns corresponding to each bit line is the same.

[0011] In some embodiments, the semiconductor structure further includes: a first word line contact corresponding to odd-numbered row word lines and a second word line contact corresponding to even-numbered row word lines, and a first bit line contact corresponding to odd-numbered column bit lines and a second bit line contact corresponding to even-numbered column bit lines; wherein the first word line contact and the second word line contact are located on both sides of the active pillar array along the row active pillar arrangement direction; the first bit line contact and the second bit line contact are located on both sides of the active pillar array along a direction perpendicular to the row active pillar arrangement direction.

[0012] In some embodiments, the semiconductor structure includes a dynamic random access memory, and the memory cell includes a memory capacitor; one end of the memory capacitor is connected to the first source / drain of an active pillar in the active pillar array, and the other end of the memory capacitor is grounded, and the memory capacitor is used to store the written data.

[0013] In some embodiments, the plurality of storage capacitors are arranged in a square or in a hexagonal arrangement.

[0014] Secondly, embodiments of this application provide a memory comprising: any of the semiconductor structures provided in the embodiments of the first aspect; word lines of the semiconductor structure are configured to receive word line voltage and control the channel of the active pillar of the semiconductor structure to be turned on or off by the word line voltage, for connecting / disconnecting the first source / drain and the second source / drain of the semiconductor structure; bit lines of the semiconductor structure are configured to perform read or write operations on the memory cells of the semiconductor structure when the channel of the active pillar is turned on.

[0015] In some embodiments, even-numbered bit lines are configured to receive word line voltage to control the channel conduction of the corresponding active pillar, and even-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the active pillar's channel is conduction; odd-numbered bit lines are configured to receive a default voltage to shield the even-numbered bit lines; or, odd-numbered bit lines are configured to receive word line voltage to control the channel conduction of the corresponding active pillar, and odd-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the active pillar's channel is conduction; even-numbered bit lines are configured to receive a default voltage to shield the odd-numbered bit lines.

[0016] Thirdly, embodiments of this application provide a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; forming an active pillar array along a first surface of the substrate; each active pillar being used to form a first source / drain, a channel, and a second source / drain, all disposed vertically; forming a plurality of word lines; each word line comprising a plurality of first portions and a plurality of second portions; each first portion at least covering one sidewall of the channel of one active pillar in a row of active pillars in the corresponding active pillar array, each second portion connecting two adjacent second portions; wherein the dimension of the first portion in the vertical direction is larger than the dimension of the second portion in the vertical direction; forming a plurality of memory cells; each memory cell being connected to a first source / drain; forming a plurality of bit lines along a second surface of the substrate; each bit line being connected to the second source / drain of each active pillar in a row of active pillars in the active pillar array; the second surface being the opposite surface to the first surface being the substrate in the vertical direction.

[0017] In some embodiments, forming an active pillar array along a first surface of a substrate includes: forming a plurality of spaced-apart first trenches and active strips along the first surface of the substrate, wherein the first trenches and active strips extend along a first direction; filling the first trenches with insulating material to form a first isolation structure; forming a plurality of spaced-apart second trenches along the first surface of the substrate in the first isolation structure and active strips, wherein the second trenches extend along a second direction; the plurality of second trenches divide each active strip into a plurality of active pillars extending along a third direction; wherein the dimension of the second trench along the third direction is smaller than the dimension of the first trench along the third direction; the third direction is perpendicular to the plane formed by the first direction and the second direction; and there is an angle between the first direction and the second direction.

[0018] In some embodiments, forming multiple word lines includes: forming a gate dielectric layer, a first conductive structure, and a second isolation structure sequentially covering the second trench in a second trench along a first surface of the substrate; forming multiple third trenches by removing at least a portion of the first conductive structure corresponding to the first sidewalls of two adjacent even-numbered active pillars in a row of active pillars along the first surface of the substrate, and forming multiple fourth trenches by removing at least a portion of the first conductive structure corresponding to the second sidewalls of two adjacent odd-numbered active pillars in a row of active pillars; filling the third trenches and fourth trenches with insulating material to form a third isolation structure; thinning the substrate along the second surface of the substrate to expose the first isolation structure and one end of the active bar away from the first surface of the substrate; removing a portion of the first isolation structure and a portion of the first conductive structure along the second surface of the substrate to form a fifth trench; the fifth trench exposing one end of the second isolation structure away from the first surface of the substrate; forming multiple word lines; the multiple word lines and the multiple second isolation structures are arranged at intervals.

[0019] In some embodiments, a fifth isolation structure is formed by filling the fifth trench with insulating material; the fifth isolation structure includes an air gap.

[0020] In some embodiments, forming a plurality of memory cells includes: forming a plurality of memory cell contacts on a first source / drain; each memory cell contact being connected to a first source / drain; forming a plurality of memory cells on the memory cell contacts; and each memory cell being connected to a memory cell contact.

[0021] In some embodiments, forming a plurality of bit lines along a second surface of a substrate includes: forming a second conductive structure along the second surface of the substrate covering a word line-bit line isolation structure and an active strip at one end away from a first surface of the substrate; wherein a portion of the second conductive structure covering the end of the active strip away from the first surface of the substrate reacts with the active strip; a portion of the second conductive structure covering the end of the word line-bit line isolation structure away from the first surface of the substrate does not react with the first isolation structure; removing the portion of the second conductive structure that does not react with the word line-bit line isolation structure to form a plurality of bit lines; filling the plurality of bit lines with insulating material to form a plurality of bit line isolation structures; the plurality of bit lines and the plurality of bit line isolation structures are spaced apart and extend along a first direction.

[0022] In some embodiments, the manufacturing method further includes: forming a first word line contact corresponding to an odd-numbered row word line and a second word line contact corresponding to an even-numbered row word line outside the active column array region; and forming a first bit line contact corresponding to an odd-numbered column bit line and a second bit line contact corresponding to an even-numbered column bit line outside the active column array region; wherein the first word line contact and the second word line contact are located on both sides of the active column array along the row active column arrangement direction; and the first bit line contact and the second bit line contact are located on both sides of the active column array along a direction perpendicular to the row active column arrangement direction.

[0023] In some embodiments, forming multiple word lines further includes: forming a gate dielectric layer, a first conductive structure, and a second isolation structure sequentially covering the second trench in a second trench along a first surface of the substrate; thinning the substrate along a second surface to expose the first conductive structure, the first isolation structure, and one end of the active pillars away from the first surface of the substrate; removing at least a portion of the first conductive structure between the first sidewalls of two adjacent even-numbered active pillars in a row along the second surface of the substrate to form multiple third trenches; and removing at least a portion of the first conductive structure between the second sidewalls of two adjacent odd-numbered active pillars in a row to form multiple fourth trenches; filling the third trenches and fourth trenches with insulating material to form a third isolation structure and a precursor structure for the word lines; removing a portion of the precursor structure for the word lines along the second surface of the substrate to form a fifth trench; the fifth trench exposing one end of the second isolation structure away from the first surface of the substrate; forming multiple word lines; and the multiple word lines and the multiple second isolation structures are arranged at intervals.

[0024] This application provides a word line structure design scheme in a memory array architecture. In this scheme, the word lines are designed with a staggered structure to reduce the row hammer effect between adjacent word lines; the spacing between bit lines is enabled, which greatly reduces the coupling between bit lines when the device is working, reduces the parasitic capacitance between adjacent even-numbered bit lines in operation, and achieves the effect of optimizing the sensing margin. Attached Figure Description

[0025] Figure 1A A three-dimensional perspective schematic diagram of a first semiconductor structure including an active pillar array, provided for embodiments of this application;

[0026] Figure 1B for Figure 1A A schematic diagram of the semiconductor structure along section AA;

[0027] Figure 1C for Figure 1A A schematic diagram of the semiconductor structure along the BB section;

[0028] Figure 2A A three-dimensional perspective schematic diagram of a second semiconductor structure including an active pillar array, provided for embodiments of this application;

[0029] Figure 2B for Figure 2A A schematic diagram of the semiconductor structure along section AA;

[0030] Figure 2C for Figure 2A A schematic diagram of the semiconductor structure along the BB section;

[0031] Figure 3AA three-dimensional perspective schematic diagram of a third semiconductor structure including an active pillar array, provided for embodiments of this application;

[0032] Figure 3B for Figure 3A A schematic diagram of the semiconductor structure along section AA;

[0033] Figure 3C for Figure 3A A schematic diagram of the semiconductor structure along the BB section;

[0034] Figure 4A A three-dimensional perspective schematic diagram of a fourth semiconductor structure including an active pillar array, provided for embodiments of this application;

[0035] Figure 4B for Figure 4A A schematic diagram of the semiconductor structure along section AA;

[0036] Figure 4C for Figure 4A A schematic diagram of the semiconductor structure along the BB section;

[0037] Figure 4D for Figure 4A A schematic diagram of the semiconductor structure along the CC section;

[0038] Figure 5 This is a schematic diagram illustrating the implementation process of a semiconductor structure manufacturing method according to an embodiment of this application;

[0039] Figures 6A to 6Q A top view schematic diagram of a semiconductor structure manufacturing process and one or more corresponding cross-sectional schematic diagrams provided for embodiments of this application;

[0040] Figure 7A and Figure 7B A schematic diagram illustrating several different arrangements of storage capacitors provided in the embodiments of this application;

[0041] Figure 8A , Figure 8B and Figure 8C Schematic diagrams of several different structural forms of storage capacitors provided in the embodiments of this application;

[0042] Figure 9A and Figure 9B Schematic diagrams illustrating several different operating modes of word lines and bit lines provided in embodiments of this application;

[0043] Figures 10A to 10G A top plan view and one or more corresponding cross-sectional views of a manufacturing process for another semiconductor structure provided in an embodiment of this application;

[0044] Figure 11A and Figure 11B A top plan view and one or more corresponding cross-sectional views of a manufacturing process for another semiconductor structure provided in the embodiments of this application;

[0045] Figure 12A and Figure 12B A top plan view and one or more corresponding cross-sectional views of a semiconductor structure manufacturing process provided for embodiments of this application are shown. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of the application will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0047] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0048] In the various embodiments of this application, the first direction is a direction that intersects with but is not orthogonal to the second direction, and is parallel to the surface of the substrate. The third direction is a direction perpendicular to the surface of the substrate (or a perpendicular direction). The first direction can be understood as the direction in which the active pillars in the active pillar array are arranged in columns, or the direction in which the bit lines in the active pillar array extend. The second direction can be understood as the direction in which the active pillars in the active pillar array are arranged in rows, or the direction in which the word lines in the active pillar array extend. The third direction can be understood as the direction in which each element, component, region, layer, or part is stacked, or the direction in which each active pillar in the active pillar array extends. Exemplarily, the first direction is represented by the direction in the figures; the second direction is represented by the direction in the figures or the X direction; the third direction is represented by the Z direction in the figures, and the Y direction in the figures is parallel to the surface of the substrate and orthogonal to the X direction.

[0049] Because transistors can be fabricated on silicon substrates, they can be used in various types of memory, such as DRAM. Typically, DRAM consists of multiple memory cell structures, each of which mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, DRAM includes an architecture of 1T1C (Transistor T and Capacitor C).

[0050] This application provides a word line structure design scheme in a memory array architecture. In this scheme, the word lines are designed with staggered heights to achieve open spacing between bit lines, which greatly reduces the coupling between bit lines when the device is working, thereby increasing the sensing tolerance of the memory device.

[0051] In a first aspect, embodiments of this application provide a semiconductor structure, with reference to... Figure 1A , Figure 2A , Figure 3A and Figure 4A The semiconductor structure includes: an active pillar array; each active pillar includes a vertically disposed first source / drain, a channel, and a second source / drain; multiple word lines; each word line includes multiple first portions and multiple second portions; each first portion at least covers one sidewall of the channel of one active pillar in a row of active pillars in the corresponding active pillar array, and each second portion connects two adjacent second portions; wherein the dimension of the first portion in the vertical direction is larger than the dimension of the second portion in the vertical direction; multiple memory cells; each memory cell is connected to a first source / drain; and multiple bit lines; each bit line is connected to the second source / drain of each active pillar in a row of active pillars in the active pillar array.

[0052] It should be noted that, in order to clearly show the positional relationships between word lines, bit lines, array cells, etc., some isolation structures are used. Figure 1A , Figure 2A , Figure 3A and Figure 4A And not shown, for example, Figure 1A , Figure 2A , Figure 3A and Figure 4A The text does not show bit-line isolation structures between adjacent bit lines, word-line-bit-line isolation structures between word lines, or isolation structures between adjacent memory cells (e.g., capacitors).

[0053] It should be noted that each first part of a word line covers at least one sidewall of the channel of one active column in a row of active columns in the corresponding active column array, and the word line receives word line voltage to control the channel of the corresponding active column to conduct; each second part of the word line covers part of the sidewall of the channel of one active column in a row of active columns in the corresponding active column array, and the word line receives word line voltage but does not cause the channel of the corresponding active column to conduct.

[0054] refer to Figure 1A , Figure 2A , Figure 3A and Figure 4A In some embodiments, the ratio between the vertical dimension of the channel and the vertical dimension of the second portion is greater than or equal to 2. Each second portion of the word line covers at most half of the channel sidewall of the corresponding active post, and receiving a word line voltage does not cause the channel of the corresponding active post to conduct.

[0055] refer to Figure 1A , Figure 1B and Figure 1C In some embodiments, multiple second portions corresponding to each word line are positioned close to the second source / drain.

[0056] refer to Figure 2A , Figure 2B and Figure 2C In some embodiments, multiple second portions corresponding to each word line are positioned close to the first source / drain.

[0057] refer to Figure 3A , Figure 3B and Figure 3C In some embodiments, multiple second portions corresponding to each character line are positioned close to the middle of the channel.

[0058] refer to Figure 1A , Figure 2A , Figure 3A and Figure 4A In some embodiments, the dimensions of the first part along the direction of the arrangement of the active columns are substantially the same as the dimensions of the second part along the direction of the arrangement of the active columns.

[0059] In some embodiments, at least a plurality of second portions corresponding to the same character line among the plurality of character lines are staggered in a vertical direction, and / or, at least a plurality of second portions corresponding to different character lines among the plurality of character lines are staggered in a vertical direction.

[0060] refer to Figure 4A , Figure 4B , Figure 4C and Figure 4D In some embodiments, at least two adjacent character lines correspond to multiple second parts that are staggered in the vertical direction.

[0061] refer to Figure 1A , Figure 1B and Figure 1C , and, in conjunction with reference Figure 6Q In some embodiments, the multiple word lines include: multiple first-type word lines; a first portion of each first-type word line covers a first sidewall of the channel of an odd-numbered active column in a row of active columns, and a second portion of each first-type word line connects two adjacent first portions and covers portions of the first sidewall of the channel of an even-numbered active column in a row of active columns; and multiple second-type word lines; a first portion of each second-type word line covers a second sidewall of the channel of an even-numbered active column in a row of active columns, and a second portion of each second-type word line connects two adjacent first portions and covers portions of the first sidewall of the channel of an odd-numbered active column in a row of active columns; the first sidewall and the second sidewall are opposite sidewalls along the extension direction of the column of active columns.

[0062] When this semiconductor structure is applied to memory, only the even-numbered bit lines corresponding to the opened word lines are active when the memory word lines are turned on. The odd-numbered bit lines between the adjacent even-numbered bit lines that are active are given a default voltage (e.g., pre-charge voltage VCC / 2), which acts as a metal shield, reducing the parasitic capacitance between the adjacent even-numbered bit lines that are active, thus optimizing the sensing margin. There will be a row hammer phenomenon when adjacent word lines are turned on. By designing the word lines into a staggered structure, the row hammer effect between adjacent word lines is reduced.

[0063] In some embodiments, the semiconductor structure further includes a word line-bit line isolation structure; the word line-bit line isolation structure includes a first extension and a second extension integrally formed with the first extension; wherein the first extension is located between two adjacent bit lines and extends along the column active pillar arrangement direction; the second extension covers one end of the word line near the bit line and extends along the row active pillar arrangement direction.

[0064] In some embodiments, the first extension and / or the second extension includes an air gap structure.

[0065] In some embodiments, each active column is located at the intersection of the row active column arrangement direction and the column active column arrangement direction; the number of active columns in the column active columns corresponding to each bit line is the same.

[0066] In some embodiments, the row active column arrangement direction and the column active column arrangement direction have an angle; the angle range is greater than 0 degrees and less than 90 degrees.

[0067] In some embodiments, the angle θ between the row active column arrangement direction and the column active column arrangement direction can be any angle within the range of greater than 0 degrees and less than 90 degrees. Preferably, the angle θ ranges from 45 degrees to 75 degrees. For example, the angle θ can be 50 degrees, 60 degrees, or 70 degrees.

[0068] In some embodiments, the semiconductor structure further includes: a first word line contact corresponding to odd-numbered row word lines and a second word line contact corresponding to even-numbered row word lines, and a first bit line contact corresponding to odd-numbered column bit lines and a second bit line contact corresponding to even-numbered column bit lines; wherein the first word line contact and the second word line contact are located on both sides of the active pillar array along the row active pillar arrangement direction; the first bit line contact and the second bit line contact are located on both sides of the active pillar array along a direction perpendicular to the row active pillar arrangement direction.

[0069] In some embodiments, the semiconductor structure further includes an active pillar connection (see reference). Figure 6Q (b) The active bar 104 shown; the active column connector and each column of active columns (see reference) Figure 6Q (b) The active column 108 shown is integrally formed and extends along the arrangement direction of the column active columns; the column active columns are located on the active column connecting part; wherein, the bit line (reference) Figure 6Q (b) The bit line 134) shown covers the end of the active post connection that is away from the active post.

[0070] In some embodiments, the semiconductor structure includes a dynamic random access memory, and the memory cell includes a memory capacitor; one end of the memory capacitor is connected to the first source / drain of an active pillar in the active pillar array, and the other end of the memory capacitor is grounded, and the memory capacitor is used to store the written data.

[0071] In some embodiments, the plurality of storage capacitors are arranged in a square (reference). Figure 7A Or arranged in a hexagonal pattern (see reference) Figure 7B ).

[0072] In some embodiments, the storage capacitor includes a cup-shaped, cylindrical, or pillar-shaped capacitor.

[0073] In some embodiments, the storage capacitor includes a cup-shaped, cylindrical, or pillar-shaped capacitor.

[0074] For example, such as Figure 8A As shown, the storage capacitor 302 may include a cup-shaped capacitor CUP; for example, as Figure 8B As shown, the storage capacitor 302 may include a cylindrical capacitor CYL; exemplarily, as... Figure 8C As shown, the storage capacitor 302 may include a pillar-shaped capacitor PIL. The cup-shaped capacitor CUP, the cylindrical capacitor CYL, and the pillar-shaped capacitor PIL all include a bottom electrode 3021, a top electrode 3023, and a dielectric layer 3022 located between the bottom electrode 3021 and the top electrode 3023. It should be noted that the bottom electrode 3021 is connected to the first source / drain of an active pillar in the active pillar array, the top electrode 3023 of the cup-shaped capacitor CUP is grounded, and the cup-shaped capacitor CUP is used to store the written data.

[0075] It should be noted that, when the areas of the bottom electrode 3021 in the cup-shaped capacitor (CUP), cylindrical capacitor (CYL), and pillar-shaped PIL are equal, the top electrode 3023 of the cylindrical capacitor (CYL) has the largest area, followed by the top electrode 3023 of both the cylindrical capacitor (CYL) and the pillar-shaped PIL. Therefore, in practical applications, the cylindrical capacitor (CYL) can be used as the storage unit of a memory, which is beneficial for achieving extremely high memory integration.

[0076] This application provides a word line structure design scheme in a memory array architecture. In this scheme, the word lines are designed with a staggered structure to reduce the row hammer effect between adjacent word lines; the spacing between bit lines is enabled, which greatly reduces the coupling between bit lines when the device is working, reduces the parasitic capacitance between adjacent even-numbered bit lines in operation, and achieves the effect of optimizing the sensing margin.

[0077] Secondly, embodiments of this application provide a memory comprising: any of the semiconductor structures provided in the embodiments of the first aspect; word lines of the semiconductor structure are configured to receive word line voltage and control the channel of the active pillar of the semiconductor structure to be turned on or off by the word line voltage, for connecting / disconnecting the first source / drain and the second source / drain of the semiconductor structure; bit lines of the semiconductor structure are configured to perform read or write operations on the memory cells of the semiconductor structure when the channel of the active pillar is turned on.

[0078] In some embodiments, even-numbered bit lines are configured to receive word line voltage to control the channel conduction of the corresponding active pillar, and even-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the active pillar's channel is conduction; odd-numbered bit lines are configured to receive a default voltage to shield the even-numbered bit lines; or, odd-numbered bit lines are configured to receive word line voltage to control the channel conduction of the corresponding active pillar, and odd-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the active pillar's channel is conduction; even-numbered bit lines are configured to receive a default voltage to shield the odd-numbered bit lines.

[0079] refer to Figure 9A Once a word line is enabled, all bit lines can operate. However, there is a problem of parasitic capacitance coupling between two bit lines adjacent to the enabled word line, which greatly reduces the sensing margin and lowers the yield.

[0080] refer to Figure 9B When even-numbered bit lines are enabled, only even-numbered bit lines are active. Odd-numbered bit lines between adjacent active even-numbered bit lines are given a default voltage (e.g., pre-charge voltage VCC / 2), which acts as a metal shield, reducing parasitic capacitance between adjacent active even-numbered bit lines. The same principle applies when odd-numbered bit lines are enabled. For example, when word line WL_2n (even-numbered bit lines) is enabled, bit lines BL_2n and BL_2n+2 (adjacent even-numbered bit lines) are active, while bit line BL_2n+1 (odd-numbered bit lines between adjacent even-numbered bit lines) acts as a shield, optimizing sensing margin. Here, n represents a natural number.

[0081] This application provides a memory in which, when a word line of the memory is turned on, only the even-numbered bit lines corresponding to the turned-on word lines are active. The odd-numbered bit lines between the adjacent active even-numbered bit lines are given a default voltage (e.g., pre-charge voltage VCC / 2) to act as a metal shield, thereby reducing the parasitic capacitance between the adjacent active even-numbered bit lines and optimizing the sensing margin. There is a row hammer phenomenon when adjacent word lines are turned on. By designing the word lines into a staggered structure, the row hammer effect between adjacent word lines is reduced.

[0082] Figure 5This is a schematic diagram illustrating the implementation process of a semiconductor structure manufacturing method provided in this application.

[0083] Thirdly, embodiments of this application provide a method for manufacturing a semiconductor structure, the method comprising the following steps:

[0084] Step S501, provide a substrate;

[0085] Step S502: An array of active pillars is formed along the first surface of the substrate; each active pillar is used to form a first source / drain, a channel, and a second source / drain, which are arranged vertically.

[0086] Step S503: Form multiple word lines; each word line includes multiple first parts and multiple second parts; each first part covers at least one sidewall of the channel of one active column in a row of active columns of the corresponding active column array, and each second part connects two adjacent second parts; wherein, the dimension of the first part in the vertical direction is larger than the dimension of the second part in the vertical direction.

[0087] Step S504: Multiple memory cells are formed; each memory cell is connected to a first source / drain.

[0088] In step S505, multiple bit lines are formed along the second surface of the substrate; each bit line is connected to the second source / drain of each active pillar in a column of active pillars of the active pillar array; the second surface is the opposite surface of the substrate to the first surface, which is perpendicular to the substrate.

[0089] Figures 6A to 6Q This application provides a top plan view and one or more corresponding cross-sectional views illustrating the manufacturing process of a semiconductor structure. For example, Figure 6A In Figure 6A (a) is a top-view plan view. Figure 6A In Figure 6A (b) is Figure 6A (a) A schematic cross-sectional view of section AA (section XZ). For example, Figure 6C In Figure 6C (a) is a top-view plan view. Figure 6C In Figure 6C (b) is Figure 6C (a) is a cross-sectional view of the BB section (a YZ section). Figure 6C In Figure 6C (c) is Figure 6C (a) A schematic cross-sectional view of the CC section (another YZ section). For example, Figure 6K In Figure 6K (a) is a top-view plan view. Figure 6K In Figure 6K (b) is Figure 6K(a) is a cross-sectional view of the BB section (a YZ section). Figure 6K In Figure 6K (c) is Figure 6K (a) Schematic cross-section of the CC section (another YZ section).

[0090] It should be understood that Figure 5 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 5 The steps shown can be rearranged in order according to actual needs. The following section combines... Figure 5 , Figures 6A to 6Q The manufacturing method of the semiconductor structure provided in the embodiments of this application will be described in detail.

[0091] In various embodiments of this application, the second surface (or back surface) of the substrate is the opposite surface to the first surface (or front surface) of the substrate along a third direction. Some elements, components, regions, layers, or portions of the semiconductor structure can be fabricated on the first surface of the substrate, and other elements, components, regions, layers, or portions of the semiconductor structure can be fabricated on the second surface of the substrate. For example, a first source / drain of the semiconductor structure can be fabricated on the first surface of the substrate, and a second source / drain of the semiconductor structure can be fabricated on the second surface of the substrate. As another example, word lines of the semiconductor structure can be fabricated on the first surface of the substrate, and bit lines of the semiconductor structure can be fabricated on the second surface of the substrate.

[0092] refer to Figure 6A Step S501 is executed to provide a substrate.

[0093] In some embodiments, the material of substrate 102 may include silicon (Si) substrate, germanium (Ge) substrate, silicon germanide (SiGe) substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc.

[0094] In some embodiments, the substrate 102 can be selected according to the actual needs of the semiconductor device. The substrate 102 has a composite stack structure, which includes a bottom substrate layer (not shown), a pad oxide layer (not shown), and a top substrate layer (not shown) stacked sequentially. The material of the top substrate layer may include silicon, germanium, or germanium-silicon; the material of the bottom substrate layer may include silicon, the material of the pad oxide layer may include silicon oxide, and the material of the top substrate layer may include polycrystalline silicon. In some specific embodiments, the pad oxide layer on the bottom substrate layer and the top substrate layer can both be formed using processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0095] In some embodiments, the substrate 102 is doped with certain impurity ions as needed. The impurity ions can be N-type or P-type impurity ions. In one embodiment, the doping includes well region doping and source / drain region doping to form an active layer (not shown) in the substrate 102. The active region is used to include the formation of active pillars.

[0096] In this way, the resulting substrate structure is a composite stacked structure, which is suitable for subsequent processes to be carried out on the front and back sides of the substrate. For example, transistors (including word lines) are manufactured on the front side of the substrate, and bit lines are manufactured on the back side of the substrate.

[0097] In various embodiments of this application, the etching (or removal) processes employed may include wet etching processes, dry etching processes, etc. For example, plasma etching processes. The deposition (or filling) processes employed may include PVD processes, CVD processes, or ALD processes, etc. For example, plasma enhanced chemical vapor deposition (PECVD) processes.

[0098] refer to Figure 6B , Figure 6C Then, execute step S502 to form an active column array.

[0099] In some embodiments, forming an active pillar array along a first surface of a substrate includes: forming a plurality of spaced-apart first trenches and active strips along the first surface of the substrate, wherein the first trenches and active strips extend along a first direction; filling the first trenches with insulating material to form a first isolation structure; forming a plurality of spaced-apart second trenches along the first surface of the substrate in the first isolation structure and active strips, wherein the second trenches extend along a second direction; the plurality of second trenches divide each active strip into a plurality of active pillars extending along a third direction; wherein the dimension of the second trench along the third direction is smaller than the dimension of the first trench along the third direction; the third direction is perpendicular to the plane formed by the first direction and the second direction; and there is an angle between the first direction and the second direction.

[0100] refer to Figure 6B The first shallow trench isolation (STI) process can be used to etch a first trench T1 extending in a first direction in the substrate 102 along the first surface of the substrate, forming multiple spaced first trenches T1 and active strips 104 in the substrate; an insulating material is deposited in the first trench T1 and chemical mechanical polishing (CMP) is performed so that the surface of the insulating material is flush with the surface of the substrate 102, forming a first isolation structure 106 filling the first trench T1, resulting in multiple spaced first isolation structures 106 and active strips 104 formed in the substrate 102.

[0101] The dimension H1 of the first trench T1 along the third direction can be smaller than the dimension H0 of the substrate 102 along the third direction. The dimension H0 of the substrate 102 along the third direction can be understood as the thickness of the active layer of the substrate 102 along the third direction.

[0102] In various embodiments of this application, the insulating material may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials.

[0103] refer to Figure 6C A second shallow trench isolation process can be used to etch a second trench T2 extending in a second direction along the first isolation structure 106 and the active strip 104 along the first surface of the substrate. Multiple second trenches T2 divide each active strip into several active pillars 108 extending in a third direction.

[0104] The dimension H2 of the second trench T2 along the third direction can be smaller than the dimension H1 of the first trench T1 along the third direction. Since the dimension of the second trench T2 along the third direction is smaller than the dimension of the first trench T1 along the third direction, in subsequent processes, word lines can be formed in the second trench T2 along the first surface of the substrate; bit lines are formed along the second surface of the substrate using the end of the second trench T2 away from the first surface of the substrate. The bit lines and word lines can be staggered in the third direction (for example, see the section below on self-aligned bit lines for the specific bit line formation process).

[0105] In some embodiments, the first trench T1 and the second trench T2 may be formed by one or more patterning processes. These patterning processes include, but are not limited to, double-patterning technology (DPT), quadruple-patterning technology (QPT), or any combination thereof.

[0106] By employing a first shallow trench isolation process and a second shallow trench isolation process, the extension direction of the first trench T1 and the extension direction of the second trench T2 intersect at an angle, i.e., the angle is greater than 0 degrees and less than or equal to 90 degrees, for example, the angle is equal to 90 degrees. This achieves the orthogonality between the row active column arrangement direction and the column active column arrangement direction of the active column array, and the number of active columns in each column active column can be the same, and the number of active columns in each row active column can be the same.

[0107] In some embodiments, the angle between the extending direction of the first groove T1 and the extending direction of the second groove T2 can be any angle within the range of greater than 0 degrees and less than 90 degrees. For example, the angle can be 50 degrees, 60 degrees, or 70 degrees.

[0108] In the following examples, the arrangement direction of the row active columns is orthogonal to the arrangement direction of the column active columns (the included angle θ is 90 degrees), but this is not intended to limit the embodiments of this application.

[0109] refer to Figures 6D to 6H as well as Figures 6K to 6O Step S503 forms multiple character lines.

[0110] In some embodiments, forming multiple word lines includes: forming a gate dielectric layer, a first conductive structure, and a second isolation structure sequentially covering the second trench in a second trench along a first surface of the substrate; forming multiple third trenches by removing at least a portion of the first conductive structure corresponding to the first sidewalls of two adjacent even-numbered active pillars in a row of active pillars along the first surface of the substrate, and forming multiple fourth trenches by removing at least a portion of the first conductive structure corresponding to the second sidewalls of two adjacent odd-numbered active pillars in a row of active pillars; filling the third trenches and fourth trenches with insulating material to form a third isolation structure; thinning the substrate along the second surface of the substrate to expose the first isolation structure and one end of the active bar away from the first surface of the substrate; removing a portion of the first isolation structure and a portion of the first conductive structure along the second surface of the substrate to form a fifth trench; the fifth trench exposing one end of the second isolation structure away from the first surface of the substrate; forming multiple word lines; the multiple word lines and the multiple second isolation structures are arranged at intervals.

[0111] refer to Figures 6D to 6H In step S503, a precursor structure for multiple word lines is formed. The precursor structure for the word lines can be obtained by removing a portion of the first conductive structure along the first surface of the substrate.

[0112] refer to Figure 6D In some embodiments, a gate dielectric layer conformally covering the second trench T2 can be formed by a deposition process. Figure 6D (Not shown). In some embodiments, an in-situ oxidation process can also be used to oxidize at least a portion of the sidewalls of each active post 108 exposed in the second trench T2 by heating or pressurizing, forming a gate dielectric layer covering at least a portion of the sidewalls of each active post 108. Figure 6D (Not shown). The material of the gate dielectric layer includes, but is not limited to, silicon oxide.

[0113] refer to Figure 6D In some embodiments, a first conductive structure 110 may be formed in the second trench T2 by a deposition process, wherein a gate dielectric layer is included between the first conductive structure 110 and the active pillar 108. Figure 6F (Not shown). The material of the first conductive structure 110 includes, but is not limited to, tungsten (W).

[0114] In some embodiments, the first conductive structure 110 includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially, wherein the material of the first conductive layer includes polysilicon, the material of the second conductive layer includes titanium nitride, and the material of the third conductive layer includes tungsten; a gate dielectric layer is included between the first conductive layer and the active pillar 108. Figure 6D (Not shown).

[0115] refer to Figure 6EIn some embodiments, an insulating material is deposited in the second trench T2 where the first conductive structure 110 is formed, and CMP treatment is performed to remove at least the insulating material located on the top surface of the active pillar, resulting in a second isolation structure 112, such that the surface of the second isolation structure 112 is flush with the top surface of the active pillar 108. The material of the second isolation structure 112 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials.

[0116] refer to Figure 6F Using a lithography-etch (LE) process, at least a portion of the first conductive structure corresponding to the first sidewall of two adjacent even-numbered active pillars 108 in the row of active pillars is removed along the first surface of the substrate to form a plurality of third trenches T3, and at least a portion of the first conductive structure corresponding to the second sidewall of two adjacent odd-numbered active pillars 108 in the row of active pillars is removed to form a plurality of fourth trenches T4; wherein each third trench T3 exposes at least a portion of the channel of an odd-numbered active pillar 108 located between two adjacent even-numbered active pillars in the row of active pillars, corresponding to the first sidewall pillar; each fourth trench T4 exposes at least a portion of the channel of an even-numbered active pillar 108 located between two adjacent odd-numbered active pillars in the row of active pillars, corresponding to the second sidewall pillar.

[0117] In various embodiments of this application, the second sidewall of the active pillar 108 and the first sidewall of the active pillar 108 are two opposite sidewalls of the active pillar 108 along the first direction, and a gate structure of a semiconductor structure can be fabricated on the first sidewall or the second sidewall of the active pillar 108.

[0118] In some embodiments, the dimension of the third trench T3 along the third direction is smaller than the dimension of the second isolation structure 112 along the third direction; and / or, the dimension H4 of the fourth trench T4 along the third direction is smaller than the dimension H3 of the second isolation structure 112 along the third direction.

[0119] In some embodiments, the dimensions of the plurality of third trenches T3 along the third direction and the dimensions of the plurality of fourth trenches T4 along the third direction may be the same or different. For example, the third trenches T3 and fourth trenches T4 with different dimensions along the third direction can be formed by multiple photolithography-etching processes. As another example, the dimensions of the plurality of third trenches T3 along the third direction may also be different, or the dimensions of the plurality of fourth trenches T4 along the third direction may also be different. In the following examples, the dimension of the third trench T3 along the third direction is equal to the dimension H4 of the fourth trench T4 along the third direction, but this is not intended to limit the embodiments of this application.

[0120] refer to Figure 6G A third isolation structure 116 can be formed by filling multiple third trenches T3 and multiple fourth trenches T4 with insulating material through a deposition process.

[0121] refer to Figure 6H The word line precursor structure 114 can be obtained by removing at least a portion of the first conductive structure 110 along the first surface of the substrate using an etch-back process; and the space formed after removing the portion of the first conductive structure 110 is filled with insulating material to obtain a fourth isolation structure 118. The third isolation structure 116 and the fourth isolation structure 118 embed the word line precursor structure 114 into the substrate structure. (Reference) Figures 6K to 6O Step S503 involves forming multiple word lines and a word line-bit line isolation structure. See below for details. Figures 6K to 6O The relevant explanations will not be repeated here.

[0122] In some embodiments, an insulating material is filled in the fifth trench to form a word line-bit line isolation structure; the word line-bit line isolation structure includes an air gap.

[0123] In some embodiments, after forming multiple word line-bit line isolation structures, the manufacturing method further includes: doping one end of the active pillar near the first surface of the substrate along the first surface of the substrate to form a first source / drain. In some embodiments, the active pillar is doped with a certain amount of impurity ions on the first surface of the substrate; the impurity ions can be N-type impurity ions or P-type impurity ions.

[0124] refer to Figure 6I and Figure 6J Step S504: Multiple storage units are formed.

[0125] In some embodiments, forming a plurality of memory cells includes: forming a plurality of memory cell contacts on a first source / drain; each memory cell contact being connected to a first source / drain; forming a plurality of memory cells on the memory cell contacts; and each memory cell being connected to a memory cell contact.

[0126] refer to Figure 6I In some embodiments, a deposition process can be used to form an insulating material covering the first surface of the substrate. A plurality of memory cell contact openings can be formed in this insulating material using a photolithography-etching process to obtain a first dielectric layer 120, with each memory cell contact opening exposing at least a portion of the top surface of an active pillar 108. A deposition process can be used to deposit conductive material in the plurality of memory cell contact openings to form memory cell contacts 122 covering at least a portion of the top surface of the active pillar. In some embodiments, the memory cell contacts 122 are connected to the first source / drain of the active pillar.

[0127] refer to Figure 6JIn some embodiments, a deposition process can be used to form an insulating material covering the first surface of the substrate; a plurality of memory cell openings can be formed in the insulating material by a photolithography-etching process to obtain a second dielectric layer 124, each memory cell opening exposing at least a portion of the top surface of a memory cell contact; a deposition process can be used to form memory cells 126 covering at least a portion of the top surface of the memory cell contacts in the plurality of memory cell openings. In some embodiments, the memory cell 126 is connected to the first source / drain of the active pillar through the memory cell contact 122.

[0128] In some embodiments, the storage cell 126 includes a storage capacitor. One end of the storage capacitor 302 is connected to the first source / drain of a transistor in the active pillar array, and the other end of the storage capacitor 302 is grounded. The storage capacitor 302 is used to store written data.

[0129] In practical applications, multiple storage capacitors can be arranged in various shapes.

[0130] In some embodiments, the plurality of storage capacitors are arranged in a square or in a hexagonal arrangement.

[0131] For example, such as Figure 7A In the XY top view plane, the array layout of the storage capacitors 302 can be arranged in a square. For example, as... Figure 7B In the XY top view plane, the array layout of the storage capacitors 302 can be arranged in a hexagonal shape.

[0132] In practical applications, storage capacitors can take on various structures.

[0133] refer to Figure 8A , Figure 8B , Figure 8C In some embodiments, the storage capacitor includes cup-shaped, cylindrical, or pillar-shaped capacitors.

[0134] refer to Figures 6K to 6O In step S503, multiple word lines and word line-bit line isolation structures are formed, wherein the word lines can be obtained by removing a portion of the word line precursor structure along the second surface of the substrate.

[0135] refer to Figure 6K and Figure 6L The substrate 102 containing the active pillar array is flipped, and the substrate 102 is thinned starting from the second surface of the substrate 102 using an etching process or a CMP process to expose the first isolation structure and the end of the active strip away from the first surface of the substrate. The first isolation structure 106 and the active strip 104 are arranged alternately at the first direction at the end away from the first surface of the substrate.

[0136] refer to Figure 6M Using an etching process, starting from the second surface of the substrate 102, and using the active strip 104 as a mask, a portion of the first isolation structure 106 is removed along the third direction to obtain the fifth trench T5. The fifth trench T5 exposes the precursor structure 114 of the word line. The fifth trench T5 is located between two adjacent active strips 104 and extends along the first direction.

[0137] refer to Figure 6N Using an etching process, starting from the second surface of the substrate 102, and using the active strip 104 and part of the first isolation structure 106 as a mask, part of the word line precursor structure 114 is removed along the third direction to obtain the sixth trench T6 and multiple word lines 128; the sixth trench T6 exposes one end of the word line near the bit line and extends along the second direction.

[0138] refer to Figure 6O An insulating material is filled into the fifth trench T5 and the sixth trench T6 using a deposition process to obtain the word line-bit line isolation structure 130.

[0139] In some embodiments, the word line-bit line isolation structure 130 includes a first extension 1301 and a second extension 1302 integrally formed with the first extension; wherein the first extension 1301 is located between two adjacent active bars 104 and extends along the column active bar arrangement direction; the second extension 1302 covers one end of the word line 128 near the second surface of the substrate and extends along the row active bar arrangement direction.

[0140] In some embodiments, the first extension 1301 and / or the second extension 1302 include an air gap structure.

[0141] refer to Figure 6P and Figure 6Q Step S505: Multiple bit lines are formed.

[0142] In some embodiments, forming a plurality of bit lines along a second surface of a substrate includes: forming a second conductive structure along the second surface of the substrate covering a word line-bit line isolation structure and an active strip at one end away from a first surface of the substrate; wherein a portion of the second conductive structure covering the end of the active strip away from the first surface of the substrate reacts with the active strip; a portion of the second conductive structure covering the end of the word line-bit line isolation structure away from the first surface of the substrate does not react with the first isolation structure; removing the portion of the second conductive structure that does not react with the word line-bit line isolation structure to form a plurality of bit lines; filling the plurality of bit lines with insulating material to form a plurality of bit line isolation structures; the plurality of bit lines and the plurality of bit line isolation structures are spaced apart and extend along a first direction.

[0143] In some embodiments, after thinning the substrate, the manufacturing method further includes: doping the active strip (also called the active pillar connection portion) and one end of the active pillar near the second surface of the substrate along the second surface of the substrate to form a second source / drain. The second source / drain and the first source / drain are located at opposite ends of the channel along a third direction. In some embodiments, the active pillar is doped with a certain amount of impurity ions on the second surface of the substrate; the impurity ions can be N-type impurity ions or P-type impurity ions. The second source / drain and the first source / drain have the same doping type.

[0144] refer to Figure 6P A second conductive structure 132 is deposited using a deposition process, such as NiPt. Starting from the second surface of the substrate 102, the word line-bit line isolation structure 130 is used as a mask. The deposited second conductive structure can diffuse in the active strip 104 and react with the active strip 104 along the third direction, for example, to form silicide, but does not react with the first isolation structure 106.

[0145] refer to Figure 6Q A wet etching process can be used to remove the unreacted second conductive structure in the region covering the first isolation structure away from the first surface of the substrate, leaving bit line 134.

[0146] refer to Figure 6Q A bit line isolation structure 136 is formed, filling the space between the bit lines; multiple bit lines 134 and multiple bit line isolation structures 136 are spaced apart and extend along a first direction. The material of the bit lines 134 includes, but is not limited to, tungsten (W). The material of the bit line isolation structure 136 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating dielectric materials. In some embodiments, the bit line isolation structure 136 includes an air gap.

[0147] In some embodiments, bit line 134 includes a fourth conductive layer, a fifth conductive layer and a sixth conductive layer stacked sequentially, wherein the material of the fourth conductive layer includes polysilicon, the material of the fifth conductive layer includes titanium nitride, and the material of the sixth conductive layer includes tungsten; the fourth conductive layer is in contact with the active strip 104.

[0148] In some embodiments, one end of the active strip of bit line 134 away from the first surface of substrate 102 is connected to the second source / drain of the active pillar in the column of active pillars.

[0149] In some embodiments, the first extension 1301 of the word line-bit line isolation structure 130 is located between two adjacent bit lines 134 and extends along the column active post arrangement direction; the second extension 1302 of the word line-bit line isolation structure 130 covers one end of the word line 128 near the bit line and extends along the row active post arrangement direction.

[0150] Figures 10A to 10GA top plan view and one or more corresponding cross-sectional views of the manufacturing process of another semiconductor structure provided in the embodiments of this application.

[0151] refer to Figures 10A to 10G Step S503 forms multiple character lines.

[0152] In some embodiments, forming multiple word lines includes: forming a gate dielectric layer, a first conductive structure, and a second isolation structure sequentially covering the second trench in a second trench along a first surface of the substrate; thinning the substrate along the second surface of the substrate to expose the first conductive structure, the first isolation structure, and one end of the active pillars away from the first surface of the substrate; removing at least a portion of the first conductive structure between the first sidewalls of two adjacent even-numbered active pillars in a row along the second surface of the substrate to form multiple third trenches; and removing at least a portion of the first conductive structure between the second sidewalls of two adjacent odd-numbered active pillars in a row to form multiple fourth trenches; filling the third trenches and fourth trenches with insulating material to form a third isolation structure and a precursor structure for the word lines; removing a portion of the precursor structure for the word lines along the second surface of the substrate to form a fifth trench; exposing one end of the second isolation structure away from the first surface of the substrate in the fifth trench; forming multiple word lines; and arranging the multiple word lines and multiple second isolation structures at intervals.

[0153] refer to Figures 6A to 6J The specific process steps, and removing the steps that form the third groove T3 and the fourth groove T4, can yield the following results. Figure 10A The semiconductor structure shown includes a precursor structure 113 for a first word line.

[0154] get Figure 10A The semiconductor structure shown can also be understood as: reference Figure 10A It is possible to remove at least [amount] along the first surface of the substrate using a back-etching process. Figure 6E The first conductive structure 110 of the semiconductor structure shown is used to obtain the precursor structure 114 of the word line; and the space formed after removing the first conductive structure 110 is filled with insulating material to obtain the fourth isolation structure 118. The fourth isolation structure 118 embeds the precursor structure 114 of the word line into the substrate structure. The substrate 102 where the active pillar array is located is flipped to obtain... Figure 10A The semiconductor structure shown.

[0155] refer to Figure 10A and Figure 10BUsing an etching process or a CMP process, the substrate 102 is thinned starting from the second surface of the substrate 102 to expose the first isolation structure and the end of the active strip away from the first surface of the substrate. The first isolation structure 106 and the active strip 104 are arranged alternately at the first end away from the first surface of the substrate, extending along the first direction.

[0156] refer to Figure 10B and Figure 10C The substrate 102 is then thinned using etching or CMP processes, starting from the second surface, to expose the precursor structure 113 of the first word line, the first isolation structure 106, and the end of the active pillar 108 away from the first surface of the substrate. At the end away from the first surface, the first isolation structure 106 and the active bar 104 are arranged alternately along a first direction. The precursor structure 113 of the first word line extends along a second direction, and the first isolation structure 106 and the active pillar 108 are arranged in an array.

[0157] refer to Figure 10D Through a photolithography-etching process, at least a portion of the first conductive structure corresponding to the first sidewall of two adjacent even-numbered active pillars 108 in the row of active pillars is removed along the second surface of the substrate to form a plurality of third trenches T3, and at least a portion of the first conductive structure corresponding to the second sidewall of two adjacent odd-numbered active pillars 108 in the row of active pillars is removed to form a plurality of fourth trenches T4; wherein each third trench T3 exposes at least a portion of the channel of an odd-numbered active pillar 108 located between two adjacent even-numbered active pillars in the row of active pillars, corresponding to the first sidewall pillar; each fourth trench T4 exposes at least a portion of the channel of an even-numbered active pillar 108 located between two adjacent odd-numbered active pillars in the row of active pillars, corresponding to the second sidewall pillar.

[0158] refer to Figure 10D The third isolation structure 117 and the precursor structure 115 of the second word line can be formed by filling insulating material in multiple third trenches T3 and multiple fourth trenches T4 through a deposition process.

[0159] refer to Figure 10E The word line 128 can be obtained by removing at least a portion of the precursor structure 115 of the second word line along the second surface of the substrate through a back etching process.

[0160] refer to Figure 10F The space formed after the removal of part of the second word line precursor structure 115 is filled with insulating material to obtain the fourth isolation structure 118, which together covers the source post 108 and the second isolation structure 112.

[0161] refer to Figure 10GBy using a photolithography-etching process, a portion of the fourth isolation structure 118 is removed along the second surface of the substrate, and bit line isolation trenches and bit line isolation structures 136 extending along the first direction are etched. The bit line isolation trenches expose one end of a row of active pillars arranged along the first direction. The bit line isolation trenches and bit line isolation structures 136 are arranged alternately.

[0162] refer to Figure 10G Bit lines 134 can be formed by filling a second conductive structure into the bit line isolation trench through a deposition process.

[0163] refer to Figures 6A to 6J The specific process steps are characterized by including: removing, from the first surface of the substrate, at least a portion of the first conductive structure between the first sidewalls of two adjacent even-numbered active pillars in the row of active pillars through a photolithography-etching process, and at least a portion of the first conductive structure between the second sidewalls of two adjacent odd-numbered active pillars in the row of active pillars (hereinafter referred to as the word line formation process on the first surface of the substrate).

[0164] refer to Figures 10A to 10G The specific process steps are characterized by including: removing, from the second surface of the substrate, at least a portion of the first conductive structure corresponding to the first sidewalls of two adjacent even-numbered active pillars in the row of active pillars through a photolithography-etching process; and at least a portion of the first conductive structure corresponding to the second sidewalls of two adjacent odd-numbered active pillars in the row of active pillars (hereinafter referred to as the word line formation process on the second surface of the substrate). This semiconductor structure can be referenced... Figure 3A , Figure 3B and Figure 3C As shown.

[0165] In some embodiments, a semiconductor structure can be formed by combining a word line formation process on a first surface of a substrate with a word line formation process on a second surface of a substrate. This semiconductor structure can be referenced... Figure 3A , Figure 3B and Figure 3C As shown, or you can refer to Figure 4A , Figure 4B , Figure 4C and Figure 4D As shown.

[0166] For example, refer to Figure 11A The word line is formed using a substrate first surface forming process, as referenced. Figures 6A to 6J The specific process steps involve reducing the depth of the third trench T3 and the fourth trench T4. Figure 11A The dimension H4 shown is smaller than Figure 6F The dimension H4 shown can be obtained Figure 11A The semiconductor structure shown includes a precursor structure 113 for a first word line.

[0167] For example, refer to Figure 11B The word lines are formed using a process on the second surface of the substrate, followed by back etching. Figure 11A The precursor structure 113 of the first word line in the semiconductor structure shown obtains the word line 128. This semiconductor structure can also be referenced... Figure 3A , Figure 3B and Figure 3C As shown.

[0168] For example, refer to Figure 12A The word line is formed using a substrate first surface forming process, as referenced. Figures 6A to 6J The specific process steps involve reducing the depth of the third trench T3 and the fourth trench T4. Figure 11A The dimension H4 shown is smaller than Figure 6F Given the dimension H4 shown, and the different depths of the third trench T3 and the fourth trench T4 (e.g., the depth of the third trench T3 is greater than the depth of the fourth trench T4), we can obtain... Figure 12A The semiconductor structure shown includes a precursor structure 113 for a first word line.

[0169] For example, refer to Figure 12B The word lines are formed using a process on the second surface of the substrate, followed by back etching. Figure 12A The semiconductor structure shown has a precursor structure 113 for the first word line, resulting in a word line 128. The sum of the dimensions H5 of the etch-back trench formed using the second surface of the substrate and the dimensions H4 of the etch-back trench formed using the first surface of the substrate is less than the dimension H2 of the second trench. This semiconductor structure can also be referenced. Figure 4A , Figure 4B , Figure 4C and Figure 4D As shown.

[0170] In some embodiments, the manufacturing method further includes: forming a first word line contact corresponding to an odd-numbered row word line and a second word line contact corresponding to an even-numbered row word line outside the active column array region; and forming a first bit line contact corresponding to an odd-numbered column bit line and a second bit line contact corresponding to an even-numbered column bit line outside the active column array region; wherein the first word line contact and the second word line contact are located on both sides of the active column array along the row active column arrangement direction; and the first bit line contact and the second bit line contact are located on both sides of the active column array along a direction perpendicular to the row active column arrangement direction.

[0171] The semiconductor structure manufactured by the semiconductor structure manufacturing method provided in this application is similar to the semiconductor structure in the embodiments of the first aspect above. For technical features not disclosed in detail in this application, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0172] This application provides a semiconductor structure manufactured by a semiconductor structure manufacturing method, and a word line structure design scheme in the memory array architecture of the semiconductor structure. In this scheme, the word lines are designed with a staggered structure to reduce the row hammer effect between adjacent word lines; the spacing between bit lines is enabled, which greatly reduces the coupling between bit lines when the device is working, reduces the parasitic capacitance between adjacent even bit lines in operation, and achieves the effect of optimizing the sensing margin.

[0173] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0174] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0175] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0176] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, include: Active column array; Each of the active pillars includes a first source / drain, a channel, and a second source / drain, all arranged vertically. Multiple letter lines; Each word line includes a plurality of first portions and a plurality of second portions; each first portion covers at least one sidewall of the channel of one of the active columns in a row of the corresponding active column array, and each second portion connects two adjacent second portions; wherein the dimension of the first portion along the vertical direction is greater than the dimension of the second portion along the vertical direction; Multiple storage cells; each of the storage cells is connected to one of the first source / drain terminals; Multiple bit lines; each bit line is connected to the second source / drain of each active pillar in a column of active pillars of the active pillar array.

2. The semiconductor structure according to claim 1, characterized in that, The ratio between the dimension of the channel along the vertical direction and the dimension of the second portion along the vertical direction is greater than or equal to 2.

3. The semiconductor structure according to claim 2, characterized in that, The plurality of second portions corresponding to each word line are disposed near the second source / drain; or, the plurality of second portions corresponding to each word line are disposed near the first source / drain; or, the plurality of second portions corresponding to each word line are disposed near the middle position of the channel.

4. The semiconductor structure according to claim 1, characterized in that, The dimensions of the first part along the direction of the arrangement of the active columns are substantially the same as the dimensions of the second part along the direction of the arrangement of the active columns.

5. The semiconductor structure according to claim 1, characterized in that, At least two adjacent character lines correspond to multiple second parts that are staggered along the vertical direction.

6. The semiconductor structure according to claim 1, characterized in that, The multiple character lines include: Multiple first-class word lines; a first portion of each first-class word line covers a first sidewall of the channel of an odd-numbered active column in a row of active columns, and a second portion of each first-class word line connects two adjacent first portions and covers a portion of the first sidewall of the channel of an even-numbered active column in a row of active columns. Multiple second-class word lines; a first portion of each second-class word line covers the second sidewall of the channel of an even-numbered active column in a row of active columns, and a second portion of each second-class word line connects two adjacent first portions and covers a portion of the first sidewall of the channel of an odd-numbered active column in a row of active columns; the first sidewall and the second sidewall are opposite sidewalls along the extension direction of the column of active columns.

7. The semiconductor structure according to claim 6, characterized in that, Each active column is located at the intersection of the row active column arrangement direction and the column active column arrangement direction; the number of active columns in the column active columns corresponding to each bit line is the same.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a first word line contact corresponding to odd-numbered row word lines and a second word line contact corresponding to even-numbered row word lines, as well as a first bit line contact corresponding to odd-numbered column bit lines and a second bit line contact corresponding to even-numbered column bit lines; The first word line contact and the second word line contact are located on both sides of the active column array along the row active column arrangement direction; the first bit line contact and the second bit line contact are located on both sides of the active column array along a direction perpendicular to the row active column arrangement direction.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a dynamic random access memory, and the memory cell includes a storage capacitor. One end of the storage capacitor is connected to the first source / drain of an active pillar in the active pillar array, and the other end of the storage capacitor is grounded. The storage capacitor is used to store the written data.

10. The semiconductor structure according to claim 9, characterized in that, Multiple storage capacitors are arranged in a square or hexagonal pattern.

11. A memory, characterized in that, include: The semiconductor structure provided in any one of claims 1 to 10; The word line of the semiconductor structure is configured to receive a word line voltage and control the channel of the active pillar to be turned on or off via the word line voltage, for connecting / disconnecting the first source / drain and the second source / drain of the semiconductor structure. The bit lines of the semiconductor structure are configured to perform read or write operations on the memory cells of the semiconductor structure when the channel of the active pillar is turned on.

12. The memory according to claim 11, characterized in that, Even-numbered digital lines are configured to receive the word line voltage to control the channel conduction of the corresponding active post. The even-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the channel of the active pillar is turned on. The odd-numbered bit lines are configured to receive a default voltage, thus shielding the even-numbered bit lines. or, The odd-number lines are configured to receive the word line voltage to control the channel conduction of the corresponding active pillar. The odd-numbered bit lines are configured to perform read or write operations on the memory cells of the semiconductor structure when the channel of the active pillar is turned on; The even-numbered bit lines are configured to receive the default voltage, thus shielding the odd-numbered bit lines.

13. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; An array of active pillars is formed along the first surface of the substrate; Each of the active posts is used to form a first source / drain, a channel, and a second source / drain, which are arranged vertically. Multiple word lines are formed; each word line includes multiple first portions and multiple second portions; each first portion at least covers one sidewall of the channel of one of the active columns in a row of the corresponding active column array, and each second portion connects two adjacent second portions; wherein the dimension of the first portion along the vertical direction is greater than the dimension of the second portion along the vertical direction; Multiple memory cells are formed; each memory cell is connected to a first source / drain. Multiple bit lines are formed along the second surface of the substrate; each bit line is connected to the second source / drain of each active pillar in a column of active pillars of the active pillar array; the second surface is the opposite surface of the substrate to the first surface along the vertical direction.

14. The manufacturing method according to claim 13, characterized in that, The array of source pillars formed along the first surface of the substrate includes: Along the first surface of the substrate, a plurality of first trenches and active stripes are formed in the substrate at intervals, wherein the first trenches and the active stripes extend along a first direction; A first isolation structure is formed by filling the first trench with insulating material; Along the first surface of the substrate, a plurality of spaced second trenches are formed in the first isolation structure and the active strip, the second trenches extending in a second direction; the plurality of second trenches divide each active strip into a plurality of active pillars extending in a third direction; Wherein, the dimension of the second groove along the third direction is smaller than the dimension of the first groove along the third direction; the third direction is perpendicular to the plane formed by the first direction and the second direction; there is an angle between the first direction and the second direction.

15. The manufacturing method according to claim 14, characterized in that, The formation of multiple character lines includes: Along the first surface of the substrate, in the second trench, a gate dielectric layer, a first conductive structure and a second isolation structure are formed sequentially covering the second trench; Along the first surface of the substrate, at least the portion of the first conductive structure between the first sidewalls of two adjacent even-numbered active pillars in the row of active pillars is removed to form a plurality of third trenches; and at least the portion of the first conductive structure between the second sidewalls of two adjacent odd-numbered active pillars in the row of active pillars is removed to form a plurality of fourth trenches. A third isolation structure is formed by filling the third trench and the fourth trench with insulating material. The substrate is thinned along its second surface to expose the first isolation structure and one end of the active strip away from the first surface of the substrate; Along the second surface of the substrate, a portion of the first isolation structure and a portion of the first conductive structure are removed to form a fifth trench; the fifth trench exposes one end of the second isolation structure away from the first surface of the substrate; the plurality of word lines are formed; the plurality of word lines and the plurality of second isolation structures are arranged at intervals.

16. The manufacturing method according to claim 15, characterized in that, The fifth trench is filled with insulating material to form a fifth isolation structure; the fifth isolation structure includes an air gap.

17. The manufacturing method according to claim 16, characterized in that, The formation of multiple storage units includes: Multiple memory cell contacts are formed on the first source / drain; each memory cell contact is connected to a first source / drain. Multiple storage cells are formed on the storage cell contact; each storage cell is connected to a storage cell contact.

18. The manufacturing method according to claim 16, characterized in that, The formation of multiple bit lines along the second surface of the substrate includes: A second conductive structure is formed along the second surface of the substrate, covering the word line-bit line isolation structure and one end of the active strip away from the first surface of the substrate; wherein, the portion of the second conductive structure covering the end of the active strip away from the first surface of the substrate reacts with the active strip; the portion of the second conductive structure covering the end of the word line-bit line isolation structure away from the first surface of the substrate does not react with the first isolation structure; The portion of the second conductive structure that does not react with the word line-bit line isolation structure is removed to form the plurality of bit lines; insulating material is filled between the plurality of bit lines to form a plurality of bit line isolation structures; the plurality of bit lines and the plurality of bit line isolation structures are arranged at intervals and extend along a first direction.

19. The manufacturing method according to claim 18, characterized in that, The manufacturing method further includes: A first word line contact corresponding to an odd-numbered row word line and a second word line contact corresponding to an even-numbered row word line are formed outside the active column array region; and a first bit line contact corresponding to an odd-numbered column bit line and a second bit line contact corresponding to an even-numbered column bit line are formed outside the active column array region. The first word line contact and the second word line contact are located on both sides of the active column array along the row active column arrangement direction; the first bit line contact and the second bit line contact are located on both sides of the active column array along a direction perpendicular to the row active column arrangement direction.

20. The manufacturing method according to claim 14, characterized in that, The formation of multiple character lines also includes: Along the first surface of the substrate, in the second trench, a gate dielectric layer, a first conductive structure and a second isolation structure are formed sequentially covering the second trench; The substrate is thinned along its second surface to expose the first conductive structure, the first isolation structure, and one end of the active pillar away from the first surface of the substrate. Along the second surface of the substrate, at least the portion of the first conductive structure corresponding to the first sidewall between two adjacent even-numbered active pillars in the row of active pillars is removed to form a plurality of third trenches; and at least the portion of the first conductive structure corresponding to the second sidewall between two adjacent odd-numbered active pillars in the row of active pillars is removed to form a plurality of fourth trenches. The third and fourth trenches are filled with insulating material to form a third isolation structure and a precursor structure for the word line; Along the second surface of the substrate, a portion of the word line precursor structure is removed to form a fifth trench; the fifth trench exposes one end of the second isolation structure away from the first surface of the substrate; the plurality of word lines are formed; the plurality of word lines and the plurality of the second isolation structures are arranged at intervals.

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