Dynamic random access memory and forming method thereof

Abstract

The invention discloses a dynamic random access memory and a forming method thereof, and the dynamic random access memory comprises a first channel column group which comprises a plurality of first channel columns; the second channel column group comprises a plurality of second channel columns; a first word line gate structure that controls each first channel pillar in one first channel pillar group; a second word line gate structure that controls each second channel pillar in one second channel pillar group; the first bit lines are electrically connected with the corresponding first channel columns in the first channel column group; and the second bit line is electrically connected with the corresponding second channel column in the second channel column group. When the bit lines are started at intervals, the transistors corresponding to the bit lines which are not opened can not be opened, so that the problems of bit line coupling and data loss of the transistors are solved. And negative pressure is applied to the word line grid structures which are not opened, so that the leakage current of the transistor can be reduced, and crosstalk shielding between the opened word line grid structures can also be realized. A word line gate structure adopts a double-gate structure, so that the control on a channel column can be improved, and the structural performance of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a dynamic random access memory and a method for forming the same. Background Technology

[0002] With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory, and it is the most commonly used solution for applications that store large amounts of data.

[0003] Typically, dynamic random access memory (DRAM) consists of multiple memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other through word lines and bit lines.

[0004] However, existing dynamic random access memory still has many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a dynamic random access memory and a method for forming the same, which simplifies the manufacturing process and improves the structural performance of the device.

[0006] To address the aforementioned problems, the present invention provides a dynamic random access memory (DRAM), comprising: a plurality of first channel post groups, each first channel post group including a plurality of first channel posts arranged along a first direction; a plurality of second channel post groups, each second channel post group including a plurality of second channel posts arranged along the first direction, the first channel post groups and the second channel post groups being alternately arranged along a second direction, the first direction being perpendicular to the second direction; a plurality of first word line grid structures, along the second direction, each first word line grid structure including a second sub-word line grid and a third sub-word line grid located on both sides of a corresponding first channel post group, each second sub-word line grid and the third sub-word line grid respectively controlling each first channel post in one first channel post group; and a plurality of second word line grid structures, along the second direction, each second word line grid structure including a fourth sub-word line grid and a first sub-word line grid located on both sides of a corresponding second channel post group, each fourth sub-word line grid and the first sub-word line grid respectively controlling... Each second channel post in a second channel post group is provided; a plurality of first bit lines, each extending along a second direction, each first bit line being electrically connected to a corresponding first channel post in each first channel post group; a plurality of second bit lines, each extending along the second direction, each second bit line being electrically connected to a corresponding second channel post in each second channel post group, the first bit lines and second bit lines being alternately arranged along the first direction; a plurality of first word line plugs, each first word line plug being electrically connected to a second sub-word line grid and a third sub-word line grid in a corresponding first word line grid structure; a plurality of second word line plugs, each second word line plug being electrically connected to a fourth sub-word line grid and a first sub-word line grid in a corresponding second word line grid structure; a plurality of first bit line plugs, each first bit line plug being electrically connected to a corresponding first bit line; and a plurality of second bit line plugs, each second bit line plug being electrically connected to a corresponding second bit line.

[0007] Optionally, it also includes: a peripheral portion that surrounds a plurality of the first trench post groups and a plurality of the second trench post groups.

[0008] Optionally, along the first direction, the first letter plug and the second letter plug are located on different sides of the first channel post group or the second channel post group.

[0009] Optionally, the central axes of adjacent first-line plugs extending along the second direction do not coincide; the central axes of adjacent second-line plugs extending along the second direction do not coincide.

[0010] Optionally, along the second direction, the first bit line plug and the second bit line plug are located on different sides of the first channel post group or the second channel post group.

[0011] Optionally, the central axes of adjacent first bit line plugs extending along the first direction do not coincide; the central axes of adjacent second bit line plugs extending along the first direction do not coincide.

[0012] Optionally, the second sub-line grid and the third sub-line grid are respectively connected to a portion of the sidewall of the first channel post; the fourth sub-line grid and the first sub-line grid are respectively connected to a portion of the sidewall of the second channel post.

[0013] Optionally, it further includes: a plurality of first gate trenches, wherein the first sub-word line gate and the second sub-word line gate are located within the first gate trenches; a plurality of second gate trenches, wherein the first gate trenches and the second gate trenches are alternately arranged along the second direction, wherein the first channel pillar group is located between adjacent first gate trenches and second gate trenches, the second channel pillar group is located between adjacent first gate trenches and second gate trenches, and the third sub-word line gate and the fourth sub-word line gate are located within the second gate trenches.

[0014] Optionally, a first gate isolation layer is located within the first gate trench, which is used for electrical isolation between the first sub-word gate and the second sub-word gate; a second gate isolation layer is located within the second gate trench, which is used for electrical isolation between the third sub-word gate and the fourth sub-word gate.

[0015] Optionally, it further includes: a first source / drain doped layer located within the first channel pillars on both sides of the first word line gate structure along the extension direction of the first channel pillar, wherein each first bit line is electrically connected to the first source / drain doped layer within each of the first channel pillars; and a second source / drain doped layer located within the second channel pillars on both sides of the second word line gate structure along the extension direction of the second channel pillar, wherein each second bit line is electrically connected to the second source / drain doped layer within each of the second channel pillars.

[0016] Optionally, the materials of the first bit line and the second bit line include: metal silicide; the metal silicide includes: nickel silicon, cobalt silicon or titanium silicon.

[0017] Optionally, it may also include a bit line isolation layer located between the first bit line and the second bit line.

[0018] Accordingly, the present invention also provides a method for forming a dynamic random access memory (DRAM), comprising: forming a plurality of first channel post groups, each first channel post group including a plurality of first channel posts arranged along a first direction; forming a plurality of second channel post groups, each second channel post group including a plurality of second channel posts arranged along the first direction, the first channel post groups and the second channel post groups being alternately arranged along a second direction, the first direction being perpendicular to the second direction; forming a plurality of first word line grid structures, each first word line grid structure including a second sub-word line grid and a third sub-word line grid located on both sides of a corresponding first channel post group along the second direction, each second sub-word line grid and the third sub-word line grid respectively controlling each first channel post in one first channel post group, forming a plurality of second word line grid structures, each second word line grid structure including a fourth sub-word line grid and a first sub-word line grid located on both sides of a corresponding second channel post group along the second direction, each fourth sub-word line grid and the first ..., each fourth sub-word line grid and the first sub-word line grid respectively controlling each first channel post in one first channel post group, the first direction being perpendicular to the second direction; forming a plurality of second word line grid structures, each second word line grid structure including a fourth sub-word line grid and a first sub-word line grid located on both sides of a corresponding second channel post group, the fourth sub-word line grid and the first sub-word line grid respectively controlling each first channel post in one first channel post group, the first direction being perpendicular to the second direction; forming a plurality of second word line grid structures, each second word line Control each second channel post in a second channel post group; form a plurality of first bit lines, each first bit line extending along a second direction and electrically connected to a corresponding first channel post in each first channel post group; form a plurality of second bit lines, each second bit line extending along a second direction and electrically connected to a corresponding second channel post in each second channel post group, the first bit lines and second bit lines being alternately arranged along the first direction; form a plurality of first word line plugs, each first word line plug being electrically connected to a second sub-word line grid and a third sub-word line grid in a corresponding first word line grid structure; form a plurality of second word line plugs, each second word line plug being electrically connected to a fourth sub-word line grid and a first sub-word line grid in a corresponding second word line grid structure; form a plurality of first bit line plugs, each first bit line plug being electrically connected to a corresponding first bit line; form a plurality of second bit line plugs, each second bit line plug being electrically connected to a corresponding second bit line.

[0019] Optionally, along the first direction, the first letter plug and the second letter plug are located on different sides of the first channel post group or the second channel post group.

[0020] Optionally, the central axes of adjacent first-line plugs extending along the second direction do not coincide; the central axes of adjacent second-line plugs extending along the second direction do not coincide.

[0021] Optionally, along the second direction, the first bit line plug and the second bit line plug are located on different sides of the first channel post group or the second channel post group.

[0022] Optionally, the central axes of adjacent first bit line plugs extending along the first direction do not coincide; the central axes of adjacent second bit line plugs extending along the first direction do not coincide.

[0023] Optionally, the second sub-line grid and the third sub-line grid are respectively connected to a portion of the sidewall of the first channel post; the fourth sub-line grid and the first sub-line grid are respectively connected to a portion of the sidewall of the second channel post.

[0024] Optionally, a method for forming a plurality of first channel pillars and a plurality of second channel pillars includes: providing a substrate, the substrate including a base and a plurality of active regions arranged in parallel along a first direction on the base, the active regions extending along a second direction; and performing patterned etching on the active regions to form a plurality of first channel pillars and a plurality of second channel pillars.

[0025] Optionally, the substrate further includes a peripheral portion located on the substrate, the peripheral portion surrounding a plurality of first channel pillar groups and a plurality of second channel pillar groups.

[0026] Optionally, after forming a plurality of the first channel pillars and a plurality of the second channel pillars, the method further includes: forming a first isolation layer on the substrate, the first isolation layer covering the sidewalls of the first channel pillars and the second channel pillars and exposing the surfaces of the first channel pillars and the second channel pillars.

[0027] Optionally, the method for forming the first sub-word grid, the second sub-word grid, the third sub-word grid, and the fourth sub-word grid includes: forming a plurality of first gate trenches and a plurality of second gate trenches in the first isolation layer, wherein the first gate trenches and the second gate trenches are alternately arranged along the second direction, the first channel pillar group is located between adjacent first gate trenches and second gate trenches, and the second channel pillar group is located between adjacent first gate trenches and second gate trenches; forming a first gate on the sidewall of the first gate trench and forming a second gate on the sidewall of the second gate trench; and cutting the first gate and the second gate, such that the first gate forms the first sub-word grid and the second sub-word grid along the second direction, and that the second gate forms the third sub-word grid and the fourth sub-word grid along the second direction.

[0028] Optionally, after forming the first gate and the second gate, the method further includes: forming a first gate isolation layer in the first gate trench, the first gate isolation layer being used for electrical isolation between the first sub-word gate and the second sub-word gate; and forming a second gate isolation layer in the second gate trench, the second gate isolation layer being used for electrical isolation between the third sub-word gate and the fourth sub-word gate.

[0029] Optionally, after forming the first word line gate structure and the second word line gate structure, the method further includes: forming a first source / drain doped layer in the first channel pillars on both sides of the first word line gate structure along the extension direction of the first channel pillars, wherein each first bit line is electrically connected to the first source / drain doped layer in each of the first channel pillars; and forming a second source / drain doped layer in the second channel pillars on both sides of the second word line gate structure along the extension direction of the second channel pillars, wherein each second bit line is electrically connected to the second source / drain doped layer in each of the second channel pillars.

[0030] Optionally, the method for forming the first bit line and the second bit line includes: performing a patterned etching process on the substrate to form a plurality of first initial bit lines, wherein the first initial bit lines extend along a second direction and each first initial bit line is connected to a corresponding first channel post in each first channel post group; and forming a plurality of second initial bit lines, wherein the second initial bit lines extend along the second direction and each second initial bit line is connected to a corresponding second channel post in each second channel post group; the plurality of first initial bit lines and the plurality of second initial bit lines are alternately arranged along the first direction; forming a bit line isolation layer between adjacent first initial bit lines and second initial bit lines, wherein the bit line isolation layer exposes the surfaces of the first initial bit lines and second initial bit lines; forming a metal layer on the bit line isolation layer, the first initial bit lines, and the second initial bit lines; and performing an annealing process such that the metal layer and the first initial bit lines generate the first bit line, and the metal layer and the second initial bit lines generate the second bit line.

[0031] Optionally, the materials of the first bit line and the second bit line include: metal silicide; the metal silicide includes: nickel silicon, cobalt silicon or titanium silicon.

[0032] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0033] In the dynamic random access memory of the present invention, the transistors corresponding to the enabled bit lines (the first bit line or the second bit line) and the transistors corresponding to the disabled bit lines (the second bit line or the first bit line) are controlled by different word line gate structures (the first word line gate structure or the second word line gate structure). When the bit line interval is activated, the transistors corresponding to the disabled bit lines can remain off. This solves both the problem of reduced sensing tolerance caused by bit line coupling and the problem of data loss of the transistors corresponding to the disabled bit lines. Since the first and second word line gate structures are alternately distributed and can be turned on independently, a negative voltage can be applied to the unactivated word line gate structure (either the first or second word line gate structure). This reduces transistor leakage current and also acts as a shield against crosstalk between the activated word line gate structures (either the second or first word line gate). Therefore, the fabrication of a back gate can be eliminated, effectively simplifying the manufacturing process and improving production efficiency. Furthermore, the conductive plugs required for back gate lead-out can be eliminated, allowing the first word line plugs leading out the first and second word line gate structures to have a larger process window. In addition, the first word line gate structure includes the second and third sub-word line gates, and the second word line gate structure includes the fourth and first sub-word line gates. This dual-gate structure effectively improves control over the first and second channel pillars, thereby enhancing device structural performance.

[0034] Furthermore, it also includes a peripheral portion that surrounds a plurality of the first groove post groups and a plurality of the second groove post groups. The peripheral portion can serve as a grinding stop layer for subsequent formation of an isolation layer, preventing over-grinding from damaging the first groove posts and the second groove posts.

[0035] Furthermore, along the first direction, the first and second word line plugs are located on different sides of the first or second channel post group. By placing the first and second word line plugs on different sides of the first or second channel post group, the exposure window during the formation of the first and second word line plugs can be increased, thereby increasing the volume of the first and second word line plugs and improving their electrical conductivity.

[0036] Furthermore, the central axes of adjacent first-line plugs extending along the second direction do not coincide; the central axes of adjacent second-line plugs extending along the second direction do not coincide. By staggering the adjacent first-line plugs along the second direction, the exposure window for forming the first-line plug can be further increased, thereby increasing the volume of the first-line plug and improving electrical conductivity. Similarly, by staggering the adjacent second-line plugs along the second direction, the exposure window for forming the second-line plug can be further increased, thereby increasing the volume of the second-line plug and improving electrical conductivity.

[0037] Furthermore, along the second direction, the first bit line plug and the second bit line plug are located on different sides of the first channel post group or the second channel post group. By placing the first bit line plug and the second bit line plug on different sides of the first channel post group or the second channel post group, the exposure window during the formation of the first bit line plug and the second bit line plug can be increased, thereby increasing the volume of the first bit line plug and the second bit line plug to improve electrical conductivity.

[0038] Furthermore, the central axes of adjacent first bit line plugs extending along the first direction do not coincide; the central axes of adjacent second bit line plugs extending along the first direction also do not coincide. By staggering the adjacent first bit line plugs along the first direction, the exposure window for forming the first bit line plug can be further increased, thereby increasing the volume of the first bit line plug and improving electrical conductivity. Similarly, by staggering the adjacent second bit line plugs along the first direction, the exposure window for forming the second bit line plug can be further increased, thereby increasing the volume of the second bit line plug and improving electrical conductivity.

[0039] The materials of the first bit line and the second bit line include metal silicides; the metal silicides include nickel silicon, cobalt silicon, or titanium silicon. Using metal silicide materials can effectively reduce the contact resistance between the first bit line and the first channel post, and also reduce the contact resistance between the second bit line and the second channel post.

[0040] In the method for forming a dynamic random access memory according to the technical solution of the present invention, the transistors corresponding to the enabled bit lines (the first bit line or the second bit line) and the transistors corresponding to the disabled bit lines (the second bit line or the first bit line) are controlled by different word line gates (the first word line gate structure or the second word line gate structure). When the bit line interval is started, the transistors corresponding to the disabled bit lines can be left off. This can solve both the problem of reduced sensing tolerance caused by bit line coupling and the problem of data loss of the transistors corresponding to the disabled bit lines. Since the first and second word line gate structures are alternately distributed and can be turned on independently, a negative voltage can be applied to the unactivated word line gate structure (either the first or second word line gate structure). This reduces transistor leakage current and also acts as a shield against crosstalk between the activated word line gate structures (either the second or first word line gate). Therefore, the fabrication of a back gate can be eliminated, effectively simplifying the manufacturing process and improving production efficiency. Furthermore, the conductive plugs required for back gate lead-out can be eliminated, allowing the first word line plugs leading out the first and second word line gate structures to have a larger process window. In addition, the first word line gate structure includes the second and third sub-word line gates, and the second word line gate structure includes the fourth and first sub-word line gates. This dual-gate structure effectively improves control over the first and second channel pillars, thereby enhancing device structural performance.

[0041] Furthermore, along the first direction, the first and second word line plugs are located on different sides of the first or second channel post group. By placing the first and second word line plugs on different sides of the first or second channel post group, the exposure window during the formation of the first and second word line plugs can be increased, thereby increasing the volume of the first and second word line plugs and improving their electrical conductivity.

[0042] Furthermore, the central axes of adjacent first-line plugs extending along the second direction do not coincide; the central axes of adjacent second-line plugs extending along the second direction do not coincide. By staggering the adjacent first-line plugs along the second direction, the exposure window for forming the first-line plug can be further increased, thereby increasing the volume of the first-line plug and improving electrical conductivity. Similarly, by staggering the adjacent second-line plugs along the second direction, the exposure window for forming the second-line plug can be further increased, thereby increasing the volume of the second-line plug and improving electrical conductivity.

[0043] Furthermore, along the second direction, the first bit line plug and the second bit line plug are located on different sides of the first channel post group or the second channel post group. By placing the first bit line plug and the second bit line plug on different sides of the first channel post group or the second channel post group, the exposure window during the formation of the first bit line plug and the second bit line plug can be increased, thereby increasing the volume of the first bit line plug and the second bit line plug to improve electrical conductivity.

[0044] Furthermore, the central axes of adjacent first bit line plugs extending along the first direction do not coincide; the central axes of adjacent second bit line plugs extending along the first direction also do not coincide. By staggering the adjacent first bit line plugs along the first direction, the exposure window for forming the first bit line plug can be further increased, thereby increasing the volume of the first bit line plug and improving electrical conductivity. Similarly, by staggering the adjacent second bit line plugs along the first direction, the exposure window for forming the second bit line plug can be further increased, thereby increasing the volume of the second bit line plug and improving electrical conductivity.

[0045] Furthermore, the substrate further includes a peripheral portion located on the substrate, the peripheral portion surrounding a plurality of the first channel pillar groups and a plurality of the second channel pillar groups. The peripheral portion can serve as a polishing stop layer for subsequent formation of an isolation layer, preventing over-polishing from damaging the first channel pillars and the second channel pillars.

[0046] The method for forming the first bit line and the second bit line includes: performing a patterned etching process on the substrate to form a plurality of first initial bit lines, wherein the first initial bit lines extend along a second direction and each first initial bit line is connected to a corresponding first channel pillar in each first channel pillar group; and forming a plurality of second initial bit lines, wherein the second initial bit lines extend along the second direction and each second initial bit line is connected to a corresponding second channel pillar in each second channel pillar group; the plurality of first initial bit lines and the plurality of second initial bit lines are alternately arranged along the first direction; forming a bit line isolation layer between adjacent first initial bit lines and second initial bit lines, wherein the bit line isolation layer exposes the surfaces of the first initial bit lines and second initial bit lines; forming a metal layer on the bit line isolation layer; and performing an annealing process such that the metal layer and the first initial bit lines generate the first bit line, and the metal layer and the second initial bit lines generate the second bit line. Using a self-aligned process to form the first bit line and the second bit line can effectively reduce the photomask required to form the first bit line and the second bit line, thereby reducing the production cost of the device structure.

[0047] Furthermore, the materials of the first bit line and the second bit line include metal silicides; the metal silicides include nickel silicon, cobalt silicon, or titanium silicon. Using metal silicide materials can effectively reduce the contact resistance between the first bit line and the first channel post, and also reduce the contact resistance between the second bit line and the second channel post. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of a dynamic random access memory.

[0049] Figures 2 to 37 This is a schematic diagram of the structure of each step in the method for forming a dynamic random access memory in an embodiment of the present invention. Detailed Implementation

[0050] As described in the background section, existing dynamic random access memories still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0051] Figure 1 This is a schematic diagram of the structure of a dynamic random access memory.

[0052] Please refer to Figure 1 A dynamic random access memory (DRAM) includes: a plurality of channel post groups 100, each channel post group 100 including a plurality of channel posts 1001 arranged along a first direction X, the plurality of channel post groups 100 being arranged along a second direction Y, the projections of corresponding channel posts 1001 in each channel post group 100 coinciding along the second direction Y, the first direction X being perpendicular to the second direction Y; a plurality of word line gates 101 extending along the first direction X, each word line gate 101 controlling each of the channel posts 1001 in one channel post group 100; a plurality of bit lines 102 extending along the second direction Y, each bit line 102 being electrically connected to a corresponding channel post 1001 in each channel post group 100; and a plurality of back gates 103 extending along the first direction X, each back gate 103 being located between partially adjacent word line gates 101.

[0053] In this embodiment, the operation of a transistor is controlled by the word line gate 101 (positive gate) and the back gate 103. The word line gate 101 is responsible for turning on the transistor, and the back gate 103 applies a negative voltage when the transistor is turned off to further suppress leakage current. It can also serve as a shield against crosstalk between adjacent transistors.

[0054] However, the word line gate 101 and the back gate 103 require two processes to complete, making the manufacturing process relatively complex. Furthermore, the word line gate 101 and the back gate 103 need to be led out separately through conductive plugs, resulting in a very small lead-out window for the conductive plugs, which can easily cause short circuits between the word line gate 101 and the back gate 103.

[0055] Furthermore, when the bit line 102 (BL) intervals are activated to prevent bit line 102 coupling (BL-BLcoupling) from reducing the sensing margin, the word line gate 101 (WL) can turn on all transistors (including the transistors corresponding to the bit line 102 that are turned on and the transistors corresponding to the bit line 102 that are not turned on), causing the data stored in the transistors that do not need to be turned on (the transistors corresponding to the bit line 102 that are not turned on) to be lost.

[0056] Therefore, in order to avoid data loss, the dynamic random access memory uses all the bit lines 102 to be enabled. However, this will cause the bit lines 102 to be coupled, resulting in a reduction in the sensing tolerance.

[0057] Based on this, the present invention provides a dynamic random access memory and its formation method. When the bit line interval is activated, the transistors corresponding to the unactivated bit lines can remain off. This solves both the problem of reduced sensing tolerance caused by bit line coupling and the data loss problem of the transistors corresponding to the unactivated bit lines. Since the first word line gate structure and the second word line gate structure are alternately distributed and can be activated independently, a negative voltage can be applied to the unactivated word line gate structure. This reduces transistor leakage current and also acts as a shield against crosstalk between activated word line gate structures. Therefore, the fabrication of the back gate can be eliminated, effectively simplifying the manufacturing process and improving production efficiency. Simultaneously, the conductive plugs required for back gate lead-out can be eliminated, allowing the first word line plugs to have a larger process window. The first and second word line gate structures adopt a dual-gate structure, which effectively improves the control of the first and second channel pillars, thereby improving the device structural performance.

[0058] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0059] Figures 2 to 37 This is a schematic diagram of the steps in a method for forming a dynamic random access memory according to an embodiment of the present invention.

[0060] Please refer to Figure 2 and Figure 3 , Figure 3 yes Figure 2 A schematic cross-sectional view along line AA shows a substrate 300, which includes a base 3001 and a plurality of active regions 3002 arranged parallel to a first direction X on the base 3001. The active regions 3002 extend along a second direction Y, and the first direction X is perpendicular to the second direction Y.

[0061] In this embodiment, the substrate 300 is made of silicon.

[0062] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.

[0063] In this embodiment, the substrate 300 includes a first surface 300a and a second surface 300b opposite to each other, the first surface 300a exposing the surface of the active region 3002, and the second surface 300b exposing the surface of the substrate 3001.

[0064] In this embodiment, the substrate 300 further includes a peripheral portion 3003 located on the substrate 3001, the peripheral portion 3003 surrounding a plurality of the active regions 3002.

[0065] Please refer to Figure 4 , Figure 4 and Figure 3 With the view direction consistent, a first isolation layer 301 is formed on the substrate 300, the first isolation layer 301 covers the active region 3002 and exposes the surface of the active region 3002.

[0066] The first isolation layer 301 is made of insulating material.

[0067] In this embodiment, the first isolation layer 301 is made of silicon dioxide.

[0068] In this embodiment, the method for forming the first isolation layer 301 includes: forming a first initial isolation layer (not shown) on the substrate 300, the first initial isolation layer covering the plurality of active regions 3002 and the peripheral portion 3003; performing planarization on the first initial isolation layer until the surfaces of the active regions 3002 and the peripheral portion 3003 are exposed, thereby forming the first isolation layer 301.

[0069] In this embodiment, the planarization process is carried out using chemical mechanical polishing. The peripheral portion 3003 can serve as a stop layer for polishing, preventing excessive polishing from damaging the active region 3002 and thus causing damage to the subsequently formed first and second channel pillars.

[0070] It should be noted that in this embodiment, during the grinding process of the first surface 300a in subsequent manufacturing processes involving the formation of an isolation layer, the peripheral portion 3003 can serve as a stop layer for grinding, which can effectively prevent the central area surrounded by the peripheral portion 3003 from becoming concave due to excessive grinding.

[0071] Please refer to Figures 5 to 7 , Figure 6 yes Figure 5 Schematic diagram of the cross section along line BB. Figure 7 yes Figure 5 A cross-sectional diagram along the CC line shows that a plurality of first channel column groups 302 are formed, each of the first channel column groups 302 including a plurality of first channel columns 3021 arranged along the first direction X; a plurality of second channel column groups 303 are formed, each of the second channel column groups 303 including a plurality of second channel columns 3031 arranged along the first direction X, and the plurality of first channel column groups 302 and the plurality of second channel column groups 303 are alternately arranged along the second direction Y.

[0072] In this embodiment, the method for forming a plurality of first channel pillars 3021 and a plurality of second channel pillars 3031 includes: etching the active region 3002 from the first surface 300a to the second surface 300b to form a plurality of first channel pillars 3021 and a plurality of second channel pillars 3031.

[0073] In this embodiment, the peripheral portion 3003 surrounds a plurality of first channel post groups 302 and a plurality of second channel post groups 303.

[0074] In this embodiment, the projections of the first channel post 3021 and the corresponding second channel post 3031 along the second direction Y have an overlapping area.

[0075] In other embodiments, the projections of the first channel post and the corresponding second channel post along the second direction Y may not overlap.

[0076] In this embodiment, since the substrate 300 is made of silicon, the first channel pillar 3021 and the second channel pillar 3031 are also made of silicon.

[0077] In other embodiments, the materials of the first channel pillar and the second channel pillar may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0078] In this embodiment, the interface morphology of the first channel post 3021 and the second channel post 3031 is semi-circular, and the cross section is a plane parallel to the first surface 300a and the second surface 300b.

[0079] In other embodiments, the interface morphology of the first channel post and the second channel post may also be circular, elliptical, trapezoidal, rectangular, rhomboid, or irregular polygon, etc., and the cross section is a plane parallel to the first surface and the second surface.

[0080] It should be noted that after etching the active region 3002, the formed opening needs to be filled with insulating material again so that the first isolation layer 301 can cover each of the first channel posts 3021 and the second channel posts 3031, and the first isolation layer 301 exposes the surfaces of the first channel posts 3021 and the second channel posts 3031.

[0081] After the first channel post 3021 and the second channel post 3031 are formed, a plurality of first character line grid structures and a plurality of second character line grid structures are formed. For the specific formation process of the first character line grid structures and the second character line grid structures, please refer to [reference needed]. Figures 8 to 20 .

[0082] Please refer to Figures 8 to 10 , Figure 9 yes Figure 8 Schematic diagram of the cross section along the DD line. Figure 10 yes Figure 8 A cross-sectional view along the EE line shows that a plurality of first gate trenches 304 and a plurality of second gate trenches 305 are formed in the first isolation layer 301. Along the second direction Y, the first gate trenches 304 and the second gate trenches 305 are arranged alternately. The first channel pillar group 302 is located between adjacent first gate trenches 304 and second gate trenches 305, and the second channel pillar group 303 is located between adjacent first gate trenches 304 and second gate trenches 305.

[0083] In this embodiment, the first gate trench 304 and the second gate trench 305 expose portions of the sidewalls of the corresponding first channel post 3021 and second channel post 3031.

[0084] In this embodiment, the first gate trench 304 and the second gate trench 305 are used to define the formation positions of the subsequently formed first word line gate structure and second word line gate structure.

[0085] In this embodiment, the method for forming the first gate trench 304 and the second gate trench 305 includes: etching the first isolation layer 301 from the first surface 300a to the second surface 300b until the surface of the substrate 3001 is exposed, thereby forming the first gate trench 304 and the second gate trench 305.

[0086] Please refer to Figure 11 and Figure 12 , Figure 11 and Figure 9 The view orientation is consistent. Figure 12 and Figure 10 With the view direction consistent, after forming the first gate trench 304 and the second gate trench 305, a second isolation layer 306 is formed in the first gate trench 304 and the second gate trench 305. The second isolation layer 306 covers part of the sidewalls of the first channel post 3021 and the second channel post 3031, and the surface of the second isolation layer 306 is lower than the first surface 300a.

[0087] In this embodiment, the second isolation layer 306 is used to define the formation height of the subsequently formed first word line gate structure and second word line gate structure.

[0088] The second isolation layer 306 is made of insulating material.

[0089] In this embodiment, the material of the second isolation layer 306 is silicon oxide.

[0090] Please refer to Figures 13 to 15 , Figure 14 yes Figure 13 Schematic diagram of the cross section along the FF line. Figure 15 yes Figure 13 A cross-sectional view along the GG line shows that a first gate 307 is formed on the sidewall of the first gate trench 304, and a second gate 308 is formed on the sidewall of the second gate trench 305.

[0091] In this embodiment, the first gate 307 and the second gate 308 are formed on the second isolation layer 306.

[0092] In this embodiment, both the first gate 307 and the second gate 308 include: a gate oxide layer and a gate layer (not shown) located on the sidewall of the gate oxide layer.

[0093] In this embodiment, the method for forming the gate oxide layer includes: oxidizing the exposed sidewalls of the first channel post 3021 and the second channel post 3031 to form a first sub-gate oxide layer (not shown); depositing a second sub-gate oxide layer (not shown) on the sidewall of the first sub-gate oxide layer, wherein the first sub-gate oxide layer and the second sub-gate oxide layer constitute the gate oxide layer.

[0094] By oxidizing the exposed sidewalls of the first channel post 3021 and the second channel post 3031 to form the first sub-gate oxide layer, the sidewalls of the first channel post 3021 and the second channel post 3031 formed by patterning etching can be repaired, thereby eliminating dangling bonds.

[0095] In other embodiments, the second sub-gate oxide layer may not be deposited, and the first sub-gate oxide layer is the gate oxide layer.

[0096] In this embodiment, the method of forming a first gate 307 on the sidewall of the first gate trench 304 and a second gate 308 on the sidewall of the second gate trench 305 includes: forming a gate material layer (not shown) on the sidewalls and bottom surfaces of the first gate trench 304 and the second gate trench 305, and on the first surface 300a; etching back the gate material layer to remove the gate material layer located on the first surface 300a and the bottom surfaces of the first gate trench 304 and the second gate trench 305, thereby forming the first gate 307 and the second gate 308.

[0097] Please refer to Figure 16 and Figure 17 , Figure 16 and Figure 14 The view orientation is consistent. Figure 17 and Figure 15 With the view direction consistent, after forming the first gate 307 and the second gate 308, a first gate isolation layer 309 is formed in the first gate trench 304 and a second gate isolation layer 310 is formed in the second gate trench 305. The first gate isolation layer 309 fills the first gate trench 304 and the second gate isolation layer 310 fills the second gate trench 305.

[0098] The first gate isolation layer 309 and the second gate isolation layer 310 are made of insulating materials.

[0099] In this embodiment, the first gate isolation layer 309 and the second gate isolation layer 310 are made of silicon oxide.

[0100] In this embodiment, the first gate isolation layer 309 is used for electrical isolation of the subsequently formed first sub-word gate and second sub-word gate, and the second gate isolation layer 310 is used for electrical isolation of the subsequently formed third sub-word gate and fourth sub-word gate.

[0101] Please refer to Figures 18 to 20 , Figure 19 yes Figure 18 Schematic diagram of the cross section along line HH in the middle. Figure 20 yes Figure 19A cross-sectional view along line II shows that after the first gate isolation layer 309 and the second gate isolation layer 310 are formed, the first gate 307 and the second gate 308 are cut off, so that the first gate 307 forms a first sub-word line gate 3071 and a second sub-word line gate 3072 along the second direction Y, and the second gate 308 forms a third sub-word line gate 3081 and a fourth sub-word line gate 3082 along the second direction Y.

[0102] In this embodiment, the method for cutting off the first gate 307 and the second gate 308 includes: etching the first isolation layer 301, a portion of the first gate 307 and a portion of the second gate 308 from the first surface 300a to the second surface 300b to form a plurality of cutting grooves (not shown), and dividing the first gate 307 into the first sub-word line gate 3071 and the second sub-word line gate 3072 by the cutting grooves, and dividing the second gate 308 into the third sub-word line gate 3081 and the fourth sub-word line gate 3082.

[0103] In this embodiment, along the second direction Y, each first character line grid structure includes a second sub-character line grid 3072 and a third sub-character line grid 3081 located on both sides of the corresponding first channel post group 302. Each second sub-character line grid 3072 and the third sub-character line grid 3081 respectively control each first channel post 3021 in one first channel post group 302. Along the second direction Y, each second character line grid structure includes a fourth sub-character line grid 3082 and a first sub-character line grid 3071 located on both sides of the corresponding second channel post group 303. Each fourth sub-character line grid 3082 and the first sub-character line grid 3071 respectively control each second channel post 3031 in one second channel post group 303.

[0104] Please continue to refer to this. Figure 18 In this embodiment, after cutting off the first gate 307 and the second gate 308, a third isolation layer 311 is filled in the cutting groove, and the third isolation layer 311 completely fills the cutting groove.

[0105] The third isolation layer 311 is made of insulating material.

[0106] In this embodiment, the material of the third isolation layer 311 is silicon oxide.

[0107] Please refer to Figure 21 and Figure 22 , Figure 21 and Figure 19 The view orientation is consistent. Figure 22 and Figure 20With the view direction consistent, after forming the third isolation layer 311, a portion of the first sub-word grid 3071, a portion of the second sub-word grid 3072, a portion of the second sub-word grid 3072, and a portion of the fourth sub-word grid 3082 are removed.

[0108] In this embodiment, removing a portion of the first sub-word gate 3071, a portion of the second sub-word gate 3072, a portion of the second sub-word gate 3072, and a portion of the fourth sub-word gate 3082 specifically involves removing a portion of the gate layer from the first surface 300a to the second surface 300b. The purpose is to ensure that the first channel pillar 3021 and the second channel pillar 3031 corresponding to the removed gate layer are no longer under gate control, so as to form the first source / drain doped layer and the second source / drain doped layer in the future.

[0109] In this embodiment, during the process of removing part of the gate layer, the first gate isolation layer 309 and the second gate isolation layer 310 also need to be removed together. After removing the part of the gate layer, the removed first gate isolation layer 309 and the second gate isolation layer 310 need to be refilled.

[0110] Please refer to Figure 23 and Figure 24 , Figure 23 and Figure 21 The view orientation is consistent. Figure 24 and Figure 22 With the view direction consistent, after removing a portion of the first sub-word gate 3071, a portion of the second sub-word gate 3072, a portion of the second sub-word gate 3072, and a portion of the fourth sub-word gate 3082, a first source / drain doped layer 312 is formed in the first channel pillar 3021 on the side of the first word gate structure; and a second source / drain doped layer 313 is formed in the second channel pillar 3031 on the side of the second word gate structure.

[0111] In this embodiment, the first surface 300a exposes the first source / drain doped layer 312 in the first channel post 3021 on the side of the first word gate structure and the second source / drain doped layer 313 in the second channel post 3031 on the side of the second word gate structure.

[0112] In this embodiment, the method for forming the first source / drain doped layer 312 in the first channel post 3021 on the first word gate structure side and the second source / drain doped layer 313 in the second channel post 3031 on the second word gate structure side includes: performing ion implantation from the first surface 300a to the second surface 300b to form the first source / drain doped layer 312 and the second source / drain doped layer 313.

[0113] Please refer to Figure 25 and Figure 26 , Figure 25 and Figure 26 The view orientation is consistent. Figure 26 and Figure 24 With the view direction consistent, after forming the first source / drain doped layer 312 and the second source / drain doped layer 313 on one side of the first channel pillar 3021 and the second channel pillar 3031, the substrate 3001 is thinned from the second surface 300b toward the first surface 300a.

[0114] The process of thinning the substrate 3001 from the second surface 300b toward the first surface 300a includes: physical mechanical polishing, chemical mechanical polishing, or wet etching.

[0115] In this embodiment, the process of thinning the substrate 3001 from the second surface 300b to the first surface 300a is a chemical mechanical polishing process.

[0116] Please refer to Figure 27 and Figure 28 , Figure 27 and Figure 25 The view orientation is consistent. Figure 28 and Figure 26 With the view direction consistent, after the thinning process, the first source / drain doped layer 312 is formed in the first channel pillar 3021 on the other side of the first word line gate structure; and the second source / drain doped layer 313 is formed in the second channel pillar 3031 on the other side of the second word line gate structure.

[0117] In this embodiment, the method for forming the first source / drain doped layer 312 in the first channel post 3021 on the other side of the first word line gate structure and the second source / drain doped layer 313 in the second channel post 3031 on the other side of the second word line gate structure includes: performing ion implantation from the second surface 300b to the first surface 300a to form the first source / drain doped layer 312 and the second source / drain doped layer 313.

[0118] At this point, the manufacturing process for each transistor in the dynamic random access memory is complete.

[0119] Please refer to Figures 29 to 31 , Figure 29 This is a top view of the dynamic random access memory (DRAM) with each isolation layer omitted. Figure 30 yes Figure 29 Schematic diagram of the cross section along line JJ. Figure 31 yes Figure 29A schematic diagram of the cross-section along the KK line shows that after forming the first source / drain doped layer 312 and the second source / drain doped layer 313 on the other side of the first channel pillar 3021 and the second channel pillar 3031, the substrate 3001 is patterned and etched to form a plurality of first initial bit lines 314. The first initial bit lines 314 extend along the second direction Y, and each first initial bit line 314 is connected to the corresponding first channel pillar 3021 in each first channel pillar group 302. A plurality of second initial bit lines 315 are also formed. The second initial bit lines 315 extend along the second direction Y, and each second initial bit line 315 is connected to the corresponding second channel pillar 3031 in each second channel pillar group 303. The plurality of first initial bit lines 314 and the plurality of second initial bit lines 315 are alternately arranged along the first direction X.

[0120] In this embodiment, the first initial bit line 314 and the second initial bit line 315 are used to define the positions of the subsequently formed second bit line and the second bit line.

[0121] Please refer to Figure 32 and Figure 33 , Figure 32 and Figure 30 The view orientation is consistent. Figure 33 and Figure 31 With the view orientation consistent, a bit line isolation layer 316 is formed between adjacent first initial bit lines 314 and second initial bit lines 315, the bit line isolation layer 316 exposing the surfaces of the first initial bit lines 314 and the second initial bit lines 315.

[0122] The bit line isolation layer 316 is made of insulating material.

[0123] In this embodiment, the bit line isolation layer 316 is made of silicon dioxide.

[0124] In this embodiment, the bit line isolation layer 316 serves not only to provide electrical isolation between the first bit line and the second bit line formed subsequently, but also because the bit line isolation layer 316 is made of a different material than the first initial bit line 314 and the second initial bit line 315, it facilitates the use of a self-aligned process to make the first initial bit line 314 form the first bit line and the second initial bit line 315 form the second bit line.

[0125] Please refer to Figures 34 to 36 , Figure 34 This is a top view of the dynamic random access memory (DRAM) with each isolation layer omitted. Figure 35 yes Figure 34 Schematic diagram of the cross section along line LL. Figure 36 yes Figure 34A cross-sectional view along the MM line shows a metal layer (not shown) formed on the bit line isolation layer 316, the first initial bit line 314, and the second initial bit line 315; annealing is performed to generate a first bit line 317 between the metal layer and the first initial bit line 314, and to generate a second bit line 318 between the metal layer and the second initial bit line 315.

[0126] During annealing, the metal layer can only react with the first initial bit line 314 and the second initial bit line 315 of the semiconductor material, and not with the bit line isolation layer 316 of the insulating material. Therefore, the first bit line 317 and the second bit line 318 can be formed in a self-aligned manner. Thus, using a self-aligned process to form the first bit line 317 and the second bit line 318 can effectively reduce the photomask required for their formation, thereby reducing the manufacturing cost of the device structure.

[0127] In this embodiment, the first bit line 317 extends along the second direction Y, and each first bit line 317 is electrically connected to the corresponding first channel post 3021 in each first channel post group 302; the second bit line 318 extends along the second direction Y, and each second bit line 318 is electrically connected to the corresponding second channel post 3031 in each second channel post group 303, and the first bit line 317 and the second bit line 318 are arranged alternately along the first direction X.

[0128] In this embodiment, the materials of the first bit line 317 and the second bit line 318 include metal silicides; the metal silicides include nickel silicon, cobalt silicon, or titanium silicon. Using metal silicide materials can effectively reduce the contact resistance between the first bit line 317 and the first channel post 3021, and reduce the contact resistance between the second bit line 318 and the second channel post 3031.

[0129] In this embodiment, each of the first bit lines 317 is electrically connected to the first source / drain doped layer 312 within each of the first channel pillars 3021; ​​and each of the second bit lines 318 is electrically connected to the second source / drain doped layer 313 within each of the second channel pillars 3031.

[0130] Please refer to Figure 37 , Figure 37 and Figure 34With the view direction consistent, after forming the first bit line 317 and the second bit line 318, a plurality of first word line plugs 319 are formed, each of the first word line plugs 319 being electrically connected to the second sub-word line grid 3072 and the third sub-word line grid 3081 in the corresponding first word line grid structure; a plurality of second word line plugs 320 are formed, each of the second word line plugs 320 being electrically connected to the fourth sub-word line grid 3082 and the first sub-word line grid 3071 in the corresponding second word line grid structure; a plurality of first bit line plugs 321 are formed, each of the first bit line plugs 321 being electrically connected to the corresponding first bit line 317; and a plurality of second bit line plugs 322 are formed, each of the second bit line plugs 322 being electrically connected to the corresponding second bit line 318.

[0131] Since the transistors corresponding to the enabled bit lines (the first bit line 317 or the second bit line 318) and the transistors corresponding to the disabled bit lines (the second bit line 318 or the first bit line 317) are controlled by different word line gates (the first word line gate structure or the second word line gate structure), when the bit line interval is started, the transistors corresponding to the disabled bit lines do not need to be turned on. This can solve both the problem of reduced sensing tolerance caused by bit line coupling and the problem of data loss of the transistors corresponding to the disabled bit lines. Since the first and second word line gate structures are alternately distributed and can be turned on independently, a negative voltage can be applied to the unactivated word line gate structure (either the first or second word line gate structure). This reduces the leakage current of the transistor and also acts as a shield against crosstalk between the activated word line gate structures (either the second or first word line gate). Therefore, the fabrication of the back gate can be eliminated, effectively simplifying the manufacturing process and improving production efficiency. Simultaneously, the conductive plugs required for back gate lead-out can be eliminated, allowing the first word line plugs 319 and 319 to have a larger process window. Furthermore, the first word line gate structure includes the second sub-word line gate 3072 and the third sub-word line gate 3081, and the second word line gate structure includes the fourth sub-word line gate 3082 and the first sub-word line gate 3071. This dual-gate structure effectively enhances the control of the first channel pillar 3021 and the second channel pillar 3031, thereby improving the device's structural performance.

[0132] In this embodiment, along the first direction X, the first word line plug 319 and the second word line plug 320 are located on different sides of the first channel post group 302 or the second channel post group 303. By placing the first word line plug 319 and the second word line plug 320 on different sides of the first channel post group 302 or the second channel post group 303, the exposure window during the formation of the first word line plug 319 and the second word line plug 320 can be increased, thereby increasing the volume of the first word line plug 319 and the second word line plug 320 to improve electrical conductivity.

[0133] In this embodiment, the central axes of adjacent first word line plugs 319 extending along the second direction Y do not coincide; the central axes of adjacent second word line plugs 320 extending along the second direction Y also do not coincide. By staggering the adjacent first word line plugs 319 along the second direction Y, the exposure window for forming the first word line plug 319 can be further increased, thereby increasing the volume of the first word line plug 319 and improving its electrical conductivity. Similarly, by staggering the adjacent second word line plugs 320 along the second direction Y, the exposure window for forming the second word line plug 320 can be further increased, thereby increasing the volume of the second word line plug 320 and improving its electrical conductivity.

[0134] In this embodiment, along the second direction Y, the first bit line plug 321 and the second bit line plug 322 are located on different sides of the first channel post group 302 or the second channel post group 303. By placing the first bit line plug 321 and the second bit line plug 322 on different sides of the first channel post group 302 or the second channel post group 303, the exposure window during the formation of the first bit line plug 321 and the second bit line plug 322 can be increased, thereby increasing the volume of the first bit line plug 321 and the second bit line plug 322 to improve electrical conductivity.

[0135] In this embodiment, the central axes of adjacent first bit line plugs 321 extending along the first direction X do not coincide; the central axes of adjacent second bit line plugs 322 extending along the first direction X also do not coincide. By staggering the adjacent first bit line plugs 321 along the first direction X, the exposure window for forming the first bit line plug 321 can be further increased, thereby increasing the volume of the first bit line plug 321 and improving its electrical conductivity. Similarly, by staggering the adjacent second bit line plugs 322 along the first direction X, the exposure window for forming the second bit line plug 322 can be further increased, thereby increasing the volume of the second bit line plug 322 and improving its electrical conductivity.

[0136] Accordingly, this embodiment of the invention also provides a dynamic random access memory (DRAM), please refer to [link / reference needed]. Figures 2 to 37 The system includes: a plurality of first channel post groups 302, each first channel post group 302 including a plurality of first channel posts 3021 arranged along a first direction X; a plurality of second channel post groups 303, each second channel post group 303 including a plurality of second channel posts 3031 arranged along the first direction X, the first channel post groups 302 and the second channel post groups 303 being alternately arranged along a second direction Y, the first direction X being perpendicular to the second direction Y; and a plurality of first character line grid structures, along the second direction Y, each first character line grid structure including two sides located on the corresponding first channel post group 302. The second sub-character line grid 3072 and the third sub-character line grid 3081 control each of the first channel post 3021 in the first channel post group 302. A plurality of second sub-character line grid structures are provided along the second direction Y. Each second sub-character line grid structure includes a fourth sub-character line grid 3082 and a first sub-character line grid 3071 located on both sides of the corresponding second channel post group 303. Each fourth sub-character line grid 3082 and the first sub-character line grid 3071 control each of the first channel post 3021 in the second channel post group 303. Second channel post 3031; a plurality of first bit lines 317, each first bit line 317 extending along the second direction Y, each first bit line 317 electrically connected to a corresponding first channel post 3021 in each first channel post group 302; a plurality of second bit lines 318, each second bit line 318 extending along the second direction Y, each second bit line 318 electrically connected to a corresponding second channel post 3031 in each second channel post group 303, the first bit lines 317 and second bit lines 318 alternating along the first direction X; a plurality of first word line plugs 319, each... The first word line plug 319 is electrically connected to the second sub-word line grid 3072 and the third sub-word line grid 3081 in the corresponding first word line grid structure; a plurality of second word line plugs 320, each of the second word line plugs 320 being electrically connected to the fourth sub-word line grid 3082 and the first sub-word line grid 3071 in the corresponding second word line grid structure; a plurality of first bit line plugs 321, each of the first bit line plugs 321 being electrically connected to the corresponding first bit line 317; and a plurality of second bit line plugs 322, each of the second bit line plugs 322 being electrically connected to the corresponding second bit line 318.

[0137] Since the transistors corresponding to the enabled bit lines (the first bit line 317 or the second bit line 318) and the transistors corresponding to the disabled bit lines (the second bit line 318 or the first bit line 317) are controlled by different word line gate structures (the first word line gate structure or the second word line gate structure), when the bit line interval is started, the transistors corresponding to the disabled bit lines do not need to be turned on. This can solve both the problem of reduced sensing tolerance caused by bit line coupling and the problem of data loss of the transistors corresponding to the disabled bit lines. Since the first and second word line gate structures are alternately distributed and can be turned on individually, a negative voltage can be applied to the unactivated word line gate structure (either the first or second word line gate structure). This reduces the leakage current of the transistor and also acts as a shield against crosstalk between the activated word line gate structures (either the second or first word line gate). Therefore, the fabrication of the back gate can be eliminated, effectively simplifying the manufacturing process and improving production efficiency. Simultaneously, the conductive plugs required for back gate lead-out can be eliminated, allowing the first word line plugs 319 and 319 to have a larger process window. Furthermore, the first word line gate structure includes the second sub-word line gate 3072 and the third sub-word line gate 3081, and the second word line gate structure includes the fourth sub-word line gate 3082 and the first sub-word line gate 3071. This dual-gate structure effectively improves the control of the first channel pillar 3021 and the second channel pillar 3031, thereby enhancing the device's structural performance.

[0138] In this embodiment, it further includes a peripheral portion 3003, which surrounds a plurality of first channel post groups 302 and a plurality of second channel post groups 303. The peripheral portion 3003 can serve as a grinding stop layer for subsequent formation of an isolation layer, preventing excessive grinding from damaging the first channel posts 3021 and the second channel posts 3031.

[0139] In this embodiment, along the first direction X, the first word line plug 319 and the second word line plug 320 are located on different sides of the first channel post group 302 or the second channel post group 303. By placing the first word line plug 319 and the second word line plug 320 on different sides of the first channel post group 302 or the second channel post group 303, the exposure window during the formation of the first word line plug 319 and the second word line plug 320 can be increased, thereby increasing the volume of the first word line plug 319 and the second word line plug 320 to improve electrical conductivity.

[0140] In this embodiment, the central axes of adjacent first word line plugs 319 extending along the second direction Y do not coincide; the central axes of adjacent second word line plugs 320 extending along the second direction Y also do not coincide. By staggering the adjacent first word line plugs 319 along the second direction Y, the exposure window for forming the first word line plug 319 can be further increased, thereby increasing the volume of the first word line plug 319 and improving its electrical conductivity. Similarly, by staggering the adjacent second word line plugs 320 along the second direction Y, the exposure window for forming the second word line plug 320 can be further increased, thereby increasing the volume of the second word line plug 320 and improving its electrical conductivity.

[0141] In this embodiment, along the second direction Y, the first bit line plug 321 and the second bit line plug 322 are located on different sides of the first channel post group 302 or the second channel post group 303. By placing the first bit line plug 321 and the second bit line plug 322 on different sides of the first channel post group 302 or the second channel post group 303, the exposure window during the formation of the first bit line plug 321 and the second bit line plug 322 can be increased, thereby increasing the volume of the first bit line plug 321 and the second bit line plug 322 to improve electrical conductivity.

[0142] In this embodiment, the central axes of adjacent first bit line plugs 321 extending along the first direction X do not coincide; the central axes of adjacent second bit line plugs 322 extending along the first direction X also do not coincide. By staggering the adjacent first bit line plugs 321 along the first direction X, the exposure window for forming the first bit line plug 321 can be further increased, thereby increasing the volume of the first bit line plug 321 and improving its electrical conductivity. Similarly, by staggering the adjacent second bit line plugs 322 along the first direction X, the exposure window for forming the second bit line plug 322 can be further increased, thereby increasing the volume of the second bit line plug 322 and improving its electrical conductivity.

[0143] In this embodiment, the second sub-line grid 3072 and the third sub-line grid 3081 are respectively connected to a portion of the sidewall of the first channel post 3021; ​​the fourth sub-line grid 3082 and the first sub-line grid 3071 are respectively connected to a portion of the sidewall of the second channel post 3031.

[0144] In this embodiment, it further includes: a plurality of first gate trenches 304, wherein the first sub-word line gate 3071 and the second sub-word line gate 3072 are located within the first gate trenches 304; a plurality of second gate trenches 305, wherein the first gate trenches 304 and the second gate trenches 305 are alternately arranged along the second direction Y, wherein the first channel post group 302 is located between adjacent first gate trenches 304 and second gate trenches 305, the second channel post group 303 is located between adjacent first gate trenches 304 and second gate trenches 305, and the third sub-word line gate 3081 and the fourth sub-word line gate 3082 are located within the second gate trenches 305.

[0145] In this embodiment, a first gate isolation layer 309 is located within the first gate trench 304, and the first gate isolation layer 309 is used for electrical isolation between the first sub-word gate 3071 and the second sub-word gate 3072; a second gate isolation layer 310 is located within the second gate trench 305, and the second gate isolation layer 310 is used for electrical isolation between the third sub-word gate 3081 and the fourth sub-word gate 3082.

[0146] In this embodiment, it further includes: a first source / drain doped layer 312 located within the first channel pillars 3021 on both sides of the first word line gate structure along the extension direction of the first channel pillar 3021, wherein each first bit line 317 is electrically connected to the first source / drain doped layer 312 within each first channel pillar 3021; ​​and a second source / drain doped layer 313 located within the second channel pillars 3031 on both sides of the second word line gate structure along the extension direction of the second channel pillar 3031, wherein each second bit line 318 is electrically connected to the second source / drain doped layer 313 within each second channel pillar 3031.

[0147] In this embodiment, the materials of the first bit line 317 and the second bit line 318 include metal silicides; the metal silicides include nickel silicon, cobalt silicon, or titanium silicon. Using metal silicide materials can effectively reduce the contact resistance between the first bit line 317 and the first channel post 3021, and reduce the contact resistance between the second bit line 318 and the second channel post 3031.

[0148] In this embodiment, a bit line isolation layer 316 is also included, located between the first bit line 317 and the second bit line 318.

[0149] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A dynamic random access memory, characterized in that, include: A plurality of first trench column groups, each first trench column group comprising a plurality of first trench columns arranged along a first direction; A plurality of second channel column groups, each second channel column group including a plurality of second channel columns arranged along the first direction, the first channel column group and the second channel column group being arranged alternately along the second direction, the first direction being perpendicular to the second direction; A plurality of first word grid structures, along the second direction, each first word grid structure includes a second sub-word grid and a third sub-word grid located on both sides of the corresponding first channel post group, each second sub-word grid and the third sub-word grid respectively controlling each first channel post in one first channel post group; A plurality of second word grid structures, along the second direction, each second word grid structure includes a fourth sub-word grid and a first sub-word grid located on both sides of a corresponding second channel post group, each of the fourth sub-word grids and the first sub-word grids respectively controlling each second channel post in one second channel post group; A plurality of first bit lines, the first bit lines extending along the second direction, each of the first bit lines being electrically connected to the corresponding first channel post in each of the first channel post groups; A plurality of second bit lines, the second bit lines extending along the second direction, each second bit line being electrically connected to the corresponding second channel post in each second channel post group, the first bit lines and the second bit lines being arranged alternately along the first direction; A plurality of first word line plugs, each first word line plug being electrically connected to the second sub-word line grid and the third sub-word line grid in the corresponding first word line grid structure; A plurality of second word line plugs, each second word line plug being electrically connected to the fourth sub-word line grid and the first sub-word line grid in the corresponding second word line grid structure; A plurality of first bit line plugs, each first bit line plug being electrically connected to a corresponding first bit line; Several second bit line plugs, each second bit line plug being electrically connected to a corresponding second bit line.

2. The dynamic random access memory as described in claim 1, characterized in that, Also includes: The outer perimeter surrounds a plurality of the first trench post groups and a plurality of the second trench post groups.

3. The dynamic random access memory as described in claim 1, characterized in that, Along the first direction, the first letter plug and the second letter plug are located on different sides of the first channel post group or the second channel post group.

4. The dynamic random access memory as described in claim 3, characterized in that, The central axes of adjacent first-line plugs extending along the second direction do not coincide; the central axes of adjacent second-line plugs extending along the second direction do not coincide.

5. The dynamic random access memory as described in claim 1, characterized in that, Along the second direction, the first bit line plug and the second bit line plug are located on different sides of the first channel post group or the second channel post group.

6. The dynamic random access memory as described in claim 5, characterized in that, The central axes of adjacent first bit line plugs extending along the first direction do not coincide; the central axes of adjacent second bit line plugs extending along the first direction do not coincide.

7. The dynamic random access memory as described in claim 1, characterized in that, The second sub-line grid and the third sub-line grid are respectively connected to a portion of the sidewall of the first channel post; the fourth sub-line grid and the first sub-line grid are respectively connected to a portion of the sidewall of the second channel post.

8. The dynamic random access memory as described in claim 1, characterized in that, Also includes: A plurality of first gate trenches, wherein the first sub-word line gate and the second sub-word line gate are located within the first gate trenches; a plurality of second gate trenches, wherein the first gate trenches and the second gate trenches are alternately arranged along the second direction, wherein the first channel pillar group is located between adjacent first gate trenches and second gate trenches, the second channel pillar group is located between adjacent first gate trenches and second gate trenches, and the third sub-word line gate and the fourth sub-word line gate are located within the second gate trenches.

9. The dynamic random access memory as described in claim 8, characterized in that, A first gate isolation layer located within the first gate trench, the first gate isolation layer being used for electrical isolation between the first sub-word gate and the second sub-word gate; a second gate isolation layer located within the second gate trench, the second gate isolation layer being used for electrical isolation between the third sub-word gate and the fourth sub-word gate.

10. The dynamic random access memory as described in claim 1, characterized in that, Also includes: Along the extension direction of the first channel pillar, there are first source / drain doped layers located in the first channel pillars on both sides of the first word line gate structure, and each first bit line is electrically connected to the first source / drain doped layer in each of the first channel pillars; along the extension direction of the second channel pillar, there are second source / drain doped layers located in the second channel pillars on both sides of the second word line gate structure, and each second bit line is electrically connected to the second source / drain doped layer in each of the second channel pillars.

11. The dynamic random access memory as described in claim 1, characterized in that, The materials of the first bit line and the second bit line include: metal silicides; metal silicides include: nickel silicon, cobalt silicon or titanium silicon.

12. The dynamic random access memory as described in claim 1, characterized in that, Also includes: Bit line isolation layer located between the first bit line and the second bit line.

13. A method for forming a dynamic random access memory, characterized in that, include: A plurality of first trench column groups are formed, each first trench column group comprising a plurality of first trench columns arranged along a first direction; A plurality of second channel column groups are formed, each second channel column group including a plurality of second channel columns arranged along the first direction, the first channel column group and the second channel column group are arranged alternately along the second direction, the first direction being perpendicular to the second direction; A plurality of first character line grid structures are formed. Along the second direction, each first character line grid structure includes a second sub-character line grid and a third sub-character line grid located on both sides of the corresponding first channel post group. Each second sub-character line grid and the third sub-character line grid control each first channel post in one first channel post group. A plurality of second word grid structures are formed. Along the second direction, each second word grid structure includes a fourth sub-word grid and a first sub-word grid located on both sides of the corresponding second channel post group. Each of the fourth sub-word grids and the first sub-word grids controls each of the second channel posts in one second channel post group. A plurality of first bit lines are formed, the first bit lines extend along the second direction, and each first bit line is electrically connected to the corresponding first channel post in each first channel post group. A plurality of second bit lines are formed, the second bit lines extend along the second direction, each second bit line is electrically connected to the corresponding second channel post in each second channel post group, and the first bit lines and the second bit lines are arranged alternately along the first direction; A plurality of first word line plugs are formed, and each first word line plug is electrically connected to the second sub-word line grid and the third sub-word line grid in the corresponding first word line grid structure; A plurality of second word line plugs are formed, each second word line plug being electrically connected to the fourth sub-word line grid and the first sub-word line grid in the corresponding second word line grid structure; A plurality of first bit line plugs are formed, and each first bit line plug is electrically connected to the corresponding first bit line. A plurality of second bit line plugs are formed, each second bit line plug being electrically connected to the corresponding second bit line.

14. The method for forming a dynamic random access memory as described in claim 13, characterized in that, Along the first direction, the first letter plug and the second letter plug are located on different sides of the first channel post group or the second channel post group.

15. The method for forming a dynamic random access memory as described in claim 14, characterized in that, The central axes of adjacent first-line plugs extending along the second direction do not coincide; the central axes of adjacent second-line plugs extending along the second direction do not coincide.

16. The method for forming a dynamic random access memory as described in claim 13, characterized in that, Along the second direction, the first bit line plug and the second bit line plug are located on different sides of the first channel post group or the second channel post group.

17. The method for forming a dynamic random access memory as described in claim 16, characterized in that, The central axes of adjacent first bit line plugs extending along the first direction do not coincide; the central axes of adjacent second bit line plugs extending along the first direction do not coincide.

18. The method for forming a dynamic random access memory as described in claim 13, characterized in that, The second sub-line grid and the third sub-line grid are respectively connected to a portion of the sidewall of the first channel post; the fourth sub-line grid and the first sub-line grid are respectively connected to a portion of the sidewall of the second channel post.

19. The method for forming a dynamic random access memory as described in claim 13, characterized in that, A method for forming a plurality of first channel pillars and a plurality of second channel pillars includes: providing a substrate, the substrate including a base and a plurality of active regions arranged parallel to each other along a first direction on the base, the active regions extending along a second direction; and performing patterned etching on the active regions to form a plurality of first channel pillars and a plurality of second channel pillars.

20. The method for forming a dynamic random access memory as described in claim 19, characterized in that, The substrate further includes a peripheral portion located on the substrate, the peripheral portion surrounding a plurality of first channel pillar groups and a plurality of second channel pillar groups.

21. The method for forming a dynamic random access memory as described in claim 19, characterized in that, After forming a plurality of the first channel pillars and a plurality of the second channel pillars, the method further includes: forming a first isolation layer on the substrate, the first isolation layer covering the sidewalls of the first channel pillars and the second channel pillars and exposing the surfaces of the first channel pillars and the second channel pillars.

22. The method for forming a dynamic random access memory as described in claim 21, characterized in that, The method for forming the first sub-word grid, the second sub-word grid, the third sub-word grid, and the fourth sub-word grid includes: forming a plurality of first gate trenches and a plurality of second gate trenches in the first isolation layer, wherein the first gate trenches and the second gate trenches are alternately arranged along the second direction, the first channel pillar group is located between adjacent first gate trenches and second gate trenches, and the second channel pillar group is located between adjacent first gate trenches and second gate trenches; forming a first gate on the sidewall of the first gate trench and forming a second gate on the sidewall of the second gate trench; and cutting the first gate and the second gate, such that the first gate forms the first sub-word grid and the second sub-word grid along the second direction, and that the second gate forms the third sub-word grid and the fourth sub-word grid along the second direction.

23. The method for forming a dynamic random access memory as described in claim 22, characterized in that, After forming the first gate and the second gate, the method further includes: forming a first gate isolation layer in the first gate trench, the first gate isolation layer being used for electrical isolation between the first sub-word gate and the second sub-word gate; and forming a second gate isolation layer in the second gate trench, the second gate isolation layer being used for electrical isolation between the third sub-word gate and the fourth sub-word gate.

24. The method for forming a dynamic random access memory as described in claim 13, characterized in that, After forming the first word line gate structure and the second word line gate structure, the method further includes: forming a first source / drain doped layer in the first channel pillars on both sides of the first word line gate structure along the extension direction of the first channel pillars, wherein each first bit line is electrically connected to the first source / drain doped layer in each of the first channel pillars; and forming a second source / drain doped layer in the second channel pillars on both sides of the second word line gate structure along the extension direction of the second channel pillars, wherein each second bit line is electrically connected to the second source / drain doped layer in each of the second channel pillars.

25. The method for forming a dynamic random access memory as described in claim 19, characterized in that, The method for forming the first bit line and the second bit line includes: performing a patterned etching process on the substrate to form a plurality of first initial bit lines, wherein the first initial bit lines extend along a second direction and each first initial bit line is connected to a corresponding first channel post in each first channel post group; and forming a plurality of second initial bit lines, wherein the second initial bit lines extend along the second direction and each second initial bit line is connected to a corresponding second channel post in each second channel post group; the plurality of first initial bit lines and the plurality of second initial bit lines are alternately arranged along the first direction; forming a bit line isolation layer between adjacent first initial bit lines and second initial bit lines, wherein the bit line isolation layer exposes the surfaces of the first initial bit lines and second initial bit lines; forming a metal layer on the bit line isolation layer, the first initial bit lines, and the second initial bit lines; and performing an annealing process such that the metal layer and the first initial bit lines generate the first bit line, and the metal layer and the second initial bit lines generate the second bit line.

26. The method for forming a dynamic random access memory as described in claim 25, characterized in that, The materials of the first bit line and the second bit line include: metal silicides; metal silicides include: nickel silicon, cobalt silicon or titanium silicon.

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