Memory cell, memory array and control method thereof, memory device and manufacturing method thereof

Abstract

The invention discloses a memory cell, a memory array, a control method of the memory array, a memory device and a manufacturing method of the memory device. The memory cell comprises a device column, a gate structure circumferentially surrounding the device column, a memory capacitor located on one side, close to a first end, of the device column, and an interconnection table located on one side, close to a second end, of the device column. The area of the storage unit is small, so that the storage density of the storage array comprising the storage unit can be effectively improved; the interconnection table electrically connected with the second end of the device column can provide a basis for formation of a subsequent bit line, and the process difficulty of bit line formation can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a memory cell, a memory array and its control method, a memory device and its manufacturing method. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. For storage devices, the requirements for storage density and read / write speed are becoming increasingly stringent.

[0003] To improve integration and reduce costs, the size of storage cells is constantly shrinking, while the circuit density inside storage devices is increasing. This shrinking of storage cell size and increasing of internal circuit density make it increasingly difficult to further increase storage density and read / write speeds. Summary of the Invention

[0004] The problem solved by this invention is how to further increase storage density and improve read / write speed in storage devices.

[0005] To address the above problems, the present invention provides a storage unit, comprising:

[0006] A device post having a first end and a second end opposite to each other along the axial direction of the device post; a gate structure surrounding the device post circumferentially; a storage capacitor located on the side of the device post near the first end along the axial direction of the device post and electrically connected to the first end of the device post; and an interconnect located on the side of the device post near the second end along the axial direction of the device post and electrically connected to the second end of the device post.

[0007] Optionally, the interconnect platform is made of the same material as the device post.

[0008] Optionally, the interconnect platform is integrally connected to the device post.

[0009] Optionally, the extension direction of the interconnect station is perpendicular to the extension direction of the gate structure.

[0010] Optionally, in a plane perpendicular to the axial direction of the device post, the dimension of the projection of the interconnect station in the direction perpendicular to the extension direction is smaller than the dimension of the projection of the device post in the same direction.

[0011] Optionally, in a plane perpendicular to the axial direction of the device post, the geometric center of the projection of the interconnecting platform does not coincide with the geometric center of the projection of the device post.

[0012] Optionally, one side of the interconnect station is tangent to the side of the device post.

[0013] Optionally, the device pillar is cylindrical, and the storage capacitor is cylindrical.

[0014] Optionally, the gate structure includes a gate electrode and a gate dielectric layer, wherein the gate dielectric layer is located between the gate electrode and the device pillar.

[0015] Optionally, the gate electrode extends from at least one side of the gate dielectric layer along the axial direction of the device pillar.

[0016] Optionally, the gate electrode is made of polycrystalline silicon or a metal; the gate dielectric layer is made of an oxide.

[0017] Optionally, the storage capacitor is located on the end face of the first end.

[0018] Accordingly, the present invention also provides a storage array, comprising:

[0019] The storage unit, which is the storage unit of the present invention, is arranged in an array in a plane perpendicular to the axial direction of the device column.

[0020] Optionally, the storage cells of adjacent rows are staggered along the row direction; the storage cells of adjacent columns are staggered along the column direction.

[0021] Optionally, interconnects of storage units in the same row can be integrated.

[0022] Optionally, in a plane perpendicular to the axial direction of the device pillar, in adjacent columns of memory cells, the geometric center of the projection of the interconnect station is offset in the opposite direction relative to the geometric center of the projection of the corresponding device pillar.

[0023] Optionally, the gate electrodes of the gate structures of adjacent memory cells are integrally connected.

[0024] Optionally, it also includes: a bit line along the axial direction of the device post, the bit line being located on the side of the interconnect away from the device post, the bit line extending along the column direction in a plane perpendicular to the axial direction of the device post; memory cells in the same column are connected to the same bit line.

[0025] Optionally, in a plane perpendicular to the axial direction of the device post, the projection of the bit line overlaps with the projection of the interconnect.

[0026] Optionally, the bit line is located on the surface of the interconnect station on the side away from the device post.

[0027] Optionally, the material of the bit line and the material of the interconnect are fused together at the interface.

[0028] Optionally, at least a portion of the bit line near the interconnect station is made of metal silicide.

[0029] Optionally, the storage cells of adjacent columns are interleaved with the two adjacent bit lines.

[0030] Optionally, it also includes: word lines, which extend in a row direction in a plane perpendicular to the axial direction of the device pillars; memory cells in the same row are connected to the same word line.

[0031] Furthermore, the present invention also provides a control method for a memory array, wherein the memory array is the memory array of the present invention; the control method includes: applying a first voltage to a bit line while applying a second voltage to an adjacent bit line, wherein the second voltage is not equal to the first voltage.

[0032] Optionally, the memory array includes a first bit line, a second bit line, ..., an nth bit line arranged sequentially, where n is the number of bit lines; the step of applying a first voltage to a bit line while applying a second voltage to an adjacent bit line includes: applying a first voltage to the (2p-1)th bit line while applying a second voltage to the 2pth bit line, where p is an integer greater than 0.

[0033] Optionally, in the step of applying a first voltage to the 2p-1 bit line and applying a second voltage to the 2p bit line, the first voltage is applied to all 2p-1 bit lines while the second voltage is applied to all 2p bit lines.

[0034] Optionally, the step of applying a first voltage to a bit line and applying a second voltage to an adjacent bit line further includes: applying a first voltage to the 2qth bit line and applying a second voltage to the 2q-1th bit line, where q is an integer greater than 0.

[0035] Optionally, in the step of applying a first voltage to the 2q-1 bit line while simultaneously applying a second voltage to the 2q-1 bit line, the first voltage is applied to all 2q bit lines while the second voltage is applied to all 2q-1 bit lines.

[0036] Optionally, the second voltage is the default voltage.

[0037] Accordingly, the present invention also provides a storage device, comprising:

[0038] The storage array is the storage array of the present invention; the controller is adapted to apply a first voltage to a bit line while simultaneously applying a second voltage to an adjacent bit line, the second voltage being unequal to the first voltage.

[0039] Optionally, the storage array includes a first bit line, a second bit line, ..., an nth bit line arranged sequentially, where n is the number of bit lines; the controller is adapted to apply a first voltage to the (2p-1)th bit line while simultaneously applying a second voltage to the 2pth bit line, where p is an integer greater than 0.

[0040] Optionally, the controller applies a first voltage to all 2p-1 bit lines while simultaneously applying a second voltage to all 2p bit lines.

[0041] Optionally, the controller is also adapted to apply a first voltage to the 2q-1 bit line while simultaneously applying a second voltage to the 2q-1 bit line, where q is an integer greater than 0.

[0042] Optionally, the controller applies a first voltage to all 2q-th bit lines while simultaneously applying a second voltage to all 2q-1-th bit lines.

[0043] Optionally, the second voltage is the default voltage.

[0044] Furthermore, the present invention also provides a method for manufacturing a storage device, comprising:

[0045] A device pillar is formed having a first end and a second end opposite to each other along the axial direction of the device pillar; a gate structure is formed circumferentially around the device pillar; a storage capacitor is formed on the side of the device pillar near the first end along the axial direction of the device pillar, the storage capacitor being electrically connected to the first end; an interconnect is formed along the axial direction of the device pillar, the interconnect being located on the side of the device pillar near the second end, the interconnect being electrically connected to the second end of the device pillar.

[0046] Optionally, the step of forming the device pillar includes: providing a substrate; etching the substrate to form a substrate and a stage to be etched protruding from the front side of the substrate; etching the stage to be etched to form a preform stage and a device pillar protruding from the first side of the preform stage.

[0047] Optionally, in the step of etching the substrate to form a substrate and an etch stage protruding from the front side of the substrate, there are discrete openings between adjacent etch stages; after etching the substrate to form a substrate and an etch stage protruding from the front side of the substrate, and before etching the etch stages, a dielectric material is filled into the discrete openings.

[0048] Optionally, in the step of forming a device pillar, the device pillar protrudes from a first surface of the preform stage, and the preform stage protrudes from the front surface of the substrate; the step of forming an interconnect stage includes: removing the substrate to expose the preform stage; and etching the preform stage to form the interconnect stage.

[0049] Optionally, the step of removing the substrate to expose the preform stage includes: removing the substrate along the back side of the substrate to expose a second side of the preform stage, wherein the back side of the substrate is disposed opposite to the front side of the substrate, and the second side of the preform stage is disposed opposite to the first side of the preform stage; the step of etching the preform stage to form the interconnect stage includes: etching the preform stage through the second side of the preform stage to form the interconnect stage.

[0050] Optionally, the step of etching the preform to form the interconnect includes: thinning the preform through a second surface of the preform; forming a second opening through the thickness in the thinned preform to form interconnects adjacent in the row direction.

[0051] Optionally, in the step of forming a second opening through the thickness within the thinned preform, the second opening through the thickness is formed within the thinned preform by self-alignment.

[0052] Optionally, prior to the step of forming a second opening through the thickness within the thinned preform, the dielectric material filling the discrete opening protrudes from a second surface of the thinned preform; the step of forming a second opening through the thickness within the thinned preform includes: forming a linear layer on the thinned preform and the dielectric material filling the discrete opening; etching the linear layer to expose a portion of the surface of the thinned preform; and etching the exposed thinned preform to form the second opening.

[0053] Optionally, it further includes: forming a bit line on the side of the interconnect station away from the device post along the axial direction of the device post, the bit line being electrically connected to the interconnect station.

[0054] Optionally, in the step of forming a bit line on the side of the interconnect station away from the device post along the axial direction of the device post, the bit line is formed on the side of the interconnect station away from the device post along the axial direction of the device post by self-alignment.

[0055] Optionally, the step of forming a bit line on the side of the interconnect away from the device post along the axial direction of the interconnect includes: forming a precursor metal layer on the surface of the interconnect; and performing an annealing process to allow the precursor metal layer and the interconnect to react with each other to form the bit line.

[0056] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0057] In the technical solution of this invention, in the memory cell, the gate structure surrounds the device pillar along the axial direction, and the storage capacitor is located on one side of the first end of the device pillar along the axial direction and connected to the first segment. The gate structure completely surrounds the device pillar, which can effectively ensure the control capability of the gate structure over the channel; moreover, in the memory cell, the channel in the device pillar extends along the axial direction; in the plane perpendicular to the axial direction of the device pillar, the area of ​​the memory cell is small, which can effectively improve the storage density of the memory array including the memory cell; the interconnection stage electrically connected to the second end of the device pillar can provide a basis for the subsequent bit line formation, which can effectively reduce the process difficulty of bit line formation.

[0058] In an optional embodiment of the present invention, the interconnect platform is integrally connected to the device pillar, and the material of the bit line and the material of the interconnect platform are fused together at the interface; at least a portion of the bit line material near the interconnect platform is metal silicide. The bit line is formed by a self-aligned process. During the formation of the bit line, the use of photolithography can be effectively reduced, the difficulty of bit line formation can be effectively lowered, the impact of overlay accuracy on performance can be effectively avoided, which is beneficial to improving device manufacturing yield and device performance.

[0059] In an optional embodiment of the present invention, the storage cells in adjacent rows of the storage array are staggered along the column direction. This staggered arrangement of storage cells in adjacent rows, with the cells densely packed in a plane perpendicular to the axis of the device pillars, effectively increases the distribution density of the storage cells. This increased storage density also provides the hardware basis for an odd-even interval operating mode, maximizing storage density, minimizing wasted area, and achieving a balance between read / write speed and storage density.

[0060] In an optional embodiment of the present invention, adjacent column storage cells are connected to adjacent bit lines along the row direction; while applying a first voltage to a bit line, a second voltage is applied to adjacent bit lines, the second voltage being unequal to the first voltage. When the storage device is operating, unequal voltages are applied to adjacent bit lines; a first voltage is applied to a bit line for reading and writing data, and a second voltage is applied to adjacent bit lines to shield coupling capacitors; this odd-even interval operating mode effectively shields the coupling between bit lines, effectively ensuring the speed of read and write operations.

[0061] In the optional embodiment of the present invention, the second voltage is the default voltage, that is, the second voltage is Vcc / 2. This solution can be implemented without making major modifications to the internal circuit of the storage device, which can effectively reduce the difficulty of implementation process. Attached Figure Description

[0062] Figure 1 This is a schematic diagram of the circuit structure of a storage array;

[0063] Figure 2 These are three-dimensional structural schematic diagrams of some embodiments of the storage array of the present invention;

[0064] Figure 3 This is along some embodiments of the storage array of the present invention. Figure 2 A top view of the structure in the direction of A;

[0065] Figure 4 This is along some embodiments of the storage array of the present invention. Figure 3 A schematic diagram of the cross-sectional structure at the location of line B1B2 in the middle;

[0066] Figure 5 This is along some embodiments of the storage array of the present invention. Figure 3 A schematic diagram of the cross-sectional structure at the location of line C1C2 in the middle;

[0067] Figure 6 These are schematic diagrams of the circuit structure of some embodiments of the storage array of the present invention;

[0068] Figures 7 to 35 This is a schematic diagram of the intermediate structures of each step in some embodiments of the storage device manufacturing method of the present invention. Detailed Implementation

[0069] As the background technology shows, with the continuous iteration of storage device technology, the storage density requirements of storage devices are getting higher and higher, and it is becoming increasingly difficult to further increase the storage density of storage devices.

[0070] Furthermore, as storage density increases, the size requirements of components within the storage device also increase, with component sizes shrinking and the distances between components decreasing. This leads to increasingly stronger coupling between storage cells, and the coupling capacitance between adjacent bit lines in the storage device becomes larger and larger.

[0071] Specifically, such as Figure 1 As shown, in the storage array of the storage device, the storage cells 11 are arranged in a rectangular array, and the row and column directions of the storage array are perpendicular to each other. In the storage array, bit lines BL extend along the column direction and are arranged parallel to each other along the row direction; word lines WL extend along the row direction and are arranged parallel to each other along the column direction. Storage cells 11 located in the same row are connected to the same word line WL; storage cells 11 located in the same column are connected to the same bit line BL.

[0072] When the storage array is working, when the word line WL is applied with working voltage, all storage cells 11 in the same row are turned on and can work. That is, all bit lines BL can be applied with working voltage so that the storage cells 11 in the entire row start working at the same time. Since the distance between adjacent bit lines BL is small, the coupling effect between adjacent bit lines BL is strong, which affects the sense margin of the storage device and affects the further improvement of read and write speed.

[0073] To solve the aforementioned technical problem, the present invention provides a storage unit, comprising:

[0074] The device post has a first end and a second end that are opposite to each other along the axial direction of the device post; a gate structure that surrounds the device post circumferentially and is separated from both the first end and the second end along the axial direction of the device post; a storage capacitor that is located on the side of the device post near the first end along the axial direction of the device post and is electrically connected to the first end of the device post; and an interconnect that is located on the side of the device post near the second end along the axial direction of the device post and is electrically connected to the second end of the device post.

[0075] In this invention, the gate structure of the memory cell surrounds the device pillar along the axial direction, and the storage capacitor is located on one side of the first end of the device pillar along the axial direction and connected to the first segment. The gate structure completely surrounds the device pillar, effectively ensuring the gate structure's control over the channel; moreover, the channel in the device pillar extends axially within the memory cell; in a plane perpendicular to the axial direction of the device pillar, the area of ​​the memory cell is small, effectively increasing the storage density of the memory array including the memory cell; the interconnection stage electrically connected to the second end of the device pillar provides a foundation for the subsequent bit line formation, effectively reducing the technological difficulty of bit line formation.

[0076] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0077] refer to Figures 2 to 5 The diagram shows a structural schematic of an embodiment of the storage array of the present invention.

[0078] in, Figure 2 This is a three-dimensional structural diagram of an embodiment of the storage array of the present invention; Figure 3 yes Figure 2 A top view of the structure along direction A; Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure along line B1B2 in the middle; Figure 5 yes Figure 3 A schematic diagram of the cross-sectional structure along line C1C2.

[0079] The storage array includes storage cells 101 arranged in a regular array.

[0080] The memory cell 101 includes: a device post 110 having a first end (not shown) and a second end (not shown) opposite each other along the axial direction of the device post 110; a gate structure 120 surrounding the device post 110 circumferentially; a storage capacitor 130 located on the side of the device post 110 near the first end along the axial direction of the device post 110 and electrically connected to the first end of the device post 110; and an interconnection platform 140 located on the side of the device post 110 near the second end along the axial direction of the device post 110 and electrically connected to the second end of the device post 110.

[0081] Within the array plane parallel to the memory array, the area of ​​the memory cell 101 is smaller, and the memory array has a higher storage density. Moreover, the memory cell 101 is a gate all around (GAA) memory cell, and the gate structure 120 has a strong control capability over the channel, which can effectively guarantee the performance of the memory array.

[0082] The interconnecting platform 140 is integrally connected to the device pillar 110, which can provide a basis for forming bit lines through self-alignment process, effectively reduce the use of photolithography process in bit line formation process, and effectively reduce the difficulty of bit line formation process.

[0083] The specific technical solutions of embodiments of the storage array and storage unit of the present invention will be described in detail below with reference to the accompanying drawings.

[0084] The memory array includes memory cells 101 arranged in a regular array. Each memory cell 101 includes a device pillar 110, a gate structure 120, and a storage capacitor 130.

[0085] The device post 110 is used to form a switching device to control the opening and closing of the storage unit 101.

[0086] Specifically, the device pillar 110 is made of silicon. For example, the material of the device pillar 110 can be selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments of the present invention, the material of the device pillar can also be other semiconductor materials; for example, the material of the device pillar can also be group IV semiconductors or group III-V semiconductor materials such as germanium or gallium arsenide, and the material of the device pillar can even be a group II-VI semiconductor material. The material of the device pillar can be selected from any material suitable for forming a switching device.

[0087] The device post 110 has an axial direction and extends along the axial direction; along the axial direction of the device post 110, the device post 110 has a first end and a second end, wherein the first end is adapted to be connected to the storage capacitor 130; and the second end is adapted to be connected to the bit line BL.

[0088] like Figures 2 to 5 As shown, in some embodiments of the present invention, the device post 110 is cylindrical. Setting the device post 110 to a cylindrical shape minimizes sharp corner structures and avoids excessive concentration of electric field that could affect the performance of the memory cell. In a plane perpendicular to the axial direction of the device post 110, the end faces of both the first and second ends of the device post 110 are circular.

[0089] The gate structure 120 is suitable for controlling the channel conduction and cutoff of the switching device formed by the device pillars 110.

[0090] The device pillar 110 also has a circumferential direction around which its axial direction is the axis of rotation; the gate structure 120 surrounds the device pillar 110 circumferentially; in the memory cell, the channel in the device pillar 110 extends along an axial direction perpendicular to the device pillar 110; and the memory cell 101 is a gate all around (GAA) memory cell, and the gate structure 120 has strong control over the channel, which can effectively ensure the performance of the memory array.

[0091] In some embodiments of the present invention, the gate structure 120 includes a gate electrode 122 and a gate dielectric layer 121, the gate dielectric layer 121 being located between the gate electrode 122 and the device pillar 110. The gate electrode 122 is adapted to be electrically connected to an external circuit, and the gate dielectric layer 121 is adapted to provide electrical insulation between the gate electrode 122 and the device pillar 110.

[0092] In some embodiments, the gate structure 120 is one of a polysilicon gate structure and a metal gate structure. In some exemplary embodiments, the gate electrode 122 is made of polysilicon or a metal; the gate dielectric layer 121 is made of an oxide, for example, the oxide may be silicon oxide or a high-k gate dielectric layer.

[0093] In some embodiments of the present invention, the gate structure 120 extends along a predetermined direction in a plane perpendicular to the axial direction of the device pillar 110. The extending direction of the gate structure 120 is perpendicular to the axial direction of the device pillar 110. For example, ... Figures 2 to 5 As shown, the gate structure 120 extends along the first direction x.

[0094] In some embodiments, the gate electrode 122 extends from at least one side of the gate dielectric layer 121 along the axial direction of the device pillar 110. For example... Figures 2 to 5 As shown, along the axial direction of the device post 110, the gate electrode 122 extends from both sides of the gate dielectric layer 121; the dimension of the gate dielectric layer 121 along the axial direction of the device post 110 is larger than the dimension of the gate electrode 122 along the axial direction of the device post 110, and the gate electrode 122 is located only on the surface of the gate dielectric layer 121.

[0095] The storage capacitor 130 is suitable for storing data.

[0096] Along the axial direction of the device post 110, the storage capacitor 130 is located on one side of the first end of the device post 110. The device post 110 and the storage capacitor 130 are stacked along the axial direction of the device post 110; in a plane perpendicular to the axial direction of the device post 110, the projected area of ​​the storage cell is small.

[0097] In some embodiments of the present invention, the storage capacitor 130 is located on the end face of the first end of the device post 110; the surface of the storage capacitor 130 facing the device post 110 is in direct contact with the end face of the first end of the device post 110, so as to realize the electrical connection between the storage capacitor 130 and the device post 110.

[0098] like Figures 2 to 5 As shown, in some embodiments of the present invention, the storage capacitor 130 is cylindrical. Setting the storage capacitor 130 to a cylindrical shape minimizes sharp corner structures, preventing excessive electric field concentration that could cause tip discharge and affect the performance of the storage cell.

[0099] Continue to refer to Figures 2 to 5 The interconnecting station 140, electrically connected to the second end of the device post 110, is suitable for realizing the electrical connection between the device post 110 and the bit line BL. The interconnecting station 140 can also provide a process basis for the formation of the bit line BL, enabling the bit line BL to be formed in a self-aligned manner, thereby reducing the process difficulty of forming the bit line BL.

[0100] In some embodiments of the present invention, the interconnect platform 140 is made of the same material as the device post 110. In some exemplary embodiments, the device post 110 is made of silicon, and the interconnect platform 140 is also made of silicon. In other embodiments, when the device post 140 is made of a different material, the interconnect platform 140 may also be made of a different material.

[0101] In some embodiments, the interconnect 140 is integrally connected to the device post 110. There is no clear boundary between the interconnect 140 and the device post 110, and the interconnect 140 and the device post 110 can be etched from the same bulk material.

[0102] In some embodiments of the present invention, the extending direction of the interconnect 140 is perpendicular to the extending direction of the gate structure 120. The extending direction of the interconnect 140 is also perpendicular to the axial direction of the device pillar 110. Both the interconnect 140 and the gate structure extend in a plane perpendicular to the axial direction of the device pillar 110. For example, as... Figures 2 to 5 As shown, the gate structure 120 extends along a first direction x; the interconnect 140 extends along a second direction y.

[0103] In some embodiments of the present invention, in a plane perpendicular to the axial direction of the device pillar 110, the dimension of the projection of the interconnect 140 in the direction perpendicular to the extension direction is smaller than the dimension of the projection of the device pillar 110 in the same direction. Specifically, in a plane perpendicular to the axis of the device pillar 110, the width of the interconnect 140 is smaller than the diameter of the device pillar 110, which enables the interconnect 140 of adjacent columns of memory cells 101 to be separated while achieving close packing of the memory cells 101, and enables bit line BL separation while ensuring storage density.

[0104] like Figures 2 to 5 As shown, the interconnect platform 140 extends along the second direction y; in a plane perpendicular to the axial direction of the device post 110, the dimension of the interconnect platform 140 along the first direction x is smaller than the dimension of the device post 110 along the first direction x.

[0105] In some embodiments of the present invention, in a plane perpendicular to the axial direction of the device post 110, the geometric center of the projection of the interconnect 140 does not coincide with the geometric center of the projection of the device post 110. Specifically, in one of the memory cells 101, in a plane perpendicular to the axial direction of the device post 110, the interconnect 140 is biased toward one side of the device post 110 along the first direction x.

[0106] like Figures 2 to 5As shown, in one of the memory cells 101, in a plane perpendicular to the axial direction of the device post 101, the geometric center of the projection of the interconnect 140 is located on one side of the geometric center of the projection of the device post 110 along a first direction.

[0107] In some embodiments of the present invention, one side of the interconnect 140 is tangent to the side of the device post 110. In one of the memory cells 101, in a plane perpendicular to the axial direction of the device post 101, the projection of the interconnect 140 has a tangent edge to the projection of the device post 110.

[0108] Specifically, of the two opposite sides of the interconnecting platform 140 along the first direction x, one side is tangent to the side of the device post 110. For example... Figure 3 As shown, in one of the storage cells 101, in a plane perpendicular to the axial direction of the device post 101, one of the two sides of the projection of the interconnect 140 along a first direction is tangent to the projection of the device post 110.

[0109] Continue to refer to Figure 2 Combined with reference Figures 3 to 5 The storage array has an array plane, and a plurality of storage cells 110 in the storage array are arranged in a regular array along the row and column directions in the array plane.

[0110] It should be noted that, Figures 2 to 5 In the array, the first direction x and the second direction y are both parallel to the array plane, and the first direction x and the second direction y are perpendicular to each other; the third direction z is perpendicular to the array plane. Here, the first direction x is the row direction, and the second direction z is the column direction.

[0111] It should also be noted that, such as Figures 2 to 5 In some embodiments shown, the row direction and the column direction are perpendicular to each other; in other embodiments of the present invention, the row direction and the column direction may intersect but not be perpendicular.

[0112] like Figures 2 to 5 As shown, in some embodiments of the example, the device pillar 110 is perpendicular to the array plane of the memory array; the axial direction of the device pillar 110 is perpendicular to the array plane; the array plane is a plane perpendicular to the axial direction of the device pillar 110; within the array plane of the memory array, the projected area of ​​the memory cell is small; and the memory density of the memory array is large.

[0113] It should be noted that the axial direction of the device pillar 110 is perpendicular to the array plane; the array plane is a plane perpendicular to the axial direction of the device pillar 110; and the circumferential direction of the device pillar 110 is parallel to the array plane. The gate structure 120 extends in a plane perpendicular to the axial direction of the device pillar 110, and the gate structure 120 extends in a plane parallel to the array plane.

[0114] In some embodiments of the present invention, in adjacent memory cells 101 along the extension direction of the gate structure, the gate electrodes 122 of the gate structure 120 are integrally connected; in adjacent memory cells 101 along the direction perpendicular to the extension direction of the gate structure, the gate electrodes 120 of the gate structure 120 are separated.

[0115] In some embodiments, in the memory cell 101, the gate structure 120 extends along the row direction, and the gate electrodes 122 of the gate structures 120 in adjacent memory cells 101 along the row direction are integrally connected, thereby enabling the simultaneous activation of the switching devices of multiple memory cells 101 in the same row under row selection; the gate electrodes 122 of the gate structures 120 in adjacent memory cells 101 along the column direction are separated, thereby enabling independent operation of the switching devices in a single memory cell 101 under row and column selection.

[0116] like Figures 2 to 5 As shown, in some embodiments, the gate structure 120 extends along a first direction x; the gate electrodes 122 of the gate structures 120 in adjacent memory cells 101 along the first direction x are integrally connected; and the gate electrodes 122 of the gate structures 120 in adjacent memory cells 101 along the second direction y are separated.

[0117] In some embodiments, the gate electrodes 122 of the gate structures 120 of the memory cells 101 in the same row are all integrally connected. Specifically, the gate electrode 122 is elongated; in the array plane, the gate electrode 122 extends along the row direction (i.e., the first direction x) and spans the range of multiple device pillars 110; each device pillar 110 and the gate electrode 122 have a gate dielectric layer 121 between them.

[0118] Reference Figure 6 In some embodiments of the present invention, storage units 101 in adjacent rows are staggered along the row direction; storage units 101 in adjacent columns are staggered along the column direction. In the column direction, a storage unit 101 is located between two adjacent storage units 101 in an adjacent row; in the row direction, a storage unit 101 is located between two adjacent storage units 101 in an adjacent column. In the storage array, the storage units 101 are arranged in a hexagonal close-packed configuration; the higher the arrangement density of the storage units 101, the higher the storage density of the storage array.

[0119] like Figure 3As shown, in the second direction y, a storage cell 101 is located between two adjacent storage cells 101 in an adjacent row; in the first direction x, a storage cell 101 is located between two adjacent storage cells 101 in an adjacent column.

[0120] Specifically, the storage unit has rows 1, 2, ..., m arranged sequentially along the column direction, where m is the number of rows of storage units in the storage array; the storage unit has columns 1, 2, ..., n arranged sequentially along the row direction, where n is the number of columns of storage units in the storage array; the storage units in the i-th row are staggered with the storage units in the (i+1)-th row along the row direction; the storage units in the j-th column are staggered with the storage units in the (j+1)-th column along the column direction, where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n.

[0121] like Figure 3 and Figure 6 As shown, storage cells 101b and 101d are located in the same row, and storage cells 101a and 101c are located in the adjacent rows of the rows where storage cells 101b and 101d are located; along the row direction, storage cells 101a and 101c are located between storage cells 101b and 101d. Storage cells 101a and 101c are located in the same column, and storage cells 101b and 101d are located in the column of the column where storage cells 101a and 101c are located; along the column direction, storage cells 101b and 101d are located between storage cells 101a and 101c.

[0122] In some embodiments, the interconnects 140 of the memory cells 101 in the same column are integrally connected. In one of the memory cells 101, the interconnects 140 extend along the column direction in the array plane; such as Figure 2 and Figure 3 As shown, in the array plane, the interconnects 140 in the storage cell 101 extend along the second direction y; the interconnects of the storage cells 101 arranged along the second direction y are integrally connected.

[0123] In addition, such as Figure 3 In some of the embodiments shown, the storage cells 101 in adjacent rows are staggered along the row direction, and the storage cells 101 in adjacent rows are in different columns; the storage cells 101 in alternate rows are in the same column; and the interconnects 140 of the storage cells 101 in alternate rows are integrally connected.

[0124] In some embodiments, the interconnects 140 of adjacent memory cells 101 are separated. The interconnects 140 of adjacent memory cells 101 are arranged in parallel to each other; as shown... Figure 2 and Figure 3As shown, in the array plane, the interconnects 140 in the storage cell 101 are arranged parallel to each other along the first direction x.

[0125] In some embodiments, in a plane perpendicular to the axial direction of the device pillar 110, the geometric center of the projection of the interconnect 140 in adjacent columns of memory cells 101 is offset in the opposite direction to the geometric center of the projection of the corresponding device pillar 110.

[0126] Specifically, within the array plane, the interconnects 140 of adjacent columns of memory cells 101 are offset in different directions relative to their corresponding device pillars 110. For example, within the array plane, the interconnects 140 of one column of memory cells 101 are offset to one side relative to their corresponding device pillars 110 along a first direction x; the interconnects 140 of adjacent columns of memory cells 101 are offset to the other side relative to their corresponding device pillars 110 along the first direction x.

[0127] Figures 3 to 5 As shown, the interconnect 140 of storage cell 101a is biased toward one side of the device post 110 of storage cell 101a along the first direction x; storage cell 101b is adjacent to storage cell 110a along the row direction, and the interconnect 140 of storage cell 101b is biased toward the other side of the device post 110 of storage cell 101b along the first direction x.

[0128] Continue to refer to Figures 3 to 6 In some embodiments of the present invention, the memory array further includes: a bit line BL (e.g., along the axial direction of the device pillar 110, located on the side of the interconnect 140 away from the device pillar 110) Figure 6 (As shown by the solid blue line and the dashed blue line), in a plane perpendicular to the axis of the device column 110, the bit line BL extends along the column direction; the memory cells 101 in the same column are connected to the same bit line BL.

[0129] The bit line BL is electrically connected to the second end of the device post 110 via the interconnect 140 to enable data manipulation within the storage cell.

[0130] In some embodiments, the bit line BL is located on the surface of the interconnect 140 away from the device post 110. The bit line BL is directly located on the surface of the interconnect 140 away from the device post, meaning the surface of the bit line near the device post 110 is in contact with the surface of the interconnect 140 away from the interconnect 140.

[0131] In some embodiments, at least a portion of the bit line BL near the interconnect 140 is made of metal silicide. The bit line BL is formed by a self-aligned process, i.e., by metallizing a portion of the material on the side of the interconnect 140 facing away from the device pillar 110; the interconnect 140 is made of silicon, and the bit line BL is made of metal silicide.

[0132] In some embodiments, the material of the bit line BL is fused with the material of the interconnect 140 at the interface. The bit line BL is formed by a self-aligned process, i.e., by metallizing a portion of the material of the interconnect 140 on the side opposite to the device post 110; during the self-aligned process, the metal material diffuses into the bit line BL material, thereby causing the two to fuse at the interface to form the bit line BL. The bit line BL and the interconnect 140 are fused at the interface without a clear boundary line between them.

[0133] In some embodiments, the projection of the bit line BL overlaps with the projection of the interconnect stage 140 in a plane perpendicular to the axial direction of the device post 110. The bit line BL is formed by a self-aligning process; the size and position of the interconnect stage 140 determine the size and position of the bit line BL in a plane perpendicular to the axial direction of the device post 110; the position of the bit line BL coincides with the position of the interconnect stage 140, and the size of the bit line BL is identical to the size of the interconnect stage 140 everywhere.

[0134] In some embodiments, memory cells in the same column are connected to the same bit line BL. In a plane perpendicular to the axis of the device pillar 110, the bit line BL runs along the column direction (i.e., Figure 3 Extending in the second direction (y), along the row direction (i.e. Figure 3 The first direction (x) is arranged sequentially; along the column direction, the bit lines BL span multiple rows of the storage cells and are connected to multiple rows of the storage cells. Specifically, each storage cell has n bit lines BL, namely the 1st bit line, the 2nd bit line, ..., the nth bit line, and the nth bit line corresponds one-to-one with the n rows of storage cells.

[0135] In some embodiments, the memory cells of adjacent columns are staggered along the column direction; in a plane perpendicular to the axial direction of the device pillar 110, the bit line BL extends along the column direction; the memory cells of adjacent columns are staggered with two adjacent bit lines BL.

[0136] Specifically, the storage cells of odd-numbered rows (or even-numbered rows) in column a are related to the root bit line (e.g., ...). Figure 6 The storage cells in the even-numbered rows (or odd-numbered rows) of the (a+1)th column are connected to the (a+1)th bit line (as shown by the solid line). Figure 6(as shown by the dashed line in the middle) are connected, where a is an integer greater than or equal to 1 and less than or equal to n-1.

[0137] like Figure 6 As shown, in some embodiments of the present invention, the storage array further includes: word lines WL (e.g. Figure 6 (As shown by the red dashed and red solid lines), in a plane perpendicular to the axis of the device column 110, the word line WL extends along the row direction; memory cells in the same row are connected to the same word line WL.

[0138] In a plane perpendicular to the axial direction of the device pillar 110 (i.e., the array plane of the memory array), the word line WL runs along the row direction (i.e., Figure 3 Extending in the first direction x), along the column direction (i.e. Figure 3 The second direction (y) is arranged sequentially; along the row direction, the word line WL spans multiple columns of the storage cells and is connected to multiple columns of the storage cells.

[0139] Specifically, the storage unit has m word lines WL, namely the 1st word line, the 2nd word line, ..., the mth word line, and the m word lines correspond one-to-one with the m rows of storage units.

[0140] like Figures 2 to 5 As shown, a word line WL is connected to the gate structure of a memory cell in the same row. Specifically, in the gate structure 120 of the memory cell in the same row, the gate electrode 122 extends along the row direction and is integrally connected; the word line WL is connected to the memory cell in the same row through the integrally connected gate electrode 122.

[0141] In some embodiments, adjacent rows of memory cells are staggered along the row direction; in a plane perpendicular to the axial direction of the device pillar 110, the word lines WL extend along the row direction; adjacent rows of memory cells are staggered with two adjacent word lines WL.

[0142] Specifically, the storage units of odd-numbered columns (or even-numbered columns) in row b are related to the root word line (e.g., ...). Figure 6 (As shown by the solid red line in the middle) are connected, and the storage units of the even-numbered columns (or odd-numbered columns) in the (b+1)th row are connected to the (b+1)th word line (as shown by the solid red line in the middle). Figure 6 (as shown by the red dashed line in the middle) are connected, where b is an integer greater than or equal to 1 and less than or equal to m-1.

[0143] Accordingly, the present invention also provides a method for controlling a storage array.

[0144] Reference Figure 6 The storage device includes: a storage array, wherein the storage array is the storage array of the present invention; the control method includes: applying a first voltage to a bit line while applying a second voltage to an adjacent bit line, wherein the second voltage is not equal to the first voltage.

[0145] like Figures 2 to 5 As shown, the storage array is the storage array of the present invention. It is reasonable to refer to the aforementioned storage array for the specific technical solution of the storage array; therefore, the present invention will not repeat it here.

[0146] In the control method, different voltages are applied to adjacent bit lines BL at the same time so that the two adjacent bit lines BL play different roles: one bit line BL is used to operate on the connected memory cell 101 (e.g., one of read operation, write operation and erase operation), and the other bit line BL is used to shield the coupling effect of other bit lines BL.

[0147] The first voltage is suitable for operating the loaded storage cell 101. The first voltage is the operating voltage for operating the connected storage cell 101. The first voltage is determined based on the operation performed on the storage cell 101.

[0148] In some examples, during a read operation, the first voltage is a read voltage; in some examples, during a write operation, the first voltage is a write voltage; in some examples, during an erase operation, the first voltage is an erase voltage.

[0149] Specifically, the read voltage is suitable for reading data stored in the connected storage unit; the write voltage is suitable for writing data to the connected storage unit; and the erase voltage is suitable for erasing data stored in the connected storage unit.

[0150] The second voltage is suitable for preventing adjacent bit lines BL from being in a floating state so that the applied bit lines BL can serve as shielding coupling.

[0151] In some embodiments, the second voltage is a default voltage. Setting the second voltage as the default voltage avoids the adjacent bit line BL from being in a floating state, while eliminating the need to introduce a new voltage and make significant changes to the circuit to generate and apply the second voltage, effectively reducing the complexity of the implementation process.

[0152] For example, the second voltage is determined based on the voltage (Vcc) of the access circuit. For instance, the second voltage is half the voltage of the access circuit, Vcc / 2. In other embodiments of the invention, the second voltage may also be other fixed voltage values ​​to avoid the loaded bit line being in a floating state.

[0153] In some embodiments, the memory array includes a first bit line, a second bit line, ..., an nth bit line arranged sequentially, where n is the number of bit lines; the step of applying a first voltage to a bit line while applying a second voltage to an adjacent bit line includes: applying a first voltage to the (2p-1)th bit line while applying a second voltage to the 2pth bit line, where p is an integer greater than 0.

[0154] Specifically, to the 2p-1th bit line (e.g. Figure 6 A first voltage is applied (as shown by the solid blue line in the middle) to operate the connected memory cell 101; simultaneously, a voltage is applied to the 2p root bit line (as shown by the solid blue line in the middle). Figure 6 (As shown by the blue dashed line in the middle) A second voltage is applied to shield the coupling effect of other surrounding bit lines BL.

[0155] Continue to refer to Figure 6 In some specific embodiments, in the step of applying a first voltage to the 2p-1 bit line and applying a second voltage to the 2p bit line, the first voltage is applied to all 2p-1 bit lines while the second voltage is applied to all 2p bit lines.

[0156] Simultaneously applying a first voltage to all 2p-1 bit lines to operate on the corresponding connected memory cell 101, a second voltage is simultaneously applied to all 2p bit lines to ensure that the bit lines with the first voltage applied (such as...) Figure 6 The bit line shown by the solid blue line in the middle) and the bit line with the applied second voltage (such as...) Figure 6 The bit lines (shown by the blue dashed lines) are spaced apart, and there are bit lines with a second voltage applied between adjacent bit lines with the first voltage applied. The bit lines with the second voltage applied act as metal shields between adjacent bit lines with the first voltage applied, which can effectively reduce or even eliminate the coupling between adjacent bit lines with the first voltage applied.

[0157] In addition, in some embodiments, the step of applying a first voltage to a bit line and applying a second voltage to an adjacent bit line simultaneously includes: applying a first voltage to the 2qth bit line and applying a second voltage to the 2q-1th bit line simultaneously, where q is an integer greater than 0.

[0158] Specifically, to the 2q-1th bit line (e.g. Figure 6 A first voltage is applied (as shown by the blue dashed line in the middle) to operate the connected memory cell 101; simultaneously, a voltage is applied to the 2qth bit line (as shown by the dashed blue line in the middle). Figure 6 (As shown by the solid blue line) A second voltage is applied to shield the coupling effect of other surrounding bit lines BL.

[0159] In some specific embodiments, in the step of applying a first voltage to the 2q-1 bit line while simultaneously applying a second voltage to the 2q-1 bit line, the first voltage is applied to all 2q-1 bit lines while the second voltage is applied to all 2q-1 bit lines, similarly ensuring that the bit lines with the first voltage applied (such as...) Figure 6 The bit line shown by the blue dashed line) and the bit line with the applied second voltage (such as...) Figure 6 The bit lines (shown by the solid blue lines) are spaced apart, and the bit line with the second voltage acts as a metal shield between adjacent bit lines with the first voltage.

[0160] While applying a first voltage to all odd-numbered bit lines, a second voltage is applied to the even-numbered bit lines; while applying a second voltage to all even-numbered bit lines, a first voltage is applied to the odd-numbered bit lines. When the storage device is working, the bit lines operate in an odd-even interval mode, which can effectively shield the coupling effect between bit lines and effectively ensure the speed of read and write operations.

[0161] In some embodiments of the present invention, the storage array further includes multiple word lines WL (e.g., Figure 6 (As shown by the solid or dashed red line in the middle), specifically, the storage array also includes the first word line, the second word line, ..., the mth word line arranged in sequence, where m is the number of word lines; the control method also includes: applying a working voltage to a word line.

[0162] Apply operating voltage to the word line to enable row selection of memory cell 101.

[0163] Specifically, the time when the working voltage is applied to the word line WL is no later than the time when the first voltage is applied to the bit line and the second voltage is applied to the adjacent bit line BL: in some embodiments, the working voltage is applied to the word line WL at the same time as the first voltage is applied to the bit line and the second voltage is applied to the adjacent bit line; in other embodiments, the working voltage is applied to the word line WL after the first voltage is applied to the bit line and the second voltage is applied to the adjacent bit line.

[0164] In some embodiments, in the memory array, memory cells in adjacent rows are alternately connected to two adjacent word lines WL; and memory cells in adjacent columns are alternately connected to two adjacent bit lines BL.

[0165] When the storage array is working, it sends data to the 2c-1th word line (e.g., ...). Figure 6 When applying the operating voltage to activate the connected memory cell (as shown by the solid line in the middle), a first voltage is applied to all 2p-1 bit lines to activate them. A second voltage is applied to the 2p bit lines between the activated 2p-1 bit lines to provide metal shielding. A second voltage is applied to the 2c word line (as shown by the solid line in the middle). Figure 6(As shown by the dashed line in the middle) When the working voltage is applied to turn on the connected memory cell, a first voltage is applied to all the 2q bit lines to make all the 2q bit lines work. A second voltage is applied to the 2q-1 bit lines between the working 2q bit lines to provide a metal shielding effect.

[0166] Accordingly, the present invention also provides a storage device.

[0167] refer to Figure 6 The diagram shows a circuit structure schematic of an embodiment of the storage device of the present invention.

[0168] The storage device includes: a storage array, wherein the storage array is the storage array of the present invention; and a controller, which is adapted to apply a first voltage to a bit line while simultaneously applying a second voltage to an adjacent bit line, wherein the second voltage is not equal to the first voltage.

[0169] like Figures 2 to 5 As shown, the storage array is the storage array of the present invention. It is reasonable to refer to the aforementioned storage array for the specific technical solution of the storage array; therefore, the present invention will not repeat it here.

[0170] It should be noted that, in some embodiments, the controller is suitable for executing the various steps of the control method of the present invention. The specific technical solution of the controller can be found in the embodiments of the aforementioned control method.

[0171] The controller is connected to the bit line BL and applies voltage to the bit line BL to make the bit line BL work.

[0172] Specifically, the controller applies different voltages to adjacent bit lines BL at the same time, so that the two adjacent bit lines BL play different roles: one bit line BL is used to operate the connected memory cell 101 (e.g., one of read operation, write operation and erase operation), and the other bit line BL is used to shield the coupling effect of the other bit lines BL.

[0173] The first voltage is suitable for operating the loaded storage cell 101. The first voltage is the operating voltage for operating the connected storage cell 101. The first voltage is determined based on the operation performed on the storage cell 101.

[0174] In some examples, during a read operation, the first voltage is a read voltage; in some examples, during a write operation, the first voltage is a write voltage; in some examples, during an erase operation, the first voltage is an erase voltage.

[0175] Specifically, the read voltage is suitable for reading data stored in the connected storage unit; the write voltage is suitable for writing data to the connected storage unit; and the erase voltage is suitable for erasing data stored in the connected storage unit.

[0176] The second voltage is suitable for preventing adjacent bit lines BL from being in a floating state so that the applied bit lines BL can serve as shielding coupling.

[0177] In some embodiments, the second voltage is a default voltage. Setting the second voltage as the default voltage avoids the adjacent bit line BL from being in a floating state, while eliminating the need to introduce a new voltage and make significant changes to the circuit to generate and apply the second voltage, effectively reducing the complexity of the implementation process.

[0178] For example, the second voltage is determined based on the voltage (Vcc) of the access circuit. For instance, the second voltage is half the voltage of the access circuit, Vcc / 2. In other embodiments of the invention, the second voltage may also be other fixed voltage values ​​to avoid the loaded bit line being in a floating state.

[0179] Continue to refer to Figure 6 The controller uses a bit-line BL parity interval operation for control.

[0180] In some embodiments of the present invention, the memory array includes a first bit line, a second bit line, ..., an nth bit line arranged in sequence, where n is the number of bit lines; the controller applies a first voltage to the (2p-1)th bit line and applies a second voltage to the 2pth bit line, where p is an integer greater than 0.

[0181] like Figure 6 As shown, specifically, the controller includes: a first control element 141, which is connected to the bit line BL; the first control element 141 applies a first voltage to the 2p-1 bit line to operate the connected memory cell 101, and applies a second voltage to the 2p bit line to shield the coupling effect of other surrounding bit lines BL.

[0182] In some embodiments, the controller applies a first voltage to all 2p-1 bit lines while simultaneously applying a second voltage to all 2p bit lines. When simultaneously applying the first voltage to all 2p-1 bit lines to operate on the corresponding connected memory cell 101, the second voltage is simultaneously applied to all 2p bit lines so that the bit lines with the first voltage applied (e.g., ...) Figure 6 The bit line shown by the solid blue line in the middle) and the bit line with the applied second voltage (such as...) Figure 6The bit lines (shown by the blue dashed lines) are spaced apart, and there are bit lines with a second voltage applied between adjacent bit lines with the first voltage applied. The bit lines with the second voltage applied act as metal shields between adjacent bit lines with the first voltage applied, which can effectively reduce or even eliminate the coupling between adjacent bit lines with the first voltage applied.

[0183] For example, such as Figure 6 As shown, the controller has a first control element 141, which is connected to a plurality of bit lines BL; the first control element 141 simultaneously applies a first voltage to all bit lines 2p-1 and simultaneously applies a second voltage to all bit lines 2p.

[0184] Furthermore, in some embodiments, the controller applies a first voltage to the 2q-th bit line while simultaneously applying a second voltage to the 2q-1-th bit line, where q is an integer greater than 0. Specifically, as shown below... Figure 6 In some embodiments shown, the first control element 141 applies a first voltage to the 2q-1th bit line to operate the connected memory cell 101, while simultaneously applying a second voltage to the 2qth bit line to shield the coupling effect of other surrounding bit lines BL.

[0185] In some corresponding embodiments, the controller applies a first voltage to all 2q-th bit lines while simultaneously applying a second voltage to all 2q-1-th bit lines, similarly causing the bit lines applying the first voltage (such as...) to... Figure 6 The bit line shown by the blue dashed line) and the bit line with the applied second voltage (such as...) Figure 6 The bit lines (shown by the solid blue lines) are spaced apart, and the bit line with the second voltage acts as a metal shield between adjacent bit lines with the first voltage.

[0186] The controller applies a first voltage to all odd-numbered bit lines while applying a second voltage to even-numbered bit lines; the controller applies a second voltage to all even-numbered bit lines while applying a first voltage to odd-numbered bit lines; when the storage device is working, the bit lines operate in an odd-even interval mode, which can effectively shield the coupling effect between bit lines and effectively ensure the speed of read and write operations.

[0187] Continue to refer to Figure 6 In some embodiments of the present invention, the storage array further includes multiple word lines WL (e.g., Figure 6 (As shown by the solid or dashed red line in the middle). Specifically, the storage array also includes the first word line, the second word line, ..., the mth word line arranged sequentially, where m is the number of word lines; the controller applies operating voltage to the word lines.

[0188] like Figure 6As shown, specifically, the controller further includes: a second control element 142, which is connected to the word line WL; the second control element 142 applies a working voltage to the word line to enable the connected memory cell, so as to perform row selection on the memory cell 101.

[0189] Specifically, the second control element 142 applies a working voltage to the word line WL at a time no later than the time the first control element 141 applies a first voltage to the bit line BL and applies a second voltage to the adjacent bit line BL. In some embodiments, the second control element 142 applies a working voltage to the word line WL while the first control element 141 applies a first voltage to the bit line and applies a second voltage to the adjacent bit line. In other embodiments, the second control element 142 applies a working voltage to the word line WL, and then the first control element 141 applies a first voltage to the bit line and applies a second voltage to the adjacent bit line.

[0190] In some embodiments, in the memory array, memory cells in adjacent rows are alternately connected to two adjacent word lines WL; and memory cells in adjacent columns are alternately connected to two adjacent bit lines BL.

[0191] When the storage array is working, it sends data to the 2c-1th word line (e.g., ...). Figure 6 When applying the operating voltage to activate the connected memory cell (as shown by the solid line in the middle), a first voltage is applied to all 2p-1 bit lines to activate them. A second voltage is applied to the 2p bit lines between the activated 2p-1 bit lines to provide metal shielding. A second voltage is applied to the 2c word line (as shown by the solid line in the middle). Figure 6 (As shown by the dashed line in the middle) When the working voltage is applied to turn on the connected memory cell, a first voltage is applied to all the 2q bit lines to make all the 2q bit lines work. A second voltage is applied to the 2q-1 bit lines between the working 2q bit lines to provide a metal shielding effect.

[0192] In addition, the present invention also provides a method for manufacturing a storage device.

[0193] It should be noted that the manufacturing method described herein is suitable for manufacturing the storage device of the present invention. Specific embodiments of the manufacturing method can be found in the aforementioned embodiments of the storage device.

[0194] refer to Figures 7 to 35 The diagram shows a structural schematic of the intermediate structures of each step in some embodiments of the manufacturing method of the storage device of the present invention.

[0195] refer to Figure 7 Combined with reference Figures 8 to 13 ,in Figure 8 yes Figure 7 A top view of the structure along direction A1; Figure 9 yes Figure 8 A schematic diagram of the cross-sectional structure along line B1B2 in the middle; Figure 11 yes Figure 10 A top view of the structure along the A2 direction; Figure 12 yes Figure 11 A schematic diagram of the cross-sectional structure along line C1C2. Figure 13 yes Figure 11 A schematic diagram of the cross-sectional structure along line D1D2.

[0196] First, a device post 110 is formed, the device post 110 having a second end and a first end that are opposite to each other along the axial direction of the device post 110.

[0197] The device post 110 is used to form a switching device to control the opening and closing of the memory cell.

[0198] In some embodiments of the present invention, the step of forming the device pillar 110 includes: providing a substrate; such as Figures 7 to 9 As shown, the substrate is etched to form a substrate 102 and an etching stage 109 protruding from the front side of the substrate 102; as Figures 10 to 13 As shown, the etching stage 109 is etched to form a preform stage 108 and a device pillar 110 protruding from the surface of the preform stage 108.

[0199] The substrate is used to provide the process foundation and mechanical support.

[0200] Specifically, the substrate material is silicon. For example, the substrate material can be selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments of the present invention, the substrate material can also be other semiconductor materials. For example, the substrate material can also be a group IV semiconductor material such as germanium or silicon-germanium; the substrate material can also be a group III-V semiconductor material such as gallium arsenide; and even, the substrate material can be a group II-VI semiconductor material. The substrate material can be selected from any material suitable for forming a switching device.

[0201] The substrate 102 is suitable for providing mechanical support during the process; the etching stage 109 is used to form the preform stage 108 and the device pillar 110.

[0202] Both the substrate 102 and the etching stage 109 are etched from the substrate, and the materials of the substrate 102 and the device pillar 110 correspond to the material of the substrate. In some exemplary embodiments, the material of the substrate is silicon; the materials of the substrate 102 and the etching stage 109 are also silicon.

[0203] In the step of etching the substrate, a portion of the substrate thickness is etched, and the remaining unetched substrate thickness is suitable for forming the substrate 102, while the etched substrate is suitable for forming the etching stage 109.

[0204] like Figures 7 to 9 As shown, in some embodiments, during the step of etching the substrate to form a substrate 102 and an etching stage 109 protruding from the front side of the substrate 102, a discrete opening 107 is provided between adjacent etching stages 109. Specifically, during the step of etching the substrate, adjacent etching stages 109 and the substrate 102 form the discrete opening 107, which extends along a second direction y.

[0205] In some embodiments, during the step of etching the substrate, a plurality of discrete openings 107 and a plurality of etching stages 109 are formed; the plurality of discrete openings 107 are arranged in parallel along a first direction x, and the plurality of etching stages 109 are arranged in parallel along the first direction x.

[0206] It should be noted that, as Figures 7 to 9 As shown, the first direction x and the second direction y are both parallel to the front surface of the substrate 102 and perpendicular to each other. In other embodiments of the present invention, the first direction x and the second direction y may intersect but not be perpendicular to each other.

[0207] In some embodiments, after forming the substrate 102 and the etching stage 109 protruding from the front side of the substrate 102, the discrete opening 107 is filled. Specifically, the discrete opening 107 can be filled with a dielectric material to achieve insulation between adjacent etching stages 109 and to provide a good process surface for subsequent processes.

[0208] In some embodiments, after the etching stage 109 is formed, such as Figures 10 to 13 As shown, the etching stage 109 is patterned to form a preform stage 108 and a device pillar 110 protruding from the surface of the preform stage 108.

[0209] The prefabrication stage 108 is suitable for providing a process basis for the formation of subsequent interconnect stages; the device post 110 is suitable for forming switching devices.

[0210] In some embodiments, the step of etching the stage 109 to be etched includes: forming a patterned layer (not shown) on the surface of the stage 109 to be etched; using the patterned layer as a mask, etching a portion of the thickness of the stage 109 to be etched to form the preform stage 108 and the device pillar 110.

[0211] The patterned layer can be a patterned photoresist layer, which can be formed by exposing and developing spin-coated photoresist; the patterned layer can also be a hard mask layer, which can be formed by etching a deposited mask material layer.

[0212] It should be noted that, Figure 12 and Figure 13 The adjacent row of device columns 110 is shown in dashed lines.

[0213] Both the preform stage 108 and the device pillar 110 are etched from the etching stage 109, and the materials of the preform stage 108 and the device pillar 110 correspond to the material of the etching stage 109. In some exemplary embodiments, the material of the etching stage 109 is silicon, the preform stage 108 and the device pillar 110 are integrally connected, there is no clear boundary between the preform stage 108 and the device pillar 110, and both the preform stage 108 and the device pillar 110 are made of silicon.

[0214] The preform stage 108 protrudes from the front side of the substrate 102; the device post 110 protrudes from a first surface of the preform stage 108, the first surface facing away from the substrate 102; the axial direction of the device post 110 is a third direction z perpendicular to the front side of the substrate 102. For example, the axial direction of the cylindrical device post 110 is parallel to the generatrix direction of the cylinder, and the generatrix direction of the device post 110 is perpendicular to the front side of the substrate 102.

[0215] The device post 110 protrudes from the first surface of the preform stage 108. The first end and the second end of the device post 110 are opposite ends along the axial direction. The end face of the second end is connected to the first surface of the preform stage 108. The first end is away from the preform stage 108.

[0216] like Figures 10 to 13 As shown, in a plane perpendicular to the axial direction of the device pillar 110, the preform stage 108 extends along the second direction y. The extension direction of the preform stage 108 is consistent with the extension direction of the formed bit line BL, so that the subsequently formed bit line BL can be connected to the device pillar 110 of the plurality of memory cells 101. In addition, the preform stage 108 has at least one side along the first direction x to fill the discrete opening 107 (e.g., Figures 7 to 9 The medium material (as shown) is used to separate it from the adjacent prefabrication platform 108.

[0217] like Figures 10 to 13As shown, along the first direction x, the device post 110 is biased towards one side of the prefabrication stage 108. The interconnect stage 140 is biased towards one side of the device post 110 along the first direction x; in one of the storage cells 101, in a plane perpendicular to the axial direction of the device post 101, the geometric center of the projection of the interconnect stage 140 does not overlap with the geometric center of the projection of the device post 110; in one of the storage cells 101, in a plane perpendicular to the axial direction of the device post 101, the geometric center of the projection of the interconnect stage 140 is located on one side of the geometric center of the projection of the device post 110 along the first direction.

[0218] In some examples, the prefabrication stage 108 has a side tangent to the side of the device pillar 110. In one of the memory cells 101, in a plane perpendicular to the axial direction of the device pillar 101, the projection of the interconnect stage 140 has an edge tangent to the projection of the device pillar 110.

[0219] Specifically, of the two opposite sides of the prefabrication stage 108 along the first direction x, one side is tangent to the side of the device pillar 110; in the storage unit 101, in a plane perpendicular to the axial direction of the device pillar 101, one of the two sides of the projection of the interconnect stage 140 along the first direction is tangent to the projection of the device pillar 110.

[0220] like Figures 10 to 13 As shown, in some embodiments, in the step of forming device pillars 110, a plurality of device pillars 110 are formed, and the plurality of device pillars 110 are regularly arrayed in a plane parallel to the front side of the substrate 102.

[0221] The array plane of the plurality of device pillars 110 arranged in a regular array is parallel to the front surface of the substrate 102; it can be seen that the first direction x and the second direction y are both parallel to the array plane; the third direction z is perpendicular to the array plane; the axial direction of the device pillars 110 is perpendicular to the array plane. For example, the first direction x is the row direction of the plurality of device pillars 110 arranged in a regular array, and the second direction y is the column direction of the plurality of device pillars 110 arranged in a regular array.

[0222] It should be noted that the arrangement of the device pillars 110 within the array plane is consistent with the arrangement of the storage cells 101, and the arrangement of the device pillars 110 can be referred to the aforementioned embodiment of the storage array.

[0223] like Figure 11 As shown, in some embodiments of the present invention, the device posts 110 in adjacent rows are staggered along the row direction; the device posts 110 in adjacent columns are staggered along the column direction, so that the plurality of device posts 110 are arranged in a hexagonal close-packed arrangement.

[0224] Specifically, the multiple device columns 110 arranged in a regular array have rows 1, 2, ..., m arranged sequentially along the column direction, where m is the number of rows of the device columns 110; the multiple device columns 110 arranged in a regular array have columns 1, 2, ..., n arranged sequentially along the row direction, where n is the number of columns of the device columns 110; the device columns 110 in the i-th row are alternately arranged with the device columns 110 in the (i+1)-th row along the row direction; the device columns 110 in the j-th column are alternately arranged with the device columns 110 in the (j+1)-th column along the column direction, where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n.

[0225] like Figure 11 As shown, device pillars 110b and 110d are located in the same row, and device pillars 110a and 110c are located in the adjacent rows of the rows containing device pillars 110b and 110d; along the row direction, device pillars 110a and 110c are located between device pillars 110b and 110d. Device pillars 110a and 110c are located in the same column, and device pillars 110b and 110d are located in the column containing device pillars 110a and 110c; along the column direction, device pillars 110b and 110d are located between device pillars 110a and 110c.

[0226] In some embodiments, the prefabrication stations 108 of adjacent memory cells 101 along the column direction are integrally connected. For example... Figure 11 As shown, the second direction y is the row direction; the prefabrication stations 108 of adjacent memory cells 101 along the second direction y are integrally connected; the prefabrication stations 108 of multiple memory cells 101 arranged along the second direction y are sequentially connected, so that the prefabrication station extends from one side of the column direction of a column of device columns 110 to the other side.

[0227] In some embodiments, adjacent device posts 110 along the row direction are biased toward the same side of the corresponding preform 108 along the row direction, while adjacent device posts 110 along the column direction are biased toward different sides of the corresponding preform 108 along the row direction.

[0228] Specifically, such as Figure 11 As shown, device post 110a is biased toward one side of the corresponding preform stage 108; device post 110b is adjacent to device post 110a along the first direction x (i.e., row direction), and device post 110b is biased toward the same side of the corresponding preform stage 108 along the first direction x (i.e., row direction); device post 110c is adjacent to device post 110a along the second direction y (i.e., column direction), and device post 110b is biased toward the other side of the corresponding preform stage 108 along the row direction x (i.e., row direction).

[0229] In some embodiments of the example, the sidewalls of adjacent device pillars 110 along the row direction are tangent to the sidewalls of their respective corresponding preforms 108 on the same side along the row direction; the sidewalls of adjacent device pillars 110 along the column direction are tangent to the sidewalls of their respective corresponding preforms 108 on different sides along the row direction.

[0230] Specifically, such as Figure 11 As shown, device pillars 110a and 110b are adjacent along the first direction x (i.e., row direction), and the sidewalls of device pillars 110a and 110b are tangent to the sidewalls of their respective preforms 108 on the same side along the row direction; device pillars 110a and 110c are adjacent along the second direction y (i.e., column direction), and the sidewalls of device pillars 110a and 110c are tangent to the sidewalls of their respective preforms 108 on different sides along the row direction.

[0231] For example, the extended prefabrication stage 108 has two columns of device posts 110; the two columns of device posts 110 are respectively biased towards one side and the other side of the prefabrication stage 108 along the row direction. Specifically, in a plane perpendicular to the axial direction of the device posts 101, the geometric centers of the projections of the two columns of device posts 110 are arranged in two columns on both sides of the geometric center of the projection of the interconnect stage 140 along the row direction.

[0232] In some embodiments, the two columns of device pillars 110 are tangent to two sides of the preform stage 108 along the row direction. Specifically, on the extended preform stage 108, the side of one column of device pillars 110 is tangent to one side of the extended preform stage 108, and the side of the other column of device pillars 110 is tangent to the other side of the extended preform stage 108.

[0233] Specifically, such as Figure 11 As shown, device pillars 110a, 110b, 110c, and 110e are located on the same extended preform stage 108; wherein device pillars 110a and 110c are arranged in a row along the second direction y, and device pillars 110b and 110e are arranged in a row along the second direction y; the side of device pillar 110a and the side of device pillar 110c are both tangent to one side of the preform stage 108; the side of device pillar 110b and the side of device pillar 110e are both tangent to the other side of the preform stage 108.

[0234] refer to Figures 14 to 22 ,in Figure 15 yes Figure 12 A cross-sectional structural diagram of the corresponding location; Figure 16 yes Figure 13 A cross-sectional structural diagram of the corresponding location; Figure 17 yes Figure 12 A cross-sectional structural diagram of the corresponding location; Figure 18 yes Figure 13 A cross-sectional structural diagram of the corresponding location; Figure 20 yes Figure 19 A top view of the structure along the A3 direction; Figure 21 yes Figure 20 A schematic diagram of the cross-sectional structure along line C3C4 in the middle; Figure 22 yes Figure 20 A schematic diagram of the cross-sectional structure along line D3D4.

[0235] After the device pillar 110 is formed, a gate structure 120 is formed around the device pillar 110 in the circumferential direction.

[0236] The circumferential direction of the device pillar 110 lies in a plane perpendicular to its axial direction. The axial direction of the device pillar 110 is perpendicular to the front surface of the substrate 102. The circumferential direction of the device pillar 110 is parallel to the front surface of the substrate 102. The circumferential direction of the device pillar 110 is parallel to the array plane of a plurality of device pillars 110 arranged in a regular array.

[0237] The gate structure 120 surrounds the device pillar 110 in a plane parallel to the array plane. The memory cell is a gate all around (GAA) memory cell. The gate structure 120 has strong control over the channel, which can effectively ensure the performance of the memory array. The channel in the device pillar 110 extends along the third direction z of the array plane of multiple device pillars 110 arranged in a regular array. Within the array plane, the area of ​​the formed memory cell is small, which can effectively improve the storage density.

[0238] In some embodiments of the present invention, the step of forming a gate structure 120 surrounding the device pillar 110 in the circumferential direction includes: forming a gate dielectric layer 121 surrounding the device pillar 110 in the circumferential direction; and forming a gate electrode 122 on the gate dielectric layer 121.

[0239] In some embodiments, the gate structure 120 is one of a polysilicon gate structure and a metal gate structure. In some exemplary embodiments, the gate electrode 122 is made of polysilicon or a metal; the gate dielectric layer 121 is made of an oxide, for example, the oxide may be silicon oxide or a high-k gate dielectric layer.

[0240] It should be noted that in the step of forming the gate structure 120, the corresponding material is patterned based on the shape and distribution of the gate structure 120; the shape and distribution of the formed gate structure 120 can be referred to the foregoing embodiments.

[0241] In some embodiments of the present invention, the gate structure 120 extends along a predetermined direction in a plane parallel to the substrate 102. The axial direction of the device pillars 110 is perpendicular to the array plane of the plurality of device pillars 110 arranged in a regular array, and the gate structure 120 extends along a predetermined direction in the array plane of the plurality of device pillars 110 arranged in a regular array.

[0242] Specifically, such as Figure 19 and Figure 20 As shown, the gate electrode 122 is elongated; in the array plane of multiple device pillars 110 arranged in a regular array, the gate electrode 122 extends along the row direction (i.e., the first direction x) and spans the range of the distribution of multiple device pillars 110; each device pillar 110 and the gate electrode 122 have a gate dielectric layer 121 between them.

[0243] In some embodiments, the gate electrode 122 extends from at least one side of the gate dielectric layer 121 along the axial direction of the device pillar 110. For example... Figure 19 As shown, along the axial direction of the device pillar 110, the gate electrode 122 extends from both sides of the gate dielectric layer 121; along the third direction z, the size of the gate dielectric layer 121 is larger than the size of the gate electrode 122, and the gate electrode 122 is located only on the surface of the gate dielectric layer 121.

[0244] It should be noted that, along the axial direction of the device post 110, the gate structure 120 surrounds the middle position of the device post 110 and is separate from both the first and second ends of the device post 110. For example... Figures 14 to 18 As shown, the manufacturing method further includes: forming a first dielectric layer after forming the device pillar 110 and before forming the gate structure 120. Figure 17 and Figure 18 (Seen in semi-transparent orange in the image), the first dielectric layer covers a portion of the sidewall of the device pillar 110 near the prefabrication stage 108; as shown in the image. Figures 19 to 22 As shown, in the step of forming the gate structure 120, the gate structure 120 is formed on the first dielectric layer.

[0245] The first dielectric layer is used to achieve electrical insulation between adjacent device pillars 110. Specifically, the material of the first dielectric layer is a dielectric material; for example, the material of the first dielectric layer can be a dielectric material such as silicon oxide, and the first dielectric layer can also be a low-k dielectric material, or even an ultra-low-k dielectric material.

[0246] For example, the steps of forming the first dielectric layer include: Figures 14 to 16 As shown, a dielectric material is formed on the substrate, and the dielectric material fills the spaces between adjacent device pillars; as Figures 17 to 18As shown, a portion of the dielectric material is removed to expose the end face of the first end of the device post 110, forming the first dielectric layer.

[0247] In addition, such as Figure 21 and Figure 22 In some embodiments shown, the manufacturing method further includes: after forming the gate structure 120, forming a second dielectric layer ( Figure 21 and Figure 22 (shown in semi-transparent orange in the image), the second dielectric layer is located on the side of the gate structure 120 away from the preform stage 108, filling the space between adjacent device pillars 110.

[0248] The second dielectric layer is used to achieve electrical insulation between adjacent device pillars 110; moreover, the top surface of the second dielectric layer is flush with the end face of the first end of the device pillar 110, which can also provide a good process operation surface for subsequent processes.

[0249] Specifically, the material of the second dielectric layer is a dielectric material; for example, the material of the second dielectric layer can be a dielectric material such as silicon oxide, or it can be a low-k dielectric material, or even an ultra-low-k dielectric material.

[0250] For example, the step of forming the second dielectric layer includes: forming a dielectric material on the gate structure 120, the dielectric material filling between adjacent device pillars 110; removing a portion of the dielectric material to expose the end face of the first end of the device pillar 110, thereby forming the second dielectric layer.

[0251] It should be noted that, Figure 19 and Figure 20 The first and second dielectric layers are omitted; only a portion of the structure is shown for clarity.

[0252] refer to Figure 23 After the gate structure 120 is formed, a storage capacitor 130 is formed on the side of the device post 110 close to the first end along the axial direction of the device post 110. The storage capacitor 130 is electrically connected to the first end.

[0253] The device pillar 110 and the storage capacitor 130 are stacked along a third direction z perpendicular to the front side of the substrate 102; the device pillar 110 is located between the storage capacitor 130 and the substrate 102.

[0254] In some specific embodiments, in the step of forming the storage capacitor 130, the storage capacitor 130 is formed on the end face of the first end of the device post 110. The surface of the storage capacitor 130 facing the device post 110 is in direct contact with the end face of the first end of the device post 110 to achieve an electrical connection between the storage capacitor 130 and the device post 110.

[0255] It should be noted that, as Figure 23 As shown, in some embodiments, the manufacturing method further includes: after forming the storage capacitor 130, forming a third dielectric layer ( Figure 23 (shown in semi-transparent orange in the image), the third dielectric layer is located on the side of the second dielectric layer away from the gate structure 120 and fills the space between adjacent storage capacitors 130.

[0256] The third dielectric layer is used to achieve electrical insulation between adjacent storage capacitors 130; moreover, the top surface of the third dielectric layer is flush with the end face of the storage capacitor 130, and the third dielectric layer can also provide a good operating surface for subsequent processes.

[0257] Specifically, the material of the third dielectric layer is a dielectric material; for example, the material of the third dielectric layer can be a dielectric material such as silicon oxide, or it can be a low-k dielectric material, or even an ultra-low-k dielectric material.

[0258] For example, the step of forming the third dielectric layer includes: forming a dielectric material on the second dielectric layer, the dielectric material filling between adjacent storage capacitors 130; removing a portion of the dielectric material to expose the end face of the storage capacitor 130, thereby forming the third dielectric layer.

[0259] refer to Figures 24 to 35 ,in Figure 25 , Figure 28 , Figure 31 and Figure 34 All Figure 21 A cross-sectional structural diagram of the corresponding location. Figure 26 , Figure 29 , Figure 32 and Figure 35 All Figure 22 A cross-sectional structural diagram of the corresponding location.

[0260] After the storage capacitor 130 is formed, an interconnect 140 is formed along the axial direction of the device post 110. The interconnect 140 is located on the side of the device post 110 closer to the second end, and the interconnect 140 is electrically connected to the second end of the device post 110.

[0261] It should be noted that, Figure 24 , Figure 27 , Figure 30 and Figure 33 The first, second, and third dielectric layers are omitted; only a portion of the structure is shown for clarity.

[0262] In some embodiments of the present invention, the step of forming the interconnect station 140 includes: as follows Figures 24 to 29 Remove the substrate 102 to expose the preform stage 108; as Figures 30 to 35 The preform stage 108 is etched to form the interconnect stage 140.

[0263] Specifically, prior to the step of forming the interconnect 140, the substrate 102 is removed to expose the prefabrication stage 108, providing a basis for the formation of the interconnect 140.

[0264] In some embodiments, the step of removing the substrate 102 to expose the preform stage 108 includes: removing the substrate 102 along the back side of the substrate 102 to expose the second side of the preform stage 108, wherein the back side of the substrate 108 is disposed opposite to the front side of the substrate 102, and the second side of the preform stage 108 is disposed opposite to the first side of the preform stage 108.

[0265] Furthermore, the step of removing the substrate 102 also includes: as Figures 24 to 26 As shown, after forming the storage capacitor 130, the structure is reversed to expose the back side of the substrate 102, wherein the back side of the substrate 102 is opposite to the front side of the substrate 102; as Figures 27 to 29 As shown, after the structure is reversed, the substrate 102 is removed along the back side of the substrate 102.

[0266] Specifically, the step of removing the substrate 102 along the back side of the substrate 102 includes: thinning the substrate 102 by grinding; etching the thinned substrate 102 until the second side of the preform stage 108 is exposed, the second side of the preform stage 108 being disposed opposite to the first side.

[0267] Furthermore, the prefabrication platform 108 has at least one side along the first direction x that fills the discrete opening 107 (e.g., Figures 7 to 9 In the step of removing the substrate 102 along the back side of the substrate 102, the dielectric material filling the discrete opening 107 is also exposed, and the surface of the exposed dielectric material filling the discrete opening 107 is flush with the second surface of the exposed preform stage 108.

[0268] In some embodiments, the step of etching the preform stage 108 to form the interconnect stage 140 includes: etching the preform stage 108 through a second surface of the preform stage 108 to form the interconnect stage 140.

[0269] In some specific embodiments, the step of etching the preform 108 to form the interconnect 140 includes: as follows Figures 30 to 32 As shown, the prefabrication platform 108 is thinned through its second surface; as Figures 33 to 35 As shown, a second opening through the thickness is formed in the thinned preform 108 to form the interconnect 140.

[0270] For example, in the step of thinning the preform stage 108 through the second surface of the preform stage 108, the preform stage 108 can be thinned from the second surface of the preform stage 108 by etching.

[0271] In some embodiments, during the step of thinning the preform stage 108 by etching, only the preform stage 108 is etched, and the dielectric material filling the discrete opening 107 is not etched. For example... Figures 30 to 32 As shown, after the preform 108 is thinned, the medium material filling the discrete opening 107 protrudes from the second surface of the thinned preform 108.

[0272] In some embodiments, in the step of forming a second opening through the thickness within the thinned preform 108, the second opening through the thickness is formed in the thinned preform 108 by self-alignment. Specifically, the second opening can be formed by forming a linear layer and a punching process.

[0273] like Figures 30 to 32 As shown, in the step of thinning the preform stage 108, only the preform stage 108 is thinned, and the dielectric material filling the discrete opening 107 is not etched; specifically, before the step of forming a second opening through the thickness in the thinned preform stage 108, the dielectric material filling the discrete opening 107 protrudes from the second surface of the thinned preform stage 108.

[0274] For example, the step of forming a second opening through the thickness within the thinned preform stage 108 includes: forming a linear layer (not shown) on the thinned preform stage 108 and the dielectric material filling the discrete opening 107; etching the linear layer to expose a portion of the surface of the thinned preform stage 108; and etching the exposed thinned preform stage 108 to form the second opening.

[0275] The dielectric material filling the discrete opening 107 protrudes from the thinned preform stage 108; in the step of forming the linear layer, the linear layer conformally covers the thinned preform stage 108 and the dielectric material filling the discrete opening 107; along the first direction x, the thickness of the portion of the linear layer located in the middle of the preform stage 108 is greater than the thickness of the portion of the linear layer near the dielectric material filling the discrete opening 107; in the step of etching the linear layer, the linear layer is etched without a mask (blank etch) to expose the surface of the middle position of the thinned preform stage 108, that is, without using a mask or photolithography, only the entire linear layer is etched to expose the surface of the middle position of the thinned preform stage 108, thereby causing the second opening to divide the preform stage 108 into two parts, forming two interconnect stages 140 respectively.

[0276] The interconnect 140 is formed by self-alignment, which eliminates the need for photolithography and masks, effectively avoiding the impact of photolithography alignment on yield and performance. This can effectively reduce process costs and manufacturing difficulty of the interconnect 140, and ensure manufacturing yield and device performance while increasing memory cell density.

[0277] like Figures 33 to 35 As shown, in some embodiments, the manufacturing method further includes: forming a second opening, forming the interconnect 140, and then forming a fourth dielectric layer. Figures 33 to 35 (shown as sparse dots), the fourth dielectric layer fills the second opening.

[0278] The fourth dielectric layer is used to achieve electrical insulation between adjacent interconnects 140; moreover, the surface of the fourth dielectric layer is flush with the surface of the interconnect 140, and the fourth dielectric layer can also provide a good operating surface for subsequent processes.

[0279] Specifically, the material of the fourth dielectric layer is a dielectric material; for example, the material of the fourth dielectric layer can be a dielectric material such as silicon oxide, or it can be a low-k dielectric material, or even an ultra-low-k dielectric material.

[0280] For example, the step of forming the fourth dielectric layer includes: forming a dielectric material on the fourth dielectric layer, the dielectric material filling the second opening; removing a portion of the dielectric material to expose the interconnect 140, thereby forming the fourth dielectric layer.

[0281] refer to Figures 2 to 5 The manufacturing method further includes forming a bit line BL on the side of the interconnect 140 away from the device post 110 along the axial direction of the device post 110, wherein the bit line BL is electrically connected to the interconnect 140.

[0282] It should be noted that, Figure 2 and Figure 3 The first, second, and third dielectric layers are omitted; only a portion of the structure is shown for clarity.

[0283] In some embodiments of the present invention, in the step of forming a bit line BL on the side of the interconnect 140 away from the device post 110 along the axial direction of the device post 110, the bit line BL is formed on the side of the interconnect 140 away from the device post 110 along the axial direction of the device post 110 by self-alignment.

[0284] The bit line BL is formed by self-alignment, which eliminates the need for photolithography and masks. This effectively avoids the impact of photolithography alignment on yield and performance, reduces process costs and manufacturing difficulty of the bit line BL, and ensures manufacturing yield and device performance while increasing memory cell density.

[0285] In some embodiments, the step of forming a bit line on the side of the interconnect 140 away from the device post 110 along the axial direction of the device post 110 includes: forming a precursor metal layer (not shown) on the surface of the interconnect 140; and performing an annealing process to allow the precursor metal layer and the interconnect 140 to react with each other to form the bit line BL.

[0286] In summary, in the aforementioned memory cell, the gate structure surrounds the device pillar along the axial direction, and the storage capacitor is located on one side of the first end of the device pillar along the axial direction and connected to the first segment. The gate structure completely surrounds the device pillar, effectively ensuring the gate structure's control over the channel; furthermore, in the memory cell, the channel in the device pillar extends axially; in the plane perpendicular to the axial direction of the device pillar, the area of ​​the memory cell is small, effectively increasing the storage density of the memory array including the memory cell; the interconnection stage electrically connected to the second end of the device pillar provides a foundation for the subsequent bit line formation, effectively reducing the technological difficulty of bit line formation.

[0287] Furthermore, the interconnect is integrally connected to the device pillar, and the material of the bit line and the material of the interconnect are fused together at the interface; at least a portion of the bit line near the interconnect is made of metal silicide. The bit line is formed using a self-aligned process, which effectively reduces the use of photolithography, lowers the difficulty of bit line formation, and avoids the impact of overlay accuracy on performance, thus improving device manufacturing yield and device performance.

[0288] Furthermore, in the storage array, adjacent rows of storage cells are staggered along the column direction. This staggered arrangement of adjacent rows of storage cells, with the cells densely packed in a plane perpendicular to the axis of the device pillars, effectively increases the distribution density of the storage cells. This increased storage density also provides the hardware basis for an odd-even interval operating mode, maximizing storage density, minimizing wasted area, and achieving a balance between read / write speed and storage density.

[0289] Furthermore, adjacent column storage cells are connected to adjacent bit lines along the row direction; while applying a first voltage to a bit line, a second voltage is applied to adjacent bit lines, the second voltage being unequal to the first voltage. During operation, the storage device applies unequal voltages to adjacent bit lines; a bit line is applied with the first voltage for reading and writing data, while adjacent bit lines are applied with the second voltage to shield coupling capacitors. This odd-even bit line interval operating mode effectively shields the coupling between bit lines, ensuring efficient read and write operations.

[0290] Furthermore, the second voltage is the default voltage, that is, the second voltage is Vcc / 2. This solution can be implemented without making major modifications to the internal circuitry of the storage device, which can effectively reduce the difficulty of implementation.

[0291] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A storage unit, characterized in that, include: A device post having a first end and a second end opposite to each other along the axial direction of the device post; A gate structure that surrounds the device pillars circumferentially; A storage capacitor is located along the axial direction of the device post, on the side of the device post closer to the first end, and is electrically connected to the first end of the device post. An interconnecting station is located along the axial direction of the device post, on the side of the device post near the second end, and is electrically connected to the second end of the device post.

2. The storage unit as claimed in claim 1, characterized in that, The interconnecting platform is made of the same material as the device pillar.

3. The storage unit as described in claim 1 or 2, characterized in that, The interconnecting platform is integrally connected to the device pillar.

4. The storage unit as claimed in claim 1, characterized in that, The extension direction of the interconnect station is perpendicular to the extension direction of the gate structure.

5. The storage unit as claimed in claim 1, characterized in that, In a plane perpendicular to the axial direction of the device post, the dimension of the projection of the interconnect station in the direction perpendicular to the extension direction is smaller than the dimension of the projection of the device post in the same direction.

6. The storage unit as claimed in claim 1, characterized in that, In a plane perpendicular to the axial direction of the device post, the geometric center of the projection of the interconnect station does not coincide with the geometric center of the projection of the device post.

7. The storage unit as claimed in claim 6, characterized in that, One side of the interconnect station is tangent to the side of the device post.

8. The storage unit as claimed in claim 1, characterized in that, The device pillars are cylindrical, and the storage capacitors are cylindrical.

9. The storage unit as claimed in claim 1, characterized in that, The gate structure includes a gate electrode and a gate dielectric layer, wherein the gate dielectric layer is located between the gate electrode and the device pillar.

10. The storage unit as claimed in claim 9, characterized in that, Along the axial direction of the device pillar, at least one side of the gate dielectric layer extends out of the gate electrode.

11. The storage cell as claimed in claim 9, characterized in that, The gate electrode is made of either polycrystalline silicon or a metal; the gate dielectric layer is made of an oxide.

12. The storage unit as claimed in claim 1, characterized in that, The storage capacitor is located on the end face of the first end.

13. A storage array, characterized in that, include: The storage cell, as described in any one of claims 1 to 12, comprises a plurality of storage cells arranged in an array in a plane perpendicular to the axial direction of the device column.

14. The storage array as claimed in claim 13, characterized in that, The storage cells of adjacent rows are staggered along the row direction; The storage cells of adjacent columns are staggered along the column direction.

15. The storage array as described in claim 13 or 14, characterized in that, The interconnects of the storage units in the same row are connected as a whole.

16. The storage array as described in claim 13 or 14, characterized in that, In a plane perpendicular to the axial direction of the device pillar, in adjacent columns of memory cells, the geometric center of the projection of the interconnect station is offset in the opposite direction relative to the geometric center of the projection of the corresponding device pillar.

17. The storage array as described in claim 13 or 14, characterized in that, The gate electrodes of the gate structure of the memory cells in the same row are connected as a single unit.

18. The storage array as described in claim 13 or 14, characterized in that, It also includes: a bit line along the axial direction of the device post, the bit line being located on the side of the interconnect away from the device post, the bit line extending along the column direction in a plane perpendicular to the axial direction of the device post; Storage cells in the same column are connected to the same bit line.

19. The storage array as claimed in claim 18, characterized in that, In a plane perpendicular to the axial direction of the device pillar, the projection of the bit line overlaps with the projection of the interconnect.

20. The storage array as claimed in claim 18, characterized in that, The bit line is located on the surface of the interconnect station on the side away from the device post.

21. The storage array as claimed in claim 18, characterized in that, The material of the bit line and the material of the interconnect are fused together at the interface.

22. The storage array as claimed in claim 18, characterized in that, In the bit line, at least a portion of the material near the interconnect is metal silicide.

23. The storage array as claimed in claim 18, characterized in that, The storage cells of adjacent columns are interleaved with the two adjacent bit lines.

24. The storage array as described in claim 13 or 14, characterized in that, Also includes: The word line extends along the row direction in a plane perpendicular to the axial direction of the device column; Storage cells in the same row are connected to the same word line.

25. A method for controlling a storage array, characterized in that, The storage array is as described in any one of claims 13 to 24; The control method includes: applying a first voltage to a bit line while simultaneously applying a second voltage to an adjacent bit line, wherein the second voltage is not equal to the first voltage.

26. The control method as described in claim 25, characterized in that, The storage array includes a first bit line, a second bit line, ..., an nth bit line arranged sequentially, where n is the number of bit lines; The step of applying a first voltage to a bit line and simultaneously applying a second voltage to an adjacent bit line includes: applying a first voltage to the (2p-1)th bit line and simultaneously applying a second voltage to the 2pth bit line, where p is an integer greater than 0.

27. The control method as described in claim 26, characterized in that, In the step of applying a first voltage to the 2p-1 bit line and applying a second voltage to the 2p bit line, the first voltage is applied to all 2p-1 bit lines while the second voltage is applied to all 2p bit lines.

28. The control method as described in claim 26, characterized in that, The step of applying a first voltage to a bit line and applying a second voltage to an adjacent bit line further includes: applying a first voltage to the 2qth bit line and applying a second voltage to the 2q-1th bit line, where q is an integer greater than 0.

29. The control method as described in claim 28, characterized in that, In the step of applying a first voltage to the 2q-1 bit line while simultaneously applying a second voltage to the 2q-1 bit line, the first voltage is applied to all 2q-1 bit lines at the same time as the second voltage is applied to all 2q-1 bit lines.

30. The control method as described in claim 25, characterized in that, The second voltage is the default voltage.

31. A storage device, characterized in that, include: A storage array as described in any one of claims 13 to 24; A controller, which is adapted to apply a first voltage to a bit line while simultaneously applying a second voltage to an adjacent bit line, the second voltage being unequal to the first voltage.

32. The storage device as claimed in claim 31, characterized in that, The storage array includes a first bit line, a second bit line, ..., an nth bit line arranged sequentially, where n is the number of bit lines; The controller is adapted to apply a first voltage to the 2p-1 bit line while simultaneously applying a second voltage to the 2p bit line, where p is an integer greater than 0.

33. The storage device as claimed in claim 32, characterized in that, The controller applies a first voltage to all bit lines 2p-1 and a second voltage to all bit lines 2p.

34. The storage device as claimed in claim 31, characterized in that, The controller is also adapted to apply a first voltage to the 2q-1 bit line while simultaneously applying a second voltage to the 2q-1 bit line, where q is an integer greater than 0.

35. The storage device as claimed in claim 34, characterized in that, The controller applies a first voltage to all 2q-th bit lines while simultaneously applying a second voltage to all 2q-1-th bit lines.

36. The storage device as claimed in claim 31, characterized in that, The second voltage is the default voltage.

37. A method for manufacturing a storage device, characterized in that, include: A device post is formed, the device post having a first end and a second end opposite to each other along the axial direction of the device post; A gate structure is formed that surrounds the device pillars in the circumferential direction; A storage capacitor is formed on the side of the device post along the axial direction of the device post near the first end, and the storage capacitor is electrically connected to the first end; An interconnect is formed along the axial direction of the device post, the interconnect being located on the side of the device post closer to the second end, and the interconnect being electrically connected to the second end of the device post.

38. The manufacturing method as described in claim 37, characterized in that, The steps for forming device pillars include: Provide a base; The substrate is etched to form a substrate and an etching stage protruding from the front side of the substrate; The etching stage is used to form a preform stage and a device post protruding from the first surface of the preform stage.

39. The manufacturing method as described in claim 38, characterized in that, In the step of etching the substrate to form a substrate and an etching stage protruding from the front side of the substrate, there are discrete openings between adjacent etching stages; After etching the substrate to form a substrate and an etching stage protruding from the front side of the substrate, and before etching the etching stage, a dielectric material is filled into the discrete opening.

40. The manufacturing method as described in claim 37, characterized in that, In the step of forming the device pillar, the device pillar protrudes from the first surface of the preform stage, and the preform stage protrudes from the front surface of the substrate; The steps to form an interconnect station include: Remove the substrate to expose the preform stage; The preform is etched to form the interconnect.

41. The manufacturing method as described in claim 40, characterized in that, The step of removing the substrate to expose the preform stage includes: removing the substrate along the back side of the substrate to expose the second side of the preform stage, wherein the back side of the substrate is disposed opposite to the front side of the substrate, and the second side of the preform stage is disposed opposite to the first side of the preform stage; The step of etching the preform to form the interconnect includes: etching the preform through a second surface of the preform to form the interconnect.

42. The manufacturing method as described in claim 41, characterized in that, The step of etching the preform to form the interconnect includes: The prefabrication platform is thinned by reducing its second surface. A second opening penetrating the thickness is formed within the thinned preform, forming interconnecting stations adjacent in the row direction.

43. The manufacturing method as described in claim 42, characterized in that, In the step of forming a second opening through the thickness within the thinned preform, the second opening through the thickness is formed within the thinned preform by self-alignment.

44. The manufacturing method as described in claim 42, characterized in that, Prior to the step of forming a second opening through the thickness within the thinned preform, the medium material filling the discrete opening protrudes from the second surface of the thinned preform. The step of forming a second opening through the thickness within the thinned preform includes: forming a linear layer on the thinned preform and the dielectric material filling the discrete opening; The linear layer is etched to expose a portion of the thinned preform stage surface; the exposed thinned preform stage is etched to form the second opening.

45. The manufacturing method as described in claim 37, characterized in that, Also includes: A bit line is formed on the side of the interconnect station away from the device post along the axial direction of the device post, and the bit line is electrically connected to the interconnect station.

46. ​​The manufacturing method as described in claim 45, characterized in that, In the step of forming a bit line on the side of the interconnect station away from the device post along the axial direction of the device post, the bit line is formed on the side of the interconnect station away from the device post along the axial direction of the device post by self-alignment.

47. The manufacturing method as described in claim 45, characterized in that, The step of forming a bit line on the side of the interconnect station away from the device post along the axial direction of the device post includes: A precursor metal layer is formed on the surface of the interconnect station; Annealing is performed to allow the precursor metal layer and the interconnect to react with each other, forming the bit line.

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