Semiconductor structure and forming method of semiconductor structure

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a first region; forming a floating gate structure located on the first region, a control gate structure located on the floating gate structure and a control gate dielectric structure located between the control gate structure and the floating gate structure; forming a mask layer which is provided with a first opening and exposes a part of the control gate structure of the first region on the substrate; removing the control gate structure exposed by the first opening until the control gate dielectric structure is exposed, and forming a second opening in the control gate structure; forming a dielectric structure on the substrate and in the second opening; a first plug is formed in the first region and located in the dielectric structure in the second opening and the control gate dielectric structure at the bottom of the second opening, and the first plug is electrically connected with the floating gate structure; and a second plug is formed on the first region and located in the dielectric structure on the control gate structure, and the second plug is electrically connected with the control gate structure. The structure can accurately measure the capacitance of the control gate dielectric structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] For eFlash devices, the control gate (CG) capacitance is crucial to device performance, directly impacting read / write efficiency. The capacitance value depends on the choice of dielectric film, requiring an effective capacitance characterization test method. Due to the complex overall structure of eFlash devices, direct control gate dielectric capacitance testing is typically not possible; only the silicon wafer capacitance of a single film layer can be tested. This method usually fails to account for capacitance variations caused by capacitive coupling effects within the overall eFlash device, thus failing to characterize the true silicon wafer capacitance of the control gate.

[0003] Therefore, a method is needed to accurately measure the actual silicon wafer capacitance value of the control gate. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to accurately measure the actual silicon wafer capacitance value of the control gate.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region; forming a floating gate structure on the first region, a control gate structure on the floating gate structure, and a control gate dielectric structure between the control gate structure and the floating gate structure; forming a mask layer on the substrate, the mask layer having a first opening, the first opening exposing a portion of the control gate structure in the first region; removing the control gate structure exposed by the first opening until the control gate dielectric structure is exposed, forming a second opening within the control gate structure; forming a dielectric structure on the substrate and within the second opening; forming a first plug on the first region, the first plug being located within the dielectric structure on the second opening, within the dielectric structure within the second opening, and within the control gate dielectric structure at the bottom of the second opening, the first plug being electrically connected to the floating gate structure; forming a second plug on the first region, the second plug being located within the dielectric structure on the control gate structure, the second plug being electrically connected to the control gate structure.

[0006] Optionally, the substrate further includes a second region and a third region, with the two first regions located on opposite sides of the second region and the two third regions located on opposite sides of the two first regions; it also includes: forming an erase gate structure on the second region and a word line gate structure on the third region.

[0007] Optionally, it further includes: forming a protective structure on the control gate structure; the second opening being located within the protective structure and the control gate structure, and the second plug being located within the protective structure and the dielectric structure on the control gate structure.

[0008] Optionally, it further includes: forming a first sidewall structure located on the sidewall of the control grid structure and the sidewall of a portion of the floating grid structure, the first sidewall structure including a first sidewall layer and a second sidewall layer located on the surface of the first sidewall layer; forming a third sidewall layer located on the sidewall of the first sidewall structure and the sidewall of the floating grid structure; and forming a second sidewall structure located on the sidewall of the word line grid structure.

[0009] Optionally, it further includes: forming a source region located within the second region; forming a drain region located within the substrate, the drain region being adjacent to the second sidewall structure.

[0010] Optionally, the source region, drain region, and substrate are all grounded.

[0011] Optionally, the control gate dielectric structure includes: a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer, wherein the first dielectric layer and the third dielectric layer are made of the same material, and the material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer.

[0012] Optionally, the substrate further includes a test region, a device region, and a logic region, wherein the test region includes a first region, a second region, and a third region; during the formation of the semiconductor structure, the process further includes: forming a logic gate structure on the logic region; forming a floating gate structure on the device region, forming a control gate structure located on the floating gate structure, and a control gate dielectric structure located between the control gate structure and the floating gate structure, forming an erase gate structure and a word line gate structure.

[0013] Optionally, the first plug and the second plug are formed simultaneously, and the method further includes: forming a third plug located on the logic region, the third plug being located within a dielectric structure on the logic gate structure and electrically connected to the logic gate structure; and forming a fourth plug located within the dielectric structure and electrically connected to the substrate.

[0014] Optionally, the protective structure includes a first protective layer and a second protective layer located on the first protective layer, wherein the first protective layer and the second protective layer are made of different materials.

[0015] Optionally, the projection range of the control gate structure on the substrate is located within the projection range of the floating gate structure on the substrate.

[0016] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a first region; a floating gate structure located on the first region, a control gate structure located on the floating gate structure, and a control gate dielectric structure located between the control gate structure and the floating gate structure; a second opening located within the control gate structure, the second opening exposing a portion of the control gate dielectric structure; a dielectric structure located on the substrate and within the second opening; a first plug located on the first region, the first plug being located within the dielectric structure on the second opening, within the dielectric structure within the second opening, and within the control gate dielectric structure at the bottom of the second opening, the first plug being electrically connected to the floating gate structure; and a second plug located on the first region, the second plug being located within the dielectric structure on the control gate structure, the second plug being electrically connected to the control gate structure.

[0017] Optionally, the substrate further includes a second region and a third region, with the two first regions located on opposite sides of the second region and the two third regions located on opposite sides of the two first regions; it also includes an erase gate structure located on the second region and a word line gate structure located on the third region.

[0018] Optionally, it further includes: a protective structure located on the control gate structure; the second opening is located within the protective structure and the control gate structure, and the second plug is located within the protective structure and the dielectric structure on the control gate structure.

[0019] Optionally, it also includes: a first sidewall structure located on the sidewall of the control grid structure and the sidewall of the partial floating grid structure, the first sidewall structure including a first sidewall layer and a second sidewall layer located on the surface of the first sidewall layer; forming a third sidewall layer located on the sidewall of the first sidewall structure and the sidewall of the floating grid structure; and a second sidewall structure located on the sidewall of the word line grid structure.

[0020] Optionally, it also includes: a source region located in the second region and a drain region located in the substrate, the drain region being adjacent to the second sidewall structure.

[0021] Optionally, the source region, drain region, and substrate are all grounded.

[0022] Optionally, the control gate dielectric structure includes: a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer, wherein the first dielectric layer and the third dielectric layer are made of the same material, and the material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer.

[0023] Optionally, the materials of the first and third dielectric layers include silicon oxide; the material of the second dielectric layer includes silicon nitride.

[0024] Optionally, the substrate further includes a test area, a device area, and a logic area, wherein the test area includes a first area, a second area, and a third area; and further includes: a logic gate structure located on the logic area; a floating gate structure located on the device area, a control gate structure located on the floating gate structure, and a control gate dielectric structure, an erase gate structure, and a word line gate structure located between the control gate structure and the floating gate structure.

[0025] Optionally, it further includes: a third plug located on the logic region, the third plug being located within a dielectric structure on the logic gate structure and electrically connected to the logic gate structure; and a fourth plug located within the dielectric structure and electrically connected to the substrate.

[0026] Optionally, the protective structure includes a first protective layer and a second protective layer located on the first protective layer, wherein the first protective layer and the second protective layer are made of different materials.

[0027] Optionally, the material of the first protective layer includes silicon oxide, and the material of the second protective layer includes silicon nitride.

[0028] Optionally, the dielectric structure includes: a transition layer and a dielectric layer located on the transition layer, wherein the material of the dielectric layer is different from the material of the transition layer, and the thickness of the dielectric layer is greater than the thickness of the transition layer.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] The method of forming the present invention involves removing the control gate structure exposed by the first opening, forming a second opening within the control gate structure, forming a dielectric structure on the substrate within the second opening, forming a first plug electrically connected to a floating gate structure at the bottom of the second opening within the dielectric structure of the second opening, and forming a second plug electrically connected to the control gate structure within the dielectric structure outside the second opening. The control gate structure and the floating gate structure serve as electrode plates of the capacitor structure, enabling precise measurement of the capacitance value of the control gate dielectric structure and improving the controllability of the product.

[0031] Furthermore, the substrate also includes a test region, a device region, and a logic region. The test region includes a first region, a second region, and a third region. During the formation of the test structure, a logic gate structure is also formed on the logic region. On the device region, a floating gate structure, a control gate structure located on the floating gate structure, a control gate dielectric structure located between the control gate structure and the floating gate structure, an erase gate structure, and a word line gate structure are formed. The process for forming the test structure is compatible with the manufacturing process, and the performance of the semiconductor structure in the device region can be obtained online through the test structure.

[0032] In the structure of this invention, the first plug is located within the dielectric structure of the second opening and is electrically connected to the floating gate structure at the bottom of the second opening. The second plug is located within the dielectric structure outside the second opening and is electrically connected to the control gate structure. The control gate structure and the floating gate structure serve as electrode plates of the capacitor structure, which can accurately measure the capacitance value of the control gate dielectric structure and improve the controllability of the product. Attached Figure Description

[0033] Figures 1 to 9 This is a schematic diagram of the method for forming a semiconductor structure in an embodiment of the present invention. Detailed Implementation

[0034] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figures 1 to 9 This is a schematic diagram of the method for forming a semiconductor structure in an embodiment of the present invention.

[0036] Please refer to Figures 1 to 3 , Figure 2 for Figure 1 A schematic diagram of the structure along section line AA1. Figure 3 This is a schematic diagram of the structure on the logic area. Figure 3 View direction and Figure 2 With the same viewing direction, a substrate 100 is provided, the substrate 100 including a first region I.

[0037] The substrate 100 further includes a second region II and a third region III, with two first regions I located on either side of the second region II, and two third regions III located on either side of the two first regions I, with the first region I located between the second region II and the third region III.

[0038] In this embodiment, the first region I, the second region II, and the third region III are arranged along a first direction X parallel to the surface of the substrate 100.

[0039] In this embodiment, the substrate 100 further includes a test region, a device region, and a logic region L. The test region includes a first region I, a second region II, and a third region III, and the semiconductor structure is located in the test region.

[0040] The test area is used to form a test structure, the device area is used to form an EFLASH memory device, and the logic area L is used to form a logic device.

[0041] In this embodiment, the substrate 100 is made of silicon.

[0042] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0043] In this embodiment, source region 122 is formed in the second region II.

[0044] Please continue to refer to this. Figure 1 and Figure 2 A floating gate structure located on the first region I, a control gate structure 106 located on the floating gate structure, and a control gate medium structure located between the control gate structure 106 and the floating gate structure are formed.

[0045] Figure 2 The floating gate structure, control gate dielectric structure, and control gate structure are parallel to the second direction Y, which is parallel to the surface of the substrate 100 and perpendicular to the first direction X.

[0046] In this embodiment, it further includes: forming a protective structure on the control gate structure 106; and forming an erase gate dielectric layer 115 on the surface of the second region II.

[0047] The protective structure includes a first protective layer 107 and a second protective layer 108 located on the first protective layer 107, wherein the first protective layer 107 and the second protective layer 108 are made of different materials.

[0048] In this embodiment, the material of the first protective layer 107 includes silicon oxide; the material of the second protective layer 108 includes silicon nitride.

[0049] In this embodiment, the projection range of the control gate structure 106 on the substrate 200 is located within the projection range of the floating gate structure on the substrate 200.

[0050] Please refer to Figure 2 The control gate dielectric structure includes: a first dielectric layer 103, a second dielectric layer 104 located on the first dielectric layer 103, and a third dielectric layer 105 located on the second dielectric layer 104. The first dielectric layer 103 and the third dielectric layer 105 are made of the same material, and the material of the second dielectric layer 104 is different from the materials of the first dielectric layer 103 and the third dielectric layer 105.

[0051] The floating gate structure includes a floating gate dielectric layer 101 and a floating gate layer 102 located on the floating gate dielectric layer 101.

[0052] In this embodiment, the floating gate dielectric layer 101 and the erase gate dielectric layer 115 are formed simultaneously.

[0053] The floating gate dielectric layer 101 and the erase gate dielectric layer 115 are made of silicon oxide; the floating gate layer 102 is made of polysilicon; and the control gate structure 106 is made of polysilicon.

[0054] In this embodiment, the first dielectric layer 103 and the third dielectric layer 105 are made of silicon oxide; the second dielectric layer 104 is made of silicon nitride.

[0055] The method for forming the control gate structure, floating gate structure, first sidewall structure, third sidewall layer 111, erase gate dielectric layer 115, and protective structure includes: forming a gate dielectric material layer (not shown) on the surface of a substrate 200; forming a gate material layer (not shown) on the gate dielectric material layer; forming a control gate dielectric material layer (not shown) on the gate material layer; forming a protective structure material layer (not shown) on the control gate dielectric material layer; forming a patterned mask layer (not shown) on the protective structure material layer; etching the protective structure material layer, control gate dielectric material layer, gate material layer, and gate dielectric material layer using the patterned mask layer as a mask to form an initial protective structure, an initial control gate structure, an initial control gate dielectric structure, an initial floating gate structure, and an erase gate dielectric layer 115; forming a mask structure on the initial protective structure; and etching the initial protective structure, initial control gate structure, initial control gate dielectric structure, and part of the initial floating gate structure using the mask structure as a mask to form a floating gate structure, a control gate dielectric structure, a control gate structure 106, and a protective structure.

[0056] In this embodiment, the process for forming the gate dielectric material layer includes a thermal oxidation process.

[0057] The second region II has a source region 122 containing doped ions. The erase gate dielectric layer 155 formed by the thermal oxidation process is relatively thick, and part of the erase gate dielectric layer 115 is located within the substrate 200.

[0058] Please continue to refer to this. Figure 1 A first sidewall structure is formed on the sidewall of the control grid structure 106 and part of the sidewall of the floating grid structure. The first sidewall structure includes a first sidewall layer 109 and a second sidewall layer 110 located on the surface of the first sidewall layer 109. A third sidewall layer 111 is formed on the sidewall of the first sidewall structure and the sidewall of the floating grid structure.

[0059] The first sidewall layer 109 and the third sidewall layer 111 are made of the same material, while the second sidewall layer 110 is made of a different material than the first sidewall layer 109 and the third sidewall layer 111.

[0060] In this embodiment, the first sidewall layer 109 and the third sidewall layer 111 are made of silicon oxide; the second sidewall layer 110 is made of silicon nitride.

[0061] Please continue to refer to this. Figure 1 This forms an erase grid structure located in the second zone II and a word line grid structure located in the third zone III; and forms a second sidewall structure located on the sidewall of the word line grid structure.

[0062] The erase gate structure includes an erase gate dielectric layer 115 and an erase gate 116 located on the erase gate dielectric layer 115; the word line gate structure includes a word line gate dielectric layer 117 and a word line gate 118 located on the word line gate dielectric layer 117.

[0063] The material of the word line gate dielectric layer 117 includes silicon oxide.

[0064] The erase gate 116 and the word line gate 118 are formed simultaneously, and the material of the erase gate 116 and the word line gate 118 includes polysilicon.

[0065] The second sidewall structure includes: a fourth sidewall layer 119 located on the sidewall of the character grid structure, a fifth sidewall layer 120 located on the sidewall of the fourth sidewall layer 119, and a sixth sidewall layer 121 located on the sidewall of the fifth sidewall layer 120. The fourth sidewall layer 119 and the sixth sidewall layer 121 are made of the same material, while the fifth sidewall layer 120 is made of a different material than the fourth sidewall layer 119 and the sixth sidewall layer 121.

[0066] In this embodiment, the materials of the fourth sidewall layer 119 and the sixth sidewall layer 121 include silicon oxide; the material of the fifth sidewall layer 120 includes silicon nitride.

[0067] Please continue to refer to this. Figure 1 A drain region 123 is formed within the substrate 200, the drain region 123 being adjacent to the second sidewall structure.

[0068] The process for forming the drain region 123 includes an ion implantation process.

[0069] In this embodiment, the source region 122, drain region 123, and substrate 200 located in the test area are all grounded. No voltage needs to be applied to the source region 122, drain region 123, and substrate 200 to facilitate subsequent measurement of the control gate dielectric structure capacitance.

[0070] In other embodiments, the source region, drain region, and substrate located in the test area may not be grounded together.

[0071] Please refer to Figure 3 In formation Figure 1 and Figure 2The process of constructing the semiconductor structure also includes: forming a logic gate on the logic region L; forming a floating gate structure on the device region, forming a control gate structure on the floating gate structure, and a control gate dielectric structure between the control gate structure and the floating gate structure; forming an erase gate structure and a word line gate structure.

[0072] The logic gate structure includes a logic gate dielectric layer 201 and a logic gate 202 located on the logic gate dielectric layer 201. The logic gate structure is formed synchronously with the word line gate structure.

[0073] The structure on the device region and Figure 1 and Figure 2 The structure on the test area is formed synchronously.

[0074] Please refer to Figures 4 to 6 , Figure 4 for Figure 5 and Figure 6 Top view, Figure 5 for Figure 4 A schematic diagram of the structure along section line BB1. Figure 6 for Figure 4 A schematic diagram along the cross-sectional line AA1 shows a mask layer 130 formed on a substrate 200. The mask layer 130 has a first opening 131 that exposes a portion of the control gate structure in the first region I.

[0075] In this embodiment, the first opening 131 is parallel to the first direction X, and the first opening 131 exposes part of the top surface of the protective structure on the control gate structure.

[0076] Please refer to Figure 7 , Figure 7 In order to be in Figure 6 Based on the schematic diagram, using the mask layer 130 as a mask, the control gate structure exposed by the first opening 131 is removed until the control gate dielectric structure is exposed, and a second opening 132 is formed within the control gate structure.

[0077] In this embodiment, the process of removing the control gate structure exposed by the first opening 131 includes a dry etching process.

[0078] The second opening 132 is located within the protective structure and the control gate structure. In this embodiment, the bottom of the second opening 132 exposes the surface of the control gate dielectric structure, or a portion of the bottom of the second opening 132 is located within the control gate dielectric structure.

[0079] In this embodiment, the material of the mask layer 130 includes photoresist.

[0080] Please refer to Figure 8 and Figure 9 , Figure 8 In order to be in Figure 7 A basic diagram. Figure 9 In order to be in Figure 3 The schematic diagram shows a dielectric structure formed on the substrate 100 within the second opening 132.

[0081] Before forming the dielectric structure, the process of removing the mask layer 130 includes a wet etching process.

[0082] The dielectric structure includes a transition layer 133 and a dielectric layer 134 located on the transition layer 133. The material of the dielectric layer 134 is different from that of the transition layer 133, and the thickness of the dielectric layer 134 is greater than that of the transition layer 133.

[0083] In this embodiment, the dielectric layer 134 is made of silicon oxide; the transition layer 133 is made of silicon nitride.

[0084] In this embodiment, the dielectric structure is located on the surfaces of the test area, device area, and logic area L, and the dielectric structure is also located on the surface of the substrate 100 in the blank area.

[0085] Please continue to refer to this. Figure 8 A first plug 141 is formed on the first region I. The first plug 141 is located within the dielectric structure on the second opening 132, within the dielectric structure inside the second opening 132, and within the control gate dielectric structure at the bottom of the second opening 132. The first plug 141 is electrically connected to the floating gate structure. A second plug 142 is formed on the first region I. The second plug 142 is located within the dielectric structure on the control gate structure 106. The second plug 142 is electrically connected to the control gate structure 106.

[0086] In this embodiment, the second plug 142 is located within the protective structure and dielectric structure of the control gate structure outside the second opening 132.

[0087] Please continue to refer to this. Figure 9 A third plug 143 is formed on the logic region L. The third plug 143 is located within the dielectric structure on the logic gate structure and is electrically connected to the logic gate structure.

[0088] In this embodiment, the method further includes forming a fourth plug located within the dielectric structure, the fourth plug being electrically connected to the substrate 100. The fourth plug is located on the substrate 100 in a blank area.

[0089] In this embodiment, the first plug 141, the second plug 142, the third plug 143, and the fourth plug are formed simultaneously.

[0090] The method for forming the first plug 141, the second plug 142, the third plug 143, and the fourth plug includes: forming a patterned layer (not shown) on the dielectric structure; etching the dielectric structure on the second opening, the dielectric structure within the second opening 132, and the control gate dielectric structure at the bottom of the second opening using the patterned layer as a mask, until the floating gate structure is exposed, forming the third opening; etching the dielectric structure on the control gate structure 106 of the first region I using the patterned layer as a mask, until the control gate structure 106 is exposed, forming the fourth opening; etching the dielectric structure on the logic region L using the patterned layer as a mask. The dielectric structure on the substrate 100 is etched using the patterned layer as a mask until the logic gate structure is exposed, forming a fifth opening; the dielectric structure on the substrate 100 is etched using the patterned layer as a mask until the surface of the substrate 100 with a blank area is exposed, forming a sixth opening; a plug material layer (not shown) is formed in the third opening, the fourth opening, the fifth opening, the sixth opening, and on the surface of the dielectric structure; the plug material layer is planarized until the surface of the dielectric structure is exposed, forming a first plug 141 in the third opening, a second plug 142 in the fourth opening, a third plug 143 in the fifth opening, and a fourth plug in the sixth opening.

[0091] The material of the plug material layer includes a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0092] The first plug 141 is located within the dielectric structure on the second opening 132, within the dielectric structure inside the second opening 132, and within the control gate dielectric structure at the bottom of the second opening 132. The first plug 141 is electrically connected to the floating gate structure. The second plug 142 is located within the dielectric structure on the control gate structure 106, and the second plug 142 is electrically connected to the control gate structure 106. Therefore, the floating gate layer 102, the control gate dielectric structure, and the control gate structure 106 constitute a capacitor structure. The floating gate layer 102 and the control gate structure 106 serve as two electrode plates of the capacitor structure, respectively. By energizing the first plug 141 and the second plug 142, the capacitance value of the control gate dielectric structure can be measured. By testing the test results on the test area, the capacitance value of the control gate dielectric structure of the device structure in the device area can be obtained, improving the controllability of the product without affecting production efficiency and production process.

[0093] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figures 1 to 9 The semiconductor structure includes:

[0094] Substrate 100, the substrate 100 including a first region I;

[0095] A floating gate structure located on the first region I, a control gate structure 106 located on the floating gate structure, and a control gate dielectric structure located between the control gate structure 106 and the floating gate structure;

[0096] A second opening is located within the control gate structure 106, the second opening exposing a portion of the control gate dielectric structure;

[0097] Dielectric structure located on substrate 100 within the second opening;

[0098] A first plug 141 is located on the first region I. The first plug 141 is located in the dielectric structure on the second opening, in the dielectric structure inside the second opening, and in the control gate dielectric structure at the bottom of the second opening. The first plug 141 is electrically connected to the floating gate structure.

[0099] The second plug 142 is located in the first region I and is located within the dielectric structure on the control gate structure 106. The second plug 142 is electrically connected to the control gate structure 106.

[0100] In this embodiment, the substrate 100 further includes a second region II and a third region III, with the two first regions I located on both sides of the second region II and the two third regions III located on one side of the two first regions I; it also includes an erase gate structure located on the second region II and a word line gate structure located on the third region III.

[0101] In this embodiment, it further includes: a protective structure located on the control gate structure 106; the second opening is located within the protective structure and the control gate structure 106, and the second plug 142 is located within the protective structure and the dielectric structure on the control gate structure 106.

[0102] In this embodiment, it further includes: a first sidewall structure located on the sidewall of the control grid structure 106 and the sidewall of a portion of the floating grid structure, the first sidewall structure including a first sidewall layer 109 and a second sidewall layer 110 located on the surface of the first sidewall layer 109; a third sidewall layer 111 formed on the sidewall of the first sidewall structure and the sidewall of the floating grid structure; and a second sidewall structure located on the sidewall of the word line grid structure.

[0103] In this embodiment, it also includes: a source region 122 located in the second region II and a drain region 123 located in the substrate 100, wherein the drain region 123 is adjacent to the second sidewall structure.

[0104] In this embodiment, the source region 122, the drain region 123, and the substrate 100 are all grounded.

[0105] In this embodiment, the control gate dielectric structure includes: a first dielectric layer 103, a second dielectric layer 104 located on the first dielectric layer 103, and a third dielectric layer 105 located on the second dielectric layer 104. The first dielectric layer 103 and the third dielectric layer 105 are made of the same material, and the material of the second dielectric layer 104 is different from the materials of the first dielectric layer 103 and the third dielectric layer 105.

[0106] In this embodiment, the first dielectric layer 103 and the third dielectric layer 105 are made of silicon oxide; the second dielectric layer 104 is made of silicon nitride.

[0107] In this embodiment, the substrate 100 further includes a test region, a device region, and a logic region L. The test region includes a first region I, a second region II, and a third region III. It also includes: a logic gate structure located on the logic region L; a floating gate structure located on the device region; a control gate structure located on the floating gate structure; and a control gate dielectric structure, an erase gate structure, and a word line gate structure located between the control gate structure and the floating gate structure.

[0108] In this embodiment, it further includes: a third plug 143 located on the logic region L, the third plug 143 being located within the dielectric structure on the logic gate structure, the third plug 143 being electrically connected to the logic gate structure; and a fourth plug located within the dielectric structure, the fourth plug being electrically connected to the substrate 100.

[0109] In this embodiment, the protective structure includes a first protective layer 107 and a second protective layer 108 located on the first protective layer 107, wherein the first protective layer 107 and the second protective layer 108 are made of different materials.

[0110] In this embodiment, the material of the first protective layer 107 includes silicon oxide, and the material of the second protective layer 108 includes silicon nitride.

[0111] In this embodiment, the dielectric structure includes a transition layer 133 and a dielectric layer 134 located on the transition layer 133. The material of the dielectric layer 134 is different from that of the transition layer 133, and the thickness of the dielectric layer 134 is greater than that of the transition layer 133.

[0112] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region; A floating gate structure located on the first region, a control gate structure located on the floating gate structure, and a control gate dielectric structure located between the control gate structure and the floating gate structure are formed. A mask layer is formed on a substrate, the mask layer having a first opening that exposes a portion of the control gate structure in the first region; Remove the control gate structure exposed by the first opening until the control gate dielectric structure is exposed, and form a second opening within the control gate structure; A dielectric structure is formed on the substrate within the second opening; A first plug is formed on the first region. The first plug is located in the dielectric structure on the second opening, in the dielectric structure inside the second opening, and in the control gate dielectric structure at the bottom of the second opening. The first plug is electrically connected to the floating gate structure. A second plug is formed on the first region. The second plug is located within the dielectric structure on the control gate structure and is electrically connected to the control gate structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes a second region and a third region, with the two first regions located on opposite sides of the second region and the two third regions located on opposite sides of the two first regions; it also includes: forming an erase gate structure on the second region and a word line gate structure on the third region.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, Also includes: A protective structure is formed on the control gate structure; the second opening is located within the protective structure and the control gate structure, and the second plug is located within the protective structure and the dielectric structure on the control gate structure.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, Also includes: A first sidewall structure is formed on the sidewall of the control grid structure and part of the sidewall of the floating grid structure. The first sidewall structure includes a first sidewall layer and a second sidewall layer located on the surface of the first sidewall layer. A third sidewall layer is formed on the sidewall of the first sidewall structure and the sidewall of the floating grid structure; a second sidewall structure is formed on the sidewall of the character grid structure.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, Also includes: A source region is formed within the second region; a drain region is formed within the substrate, the drain region being adjacent to the second sidewall structure.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The source region, drain region, and substrate are all grounded.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The control gate dielectric structure includes: a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer. The first dielectric layer and the third dielectric layer are made of the same material, and the material of the second dielectric layer is different from that of the first dielectric layer and the third dielectric layer.

8. The method for forming a semiconductor structure as described in claim 2, characterized in that, The substrate further includes a test region, a device region, and a logic region. The test region includes a first region, a second region, and a third region. In the process of forming the semiconductor structure, the process also includes: forming a logic gate structure on the logic region; forming a floating gate structure on the device region, forming a control gate structure on the floating gate structure, and a control gate dielectric structure between the control gate structure and the floating gate structure; forming an erase gate structure and a word line gate structure.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The first plug and the second plug are formed simultaneously, and the method further includes: forming a third plug located on the logic region, the third plug being located within a dielectric structure on the logic gate structure and electrically connected to the logic gate structure; and forming a fourth plug located within the dielectric structure and electrically connected to the substrate.

10. The method for forming a semiconductor structure as described in claim 3, characterized in that, The protective structure includes a first protective layer and a second protective layer located on the first protective layer, wherein the first and second protective layers are made of different materials.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The projection range of the control gate structure on the substrate is within the projection range of the floating gate structure on the substrate.

12. A semiconductor structure, characterized in that, include: Substrate, the substrate including a first region; The floating gate structure located on the first region, the control gate structure located on the floating gate structure, and the control gate dielectric structure located between the control gate structure and the floating gate structure; A second opening located within the control gate structure, the second opening exposing a portion of the control gate dielectric structure; A dielectric structure located on the substrate, within the second opening; A first plug is located on the first region. The first plug is located in the dielectric structure on the second opening, in the dielectric structure inside the second opening, and in the control gate dielectric structure at the bottom of the second opening. The first plug is electrically connected to the floating gate structure. A second plug is located on the first region, the second plug is located within the dielectric structure on the control gate structure, and the second plug is electrically connected to the control gate structure.

13. The semiconductor structure as described in claim 12, characterized in that, The substrate further includes a second region and a third region, with the two first regions located on opposite sides of the second region and the two third regions located on opposite sides of the two first regions; it also includes an erase gate structure located on the second region and a word line gate structure located on the third region.

14. The semiconductor structure as described in claim 13, characterized in that, Also includes: A protective structure located on the control gate structure; the second opening is located within the protective structure and the control gate structure, and the second plug is located within the protective structure and the dielectric structure on the control gate structure.

15. The semiconductor structure as described in claim 13, characterized in that, Also includes: A first sidewall structure located on the sidewall of the control grid structure and part of the sidewall of the floating grid structure, the first sidewall structure including a first sidewall layer and a second sidewall layer located on the surface of the first sidewall layer; A third sidewall layer is formed on the sidewall of the first sidewall structure and the sidewall of the floating grid structure; The second sidewall structure located on the sidewall of the character line grid structure.

16. The semiconductor structure as claimed in claim 15, characterized in that, Also includes: The source region is located in the second region, and the drain region is located in the substrate, the drain region being adjacent to the second sidewall structure.

17. The semiconductor structure as claimed in claim 16, characterized in that, The source region, drain region, and substrate are all grounded.

18. The semiconductor structure as claimed in claim 12, characterized in that, The control gate dielectric structure includes: a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer. The first dielectric layer and the third dielectric layer are made of the same material, and the material of the second dielectric layer is different from that of the first dielectric layer and the third dielectric layer.

19. The semiconductor structure as claimed in claim 18, characterized in that, The first and third dielectric layers are made of silicon oxide; the second dielectric layer is made of silicon nitride.

20. The semiconductor structure as claimed in claim 13, characterized in that, The substrate further includes a test area, a device area, and a logic area. The test area includes a first area, a second area, and a third area. It also includes: a logic gate structure located on the logic area; a floating gate structure located on the device area; a control gate structure located on the floating gate structure; and a control gate dielectric structure, an erase gate structure, and a word line gate structure located between the control gate structure and the floating gate structure.

21. The semiconductor structure as claimed in claim 20, characterized in that, Also includes: A third plug located on the logic region, the third plug being located within the dielectric structure on the logic gate structure, and the third plug being electrically connected to the logic gate structure; A fourth plug is located within the dielectric structure and is electrically connected to the substrate.

22. The semiconductor structure as described in claim 14, characterized in that, The protective structure includes a first protective layer and a second protective layer located on the first protective layer, wherein the first and second protective layers are made of different materials.

23. The semiconductor structure as described in claim 22, characterized in that, The first protective layer is made of silicon oxide, and the second protective layer is made of silicon nitride.

24. The semiconductor structure as claimed in claim 12, characterized in that, The dielectric structure includes a transition layer and a dielectric layer located on the transition layer, wherein the material of the dielectric layer is different from that of the transition layer, and the thickness of the dielectric layer is greater than that of the transition layer.

Images