Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device. The semiconductor device comprises a substrate; the transistor is positioned on the substrate; the dielectric layer is positioned on the substrate and covers the transistor; a metal compound layer on the dielectric layer; the first electrode layer covers the metal compound layer, and the capacitor dielectric layer and the second electrode layer are located on the first electrode layer. According to the semiconductor device, the metal compound layer is formed below the first electrode layer, so that the first electrode layer can obtain tensile stress, the first electrode layer is favorable for forming a required crystal phase, the polarization intensity in a unit area of the semiconductor device is improved, and the performance of a corresponding product is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] Ferroelectric RAM (FRAM) is a new type of memory that combines the non-volatility of ROM with the non-volatility of RAM, as well as the advantages of high durability, high-speed read and write, and low power consumption, and is widely used in various fields.

[0003] The core of ferroelectric memory is the ferroelectric capacitor (Fe-cap). Typically, the ferroelectric capacitor in ferroelectric memory adopts a MIM (metal / insulator / metal) structure. This structure consists of two layers: the electrodes and the thin ferroelectric film material in between. Currently, the MIM structure of ferroelectric capacitors results in low polarization intensity per unit area, leading to poor performance in ferroelectric products. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, the present invention provides a semiconductor device, comprising:

[0006] Substrate;

[0007] Transistors located on the substrate;

[0008] The first dielectric layer is located on the substrate and covers the transistor;

[0009] A metal compound layer located on the first dielectric layer;

[0010] A first electrode layer covering the metal compound layer, and a capacitor dielectric layer and a second electrode layer located on the first electrode layer.

[0011] For example, the metal compound layer includes titanium nitride or aluminum oxide, and the capacitor dielectric layer includes a ferroelectric material.

[0012] For example, the first electrode layer covers the upper surface and sidewalls of the metal compound layer.

[0013] For example, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked together, wherein the first dielectric layer covers the transistor, a first conductive plug electrically connected to the source of the transistor is formed in the first dielectric layer, a first conductive layer electrically connected to the first conductive plug is formed on the first dielectric layer, the second dielectric layer covers the first dielectric layer and the first conductive layer, a second conductive plug electrically connected to the first conductive layer is formed in the second dielectric layer, and the metal compound layer covers the top surface of the second conductive plug.

[0014] On the other hand, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0015] A substrate is provided on which transistors are formed;

[0016] A dielectric layer is formed covering the transistor;

[0017] A patterned metal compound layer is formed on the dielectric layer;

[0018] A first electrode layer, a capacitor dielectric layer, and a second electrode layer are formed on the metal compound layer, covering the metal compound layer.

[0019] For example, forming a first electrode layer, a capacitor dielectric layer, and a second electrode layer covering the metal compound layer on the metal compound layer includes: sequentially forming a first electrode material layer, a capacitor dielectric material layer, and a second electrode material layer covering the metal compound layer on the dielectric layer using an atomic layer deposition process; and patterning away portions of the first electrode material layer, the capacitor dielectric layer, and the second electrode material layer located on the dielectric layer to form a first electrode layer, a capacitor dielectric layer, and a second electrode layer covering the metal compound layer and the sidewalls of the metal compound layer.

[0020] For example, the metal compound layer includes titanium nitride or aluminum oxide, and the capacitor dielectric layer includes a ferroelectric material.

[0021] For example, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked together, wherein the first dielectric layer covers the transistor, a first conductive plug electrically connected to the source of the transistor is formed in the first dielectric layer, a first conductive layer electrically connected to the first conductive plug is formed on the first dielectric layer, the second dielectric layer covers the first dielectric layer and the first conductive layer, a second conductive plug electrically connected to the first conductive layer is formed in the second dielectric layer, and the metal compound layer covers the top surface of the second conductive plug.

[0022] For example, forming a patterned metal compound layer on the dielectric layer includes forming a metal compound material layer on the dielectric layer and patterning the metal compound material layer using a mask for forming a first electrode layer.

[0023] In another aspect, the present invention provides an electronic device including the aforementioned semiconductor device.

[0024] The semiconductor device and its manufacturing method, and electronic device of the present invention, by forming a metal compound layer under the first electrode layer, can make the first electrode layer obtain tensile stress, thereby making the first electrode layer more conducive to forming the desired crystal phase, thereby improving the polarization intensity per unit area of ​​the semiconductor device and improving the performance of the corresponding product. Attached Figure Description

[0025] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0026] In the attached image:

[0027] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an illustrative embodiment of the present invention is shown.

[0028] Figure 2A-2G A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of the present invention is shown, showing the device obtained by sequentially performing the manufacturing method.

[0029] Figure 2H A cross-sectional schematic diagram of a semiconductor device obtained by a method for manufacturing a semiconductor device according to another illustrative embodiment of the present invention is shown.

[0030] Figure 3 A circuit netlist diagram of a 1T1C cell structure according to an illustrative embodiment of the present invention is shown. Detailed Implementation

[0031] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an ideal or overly formal sense, unless expressly defined herein.

[0037] To fully understand this invention, detailed steps and structures will be set forth in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0038] In related technologies, the MIM structure used in ferroelectric capacitors consists of two metal layers forming the capacitor electrodes, with a ferroelectric thin film material in the middle. Because the upper and lower electrodes are two metal layers, the polarization intensity per unit area of ​​the capacitor is not high, which leads to low performance of ferroelectric products.

[0039] Therefore, in view of the aforementioned technical problems, the present invention proposes a method for manufacturing a semiconductor device, such as... Figure 1 As shown, it includes the following steps:

[0040] Step S110: Provide a substrate on which transistors are formed;

[0041] Step S120: Form a dielectric layer covering the transistor;

[0042] Step S130: Form a patterned metal compound layer on the dielectric layer;

[0043] Step S140: Form a first electrode layer, a capacitor dielectric layer, and a second electrode layer on the metal compound layer, covering the metal compound layer.

[0044] According to the semiconductor device manufacturing method provided by the present invention, before forming the first electrode layer, a patterned metal compound layer is first formed on the dielectric layer. The first electrode layer is subjected to tensile stress through the metal compound layer, thereby making the first electrode layer conducive to forming the desired crystal phase and greatly improving the polarization intensity per unit area and the performance of the product.

[0045] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0046] Example 1

[0047] Below, for reference Figures 2A to 2G The method for manufacturing the semiconductor device of the present invention will be described in detail, wherein, Figures 2A to 2G A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0048] For example, the method for manufacturing the semiconductor device of the present invention includes the following steps:

[0049] First, execute step S110 to obtain the following: Figure 2A The structure shown. A substrate 200 is provided, on which transistors 210 are formed.

[0050] Exemplarily, the substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate, and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can also be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz, or a glass substrate. The substrate also includes a shallow trench isolation structure (not shown).

[0051] For example, the transistor may be a selective switching transistor, and forming the transistor 210 on the substrate may include the following steps:

[0052] A gate dielectric layer (not shown) is formed on the upper surface of the substrate 200. Specifically, the gate dielectric layer can be formed by thermal oxidation, physical vapor deposition, or chemical vapor deposition. The gate dielectric layer includes, but is not limited to, a silicon oxide layer.

[0053] A gate material layer is formed on the upper surface of the gate dielectric layer. Specifically, the gate material layer can be formed by physical vapor deposition or chemical vapor deposition. The gate material layer includes, but is not limited to, a doped polysilicon layer or a metal layer.

[0054] The gate material layer and the gate dielectric layer are etched to form the gate 211; sidewalls may also be formed on both sides of the gate 211. Specifically, the sidewalls may be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition, etc. The sidewalls include, but are not limited to, silicon oxide layer, silicon nitride layer or ONO structure (i.e., stacked structure of silicon oxide layer, silicon nitride layer and silicon oxide layer); the gate is subsequently used as a word line.

[0055] Ion implantation is performed on the substrate 200 based on the gate 211 and the sidewall to form a source 212 and a drain 213 on both sides of the gate 211 and the sidewall, respectively.

[0056] In one example, after forming the source 212 and drain 213, a step of forming a metal silicide (not shown) on the upper surfaces of the source 212 and drain 213 may also be included. By forming a metal silicide on the upper surfaces of the source 212 and drain 213, the contact resistance between the source 212 and drain 213 and the conductive plugs from which they are led out can be reduced.

[0057] Next, proceed to step 120, as follows: Figure 2B As shown, a dielectric layer is formed covering the transistor. Exemplarily, as... Figure 2G As shown, the dielectric layer includes a first dielectric layer 201. First, a first dielectric layer 201 covering the transistor is formed. Exemplarily, various deposition methods commonly used in the art can be employed to form the first dielectric layer 201, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the first dielectric layer 201 can be an insulating material such as silicon dioxide, fluorocarbon, carbon-doped silicon oxide, or silicon carbonitride; this application is not limited in this regard. Exemplarily, after forming the first dielectric layer 201, the method further includes planarizing the first dielectric layer 201. Exemplarily, non-limiting examples of this planarization method include mechanical planarization and chemical mechanical polishing planarization. Exemplarily, before planarization, the thickness of the first dielectric layer 201 ranges from 6000 angstroms to 7000 angstroms; after planarization, the thickness of the first dielectric layer 201 ranges from 3000 angstroms to 3500 angstroms. The second dielectric layer 207 subsequently formed on the first dielectric layer 201 can be deposited and planarized using the same method.

[0058] Then as Figure 2C , Figure 2G As shown, conductive plugs communicating with the source and drain can be formed in the dielectric layer. Exemplarily, the first dielectric layer 201 is etched to form a first interconnect via penetrating the first dielectric layer 201. Exemplarily, the first interconnect via is formed using a dry etching process or the like. The first interconnect via is filled to form a first conductive plug 204. Exemplarily, the first conductive plug 204 is formed using an electroplating process or the like. The material of the first conductive plug 204 includes, but is not limited to, tungsten or copper. This allows the bottom of the first conductive plug 204 to be electrically connected to the source 212 (or the metal silicide on the source surface) of the transistor 210. A third conductive plug 205 is formed using the same method, so that the bottom of the third conductive plug 205 is electrically connected to the drain 213 (or the metal silicide on the drain surface) of the transistor 210.

[0059] Next, step 130 is performed to form a patterned metal compound layer on the dielectric layer. For example, as shown... Figure 2D , 2G As shown, a patterned metal compound layer 203 is formed on the first dielectric layer 201, and the patterned metal compound layer 203 is electrically connected to a first conductive plug 204 located in the first dielectric layer 201.

[0060] Exemplarily, various deposition methods commonly used in the art can be employed to form the metal compound material layer, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Subsequently, a patterned mask layer, such as a photoresist layer, is formed on the metal compound material layer. Then, an etching process is used to remove the portion of the metal compound material layer not covered by the mask layer. Exemplarily, dry etching, including but not limited to reactive ion etching (RIE), ion beam etching, and plasma etching, can be used in this step to remove the portion of the metal compound material layer not covered by the mask layer, thereby forming the final patterned metal compound layer 203. The metal compound material layer comprises titanium nitride or aluminum oxide, and its thickness can be 200-1000 angstroms. This invention can use a mask pattern for forming the first electrode layer to pattern the metal compound material layer, thus utilizing existing masks, ensuring compatibility with existing manufacturing processes, and saving costs. For example, the first electrode layer may be the lower electrode of a ferroelectric capacitor, and therefore the metal compound material layer may be patterned using a mask pattern for forming the lower electrode of a ferroelectric capacitor.

[0061] Next, proceed to step 140, as follows: Figure 2E and 2FAs shown, a first electrode layer 2021, a capacitor dielectric layer 2022, and a second electrode layer 2023 are formed on the metal compound layer 203, covering the metal compound layer 203. The first electrode layer 2021, capacitor dielectric layer 2022, and second electrode layer 2023 constitute a capacitor structure 202. Exemplarily, various deposition methods commonly used in the art can be employed to sequentially form the first electrode material layer 2024, capacitor dielectric material layer 2025, and second electrode material layer 2026, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Subsequently, a patterned mask layer, such as a photoresist layer 217, is formed on the second electrode material layer 2026; then, an etching process is used to form the first electrode layer 2021, capacitor dielectric layer 2022, and second electrode layer 2023 covering the metal compound layer 203. In this invention, atomic layer deposition (ALD) is preferably used to form the first electrode material layer 2024, the capacitor dielectric material layer 2025, and the second electrode material layer 2026. This can effectively control the crystal phase required for the formation of the film layer and greatly improve the polarization intensity per unit area.

[0062] For example, such as Figure 2E and Figure 2F As shown, a first electrode layer 2021, a capacitor dielectric layer 2022, and a second electrode layer 2023 covering the metal compound layer 203 are formed on the metal compound layer 203. This includes: sequentially forming a first electrode material layer 2024, a capacitor dielectric material layer 2025, and a second electrode material layer 2026 covering the metal compound layer 203 on the dielectric layer using an atomic layer deposition process; and patterning to remove portions of the first electrode material layer 2024, the capacitor dielectric material layer 2025, and the second electrode material layer 2026 located on the dielectric layer to form the first electrode layer 2021, the capacitor dielectric layer 2022, and the second electrode layer 2023 covering the metal compound layer 203 and the sidewalls of the metal compound layer. In one embodiment, a first electrode material layer 2024 is formed on the metal compound layer 203 using atomic layer deposition (ALD). The first electrode material layer 2024 covers the metal compound layer 203. Then, a capacitor dielectric material layer 2025 and a second electrode material layer 2026 are sequentially formed on the first electrode material layer 2024. Next, photoresist is applied over the second electrode material layer to form a photoresist layer 217. The size of the photoresist layer 217 can be set according to actual needs, for example... Figure 2EAs shown, a photoresist layer 217 with a width greater than that of the metal compound layer 203 is formed. Finally, etching is performed to remove excess first electrode material layer 2024, capacitor dielectric material layer 2025, and second electrode material layer 2026, thereby forming first electrode layer 2021, capacitor dielectric layer 2022, and second electrode layer 2023. Exemplarily, the etching is dry etching, and the specific etching conditions are well known to those skilled in the art and will not be discussed further here. Exemplarily, using... Figure 2E After the photoresist layer 217 etches the first electrode material layer 2024, the capacitor dielectric material layer 2025, and the second electrode material layer 2026, the sidewalls of the metal compound layer 203 are also covered with the first electrode layer 2021, the capacitor dielectric layer 2022, and the second electrode layer 2023. The materials of the first electrode material layer 2024 and the second electrode material layer 2026 can be the same or different. For example, both the first electrode material layer 2024 and the second electrode material layer 2026 can be titanium nitride (TiN), and their thicknesses can be 200-250 angstroms in this invention. The capacitor dielectric material layer 2025 includes a ferroelectric material, for example, hafnium oxide, and its thickness can be 6-10 nanometers.

[0063] In one example, such as Figure 2G As shown, a second conductive layer 206 is formed above the first dielectric layer 201, and the top of the third conductive plug 205 is electrically connected to the second conductive layer 206. The first conductive layer 206 is subsequently connected to a bit line. The second conductive layer 206 may also be formed before the formation of the patterned metal compound layer 203, and the present invention does not specifically limit this.

[0064] In one example, such as Figure 2GAs shown, the dielectric layer further includes a second dielectric layer 207, which is located above the first dielectric layer 201 and covers the capacitor structure 202. After forming the second dielectric layer 207, the process further includes planarizing the second dielectric layer 207. The method for forming the second dielectric layer 207 is the same as the method for forming the first dielectric layer 201, and the method for planarizing the second dielectric layer 207 is the same as the method for planarizing the first dielectric layer 201, and will not be described again here. Exemplarily, the material of the second dielectric layer 207 can be insulating materials such as silicon dioxide, fluorocarbons, carbon-doped silicon oxide, or silicon carbonitride, and this application does not limit this. Exemplarily, after forming the second dielectric layer 207, the process further includes performing an annealing process to activate the ferroelectric properties of the capacitor dielectric layer 2022 in the ferroelectric capacitor. Since hafnium oxide formed by conventional processes does not have ferroelectric properties, annealing is required to form a special crystal phase in the capacitor dielectric layer to achieve ferroelectricity. Specifically, the annealing temperature range during the annealing process can be 450°C to 750°C.

[0065] Next, the second dielectric layer 207 is etched to form a third interconnect via penetrating the second dielectric layer 207 and exposing a portion of the second electrode layer 207. Specifically, the third interconnect via is formed using a dry etching process or the like. The third interconnect via is then filled to form a fourth conductive plug 208. Specifically, the fourth conductive plug 208 is formed using an electroplating process or the like. The material of the fourth conductive plug 208 includes, but is not limited to, tungsten or copper, so that the bottom of the fourth conductive plug 208 is electrically connected to the second electrode layer 2023 of the capacitor structure 202. A third conductive layer 209 is also formed above the second dielectric layer 207, and the top of the fourth conductive plug 208 is electrically connected to the third conductive layer 209. The third conductive layer serves as the plate line (PL) of the capacitor structure 202.

[0066] Example 2

[0067] To avoid repetition, the steps in Example 2 that are the same as in Example 1 will be briefly described. For detailed explanations and descriptions, please refer to the descriptions in the foregoing examples.

[0068] Below, for reference Figure 2H The method for manufacturing the semiconductor device of the present invention will be described in detail.

[0069] For example, the method for manufacturing the semiconductor device of the present invention includes the following steps:

[0070] First, step S110 is performed to provide a substrate 200 on which transistors 210 are formed.

[0071] Next, step 120 is performed to form a dielectric layer covering the transistor.

[0072] For example, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked together, wherein the first dielectric layer covers the transistor, a first conductive plug electrically connected to the source of the transistor is formed in the first dielectric layer, a first conductive layer electrically connected to the first conductive plug is formed on the first dielectric layer, the second dielectric layer covers the first dielectric layer and the first conductive layer, a second conductive plug electrically connected to the first conductive layer is formed in the second dielectric layer, and the metal compound layer formed in a subsequent step covers the top surface of the second conductive plug.

[0073] like Figure 2H As shown, the dielectric layer includes a first dielectric layer 201 and a second dielectric layer 207 stacked together. The first dielectric layer 201 covers the transistor. A first conductive plug 204 electrically connected to the source of the transistor is formed in the first dielectric layer 201. A first conductive layer 215 electrically connected to the first conductive plug 204 is formed on the first dielectric layer 201. The second dielectric layer 207 covers the first conductive layer 215 of the first dielectric layer 201. A second conductive plug 218 electrically connected to the first conductive layer 215 is formed in the second dielectric layer 207.

[0074] A third conductive plug 205 electrically connected to the drain of the transistor is also formed in the first dielectric layer 201, and a second conductive layer 206 electrically connected to the third conductive plug 205 is formed on the first dielectric layer 201.

[0075] Next, step 130 is performed to form a patterned metal compound layer on the dielectric layer.

[0076] like Figure 2H As shown, a metal compound layer 203 is formed on the second dielectric layer 207. The patterned metal compound layer 203 covers the top surface of the second conductive plug 218. That is, the patterned metal compound layer is electrically connected to the top of the second conductive plug 218, and the bottom of the second conductive plug 218 is electrically connected to the first conductive layer 215.

[0077] Next, step 140 is performed to form a first electrode layer, a capacitor dielectric layer, and a second electrode layer covering the metal compound layer. For example... Figure 2H As shown, a first electrode layer 2021, a capacitor dielectric layer 2022, and a second electrode layer 2023 covering the metal compound layer are formed on the metal compound layer in the same manner as in Embodiment 1. The first electrode layer 2021, the capacitor dielectric layer 2022, and the second electrode layer 2023 constitute a capacitor structure 202.

[0078] A third dielectric layer 214 is also formed on the second dielectric layer 207, covering the capacitor structure 202. A third conductive layer 209 is formed on the third dielectric layer 214, and a fourth conductive plug 208 is formed in the third dielectric layer 214. The bottom of the fourth conductive plug 208 is electrically connected to the second electrode layer 2023 of the capacitor structure 202, and the top of the fourth conductive plug 208 is electrically connected to the third conductive layer 209.

[0079] In this embodiment, the metal compound layer 203 is electrically connected to the source 212 of the transistor 210 through the first conductive layer 215 in connection with the second conductive plug 218 and the first conductive plug 204.

[0080] In the two embodiments described above in this application, in Embodiment 1, the metal compound layer is directly electrically connected to the source of the transistor via a first conductive plug instead of a metal conductive layer; in Embodiment 2, the metal compound layer is electrically connected to the source of the transistor via a first conductive layer and a second conductive plug. Comparing the two methods, Embodiment 1 yields a better semiconductor device, and the annealing temperature can be higher during the annealing process. Embodiment 2 can achieve a more hierarchical structure within a limited chip area, thereby increasing the integration density of the semiconductor device.

[0081] In one example, a transistor and a ferroelectric capacitor can together form a 1T1C (1 Transistor-1 Capacitor) cell structure, wherein the polysilicon gate layer in the transistor gate 211 serves as the word line (WL), the second conductive layer 206 serves as the bit line (BL), and the third conductive layer 209 serves as the plate line (PL). The circuit netlist diagram of this 1T1C cell structure is shown below. Figure 3 For example, by controlling WL to select the ferroelectric capacitor, BL and PL apply positive and negative voltages to the ferroelectric capacitor respectively. Since the intermediate capacitor dielectric layer 2022 has ferroelectric properties, it forms different iron domains (polarizations) under positive and negative electric fields. These iron domains will not disappear when the external electric field is removed, thereby enabling the ferroelectric capacitor to store different charges and realize the storage function.

[0082] This concludes the introduction of the key steps in the manufacturing method of the semiconductor device of the present invention. For complete device manufacturing, multiple other processes may be required, which will not be elaborated here.

[0083] It is worth mentioning that the order of the above steps is only for example. Without conflict, the order of the above steps can be changed or performed alternately.

[0084] Example 3

[0085] The present invention also provides a semiconductor device, such as Figure 2G , 2H As shown, it includes: a substrate 200; a transistor 210 located on the substrate 200; a dielectric layer located on the substrate 200 and covering the transistor; a metal compound layer 203 located on the dielectric layer; a first electrode layer 2021 covering the metal compound layer 203; and a capacitor dielectric layer 2022 and a second electrode layer 2023 located on the first electrode layer 2021. The first electrode layer 2021, the capacitor dielectric layer 2022, and the second electrode layer 2023 constitute a capacitor structure 202.

[0086] For example, the metal compound layer 203 comprises titanium nitride or aluminum oxide. The thickness of the metal compound layer 203 ranges from 200 angstroms to 1000 angstroms. For example, the thickness of the metal compound layer 203 can be 200 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 500 angstroms, 550 angstroms, 600 angstroms, 1000 angstroms, etc.

[0087] Exemplarily, the capacitor dielectric layer 2022 comprises a ferroelectric material. Specifically, the capacitor dielectric layer 2022 comprises zirconium-doped hafnium oxide (HZO, Hf). 1-x Zr x Hafnium oxide (HfO) is an extension of hafnium oxide (HfO)-based ferroelectric materials and is a novel type of ferroelectric material. Compared to traditional ferroelectric materials, the components of HfO... 1-x Zr x Hafnium dioxide (HfO2) and zirconium dioxide (ZrO2) have been used as gate oxides in MOSFETs (Metal-O-Semiconductor Field-Effect Transistors) and dielectric layers in DRAMs (Dynamic Random Access Memory). Therefore, HZO ferroelectric materials are well-compatible with CMOS (Complementary Metal-O-Semiconductor) processes and exhibit strong ferroelectricity even at ultra-thin thicknesses of around 10 nm, demonstrating excellent scalability. Furthermore, based on ultra-thin thicknesses, HfO2... 1-x Zr x O2 also exhibits significant advantages in ferroelectricity and erase / write speed. For example, the thickness of the capacitor dielectric layer 2022 ranges from 6 nm to 10 nm, such as 6 nm, 7 nm, 7.5 nm, 8 nm, 9 nm, 10 nm, etc., wherein the doping ratio of zirconium, hafnium, and oxygen is 0.4:0.4:1 to 0.6:0.6:2, more specifically, the doping ratio of zirconium, hafnium, and oxygen is 0.4:0.4:1, 0.5:0.5:2, or 0.6:0.6:2. Therefore, the first electrode layer 2021, the capacitor dielectric layer 2022, and the second electrode layer 2023 can constitute a ferroelectric capacitor.

[0088] In one example, such as Figure 2G As shown, the dielectric layer includes a first dielectric layer 201 and a second dielectric layer 207 stacked together. The second dielectric layer 207 covers the capacitor structure 202. The bottom of the first conductive plug 204 located in the first dielectric layer 201 is electrically connected to the source 212 of the transistor 210. The top of the first conductive plug 204 is electrically connected to the metal compound layer 203. The bottom of the third conductive plug 205 located in the first dielectric layer 201 is electrically connected to the drain 213 of the transistor 210, and the top of the third conductive plug 205 is electrically connected to the first conductive layer 206 located above the first dielectric layer 201.

[0089] In one example, a fourth conductive plug 208 is located within the second dielectric layer 207, with its bottom electrically connected to the second electrode layer 2023 of the capacitor structure 202; a third conductive layer 209 is located above the second dielectric layer 207, with the top of the fourth conductive plug 208 electrically connected to the third conductive layer 209. Exemplarily, a shallow trench isolation structure (not shown) is also provided on the substrate 200.

[0090] In another example, such as Figure 2H As shown, the dielectric layer includes a first dielectric layer 201 and a second dielectric layer 207 stacked together. The first dielectric layer 201 covers the transistor. A first conductive plug 204 electrically connected to the source of the transistor is formed in the first dielectric layer 201. A first conductive layer 215 electrically connected to the first conductive plug 204 is formed on the first dielectric layer. The second dielectric layer 207 covers the first dielectric layer 201 and the first conductive layer 215. A second conductive plug 218 electrically connected to the first conductive layer 215 is formed in the second dielectric layer 207 using the same method as the first conductive plug 204. The metal compound layer 203 covers the top surface of the second conductive plug 218. That is, the bottom of the second conductive plug 218 is electrically connected to the first conductive layer 215, and the top of the second conductive plug 218 is electrically connected to the metal compound layer 203. A third dielectric layer 214 is also formed on the second dielectric layer 207, covering the capacitor structure 202. At this time, the fourth conductive plug 208 is covered by the third dielectric layer 214, and the third conductive layer 209 is above the third dielectric layer 214. The bottom of the fourth conductive plug 208 is electrically connected to the second electrode layer 2023 of the capacitor structure 202, and the top of the fourth conductive plug 208 is electrically connected to the third conductive layer 209. In this example, the metal compound layer 203 is electrically connected to the source 212 of the transistor 210 through the first conductive layer 215 connecting the second conductive plug 218 and the first conductive plug 204.

[0091] Example 4

[0092] The present invention also provides an electronic device, including the semiconductor device described above or the semiconductor device obtained by the manufacturing method of the semiconductor device described above.

[0093] The electronic device can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., or it can be an intermediate product with the above-mentioned semiconductor devices, such as a mobile phone motherboard with the integrated circuit.

[0094] According to the semiconductor device and its manufacturing method and electronic equipment provided by the present invention, by adding a metal compound layer below the first electrode layer of the ferroelectric capacitor with a MIM structure in the related art, the lower electrode plate (i.e., the first electrode layer) of the ferroelectric capacitor is subjected to tensile stress, thereby making the first electrode layer conducive to the formation of the desired crystal phase, improving the polarization intensity per unit area, and improving the performance of the corresponding product. At the same time, the capacitor structure also covers the sidewall of the metal compound layer, thereby increasing the area of ​​the ferroelectric capacitor, further improving the polarization intensity per unit area of ​​the ferroelectric capacitor and improving the performance of the corresponding product.

[0095] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Transistors located on the substrate; A dielectric layer located on the substrate and covering the transistor; A metal compound layer located on the dielectric layer; A first electrode layer covering the metal compound layer, and a capacitor dielectric layer and a second electrode layer located on the first electrode layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The metal compound layer includes titanium nitride or aluminum oxide, and the capacitor dielectric layer includes a ferroelectric material.

3. The semiconductor device as described in claim 1, characterized in that, The first electrode layer covers the upper surface and sidewalls of the metal compound layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer stacked together. The first dielectric layer covers the transistor. A first conductive plug electrically connected to the source of the transistor is formed in the first dielectric layer. A first conductive layer electrically connected to the first conductive plug is formed on the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first conductive layer. A second conductive plug electrically connected to the first conductive layer is formed in the second dielectric layer. The metal compound layer covers the top surface of the second conductive plug.

5. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which transistors are formed; A dielectric layer is formed covering the transistor; A patterned metal compound layer is formed on the dielectric layer; A first electrode layer, a capacitor dielectric layer, and a second electrode layer are formed on the metal compound layer, covering the metal compound layer.

6. The method for manufacturing a semiconductor device as described in claim 5, characterized in that, The step of forming a first electrode layer, a capacitor dielectric layer, and a second electrode layer covering the metal compound layer on the metal compound layer includes: sequentially forming a first electrode material layer, a capacitor dielectric material layer, and a second electrode material layer covering the metal compound layer on the dielectric layer using an atomic layer deposition process; and patterning away portions of the first electrode material layer, the capacitor dielectric layer, and the second electrode material layer located on the dielectric layer to form a first electrode layer, a capacitor dielectric layer, and a second electrode layer covering the metal compound layer and the sidewalls of the metal compound layer.

7. The method for manufacturing a semiconductor device as described in claim 5, characterized in that, The metal compound layer includes titanium nitride or aluminum oxide, and the capacitor dielectric layer includes a ferroelectric material.

8. The method for manufacturing a semiconductor device as described in claim 5, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer stacked together. The first dielectric layer covers the transistor. A first conductive plug electrically connected to the source of the transistor is formed in the first dielectric layer. A first conductive layer electrically connected to the first conductive plug is formed on the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first conductive layer. A second conductive plug electrically connected to the first conductive layer is formed in the second dielectric layer. The metal compound layer covers the top surface of the second conductive plug.

9. The method for manufacturing a semiconductor device as described in claim 5, characterized in that, The formation of a patterned metal compound layer on the dielectric layer includes forming a metal compound material layer on the dielectric layer and patterning the metal compound material layer using a mask for forming the first electrode layer.

10. An electronic device, characterized in that, The semiconductor device includes any one of claims 1 to 4.

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