Semiconductor device, manufacturing method thereof and electronic device
By filling the vias of FRAM ferroelectric capacitors with metal, barrier, and filler layers, the problem of gaps affecting product reliability after CMP polishing is solved, thus improving the reliability and storage performance of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-06
- Publication Date
- 2026-03-13
AI Technical Summary
In existing FRAM ferroelectric capacitors, gaps in the holes after CMP polishing can affect product reliability and lead to a decrease in semiconductor device performance.
A metal layer, a barrier layer, and a filler layer are sequentially filled into the through-hole to ensure that no gaps are generated after CMP polishing. The reliability of the device is improved by forming the barrier layer and the filler layer.
It improves the reliability of semiconductor devices, enhances storage performance, and avoids reliability issues caused by gaps.
Smart Images
Figure CN121665580A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to semiconductor devices and their manufacturing methods, and electronic devices. Background Technology
[0002] Ferroelectric random access memory (FRAM) is a novel type of memory that combines the non-volatility of read-only memory (ROM) with the non-volatility of random access memory (RAM), along with advantages such as high durability, high-speed read / write, and low power consumption. FRAM ferroelectric capacitors in related technologies employ a metal-insulator-metal (MIM) structure. The lower electrode of the MIM structure is grown on metal vias. After filling the vias with metal, chemical mechanical polishing (CMP) is performed, which grinds away the gaps in the vias. Capacitors grown on these gaps can affect product reliability. Summary of the Invention
[0003] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0004] One aspect of the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate on which a transistor is formed; forming a dielectric layer covering the transistor; forming a via in the dielectric layer; filling the via with a metal material layer and etching back the metal material layer to form a metal layer at the bottom of the via; sequentially forming a barrier layer and a filling layer on the dielectric layer, on the metal layer and in the via; forming a first electrode material layer, a capacitor dielectric material layer and a second electrode material layer on the filling layer; and patterning the second electrode material layer, the capacitor dielectric material layer, the first electrode material layer, the filling layer and the barrier layer to form a capacitor electrically connected to the transistor.
[0005] For example, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked together. The step of forming a dielectric layer covering the transistor includes: forming a first dielectric layer covering the transistor; forming a first conductive plug in the first dielectric layer, the bottom of the first conductive plug being electrically connected to the source of the transistor; forming a conductive layer on the first dielectric layer that contacts the top of the first conductive plug; forming a second dielectric layer covering the first dielectric layer and the conductive layer; the step of forming a via in the dielectric layer includes: forming a via in the second dielectric layer, the via exposing at least a portion of the top surface of the conductive layer.
[0006] For example, before forming the first electrode material layer, the capacitor dielectric material layer, and the second electrode material layer on the filler layer, a step of chemical mechanical polishing of the surface of the filler layer is included.
[0007] For example, the metal material layer includes tungsten, the barrier layer includes titanium nitride, and the filler layer includes titanium nitride or tungsten.
[0008] For example, the capacitor dielectric material layer includes a ferroelectric material.
[0009] For example, the thickness of the metal material layer is 800-1500 Å, the thickness of the barrier layer is 100-200 Å, and the thickness of the filler layer is 2500-3500 Å.
[0010] Another aspect of the present invention provides a semiconductor device, comprising: a substrate on which a transistor is formed; a dielectric layer covering the transistor; a via formed in the dielectric layer; a metal layer formed at the bottom of the via; a barrier layer covering a portion of the dielectric layer, a portion of the via, and the metal layer; and a filling layer located on the barrier layer; a first electrode layer, a capacitor dielectric layer, and a second electrode layer formed on the filling layer, wherein the first electrode layer, the capacitor dielectric layer, and the second electrode layer constitute a capacitor.
[0011] For example, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked together; wherein, the first dielectric layer covers the transistor, a first conductive plug is formed in the first dielectric layer, the bottom of the first conductive plug is electrically connected to the source of the transistor; a conductive layer is formed on the first dielectric layer that contacts the top of the first conductive plug; the second dielectric layer covers the first dielectric layer and the conductive layer; the via is formed in the second dielectric layer, and the via exposes at least a portion of the top surface of the conductive layer.
[0012] For example, the metal layer comprises tungsten, the barrier layer comprises titanium nitride, and the filler layer comprises titanium nitride or tungsten.
[0013] The present invention also provides an electronic device comprising any of the semiconductor devices described above.
[0014] The semiconductor device and its manufacturing method and electronic device provided by the present invention, by sequentially filling the through-hole with a metal layer, a barrier layer and a filler layer, can prevent gaps from being generated after CMP polishing, thereby improving the reliability of the semiconductor device and improving the storage performance of the semiconductor device. Attached Figure Description
[0015] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.
[0016] In the attached image:
[0017] Figure 1 A schematic diagram of the hysteresis loop of hafnium oxide doped with it;
[0018] Figure 2 This is a schematic diagram showing the relationship between a hafnium oxide-doped capacitor and voltage.
[0019] Figure 3 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0020] Figures 4A-4E A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of the present invention is shown, showing the device obtained by sequentially performing the manufacturing method.
[0021] Figure 4F A cross-sectional schematic diagram of a semiconductor device obtained by a method for manufacturing a semiconductor device according to another illustrative embodiment of the present invention is shown.
[0022] Figure 5 A circuit netlist diagram of a 1T1C cell structure according to an illustrative embodiment of the present invention is shown. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein. Based on the embodiments of the present invention described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of the present invention.
[0024] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.
[0025] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
[0026] To fully understand this invention, a detailed structure will be presented in the following description to illustrate the technical solution proposed by this invention. Optional embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.
[0027] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0028] The ferroelectric effect refers to the phenomenon that when certain crystals are subjected to an external electric field, their polarization state can change with the direction of the electric field, and this change can be partially maintained after the electric field is removed, that is, they have residual polarization intensity. This characteristic enables ferroelectric materials to be used in the field of data storage.
[0029] Ferroelectric materials can be zirconium-doped hafnium oxide, such as Figure 1 and Figure 2 As shown, when an external electric field is applied between the upper and lower electrodes, the iron domains (i.e., polarized regions) of hafnium oxide material exhibit different polarization states depending on the direction of the electric field. This change in polarization state directly affects the material's capacitance characteristics. Specifically, as the polarization state changes, the capacitance of the dielectric also changes, consequently altering the polarity and quantity of charge that the capacitor can store. Furthermore, since ferroelectric materials maintain a high residual polarization intensity after the external electric field is removed, this indicates that the capacitor can retain a certain level of charge storage even after the electric field is removed. This gives the capacitor a non-volatile charge storage capability, enabling data storage.
[0030] To improve the reliability of semiconductor devices, this invention provides a method for manufacturing semiconductor devices, such as... Figure 3 As shown, the method for manufacturing a semiconductor device includes:
[0031] Step S110: Provide a substrate on which transistors are formed.
[0032] Step S120: Form a dielectric layer covering the transistor.
[0033] Step S130: Form a via in the dielectric layer.
[0034] Step S140: Fill the via with a metal material layer and etch back the metal material layer to form a metal layer at the bottom of the via.
[0035] Step S150: A barrier layer and a fill layer are sequentially formed on the dielectric layer, the metal layer, and inside the via.
[0036] Step S160: Form a first electrode material layer, a capacitor dielectric material layer, and a second electrode material layer on the filler layer.
[0037] Step S170: Pattern the second electrode material layer, the capacitor dielectric material layer, the first electrode material layer, the filling layer, and the barrier layer to form a capacitor electrically connected to the transistor.
[0038] The semiconductor device manufacturing method of this invention, by sequentially filling a metal layer, a barrier layer and a filler layer in a through-hole, can prevent gaps from being generated after CMP polishing, thereby improving the reliability and storage performance of the semiconductor device.
[0039] Example 1
[0040] Below, for reference Figures 4A to 4E The method for manufacturing the semiconductor device of the present invention will be described in detail, wherein, Figures 4A to 4E A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.
[0041] For example, the method for manufacturing the semiconductor device of the present invention includes the following steps:
[0042] First, step S110 is performed, providing a substrate 200 on which a transistor 201 is formed. This yields... Figure 4A The structure shown.
[0043] As an example, transistor 201 may be a selector switch transistor.
[0044] Exemplarily, the substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate, and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can also be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz, or a glass substrate. The substrate 200 also includes a shallow trench isolation structure (not shown).
[0045] For example, forming a transistor 201 on a substrate 200 may include the following steps:
[0046] A gate dielectric layer (not shown) is formed on the upper surface of the substrate 200. Specifically, the gate dielectric layer can be formed by thermal oxidation, physical vapor deposition or chemical vapor deposition, etc. The gate dielectric layer includes, but is not limited to, a silicon oxide layer.
[0047] A gate material layer is formed on the upper surface of the gate dielectric layer. Specifically, the gate material layer can be formed by physical vapor deposition or chemical vapor deposition. The gate material layer includes, but is not limited to, a doped polysilicon layer or a metal layer.
[0048] The gate material layer and the gate dielectric layer are etched to form the gate 2011; sidewalls can also be formed on both sides of the gate 2011. Specifically, physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes can be used to form the sidewalls, which include, but are not limited to, silicon oxide layers, silicon nitride layers, or ONO structures (i.e., stacked structures of silicon oxide layers, silicon nitride layers, and silicon oxide layers); the gate 2011 is subsequently used as a word line (WL).
[0049] Ion implantation is performed on the substrate 200 based on the gate 2011 and the sidewalls to form the source 2012 and the drain 2013 on both sides of the gate 2011, respectively.
[0050] In one example, after forming the source 2012 and drain 2013, a step of forming metal silicide on the upper surfaces of the source 2012 and drain 2013 may also be included. By forming metal silicide on the upper surfaces of the source 2012 and drain 2013, the contact resistance between the source 2012 and drain 2013 and the conductive plugs from which they are led out can be reduced.
[0051] Next, proceed to step 120, as follows: Figure 4B As shown, a dielectric layer 202 is formed covering the transistor 201.
[0052] Exemplarily, the dielectric layer 202 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the dielectric layer 202 can be an insulating material such as silicon dioxide, fluorocarbon, carbon-doped silicon oxide, or silicon carbonitride, and this application is not limited in this regard. Exemplarily, after forming the dielectric layer 202, the method further includes planarizing the dielectric layer 202. Exemplarily, non-limiting examples of this planarization method include mechanical planarization and chemical mechanical polishing planarization. Exemplarily, before planarization, the thickness of the dielectric layer 202 ranges from 6000 Å to 7000 Å, and after planarization, the thickness of the dielectric layer 202 ranges from 3000 Å to 3500 Å.
[0053] Next, proceed to step S130, as follows: Figure 4C As shown, a via 203 is formed in the dielectric layer 202.
[0054] For example, the dielectric layer 202 is etched to form a via 203 penetrating the dielectric layer 202. Specifically, the via 203 can be formed by a dry etching process or the like. The bottom of the via 203 exposes the source 2012 of the transistor 201 (or the metal silicide on the surface of the source 2012).
[0055] Accordingly, such as Figure 4C As shown, a conductive plug communicating with the drain 2013 can be formed in the dielectric layer 202. For example, the dielectric layer 202 is etched to form a first interconnect via penetrating the dielectric layer 202. Specifically, the first interconnect via is formed using a dry etching process or the like. The first interconnect via is filled to form a second conductive plug 204. Specifically, the second conductive plug 204 is formed using an electroplating process or the like. The material of the second conductive plug 204 includes, but is not limited to, tungsten or copper. This allows the bottom of the second conductive plug 204 to be electrically connected to the drain 2013 of the transistor 201 (or the metal silicide on the surface of the drain 2013).
[0056] For example, such as Figure 4C As shown, a bit line (BL) 205 is formed above the second conductive plug 204, and the bit line is electrically connected to the drain 2013 of the transistor 201 through the second conductive plug 204.
[0057] Traditional FRAM ferroelectric capacitors use a MIM structure. The first electrode of the MIM structure is grown on the connection hole. After filling the hole with metal, the gaps in the hole are ground out by CMP. The capacitors grown on the gaps will affect the reliability of the product.
[0058] Next, proceed to step S140, as follows: Figure 4D As shown, a metal material layer is filled in the via 203, and the metal material layer is etched back to form a metal layer 2031 at the bottom of the via 203.
[0059] For example, a metal material layer with a thickness of 800 Å to 1500 Å can be filled into the through hole 203 first. Specifically, the metal material layer includes tungsten. Then, the initially filled tungsten is etched back to form a metal layer 2031 at the bottom of the through hole 203. The etching back can remove uneven or excess tungsten on the surface, ensuring the uniformity of the subsequent barrier layer 2032.
[0060] Next, proceed to step S150, as follows: Figure 4D As shown, a barrier layer 2032 and a fill layer 2033 are sequentially formed on the dielectric layer 202, the metal layer 2031, and the via 203.
[0061] It should be noted that the through hole 203 includes a sidewall, which can form a barrier layer 2032 on the sidewall of the through hole 203.
[0062] For example, a barrier layer 2032 with a thickness of 100-200 Å is grown on the tungsten surface after etching. Specifically, the barrier layer 2032 includes titanium nitride. Then, a filling layer 2033 with a thickness of 2500-3500 Å is grown on the barrier layer 2032 to further fill the pores and ensure the integrity and density of the filling material, eliminating gap problems that may be caused by CMP treatment. Specifically, the filling layer 2033 includes titanium nitride or tungsten.
[0063] For example, the barrier layer 2032 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0064] Next, proceed to step S160, as follows: Figure 4D As shown, a first electrode material layer, a capacitor dielectric material layer, and a second electrode material layer are formed on the filler layer 2033.
[0065] Exemplarily, the first electrode material layer, the capacitor dielectric material layer, and the second electrode material layer can be sequentially formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Specifically, portions of the first electrode material layer, the capacitor dielectric material layer, and the second electrode material layer located on the dielectric layer 202 can be patterned and removed to form a first electrode layer 2061, a capacitor dielectric layer 2062, and a second electrode layer 2063 covering the filling layer 2033.
[0066] For example, before forming the first electrode material layer, the capacitor dielectric material layer, and the second electrode material layer on the filler layer 2033, the method further includes a step of chemical mechanical polishing the surface of the filler layer 2033.
[0067] For example, the capacitor dielectric material layer includes a ferroelectric material. Specifically, the capacitor dielectric material layer includes zirconium-doped hafnium oxide (HZO, Hf1-xZrxO2), which is an extension of hafnium oxide (HfO)-based ferroelectric materials and is a novel type of ferroelectric material. Compared to traditional ferroelectric materials, HfO2 (hafnium dioxide) and ZrO2 (zirconia) constituting Hf1-xZrxO2 have been applied to the gate oxides of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and DRAMs (Dynamic Random Access Memory). Therefore, HZO ferroelectric materials are well compatible with CMOS (Complementary Metal-Oxide-Semiconductor) processes and exhibit strong ferroelectricity even at ultra-thin thicknesses of around 10 nm, demonstrating excellent scalability. Furthermore, based on its ultra-thin thickness, Hf1-xZrxO2 also exhibits significant advantages in ferroelectricity and erase / write speed. For example, the thickness of the capacitor dielectric layer 2062 ranges from 6 nm to 10 nm. For instance, the thickness of the capacitor dielectric layer 2062 can be 6 nm, 7 nm, 7.5 nm, 8 nm, 9 nm, 10 nm, etc., wherein the doping ratio of zirconium, hafnium, and oxygen is 0.4:0.4:1 to 0.6:0.6:2. More specifically, the doping ratio of zirconium, hafnium, and oxygen is 0.4:0.4:1, 0.5:0.5:2, or 0.6:0.6:2. Therefore, the first electrode layer 2061, the capacitor dielectric layer 2062, and the second electrode layer 2063 can constitute a ferroelectric capacitor structure.
[0068] Next, proceed to step S170, as follows: Figure 4D As shown, the second electrode material layer, the capacitor dielectric material layer, the first electrode material layer, the fill layer 2033, and the barrier layer 2032 are patterned to form a capacitor electrically connected to the transistor 201.
[0069] In one embodiment, photoresist is applied over the second electrode material layer to form a photoresist layer. The size of the photoresist layer can be set according to actual needs. Finally, etching is performed to remove excess first electrode material layer, capacitor dielectric material layer and second electrode material layer, thereby forming a capacitor.
[0070] For example, after forming the capacitor, the process further includes an annealing process to activate the ferroelectric properties of the capacitor dielectric material layer. Since hafnium oxide formed by conventional processes lacks ferroelectricity, annealing is required to form a special crystalline phase in the capacitor dielectric layer 2062 to achieve ferroelectricity. Specifically, the annealing temperature range during the annealing process can be 450°C to 750°C.
[0071] Then as Figure 4E As shown, first, a third dielectric layer 207 covering the capacitor is formed; then, a third conductive plug 208 connected to the second electrode material layer is formed in the third dielectric layer 207; finally, a plate line (PL) 209 is formed above the third conductive plug 208.
[0072] Example 2
[0073] In another example, dielectric layer 202 includes a first dielectric layer 210 and a second dielectric layer 214 stacked together, as shown below. Figure 4F As shown, step S120 includes:
[0074] A first dielectric layer 210 is formed over the transistor 201. Exemplarily, the first dielectric layer 210 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0075] A first conductive plug 212 is formed in the first dielectric layer 210, wherein the bottom of the first conductive plug 212 is electrically connected to the source 2012 of the transistor 201 (or the metal silicide on the surface of the source 2012).
[0076] A fourth conductive plug 211 is formed in the first dielectric layer 210, wherein the bottom of the fourth conductive plug 211 is electrically connected to the drain 2013 of the transistor 201 (or the metal silicide on the surface of the drain 2013).
[0077] A conductive layer 213 is formed on the first dielectric layer 210, which contacts the top of the first conductive plug 212. Exemplarily, a conductive layer 213 may be deposited and patterned on the first dielectric layer 210, wherein the conductive layer 213 comprises aluminum or copper.
[0078] A second dielectric layer 214 is formed covering the first dielectric layer 210 and the conductive layer 213. Exemplarily, the second dielectric layer 214 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0079] A via 203 is formed in the second dielectric layer 214, at least exposing a portion of the top surface of the conductive layer 213. A metal material layer is filled in the via 203, and the metal material layer is etched back to form a metal layer 2031 at the bottom of the via 203. A barrier layer 2032 and a fill layer 2033 are sequentially formed on the second dielectric layer 214, on the metal layer 2031, and in the via 203.
[0080] A first electrode layer 2061, a capacitor dielectric layer 2062, and a second electrode layer 2063 are covered on the fill layer 2033 to form a capacitor.
[0081] A third dielectric layer 207 is formed to cover the capacitor. A third conductive plug 208 connected to the second electrode layer 2063 is formed in the third dielectric layer 207. A plate line 209 is formed above the third conductive plug 208.
[0082] In this embodiment, by stacking the first dielectric layer 210 and the second dielectric layer 214, a more hierarchical structure can be achieved within a limited chip area, thereby increasing the integration density of the semiconductor device. It is worth noting that the semiconductor device yield is higher and the annealing process temperature can be higher when the dielectric layer 202 is not formed by stacking.
[0083] In one example, transistor 201 and capacitor can together form a 1T1C (1 Transistor-1 Capacitor) cell structure, wherein the polysilicon gate layer in the gate 2011 of transistor 201 serves as a word line. See the circuit netlist diagram of this 1T1C cell structure. Figure 5 For example, by controlling WL to select the ferroelectric capacitor, the bit line and the plate line apply positive and negative voltages to the ferroelectric capacitor respectively. Since the intermediate capacitor dielectric layer 2062 has ferroelectric properties, it forms different iron domains (polarizations) under positive and negative electric fields. These iron domains will not disappear when the external electric field is removed, so that the ferroelectric capacitor stores different charges and realizes the storage function.
[0084] This concludes the introduction of the key steps in the manufacturing method of the semiconductor device of the present invention. For complete device manufacturing, multiple other processes may be required, which will not be elaborated here.
[0085] It is worth mentioning that the order of the above steps is only for example. Without conflict, the order of the above steps can be changed or performed alternately.
[0086] Example 3
[0087] The present invention also provides a semiconductor device, such as Figure 4E , 4FAs shown, the device includes: a substrate 200 on which a transistor 201 is formed; a dielectric layer 202 covering the transistor 201; a via 203 formed in the dielectric layer 202; a metal layer 2031 formed at the bottom of the via 203; a barrier layer 2032 covering a portion of the dielectric layer 202, a portion of the via 203, and the metal layer 2031; and a fill layer 2033 located on the barrier layer 2032; a first electrode layer 2061, a capacitor dielectric layer 2062, and a second electrode layer 2063 formed on the fill layer 2033, wherein the first electrode layer 2061, the capacitor dielectric layer 2062, and the second electrode layer 2063 constitute a capacitor.
[0088] For example, dielectric layer 202 includes a first dielectric layer 210 and a second dielectric layer 214 stacked together. The first dielectric layer 210 covers transistor 201, and a first conductive plug 212 is formed in the first dielectric layer 210, the bottom of which is electrically connected to the drain 2013 of transistor 201. A conductive layer 213 is formed on the first dielectric layer 210, contacting the top of the first conductive plug 212. The second dielectric layer 214 covers the first dielectric layer 210 and the conductive layer 213. A via 203 is formed in the second dielectric layer 214, and the via 203 exposes at least a portion of the top surface of the conductive layer 213.
[0089] For example, metal layer 2031 comprises tungsten, and the thickness of metal layer ranges from 800 Å to 1500 Å. Barrier layer 2032 comprises titanium nitride, and the thickness of barrier layer 2032 ranges from 100-200 Å. Filler layer 2033 comprises titanium nitride or tungsten, and the thickness of filler layer 2033 ranges from 2500 Å to 3500 Å.
[0090] Example 4
[0091] The present invention also provides an electronic device comprising the semiconductor device described above or a semiconductor device obtained by the manufacturing method of the semiconductor device described above.
[0092] The electronic device can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., or it can be an intermediate product with the above-mentioned semiconductor devices, such as a mobile phone motherboard with the integrated circuit.
[0093] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.
[0094] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0095] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.
[0096] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0097] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.
[0098] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.
[0099] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.
[0100] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some modules according to the embodiments of this application. This application can also be implemented as an apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such an implementation of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.
[0101] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.
[0102] The above description is merely a specific embodiment or illustration of the embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which transistors are formed; A dielectric layer is formed covering the transistor; Through-holes are formed in the dielectric layer; A metal material layer is filled into the through hole, and the metal material layer is etched back to form a metal layer at the bottom of the through hole; A barrier layer and a filling layer are sequentially formed on the dielectric layer, on the metal layer, and inside the via. A first electrode material layer, a capacitor dielectric material layer, and a second electrode material layer are formed on the filling layer; The second electrode material layer, the capacitor dielectric material layer, the first electrode material layer, the fill layer, and the barrier layer are patterned to form a capacitor electrically connected to the transistor.
2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer stacked together, and the step of forming a dielectric layer covering the transistor includes: A first dielectric layer is formed to cover the transistor; A first conductive plug is formed in the first dielectric layer, and the bottom of the first conductive plug is electrically connected to the source of the transistor. A conductive layer is formed on the first dielectric layer that contacts the top of the first conductive plug; A second dielectric layer is formed covering the first dielectric layer and the conductive layer; The step of forming a via in the dielectric layer includes: A via is formed in the second dielectric layer, the via exposing at least a portion of the top surface of the conductive layer.
3. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Before forming the first electrode material layer, the capacitor dielectric material layer, and the second electrode material layer on the filler layer, the method further includes a step of chemical mechanical polishing the surface of the filler layer.
4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The metallic material layer includes tungsten, the barrier layer includes titanium nitride, and the filler layer includes either titanium nitride or tungsten.
5. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The capacitor dielectric material layer includes ferroelectric materials.
6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that, The thickness of the metal material layer is 800-1500 Å, the thickness of the barrier layer is 100-200 Å, and the thickness of the filler layer is 2500-3500 Å.
7. A semiconductor device, characterized in that, include: A substrate on which transistors are formed; A dielectric layer covering the transistor; Through-holes formed in the dielectric layer; A metal layer formed at the bottom of the through hole; A barrier layer covering part of the dielectric layer, part of the via and the metal layer, and a fill layer on the barrier layer; A first electrode layer, a capacitor dielectric layer, and a second electrode layer are formed on the filling layer, and the first electrode layer, the capacitor dielectric layer, and the second electrode layer constitute a capacitor.
8. The semiconductor device as claimed in claim 7, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer stacked together; Wherein, the first dielectric layer covers the transistor, a first conductive plug is formed in the first dielectric layer, and the bottom of the first conductive plug is electrically connected to the source of the transistor; a conductive layer is formed on the first dielectric layer that contacts the top of the first conductive plug; a second dielectric layer covers the first dielectric layer and the conductive layer; the via is formed in the second dielectric layer, and the via exposes at least a portion of the top surface of the conductive layer.
9. The semiconductor device as claimed in claim 7 or 8, characterized in that, The metal layer comprises tungsten, the barrier layer comprises titanium nitride, and the filler layer comprises either titanium nitride or tungsten.
10. An electronic device, characterized in that, The semiconductor device included in any one of claims 7-9.