Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. The manufacturing method comprises the following steps: providing a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; a well region and a first region are formed on the semiconductor body, the first region is located on the first surface, and the well region is located on one side of the first region away from the first surface; forming a gate trench on the first surface; performing primary ion implantation on the semiconductor body to form a third sub-region, and then performing secondary ion implantation to form a second region; the second region and the third sub-region are located at the bottom of the gate trench, the position of the second region is the same as the position of the third sub-region, and the implanted ion conduction type of the primary ion implantation is opposite to the implanted ion conduction type of the secondary ion implantation; and forming a grid electrode in the grid electrode groove. According to the embodiment of the invention, the voltage endurance capability of the gate oxide layer of the trench gate can be improved, and the reliability of the semiconductor device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) made of third-generation wide-bandgap semiconductors such as silicon carbide (SiC) or gallium nitride (GaN) possess characteristics such as large critical breakdown electric field strength, high thermal conductivity, large bandgap width, and high electron saturation drift velocity. These characteristics have made SiC or GaN a research hotspot for power semiconductor devices. In high-power applications such as high-speed rail, hybrid electric vehicles, and intelligent high-voltage direct current transmission, SiC devices are highly anticipated.

[0003] However, in existing trench MOS devices, the gate oxide layer formed at the bottom of the gate is prone to breakdown, affecting the performance of the MOS device. Summary of the Invention

[0004] This application provides a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle to improve the withstand voltage capability of the trench gate oxide layer and enhance the reliability of the semiconductor device.

[0005] In a first aspect, a method for manufacturing a semiconductor device is provided, comprising:

[0006] A semiconductor body is provided; the semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other;

[0007] A well region and a first region are formed in the semiconductor body. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface.

[0008] A gate trench is formed on the first surface;

[0009] The semiconductor body is subjected to a first ion implantation to form a third sub-region, and then a second ion implantation is performed to form a second region; the second region and the third sub-region are located at the bottom of the gate trench, and the position of the second region is the same as that of the third sub-region; the conductivity type of the implanted ions in the first ion implantation is opposite to that in the second ion implantation.

[0010] A gate is formed within the gate trench;

[0011] A source electrode is formed on the first surface;

[0012] A drain electrode is formed on the second surface.

[0013] Optionally, when forming the gate trench on the first surface, the method further includes:

[0014] A source trench is formed on the first surface;

[0015] The process of performing a first ion implantation on the semiconductor body to form a third sub-region, followed by a second ion implantation to form a second region, includes:

[0016] The gate trench and the source trench are implanted with first conductive ions to form a third region and a third sub-region; the third region is located on the periphery of the source trench.

[0017] The gate trench is implanted with a second conductive ion to form the second region; wherein the first conductive ion has the second conductivity type, and the second conductive ion has the first conductivity type; the ion concentration in the second region is less than the ion concentration in the third region.

[0018] Optionally, the step of performing one ion implantation on the gate trench and the source trench using a first conductive ion includes:

[0019] A first conductive ion with a first atomic radius and a first ion concentration is used to perform one ion implantation on the gate trench and the source trench respectively with a first implantation energy;

[0020] The second ion implantation of the gate trench using a second conductive ion includes:

[0021] A second conductive ion with a second atomic radius and a second ion concentration is used to perform secondary ion implantation on the gate trench with a second implantation energy;

[0022] Wherein, the second atomic radius is greater than the first atomic radius, and the second injection energy is greater than the first injection energy; or, the second atomic radius is less than the first atomic radius, and the second injection energy is less than the first injection energy.

[0023] Optionally, both the first ion concentration and the second ion concentration are greater than [amount missing]. ;

[0024] Both the first injection energy and the second injection energy are greater than 1000 keV.

[0025] Optionally, forming a gate trench on the first surface includes:

[0026] The gate trench and the source trench are formed on the first surface;

[0027] A barrier material layer is formed on the first surface;

[0028] Remove the barrier material layer located on the first surface, inside the source trench, and at the bottom of the gate trench, and form a barrier layer on the sidewall of the gate trench;

[0029] After performing a first ion implantation to form a third sub-region on the semiconductor body, and then performing a second ion implantation to form a second region, the method further includes:

[0030] Remove the barrier layer located on the sidewall of the gate trench.

[0031] Optionally, before forming the source electrode on the first surface, the method further includes:

[0032] An insulating layer is formed on the first surface; the orthogonal projection of the insulating layer onto the semiconductor body completely covers the orthogonal projection of the gate onto the semiconductor body;

[0033] A contact metal layer is formed on the first surface; the contact metal layer covers the insulating layer and the first surface.

[0034] Optionally, forming the source electrode on the first surface includes:

[0035] The source electrode is formed on the side of the contact metal layer away from the first surface.

[0036] In a second aspect, a semiconductor device is provided, comprising:

[0037] The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region, the first region being configured with the first conductivity type and located on the first surface, and the well region being configured with the second conductivity type and located on the side of the first region away from the first surface; the first surface is provided with a gate trench.

[0038] A gate is located inside the gate trench; a second region is provided at the bottom of the gate trench;

[0039] The source electrode is located on the first surface;

[0040] The drain electrode is located on the second surface.

[0041] Optionally, it also includes: a source trench and a source trench structure;

[0042] The source trench is located on the first surface, the source trench structure is located inside the source trench, and a third region is provided around the source trench.

[0043] The ion concentration in the second region is lower than that in the third region.

[0044] Optionally, the semiconductor device further includes: an insulating layer and a contact metal layer;

[0045] The insulating layer is located on the first surface, and the orthographic projection of the insulating layer onto the semiconductor body completely covers the orthographic projection of the gate onto the semiconductor body.

[0046] The contact metal layer is located on the first surface and covers the insulating layer and the first surface.

[0047] Thirdly, a power module is provided, including a substrate and a semiconductor device as described in any embodiment of the second aspect, wherein the substrate is used to support the semiconductor device.

[0048] Fourthly, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction;

[0049] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the second aspect, the semiconductor device being electrically connected to the circuit board.

[0050] Fifthly, a vehicle is provided, including a load and a power conversion circuit as described in the fourth aspect embodiment, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0051] The semiconductor device manufacturing method provided in this application involves forming a gate trench on a first surface of a semiconductor body. The gate trench is then subjected to two ion implantations with a high implantation energy, resulting in two ion bombardments of the bottom of the gate trench, forming a second region. This alters the lattice structure of the epitaxial layer in the semiconductor body corresponding to the bottom of the gate trench and reduces the atomic bond energy of the epitaxial layer region at the bottom, thereby increasing the gate oxide growth rate at the bottom of the gate trench. Therefore, when the gate oxide layer is subsequently grown using thermal oxidation, the thickness of the gate oxide layer grown at the bottom of the gate trench is greater than the thickness of the gate oxide layer grown on the sidewalls of the gate trench. This effectively improves the breakdown voltage of the gate oxide layer in the gate, prevents the gate oxide layer at the bottom of the gate trench from being broken down, and contributes to improving the reliability and performance of the semiconductor device.

[0052] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic flowchart of a semiconductor device manufacturing method according to an embodiment of this application.

[0055] Figures 2 to 7 for Figure 1 A structural diagram corresponding to each relevant step in the process;

[0056] Figure 8 This is a schematic flowchart of step S140 in a semiconductor device manufacturing method according to an embodiment of this application;

[0057] Figures 9 to 10 yes Figure 8 A structural diagram corresponding to each relevant step in the process;

[0058] Figure 11 This is a schematic diagram of the specific process of step S130 in a semiconductor device manufacturing method according to an embodiment of this application;

[0059] Figures 12 to 13 yes Figure 11 A structural diagram corresponding to each relevant step in the process.

[0060] Figure 14 This is a schematic flowchart illustrating a method for manufacturing another semiconductor device according to an embodiment of this application.

[0061] Figure 15 yes Figure 14 A schematic diagram of the structure corresponding to the relevant steps. Detailed Implementation

[0062] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0063] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0064] This application provides a method for manufacturing a semiconductor device. Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figures 2 to 7 for Figure 1 A structural diagram corresponding to each relevant step in the process. Combined with... Figures 1 to 7 The manufacturing method of this semiconductor device specifically includes the following steps:

[0065] S110, Provide a semiconductor body; the semiconductor body is configured as a first conductivity type and includes a first surface and a second surface disposed opposite to each other.

[0066] Specifically, see Figure 2 The semiconductor body 100 is configured with a first conductivity type and includes a first surface 101 and a second surface 102 disposed opposite to each other. Exemplarily, the semiconductor body 100 may include a substrate 10 and an epitaxial layer 20; in some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE). Exemplarily, the semiconductor body 100 may be a silicon carbide semiconductor body or a gallium nitride semiconductor body, without limitation.

[0067] S120. A well region and a first region are formed in the semiconductor body. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface.

[0068] Specifically, see Figure 3 A well region 103 and a first region 104 are formed in the semiconductor body 100. The first region 104 is configured with a first conductivity type and is located on the first surface 101, while the well region 103 is configured with a second conductivity type and is located on the side of the first region 104 away from the first surface 101. Exemplarily, the MOSFET semiconductor device may include an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. In this embodiment, an N-type MOSFET semiconductor device is used as an example for illustration. The semiconductor body 100 is an N-type semiconductor body, the well region 103 is a P-type well region, and the first region 104 is an N+ doped region.

[0069] S130, A gate trench is formed on the first surface.

[0070] Specifically, see Figure 4 A gate trench T1 is formed on the first surface 101. The gate trench T1 extends from the first surface 101 through the first region 104 and the well region 103, and extends into the epitaxial layer 20 of the semiconductor body 100.

[0071] S140. A first ion implantation is performed on the semiconductor body to form a third sub-region, followed by a second ion implantation to form a second region. The second region and the third sub-region are located at the bottom of the gate trench, and the position of the second region is the same as that of the third sub-region. The conductivity type of the implanted ions in the first ion implantation is opposite to that in the second ion implantation.

[0072] Specifically, see Figure 5The semiconductor body 100 undergoes a first ion implantation to form a third sub-region 112, followed by a second ion implantation to form a second region 106. The second region 106 and the third sub-region 112 are located at the bottom of the gate trench T1, with the second region 106 positioned at the same location as the third sub-region 112. The conductivity types of the implanted ions in the first ion implantation are opposite to those in the second ion implantation. Ion implantation is performed on the gate trench T1 within the semiconductor body 100 to form a certain range of ion-doped regions outside the gate trench T1. This ion implantation process can be divided into two steps: first, a first ion implantation treatment of the gate trench T1 is performed using implanted ions of one conductivity type, followed by a second ion implantation treatment of the gate trench T1 using implanted ions of another conductivity type. The conductivity types of the conductive ions used in the two ion implantations are opposite. The ion implantation process is essentially an ion bombardment process. By sequentially bombarding the gate trench T1 with two different types of conductive ions, the lattice structure of the epitaxial layer 20 at the bottom of the gate trench T1 can be effectively altered, reducing the atomic bond energy in the epitaxial layer 20 region and thus effectively increasing the gate oxide growth rate at the bottom of the gate trench T1. For example, Figure 5 The diagram shows a second ion-doped region 106 formed by a second ion implantation in the epitaxial layer 20 corresponding to the bottom of the gate trench T1. The third sub-region 112 formed after the first ion implantation is not shown.

[0073] S150, A gate is formed in the gate trench.

[0074] Specifically, see Figure 6 A gate 108 is formed within a gate trench T1. Specifically, silicon oxide material is grown inside the gate trench T1 by thermal oxidation to form a gate oxide layer 1081 covering the inner wall of the gate trench T1; and polysilicon material is filled inside the gate oxide layer 1081 to form gate polysilicon 1082, thereby forming the gate 108.

[0075] By bombarding the bottom of the gate trench T1 with ions twice with a higher injection energy before forming the gate 108, a second region 106 is formed at the bottom. This changes the lattice structure of the epitaxial layer 20 region corresponding to the bottom of the gate trench T1, reducing the atomic bond energy at the bottom of the gate trench T1. This increases the gate oxide growth rate at the bottom, allowing the silicon oxide material to grow at a higher growth rate at the bottom of the gate trench T1 than at the sidewall of the gate trench T2 when the gate oxide layer 1081 is grown inside the gate trench T1 using thermal oxidation. Therefore, the thickness of the gate oxide layer 1081 grown at the bottom of the gate trench T1 is greater than that grown at the sidewall of the gate trench T1. This effectively improves the breakdown voltage of the gate oxide layer 1081 in the gate 108, preventing the gate oxide layer 1081 at the bottom of the gate trench T1 from being broken down. This is beneficial for improving the reliability and performance of the semiconductor device.

[0076] S160, the source electrode is formed on the first surface.

[0077] Specifically, see Figure 7 A source electrode 110 is formed on the first surface 101. By depositing metal material on the first surface 101, a flat source electrode 110 is formed on the side away from the first surface 101. The source electrode 110 and the gate electrode 108 are provided with corresponding structures to achieve insulation, and a good ohmic contact is formed between the source electrode 110 and the source trench structure 109.

[0078] S170, a drain electrode is formed on the second surface.

[0079] Specifically, see [link to relevant documentation] Figure 7 A drain 111 is formed on the second surface 102. The drain 111 may include a stack of metals Ti, Ni, and Ag.

[0080] The semiconductor device manufacturing method provided in this application involves forming a gate trench T1 on the first surface 101 of a semiconductor body 100. The gate trench T1 is subjected to two ion implantations with a high implantation energy, resulting in two ion bombardments of the bottom of the gate trench T1, forming a second region 106. This alters the lattice structure of the epitaxial layer 20 in the semiconductor body 100 corresponding to the bottom of the gate trench T1 and reduces the atomic bond energy of the epitaxial layer 20 region corresponding to the bottom, thereby increasing the gate oxide growth rate at the bottom of the gate trench T1. Therefore, when the gate oxide layer 1081 is subsequently grown using thermal oxidation, the thickness of the gate oxide layer 1081 grown at the bottom of the gate trench T1 is greater than the thickness of the gate oxide layer 1081 grown on the sidewall of the gate trench T1. This effectively improves the breakdown voltage of the gate oxide layer 1081 in the gate 108, prevents the gate oxide layer 1081 at the bottom of the gate trench T1 from being broken down, and helps improve the reliability and performance of the semiconductor device.

[0081] Based on the above embodiments, see below. Figure 4 Optionally, when forming a gate trench on the first surface in step S130, the method further includes forming a source trench T2 on the first surface 101.

[0082] Specifically, in a single cell of a semiconductor device, a gate trench T1 can be provided at the center of the cell, and a source trench T2 can be provided on both sides of the gate trench T1; or, the gate trench T1 can be provided only in the semiconductor body 100 of the single cell to obtain a single-trench MOS semiconductor device, which is not limited here. Figure 4 This diagram illustrates a semiconductor device structure in which a gate trench T1 and a source trench T2 are formed in a semiconductor body 100. The gate trench T1 and the source trench T2 can have the same depth, allowing both to be formed simultaneously in a single etching process, thus simplifying the process.

[0083] See also Figure 6 In step S150, forming a gate in the gate trench also includes forming a source trench structure 109 in the source trench T2.

[0084] Specifically, silicon oxide material is grown inside the source trench T2 by thermal oxidation to form an oxide layer 1091 covering the inner wall of the source trench T2; and polycrystalline silicon material is filled inside the oxide layer 1091 to form source polycrystalline silicon 1092, thereby forming the source trench structure 109.

[0085] Figure 8 This is a schematic flowchart of step S140 in a semiconductor device manufacturing method provided in an embodiment of this application. Figures 9 to 10 yes Figure 8 A structural diagram corresponding to each relevant step. See also... Figure 5 , Figures 8 to 10 Optionally, step S140, which involves performing a first ion implantation on the semiconductor body to form a third sub-region and then performing a second ion implantation to form a second region, specifically includes the following steps:

[0086] S141. The first conductive ions are used to perform one ion implantation on the gate trench and the source trench respectively to form a third region and a third sub-region; the third region is located on the periphery of the source trench.

[0087] Specifically, see Figure 9 The first conductive ions are used to implant ions into the gate trench T1 and the source trench T2 once to form the third region 107 and the third sub-region 112; the third region 107 is located on the periphery of the source trench T2.

[0088] S142. A second ion implantation is performed on the gate trench using second conductive ions to form a second region; wherein, the first conductive ion has a second conductivity type, and the second conductive ion has a first conductivity type; the ion concentration in the second region is less than the ion concentration in the third region.

[0089] Specifically, see Figure 10 A second ion implantation is performed on the gate trench T1 using second conductive ions to form a second region 106. The first conductive ions have a second conductivity type, and the second conductive ions have a first conductivity type. The ion concentration in the second region 106 is less than the ion concentration in the third region 107. Exemplarily, in this embodiment, an N-type MOSFET semiconductor device is used as an example. If the semiconductor body 100 is an N-type semiconductor body, then the first conductive ions are P-type conductive ions, and the second conductive ions are N-type conductive ions. P-type conductive ions are used to bombard the gate trench T1 and source trench T2 with higher energy, forming a heavily P-type doped third region 107 around the source trench T2 and a heavily P-type doped third sub-region 112 at the bottom of the gate trench T1. This completes one ion bombardment of the bottom of the gate trench T1. N-type conductive ions are used to bombard the gate trench T1 with high energy to N-type dope the third sub-region 112 corresponding to the bottom of the gate trench T1, neutralizing the implanted P-type conductive ions in the third sub-region 112, thereby forming a P-type doped second region 106. That is, the ion concentration of the formed second region 106 is lower than the ion concentration of the third region 107. This achieves two ion bombardments on the bottom of the gate trench T1, effectively changing the lattice structure of the epitaxial layer 20 corresponding to the bottom of the gate trench T1, reducing atomic bond energies, and improving the gate oxide growth rate at the bottom of the gate trench T1. This results in the thickness of the gate oxide layer 1081 grown at the bottom being greater than the thickness of the gate oxide layer 1081 grown on the sidewalls, thus improving the reliability of the semiconductor device.

[0090] Based on the above embodiments, optionally, step S141, which involves performing ion implantation on the gate trench and the source trench using first conductive ions, includes the following steps:

[0091] Using a first conductive ion with a first atomic radius and a first ion concentration, the gate trench and the source trench are implanted once with a first implantation energy.

[0092] Specifically, a first ion implantation is performed on the gate trench T1 and the source trench T2 using a first conductive ion. For example, the first conductive ion can be an aluminum ion with a first atomic radius. The ion implantation beam used has a first ion concentration, and the gate trench T1 and the source trench T2 are bombarded with ions using a first implantation energy to achieve the first ion implantation.

[0093] Step S142, which involves secondary ion implantation of the gate trench using second conductive ions, includes the following steps:

[0094] A second conductive ion with a second atomic radius and a second ion concentration is used to perform secondary ion implantation on the gate trench with a second implantation energy;

[0095] Wherein, the second atomic radius is greater than the first atomic radius, and the second injection energy is greater than the first injection energy; or, the second atomic radius is less than the first atomic radius, and the second injection energy is less than the first injection energy.

[0096] Specifically, a second conductive ion is used to perform a second ion implantation on the bottom of the gate trench T1. For example, the second conductive ion can be a phosphorus ion with a second atomic radius. The ion implantation beam used has a second ion concentration, and the bottom of the gate trench T1 is bombarded with ions for the second time with a second implantation energy to achieve the second ion implantation.

[0097] It should be noted that, to ensure that the depths of the two ion implantations at the bottom of the gate trench T1 are similar or the same, and that the areas of the two ion implantations overlap, the implantation energy needs to be adjusted according to the different conductive ions used in the two ion implantations. For implanted ions with larger atomic radii, since their penetration power in the epitaxial layer 20 is weaker, the implantation energy should be adjusted to be larger. For example, in this embodiment, the first conductive ion is aluminum ion and the second conductive ion is phosphorus ion. The second atomic radius of the second conductive ion is relatively large, so the second implantation energy should be adjusted to be larger; the first atomic radius of the first conductive ion is relatively small, so the first implantation energy should be adjusted to be smaller. Generally, for example, both the first ion concentration and the second ion concentration are greater than [a certain value]. Both the first and second injection energies are greater than 1000 keV.

[0098] Based on the above embodiments, Figure 11 This is a schematic flowchart of step S130 in a semiconductor device manufacturing method provided in an embodiment of this application. Figures 12 to 13 yes Figure 11 A structural diagram corresponding to each relevant step. See also... Figure 4 , Figures 11 to 13 Optionally, forming a gate trench on the first surface in step S130 specifically includes the following steps:

[0099] S131, forming a gate trench and a source trench on the first surface.

[0100] Specifically, see Figure 12A gate trench T1 and a source trench T2 are formed on the first surface 101.

[0101] S132, A barrier material layer is formed on the first surface.

[0102] Specifically, see Figure 13 A barrier material layer 1051 is formed on the first surface 101. A barrier material is deposited on the first surface 101, where a gate trench T1 and a source trench T2 are provided, to form a complete barrier material layer 1051. The barrier material layer 1051 covers the first surface 101 and the inner walls of the gate trench T1 and the source trench T2.

[0103] S133. Remove the barrier material layer located on the first surface, inside the source trench, and at the bottom of the gate trench, and form a barrier layer on the sidewall of the gate trench.

[0104] Specifically, see [link to relevant documentation] Figure 4 The barrier material layer 1051 located on the first surface 101, inside the source trench T2, and at the bottom of the gate trench T1 is removed, and a barrier layer 105 is formed on the sidewall of the gate trench T1. The barrier material layer 1051 is formed across the entire first surface 101 by depositing silicon nitride material, and then a wet etching process is used to etch away some unnecessary barrier material layers 1051, leaving only the barrier material layer 1051 on the sidewall of the gate trench T1, thus forming the barrier layer 105. This prevents ions from being implanted into the channel region outside the gate trench T1 during subsequent ion implantation, thus affecting the performance of the semiconductor device.

[0105] After performing a first ion implantation on the semiconductor body to form the third sub-region in step S140, and then performing a second ion implantation to form the second region, the following steps are also included:

[0106] Remove the barrier layer located on the sidewall of the gate trench.

[0107] Specifically, see [link to relevant documentation] Figure 5 The barrier layer located on the sidewall of the gate trench T1 is removed. Exemplarily, the barrier layer can be made of silicon nitride. A wet etching process is used to remove the barrier layer formed on the sidewall of the gate trench T1 to facilitate the subsequent fabrication of the gate and source trench structures.

[0108] Based on the above embodiments, Figure 14 This is a schematic diagram illustrating the specific process of another semiconductor device manufacturing method provided in this embodiment of the invention. Figure 15 yes Figure 14 A structural diagram corresponding to the relevant steps. See also... Figure 6 , Figure 7 , Figure 14 and Figure 15Optionally, the method for manufacturing the semiconductor device specifically includes the following steps:

[0109] S210, Provide a semiconductor body; the semiconductor body is configured as a first conductivity type and includes a first surface and a second surface disposed opposite to each other.

[0110] S220. A well region and a first region are formed in the semiconductor body. The first region is configured with a first conductivity type and is located on a first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface.

[0111] S230, A gate trench is formed on the first surface.

[0112] S240. A first ion implantation is performed on the semiconductor body to form a third sub-region, followed by a second ion implantation to form a second region. The second region and the third sub-region are located at the bottom of the gate trench, and the position of the second region is the same as that of the third sub-region. The conductivity type of the implanted ions in the first ion implantation is opposite to that in the second ion implantation.

[0113] S250, A gate is formed in the gate trench.

[0114] S260, An insulating layer is formed on the first surface; the orthogonal projection of the insulating layer onto the semiconductor body completely covers the orthogonal projection of the gate onto the semiconductor body.

[0115] Specifically, see Figure 15 An insulating layer 113 is formed on the first surface 101; the orthogonal projection of the insulating layer 113 onto the semiconductor body 100 completely covers the orthogonal projection of the gate 108 onto the semiconductor body 100. The insulating layer 113 is formed by depositing an insulating material on the first surface 101, such that the insulating layer 113 covers the gate 108, thereby achieving insulation between the gate 108 and the source 110.

[0116] S270, A contact metal layer is formed on the first surface; the contact metal layer covers the insulating layer and the first surface.

[0117] Specifically, see [link to relevant documentation] Figure 6 and Figure 7 A contact metal layer 114 is formed on the first surface 101; the contact metal layer 114 covers the insulating layer 113 and the first surface 101. Exemplarily, the contact metal layer 114 may be deposited using a conductive material that does not react with the source trench structure 109, so that the source 110 and the source trench structure 109 can achieve good ohmic contact.

[0118] S280, A source electrode is formed on the side of the contact metal layer away from the first surface.

[0119] Specifically, see [link to relevant documentation] Figure 7A source electrode 110 is formed on the side of the contact metal layer 114 away from the first surface 101.

[0120] S290, a drain electrode is formed on the second surface.

[0121] This application also provides a semiconductor device. See [link to relevant documentation]. Figure 7 The semiconductor device includes:

[0122] The semiconductor body 100 is configured with a first conductivity type and includes a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body 100 also includes a well region 103 and a first region 104. The first region 104 is configured with the first conductivity type and is located on the first surface 101, and the well region 103 is configured with the second conductivity type and is located on the side of the first region 104 away from the first surface 101. The first surface 101 is provided with a gate trench T1.

[0123] The gate 108 is located inside the gate trench T1; a second region 106 is provided at the bottom of the gate trench T1;

[0124] Source electrode 110 is located on the first surface 101;

[0125] Drain 111 is located on the second surface 102.

[0126] Specifically, after forming the gate trench T1, the bottom of the gate trench T1 is bombarded twice with higher ion energy. This alters the lattice structure of the bottom silicon carbide epitaxial layer, reducing the atomic bond energy and thus increasing the gate oxide growth rate at the bottom of the gate trench T1. When growing the gate oxide layer inside the gate trench T1 using thermal oxidation, the growth rate of silicon oxide at the bottom of the gate trench T1 is greater than that at the sidewalls of the gate trench T2. This results in a thicker gate oxide layer at the bottom of the gate trench T1 than that on the sidewalls, effectively improving the voltage withstand capability of the gate oxide layer in the gate 108, preventing the gate oxide layer at the bottom of the gate trench T1 from being broken down, and ultimately improving the reliability and performance of the semiconductor device.

[0127] Furthermore, after two ion bombardments, a second region 106 with a second conductivity type is formed at the bottom of the gate trench T1. This region can form a space charge region (PN junction) with the epitaxial layer with a first conductivity type in the semiconductor body 100. This avoids the accumulation of sharp charge in the corner region of the gate trench T1, prevents the gate oxide layer from breaking down due to the increase of the electric field in the corner region, and further improves the withstand voltage capability of the gate oxide layer in the gate trench T1, which is beneficial to improving the reliability of the semiconductor device.

[0128] The semiconductor device provided in this application embodiment, by subjecting the gate trench T1 to two ion bombardments with high energy and implanting a second region 106 with a second conductivity type at the bottom of the gate trench T1, can modify the lattice structure of the corresponding silicon carbide epitaxial layer at the bottom, reduce the atomic bond energy of the bottom silicon carbide epitaxial layer, and increase the gate oxide growth rate at the bottom of the gate trench T1. This allows the thickness of the gate oxide layer grown at the bottom of the gate trench T1 to be greater than the thickness of the gate oxide layer grown on the sidewall of the gate trench T1, effectively improving the voltage withstand capability of the gate oxide layer in the gate 108. Furthermore, the second region at the bottom of the gate trench T1 forms a space charge region with the epitaxial layer in the semiconductor body 100, effectively preventing the accumulation of tip charge in the trench corner region, further improving the voltage withstand capability of the gate oxide layer in the gate trench T1, preventing gate oxide breakdown, and thus improving the reliability and performance of the semiconductor device.

[0129] Based on the above embodiments, see below. Figure 6 , Figure 9 and Figure 10 Optionally, the semiconductor device further includes: a source trench T2 and a source trench structure 109;

[0130] The source trench T2 is located on the first surface 101, the source trench structure 109 is located inside the source trench T2, and a third region 107 is provided around the source trench T2.

[0131] The ion concentration in the second region 106 is lower than that in the third region 107.

[0132] Exemplarily, in this embodiment, an N-type MOSFET semiconductor device is still used as an example for explanation. Since the semiconductor body 100 is an N-type semiconductor body, the second conductive ion is an N-type conductive ion. The gate trench T1 is bombarded with N-type conductive ions at higher energy to N-type dope the third sub-region 112 corresponding to the bottom of the gate trench T1, neutralizing the P-type conductive ions implanted in the third sub-region 112, thereby forming a P-type doped second region 106. That is, the ion concentration of the formed second region 106 is less than the ion concentration of the third region 107. This achieves two ion bombardments on the bottom of the gate trench T1, thereby increasing the gate oxide growth rate at the bottom of the gate trench T1, making the thickness of the gate oxide layer 1081 grown at the bottom greater than the thickness of the gate oxide layer 1081 grown on the sidewalls, thus improving the reliability of the semiconductor device.

[0133] Based on the above embodiments, see below. Figure 7 Optionally, the semiconductor device further includes an insulating layer 113 and a contact metal layer 114.

[0134] The insulating layer 113 is located on the first surface 101, and the orthogonal projection of the insulating layer 113 onto the semiconductor body 100 completely covers the orthogonal projection of the gate 108 onto the semiconductor body 100.

[0135] The contact metal layer 114 is located on the first surface 101 and covers the insulating layer 113 and the first surface 101.

[0136] Specifically, by providing an insulating layer 113 on the first surface 101 to cover the gate 108, insulation can be achieved between the gate 108 and the source 110. A contact metal layer 114 is formed on the side of the insulating layer 113 away from the first surface 101 and covers the source trench structure, which can achieve good ohmic contact between the source trench structure and the source 110, thereby improving the performance of the semiconductor device.

[0137] This application provides a power module including a substrate and at least one semiconductor device provided in any of the embodiments of this application, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of this power module including the semiconductor device provided in any of the embodiments of this application will not be elaborated further here.

[0138] This application provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device provided in any of the embodiments of this application, and the semiconductor device is electrically connected to the circuit board.

[0139] Therefore, the beneficial effects of this power conversion circuit, which includes any of the semiconductor devices provided in the embodiments of this application, will not be elaborated further here.

[0140] This application also provides a vehicle, including a load and a power conversion circuit as provided in any embodiment of this application. The power conversion circuit is used to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power and then input it to the load. Therefore, the beneficial effects of this vehicle including the power conversion circuit provided in any embodiment of this application will not be elaborated further here.

[0141] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provide semiconductor body; The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other; A well region and a first region are formed in the semiconductor body. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. A gate trench is formed on the first surface; The semiconductor body is subjected to a first ion implantation to form a third sub-region, and then a second ion implantation is performed to form a second region; the second region and the third sub-region are located at the bottom of the gate trench, and the position of the second region is the same as that of the third sub-region; the conductivity type of the implanted ions in the first ion implantation is opposite to that in the second ion implantation. A gate is formed within the gate trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, When forming the gate trench on the first surface, the method further includes: A source trench is formed on the first surface; The process of performing a first ion implantation on the semiconductor body to form a third sub-region, followed by a second ion implantation to form a second region, includes: The gate trench and the source trench are implanted with first conductive ions to form a third region and a third sub-region; the third region is located on the periphery of the source trench. The gate trench is implanted with a second conductive ion to form the second region; wherein the first conductive ion has the second conductivity type, and the second conductive ion has the first conductivity type; the ion concentration in the second region is less than the ion concentration in the third region.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The step of performing one ion implantation on the gate trench and the source trench using a first conductive ion includes: A first conductive ion with a first atomic radius and a first ion concentration is used to perform one ion implantation on the gate trench and the source trench respectively with a first implantation energy; The second ion implantation of the gate trench using a second conductive ion includes: A second conductive ion with a second atomic radius and a second ion concentration is used to perform secondary ion implantation on the gate trench with a second implantation energy; Wherein, the second atomic radius is greater than the first atomic radius, and the second injection energy is greater than the first injection energy; or, the second atomic radius is less than the first atomic radius, and the second injection energy is less than the first injection energy.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, Both the first ion concentration and the second ion concentration are greater than ; Both the first injection energy and the second injection energy are greater than 1000 keV.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The step of forming a gate trench on the first surface includes: The gate trench and the source trench are formed on the first surface; A barrier material layer is formed on the first surface; Remove the barrier material layer located on the first surface, inside the source trench, and at the bottom of the gate trench, and form a barrier layer on the sidewall of the gate trench; After performing a first ion implantation to form a third sub-region on the semiconductor body, and then performing a second ion implantation to form a second region, the method further includes: Remove the barrier layer located on the sidewall of the gate trench.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before the source electrode is formed on the first surface, the following is also included: An insulating layer is formed on the first surface; the orthogonal projection of the insulating layer onto the semiconductor body completely covers the orthogonal projection of the gate onto the semiconductor body; A contact metal layer is formed on the first surface; the contact metal layer covers the insulating layer and the first surface.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The process of forming a source electrode on the first surface includes: The source electrode is formed on the side of the contact metal layer away from the first surface.

8. A semiconductor device, characterized in that, include: A semiconductor body, configured for a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region, the first region being configured for the first conductivity type and located on the first surface, the well region being configured for the second conductivity type and located on the side of the first region away from the first surface; the first surface is provided with a gate trench. A gate is located inside the gate trench; a second region is provided at the bottom of the gate trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

9. The semiconductor device according to claim 8, characterized in that, Also includes: Source trench and source trench structure; The source trench is located on the first surface, the source trench structure is located inside the source trench, and a third region is provided around the source trench. The ion concentration in the second region is lower than that in the third region.

10. The semiconductor device according to claim 8, characterized in that, Also includes: Insulating layer and contact metal layer; The insulating layer is located on the first surface, and the orthographic projection of the insulating layer onto the semiconductor body completely covers the orthographic projection of the gate onto the semiconductor body. The contact metal layer is located on the first surface and covers the insulating layer and the first surface.

11. A power module, characterized in that, The device includes a substrate and the semiconductor device according to any one of claims 8-10, wherein the substrate is used to support the semiconductor device.

12. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 8-10, wherein the semiconductor device is electrically connected to the circuit board.

13. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 12, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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