Semiconductor device, preparation method of semiconductor device and electronic equipment
By adding a barrier layer to the first electrode of a P-type transistor, the problem of boron diffusion into the channel was solved, hole mobility and device performance were improved, and efficient transistor fabrication was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2026-03-13
AI Technical Summary
When fabricating P-type transistors, boron in a high-concentration boron film layer may diffuse into the channel, leading to a short-channel effect and affecting device performance.
A barrier layer is added to the first electrode of the P-type transistor. The barrier layer covers the area surrounding the first electrode to suppress boron diffusion. Pure silicon or a barrier layer material containing silicon and boron is used, which is process-compatible and low-cost.
It effectively suppressed the diffusion of boron into the channel, improved hole mobility, optimized device performance, and increased the driving current of the transistor.
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Figure CN121665616A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, a semiconductor device packaging structure, an electronic device, and a method for fabricating a semiconductor device. Background Technology
[0002] With the development of integrated circuits, for example, embedded source-drain epitaxial silicon germanium is currently a core technology in 45nm and below processes.
[0003] Embedded source / drain epitaxial silicon-germanium can be understood as creating trenches in a substrate and epitaxially growing silicon-germanium inside and outside the trenches to form the source and drain electrodes. This technology utilizes the stress generated by the lattice mismatch between germanium (Ge) and silicon (Si) to improve hole mobility. Since the lattice constant of Ge is about 4% larger than that of Si, it generates lateral compressive stress in the channel, reducing the lattice constant of Si within the channel and decreasing the effective hole mass, thereby achieving the goal of improving hole mobility.
[0004] However, when using this technology to manufacture transistors, some materials diffuse into the channel, creating a short-channel effect that affects device performance. Summary of the Invention
[0005] This application provides a semiconductor device, a semiconductor device packaging structure, an electronic device including the semiconductor device packaging structure, and a method for fabricating the semiconductor device. The main objective is to suppress the short-channel effect of P-type transistors, improve carrier mobility, and enhance device performance.
[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:
[0007] In one aspect, this application provides a semiconductor device, which may include a memory circuit, a logic circuit, or a digital circuit.
[0008] The semiconductor device includes a substrate and a P-type transistor, the P-type transistor including a first electrode, a second electrode, a channel, and a gate. The substrate has the first electrode, the second electrode, and the channel of the P-type transistor, the channel being located between the first electrode and the second electrode, and the gate being located on the channel. The first electrode includes boron. In addition, the semiconductor device also includes a first film layer and a barrier layer. The first film layer is located on the first electrode and includes boron. The boron content in the first film layer is greater than the boron content in the first electrode. The barrier layer is stacked between the first electrode and the first film layer. The surface of the substrate includes a first region located around the first electrode. The first region can correspond to the channel of the P-type transistor. At least a portion of the first region is covered by the barrier layer. The barrier layer is used to suppress the diffusion of boron in the first film layer into the substrate, for example, to suppress the diffusion of boron in the first film layer into the channel of the P-type transistor.
[0009] In the semiconductor device provided in this application, a first film layer with a high boron content is provided on the first electrode of a P-type transistor. This first film layer can reduce the resistance in the circuit and optimize the device performance. However, in some fabrication processes, after obtaining a first film layer with a high boron concentration, the boron in the first film layer may diffuse into the channel of the P-type transistor, resulting in a short-channel effect. This application adds a barrier layer between the first film layer and the first electrode, and at least part of the first region surrounding the first electrode is covered by the barrier layer, that is, at least part of the channel surrounding the first electrode is covered by the barrier layer. The barrier layer can suppress the diffusion of boron in the first film layer into the channel, thereby suppressing the short-channel effect, improving hole mobility, and optimizing device performance.
[0010] In one possible implementation, the first film layer and the first electrode further include silicon, and the barrier layer includes pure silicon; or; the barrier layer includes silicon and boron, wherein the boron content in the barrier layer is less than the boron content in the first film layer, and the silicon content in the barrier layer is greater than the silicon content in the first film layer; and, the boron content in the barrier layer is less than the boron content in the first electrode, and the silicon content in the barrier layer is greater than the silicon content in the first electrode.
[0011] In some structures, pure silicon is used as a barrier layer. The high concentration of silicon can suppress the diffusion of high boron content from the first film layer into the transistor channel. In other structures, a barrier layer containing both silicon and boron is used. Because the silicon content in this barrier layer is greater than the boron content in the first film layer and the first electrode, and the boron content in the barrier layer is less than the boron content in the first film layer and the first electrode, the diffusion of high boron content from the first film layer into the transistor channel can be effectively suppressed.
[0012] In addition, the barrier layer can be made of pure silicon or materials containing silicon and boron. The process is easy to implement, compatible with the fabrication process of P-type transistors, does not increase the process steps, and has a relatively low manufacturing cost.
[0013] In one possible implementation, the first pole includes: an embedded portion located in a substrate, and a protruding portion protruding from the surface of the substrate, the first region surrounding the protruding portion; the peripheral side surface of the protruding portion and the surface facing away from the substrate are both covered by a barrier layer; the barrier layer located on the peripheral side surface of the protruding portion extends to and covers the first region.
[0014] Since the barrier layer located on the peripheral side of the protrusion extends to a first region on the substrate surface, which corresponds to the channel of the transistor, that is, part of the channel in the substrate is covered by the barrier layer, the diffusion of high concentrations of boron in the first film layer into the channel can be suppressed.
[0015] In one possible implementation, the peripheral side of the protrusion near the gate is tilted away from the gate.
[0016] This allows for the fabrication of the first electrode using epitaxial growth technology, a simple and easily implemented process.
[0017] In one feasible manner, the thickness of the barrier layer located in the first region on the substrate surface is greater than the thickness of the barrier layer located on the first electrode.
[0018] In this structure, the thickness of the barrier layer on the substrate surface is greater than the thickness of the barrier layer on the first electrode, which can suppress the diffusion of boron in the first film layer into the channel.
[0019] In one feasible approach, the first membrane layer and the first region are separated by a barrier layer.
[0020] This can be understood as: the first film layer stacked on the barrier layer does not contact the first region of the substrate.
[0021] For example, when preparing the first film layer, a deposition process is used to prepare the first film layer on the surface of the barrier layer. The first film layer cannot extend to the substrate surface to avoid the diffusion of boron in the first film layer into the trench located on the substrate.
[0022] In one possible implementation, the first electrode further includes silicon and germanium, and the first electrode includes: a stacked first sub-electrode layer and a second sub-electrode layer, the first sub-electrode layer being closer to the channel than the second sub-electrode layer; the germanium content in the second sub-electrode layer being greater than the germanium content in the first sub-electrode layer; and the boron content in the second sub-electrode layer being greater than the boron content in the first sub-electrode layer.
[0023] The first sub-electrode layer can be considered as a buffer layer, and the second sub-electrode layer can be considered as a stress application layer. The buffer layer can increase the stress value applied to the channel by the second sub-electrode layer, further improving the channel carrier mobility and increasing the drive current of the P-type transistor.
[0024] In one possible implementation, the barrier layer comprises silicon and boron, wherein the boron content in the barrier layer is less than the boron content in the second sub-electrode layer, and the silicon content in the barrier layer is greater than the silicon content in the second sub-electrode layer.
[0025] When the barrier layer contains silicon and boron, the barrier layer can suppress the diffusion of boron from the first film layer into the channel by having a lower boron content in the barrier layer than in the second sub-electrode layer and a higher silicon content in the barrier layer than in the second sub-electrode layer.
[0026] In one feasible manner, the radial dimension of the first pole first increases and then decreases from the bottom to the top surface of the first pole.
[0027] In some feasible processes, trenches can be formed in the substrate, with the radial dimension of the trench first increasing and then decreasing from the bottom surface to the opening direction. Such a trench structure can be called a sigma trench. Filling the sigma trench with a first electrode can cause the germanium-silicon first electrode of the structure to apply stress to the channel.
[0028] In one possible implementation, the semiconductor device further includes: a first gate sidewall and a second gate sidewall, the first gate sidewall and the second gate sidewall being stacked sequentially on the peripheral side surface of the gate; the peripheral side surface of the first film layer and the peripheral side surface of the barrier layer are both in contact with the second gate sidewall.
[0029] In one example, the materials of the first gate sidewall and the second gate sidewall can be the same or different.
[0030] Secondly, this application also provides a semiconductor device packaging structure, which includes a substrate and a semiconductor device as described in any of the above implementations, wherein the semiconductor device is disposed on the substrate.
[0031] In the semiconductor device packaging structure provided in this application, the semiconductor device integrated on the substrate has a barrier layer added between the first film layer and the first electrode. At least part of the first region surrounding the first electrode is covered by the barrier layer, that is, the channel is covered by the barrier layer. The barrier layer can suppress the diffusion of boron in the first film layer into the channel. In this way, the short-channel effect can be suppressed, the hole mobility can be improved, the device performance can be optimized, and the performance of the semiconductor device packaging structure can be improved.
[0032] Thirdly, this application also provides an electronic device, which includes a circuit board and a semiconductor device packaging structure as described in any of the above implementations, wherein the semiconductor device packaging structure is disposed on the circuit board.
[0033] The electronic device provided in this application includes a semiconductor device in any of the above implementations, including a barrier layer disposed between a first film layer and a first electrode. The barrier layer can suppress the diffusion of boron in the first film layer into the channel, thereby suppressing the short-channel effect, improving hole mobility, and optimizing device performance.
[0034] Fourthly, this application also provides a method for fabricating a semiconductor device, the method comprising:
[0035] Trenches are formed in the electrode region of the substrate, and the electrode region is used to form the first electrode of the P-type transistor;
[0036] The first electrode of a P-type transistor is formed within the trench, and the first electrode includes boron;
[0037] A barrier layer is formed on the first electrode, and at least a portion of the substrate surface and the area surrounding the first electrode is covered by the barrier layer;
[0038] A first film layer is formed on the barrier layer. The first film layer includes boron, and the boron content in the first film layer is greater than the boron content in the first electrode. The barrier layer is used to suppress the diffusion of boron in the first film layer into the channel of the P-type transistor.
[0039] When using this method to fabricate a P-type transistor in a semiconductor device, a barrier layer is first fabricated before the first film layer containing a high boron content is fabricated, and the corresponding channel region of the substrate is covered by the barrier layer. In this way, after the first film layer is fabricated, the high boron content in the first film layer will not diffuse into the channel, thus preventing a short-channel effect from occurring in the channel.
[0040] In one feasible approach, the fabrication method further includes, before creating a trench in the electrode region of the substrate used to form the first electrode of the P-type transistor:
[0041] A first mask layer and a second mask layer are formed. The first mask layer includes silicon oxide. The electrode region surface of the substrate is covered by the first mask layer. The second mask layer is located on the side of the first mask layer away from the substrate.
[0042] After creating trenches in the electrode region of the substrate used to form the first electrode of the P-type transistor, the fabrication method further includes:
[0043] The inner wall of the trench is cleaned, and the portion of the first mask layer near the trench is cleaned away, exposing the surface of the substrate near the trench.
[0044] For example, after trenches are created, silicon dioxide will be generated on the inner wall of the trench due to natural oxidation. Therefore, the silicon dioxide in the trench needs to be cleaned. During the cleaning process, part of the first mask layer of the silicon dioxide layer will also be cleaned away.
[0045] In one feasible approach, cleaning the inner wall surface of the trench includes:
[0046] The inner wall of the trench is cleaned with a gas containing ammonia and hydrogen fluoride, which removes the silicon oxide on the inner wall of the trench and the silicon oxide of the first mask layer near the trench.
[0047] In one feasible manner, forming the first electrode of a P-type transistor within the trench includes:
[0048] The first sub-electrode layer is formed within the trench;
[0049] A second sub-electrode layer is fabricated on the first sub-electrode layer. The germanium content in the second sub-electrode layer is greater than that in the first sub-electrode layer, and the boron content in the second sub-electrode layer is greater than that in the first sub-electrode layer.
[0050] The first sub-electrode layer can be considered as a buffer layer, and the second sub-electrode layer can be considered as a stress application layer. The buffer layer can increase the stress value applied to the channel by the second sub-electrode layer, further improving the channel carrier mobility and increasing the drive current of the P-type transistor. Attached Figure Description
[0051] Figure 1 This is a partial structural diagram of an electronic device as exemplified in this application;
[0052] Figure 2 This is a partial structural diagram of a semiconductor device provided in an embodiment of this application;
[0053] Figure 3 This is a partial structural diagram of a P-type transistor in a semiconductor device provided in an embodiment of this application;
[0054] Figure 4 A top view of the first electrode of a P-type transistor in a semiconductor device provided in an embodiment of this application;
[0055] Figures 5 to 14 A process structure diagram corresponding to some steps in the fabrication process of a semiconductor device provided in an embodiment of this application;
[0056] Figure 15 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;
[0057] Figure 16 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;
[0058] Figure 17 A structural diagram of a trench for filling the first electrode of a P-type transistor provided in an embodiment of this application;
[0059] Figure 18 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.
[0060] Figure label:
[0061] 100 - Circuit board; 200 - Substrate; 300 - Semiconductor device; 400 - Electrical connection structure; 11 - First electrode; 12 - Second electrode; 13 - Channel; 14 - Gate; 15 - First film layer; 16 - Barrier layer; 17 - First gate sidewall; 18 - Second gate sidewall; 111 - First sub-electrode layer; 112 - Second sub-electrode layer; 11A - Embedded portion; 11B - Protruding portion;
[0062] 20 - Silicon oxide layer; 21 - Polycrystalline silicon hard mask layer; 22 - Hard mask silicon oxide layer; 23 - Hard mask silicon nitride layer; 24 - Trench; 25 - Notch. Detailed Implementation
[0063] The following embodiments of this application will be described in conjunction with the accompanying drawings.
[0064] The technical solutions of this application can be applied to various electronic devices employing semiconductor devices. For example, the electronic devices in the embodiments of this application can be mobile phones, tablets, laptops, smart home devices, smart wearable devices (e.g., smartwatches, smart bracelets, smart glasses, smart helmets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, etc. The electronic devices can also be handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, electronic devices in 5G networks, or electronic devices in future evolved public land mobile networks (PLMNs), etc. The embodiments of this application are not limited in this regard.
[0065] like Figure 1 As shown, the aforementioned electronic device may include a circuit board 100, such as a printed circuit board (PCB), on which a semiconductor device package structure is disposed. The semiconductor device package structure can be electrically connected to the circuit board 100 via an electrical connection structure 400, thereby enabling the semiconductor device package structure to achieve signal interconnection with other chips or other electronic modules on the circuit board 100.
[0066] In alternative implementations, the electrical connection structure 400 may include a plurality of solder balls, such as a ball grid array (BGA), or a plurality of metal pillars.
[0067] In some examples, such as Figure 1 The semiconductor device packaging structure includes multiple semiconductor devices 300, which are disposed on a substrate 200, for example, on a packaging substrate. The substrate 200 is disposed on a circuit board 100 via an electrical connection structure 400.
[0068] Figure 1 The semiconductor device 300 shown can be a single chip or multiple chips stacked in three dimensions.
[0069] In some implementation structures, the semiconductor device 300 may include memory, logic circuits, system on chip (SOC), or analog chips, digital chips, etc.
[0070] The semiconductor device shown above may contain multiple transistors. For example, when the semiconductor device is a memory, the memory cell may be a 6T memory cell, or it may be a 4T2C memory cell.
[0071] A semiconductor device may include a plurality of electrically connected P-type transistors; or, a plurality of electrically connected N-type transistors; or, a plurality of electrically connected P-type transistors and N-type transistors.
[0072] For example, in a P-type transistor, the application of compressive stress along the channel length can reduce the lattice constant of silicon in the channel, decrease the effective hole mass, thereby increasing the hole mobility, which will increase the drive current of the P-type transistor and optimize circuit performance.
[0073] However, during the fabrication of P-type transistors, some materials in the film structure diffuse into the channel of the P-type transistor, resulting in a short-channel effect and degrading the performance of the P-type transistor.
[0074] This application provides several methods for applying compressive stress to the channel of a P-type transistor and suppressing the diffusion of certain materials into the channel. Specific implementation methods are described below.
[0075] Figure 2 This is a partial structural schematic diagram of a semiconductor device according to an embodiment of this application. The semiconductor device includes: a substrate and a plurality of transistors; Figure 2 The example shows one P-type transistor (PMOS) and two N-type transistors (NMOS). Figure 2 This is one example, and of course it can include more transistors.
[0076] See Figure 2 The P-type transistor in this application includes a first electrode 11, a second electrode 12, a channel 13, and a gate 14. For example, one of the first electrode 11 and the second electrode 12 can be the drain and the other can be the source.
[0077] The first electrode 11, the second electrode 12 and the channel 13 are located in the substrate, the channel 13 is located between the first electrode 11 and the second electrode 12, and the gate 14 is located on the channel 13. For example, the gate 14 can be fabricated by epitaxial growth technology.
[0078] In the P-type transistor of this application example, the first electrode 11 may include boron B, for example, it may include silicon Si, germanium Ge, and boron B, such as a SiGe material containing boron B. The second electrode 12 may also include silicon Si, germanium Ge, and boron B, such as a SiGe material containing boron B.
[0079] Due to the lattice constant of germanium (Ge) The lattice constant of silicon Si Approximately 4% increase will have the following effect on channel 13: Figure 2 The transverse compressive stress F shown reduces the Si lattice constant in channel 13, decreases the effective hole mass, and thus improves the hole mobility.
[0080] Figure 3 A detailed schematic diagram of the structure of the first electrode 11, gate 14, and other films in a P-type transistor is shown. At least a portion of the first electrode 11 is located in the substrate, and the P-type transistor also includes a first film layer 15 and a barrier layer 16, the first film layer 15 being located on the first electrode 11, and the barrier layer 16 being stacked between the first electrode 11 and the first film layer 15.
[0081] The first film layer 15 includes boron (B), for example, silicon (Si) and boron (B). The boron (B) content in the first film layer 15 is greater than the boron (B) content in the first electrode 11. The first film layer 15 is electrically coupled to the first electrode 11. Because the first film layer 15 has a higher content (or concentration) of boron (B), the resistance of the circuit containing the P-type transistor can be effectively reduced, thus optimizing the circuit performance.
[0082] In some examples of this application, the boron content in the first film layer 15 is greater than the boron content in the first electrode 11. This can be understood as follows: in the first film layer, the boron content = number of boron B atoms / (number of boron B atoms + number of silicon Si atoms); in the first electrode, the boron content = number of boron B atoms / (number of boron B atoms + number of silicon Si atoms + number of germanium Ge atoms).
[0083] In some examples, the boron content in the first film layer 15 is greater than the boron content in the first electrode 11. This can be understood as: the proportion of boron atoms in the first film layer 15 is greater than the proportion of boron atoms in the first electrode 11; or, the boron concentration in the first film layer 15 is greater than the boron concentration in the first electrode 11.
[0084] See Figure 3 The approximate extent of the channel 13 of the P-type transistor is simply shown in the substrate using a dashed box. Of course, Figure 3 This is one example.
[0085] like Figure 3 and Figure 4 As shown, Figure 4 It shows Figure 3A top view of the first electrode 11 and the first region. The surface of the substrate includes a first region located around the first electrode 11, which can be understood as the first region circumferentially surrounding the first electrode 11, see [reference]. Figure 3 In the substrate, the channel 13 of the P-type transistor corresponds to the location of the first region. In this example, at least a portion of the first region is covered by a barrier layer 16.
[0086] The first region is at least partially covered by the blocking layer 16, which can be understood as: part or all of the first region is covered by the blocking layer 16.
[0087] In addition, the barrier layer 16 is used to suppress the diffusion of boron B in the first film layer 15 into the substrate. For example, the barrier layer 16 is used to suppress the diffusion of boron B in the first film layer 15 into the channel 13 of the P-type transistor.
[0088] The barrier layer 16 can suppress the diffusion of boron (B) from the first film layer 15 into the channel 13 of the P-type transistor. This can be understood as follows: in some structures, the barrier layer 16 can completely suppress the diffusion of boron (B) from the first film layer 15 into the channel 13 of the P-type transistor, and boron (B) is essentially absent in the channel 13; or, in other structures, the barrier layer 16 can have a strong suppressive effect, and a small amount of boron (B) will exist in the channel 13, but this small amount of boron (B) will not cause a short-channel effect. The following explanation, in conjunction with the accompanying drawings, explains how to fabricate the barrier layer 16. Figure 3 The structure shown illustrates how the barrier layer 16 can be used to suppress the diffusion of boron B from the first film layer 15 into the substrate.
[0089] like Figure 5 A gate 14 and a first gate sidewall 17 are fabricated on a substrate, with the first gate sidewall 17 formed on the peripheral side surface of the gate 14.
[0090] For example, if the substrate is a silicon substrate, it will naturally oxidize into a silicon oxide layer 20 on the substrate surface.
[0091] Among the available materials, the gate 14 can be a conductive material, such as a metallic material. In alternative embodiments, it can be one or more of the following conductive materials: TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), InTiO (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).
[0092] Among a number of selectable materials, the first gate sidewall 17 may be a dielectric material, such as a dielectric material with a high dielectric constant. For example, it could be silicon nitride.
[0093] The first gate sidewall 17 can have a protective function, controlling the distance from the channel when ions are implanted into the substrate to form the channel, thereby suppressing the short-channel effect.
[0094] In some selectable processes, such as Figure 5 A polysilicon hard mask layer 21 of a certain thickness can be formed on top of the gate 14. The polysilicon hard mask layer 21 serves as a sacrificial layer to protect the gate 14 in subsequent processes.
[0095] like Figure 6 Hard mask silicon oxide layer 22 and hard mask silicon nitride layer 23 are formed. For example, hard mask silicon oxide layer 22 and hard mask silicon nitride layer 23 are prepared by epitaxial growth technology.
[0096] The hard mask silicon oxide layer 22 serves as a buffer layer between the hard mask silicon nitride layer 23 and the first sidewall 17, allowing for better fabrication of the hard mask silicon nitride layer 23. For example, a hard mask silicon oxide layer 22 with a thickness of 1 nm to 6 nm can be deposited using CVD.
[0097] In some processes, a hard mask silicon nitride layer with a thickness of 5 nm to 30 nm can be deposited using a furnace tube.
[0098] See Figure 6 The silicon oxide layer located on the substrate surface includes Figure 5 The naturally oxidized silicon oxide layer 20 shown, and Figure 6 The hard mask silicon oxide layer 22 is formed.
[0099] like Figure 7 Trench 24 is formed in the substrate in the source and drain regions used to form P-type transistors. For example, the trench 24 can be formed by dry etching or wet etching.
[0100] For example, dry etching can use at least one of the following gases: chlorine, hydrogen chloride, hydrogen bromide, carbon tetrafluoride, and nitrogen trifluoride. The etching time can be 50-150 seconds.
[0101] For another example, wet etching can use tetramethylammonium hydroxide. The etching time can be 100s-400s.
[0102] See Figure 7 When etching trench 24, the hard mask silicon nitride layer 23 and silicon oxide layer (including hard mask silicon oxide layer 22 and naturally oxidized silicon oxide layer 20) located on the substrate surface will be etched away.
[0103] like Figure 8 In such Figure 7 After the trench 24 is etched, for example, when the substrate is a silicon substrate, the inner wall of the trench 24 will be oxidized to form silicon oxide.
[0104] To improve the performance of the P-type transistor, the inner wall of the trench 24 needs to be cleaned before the source and drain are fabricated in the trench 24 to remove the silicon oxide adhering to the wall of the trench 24.
[0105] like Figure 9 Clean the inner wall of groove 24.
[0106] In some alternative processes, gases containing hydrogen fluoride (HF) and ammonia (NH3) can be used to remove silicon oxide from the inner wall surface of trench 24.
[0107] See Figure 9 When cleaning the silicon oxide on the inner wall of trench 24, since the side of the silicon oxide layer in contact with the substrate is exposed, the silicon oxide layer at the bottom of the hard mask silicon nitride layer 23 that is in contact with the substrate will also be cleaned away, thereby forming... Figure 9 The notch 25 shown. The formation of notch 25 exposes part of the substrate surface.
[0108] The exposed substrate likely corresponds to channel 13 of a P-type transistor. If... Figure 10 The method shown, which continues to fabricate the source and drain of the P-type transistor and the first film layer 15, presents some technical problems.
[0109] like Figure 10 The first electrode 11 of the P-type transistor is formed in the trench 24, and the first film layer 15 is formed on the first electrode 11.
[0110] Because the first film layer 15 has a high boron content, the high boron content will diffuse into the substrate through the notch 25, for example, into the channel 13 of the P-type transistor, resulting in a short-channel effect and degrading the transistor performance.
[0111] To suppress the diffusion of high boron (B) content into the substrate through notch 25, an example of this application may employ... Figure 11 and Figure 12 The method shown.
[0112] like Figure 11 A first electrode 11 of a P-type transistor is formed in the trench 24, and a barrier layer 16 is formed on the first electrode 11.
[0113] The barrier layer 16 covers the substrate surface, which can be understood as: at least the exposed area of the substrate located around the first electrode 11 (that is, the aforementioned...) Figure 3 and Figure 4 The first area is covered by the barrier layer 16.
[0114] like Figure 12 A first film layer 15 is formed on the barrier layer 16.
[0115] Because a barrier layer 16 is formed before the first film layer 15 is formed, and the barrier layer 16 covers some exposed areas of the substrate surface, the high boron content in the first film layer 15 will not diffuse into the substrate or into the channel of the P-type transistor. Therefore, in the fabrication of the P-type transistor in this application example, as... Figure 9 As shown, the presence of the notch 25 will not expose the channel in the substrate, thus preventing the boron B in the first film layer 15 from diffusing into the channel of the P-type transistor.
[0116] In some processes, the polysilicon hard mask layer 21, the hard mask silicon oxide layer 22, and the hard mask silicon nitride layer 23 are removed to obtain a product as shown in the figure. Figure 13 The structure shown.
[0117] For example, wet etching can use phosphoric acid treatment for 200s-500s to remove the hard mask silicon nitride layer 23 and polysilicon hard mask layer 21; wet etching can use HF to remove the hard mask silicon oxide layer 22.
[0118] like Figure 14 A second gate sidewall 18 is formed on the side of the first gate sidewall 17.
[0119] Among a number of selectable materials, the second gate sidewall 18 may be a dielectric material, such as a dielectric material with a high dielectric constant. For example, it could be silicon nitride.
[0120] The materials of the first gate sidewall 17 and the second gate sidewall 18 can be the same or different.
[0121] In this application example, the barrier layer 16 can be made of a variety of materials.
[0122] For example, the barrier layer 16 can be made of metal. A barrier layer 16 made of metal can achieve electrical coupling between the first electrode 11 and the first film layer 15.
[0123] For example, the barrier layer 16 is pure silicon (Pure Si). Pure silicon can be understood as having a silicon content that is close to 100%, or at least 98% or more. In some structures, the barrier layer 16 covering the first electrode 11 can be relatively thin, thus enabling electrical coupling between the first electrode 11 and the first film layer 15. For example, the thickness of the barrier layer 16 covering the first electrode 11 can be 2 nm or more.
[0124] For example, the barrier layer 16 includes silicon Si and boron B. The barrier layer 16, which includes silicon Si and boron B, is conductive, allowing the first electrode 11 to be electrically coupled to the first film layer 15.
[0125] When the barrier layer 16 comprises silicon (Si) and boron (B), the boron content in the barrier layer 16 is less than the boron content in the first film layer 15, and the silicon content in the barrier layer 16 is greater than the silicon content in the first film layer 15; and the boron content in the barrier layer 16 is less than the boron content in the first electrode 11, and the silicon content in the barrier layer 16 is greater than the silicon content in the first electrode 11.
[0126] In this application example, in the barrier layer 16, the boron B content = the number of boron B atoms / (the number of boron B atoms + the number of silicon Si atoms), and the silicon Si content = the number of silicon Si atoms / (the number of boron B atoms + the number of silicon Si atoms); in the first film layer, the boron B content = the number of boron B atoms / (the number of boron B atoms + the number of silicon Si atoms), and the silicon Si content = the number of silicon Si atoms / (the number of boron B atoms + the number of silicon Si atoms); in the first electrode, the boron B content = the number of boron B atoms / (the number of boron B atoms + the number of silicon Si atoms + the number of germanium Ge atoms), and the silicon Si content = the number of silicon Si atoms / (the number of boron B atoms + the number of silicon Si atoms + the number of germanium Ge atoms).
[0127] In some examples, the boron content in the barrier layer 16 is less than the boron content in the first film layer 15. This can be understood as: the proportion of boron atoms in the barrier layer 16 is less than the proportion of boron atoms in the first film layer 15, or the boron concentration in the barrier layer 16 is less than the boron concentration in the first film layer 15.
[0128] In some feasible structures, such as Figure 15 The first electrode 11 of the P-type transistor may include a stacked first sub-electrode layer 111 and a second sub-electrode layer 112, wherein the first sub-electrode layer 111 is closer to the channel 13 of the P-type transistor than the second sub-electrode layer 112. In the fabrication process, the first sub-electrode layer 111 can be fabricated first, and then the second sub-electrode layer 112 can be fabricated on the first sub-electrode layer 111.
[0129] The first sub-electrode layer 111 includes silicon (Si), germanium (Ge), and boron (B); the second sub-electrode layer 112 includes silicon (Si), germanium (Ge), and boron (B).
[0130] The germanium (Ge) content in the second sub-electrode layer 112 is greater than the germanium (Ge) content in the first sub-electrode layer 111, and the boron (B) content in the second sub-electrode layer 112 is greater than the boron (B) content in the first sub-electrode layer 111.
[0131] The germanium (Ge) content in the first sub-electrode layer 111 is less than that in the second sub-electrode layer 112, and the boron (B) content in the first sub-electrode layer 111 is less than that in the second sub-electrode layer 112. The first sub-electrode layer 111 can be considered a buffer layer, and the second sub-electrode layer 112 can be considered a stress-applying layer. The buffer layer can increase the stress applied to the channel by the second sub-electrode layer 112, further improving the channel carrier mobility and increasing the drive current of the P-type transistor. For example, the on-state current of the semiconductor device can be increased by 50%.
[0132] When Figure 15 The first electrode 11 shown includes a stacked first sub-electrode layer 111 and a second sub-electrode layer 112. When the barrier layer 16 comprises silicon and boron, the boron (B) content in the barrier layer 16 is less than the boron content in the second sub-electrode layer 112, and the silicon content in the barrier layer 16 is greater than the silicon content in the second sub-electrode layer 112. In this way, the barrier layer 16 does not affect the function of the first electrode 11, and the barrier layer 16 also serves to suppress the diffusion of boron from the first film layer 15 into the channel.
[0133] like Figure 16 As shown, Figure 16 The example illustrates another P-type transistor structure, in which the first electrode 11 may include an embedded portion 11A located in a substrate, and a protruding portion 11B protruding from the substrate surface. The peripheral side surface and the surface of the protruding portion 11B facing away from the substrate are both covered by a barrier layer 16; and the barrier layer 16 located on the peripheral side surface of the protruding portion 11B extends to the substrate surface, for example, to a first region of the substrate (the region surrounding the periphery of the protruding portion 11B), and the barrier layer 16 covers the first region.
[0134] In making Figure 16 When the first pole 11 shown includes the embedded portion 11A and the protruding portion 11B, the embedded portion 11A and the protruding portion 11B can be obtained by epitaxial growth process.
[0135] See you later Figure 16 The protruding portion 11B of the first electrode 11 is inclined in the direction away from the gate 14 near the peripheral side of the gate 14, so that the thickness of the barrier layer 16 on the substrate is greater than the thickness of the barrier layer 16 on the first electrode 11.
[0136] See you later Figure 16 The first film layer 15 stacked on the barrier layer 16 does not contact the substrate surface. The peripheral side surface of the first film layer 15 can contact the second gate sidewall 18, and the peripheral side surface of the barrier layer 16 can contact the second gate sidewall 18.
[0137] In other examples, other film structures may be provided between the peripheral side of the first film layer 15 and the second gate sidewall 18, and other film structures may be provided between the peripheral side of the barrier layer 16 and the second gate sidewall 18.
[0138] In some possible implementations, the trench used to house the first pole 11 can have various shapes; for example, it can be a rectangular trench; or, for example, it can be... Figure 17 The trench structure shown.
[0139] exist Figure 17 In the shown trench 24 structure, from the bottom surface of the trench 24 to the opening direction (e.g. along the P direction), the radial dimension of the trench 24 (e.g., the dimension along the L direction) first increases and then decreases.
[0140] For example, trench 24 has opposing first inner walls S1 and second inner walls S2, and opposing third inner walls S3 and fourth inner walls S4. The first inner wall S1 and third inner wall S3 are connected, and the second inner wall S2 and fourth inner wall S4 are connected. From the bottom surface of trench 24 to the opening direction (e.g., along the P direction), the first inner wall S1 and second inner wall S2 are inclined towards the outside of trench 24, while the third inner wall S3 and fourth inner wall S4 are inclined towards the inside of trench 24. Such a trench structure can be referred to as a sigma-shaped trench. The sigma-shaped trench shape facilitates the application of stress from the germanium-silicon of the first electrode to the channel, improving the carrier mobility of the channel. For example, the on-state current of the semiconductor device can be increased by 50%.
[0141] Thus, the first pole 11 is formed from the bottom surface to the top surface (e.g.) Figure 17 (in the P direction), the radial direction of the first pole 11 (such as...) Figure 17 The dimension in the L direction first increases and then decreases.
[0142] Based on the different structures of semiconductor devices and the corresponding fabrication methods described above, the following can be followed: Figure 18 The process flow diagram shown is obtained.
[0143] Step S1: Create trenches in the electrode region of the substrate. The electrode region is used to form the first electrode of the P-type transistor.
[0144] The first electrode can be either the source or the drain of a P-type transistor.
[0145] In some selectable processes, trenches can be obtained by etching the source and drain regions of the substrate using either dry or wet etching.
[0146] For example, the trench can be a sigma trench, which is beneficial for the first electrode of the P-type transistor to apply stress to the channel.
[0147] In some processes, the fabrication method may also include the following steps before creating trenches in the electrode region of the substrate:
[0148] The gate of a P-type transistor is fabricated on a substrate;
[0149] A first mask layer and a second mask layer are formed. The first mask layer includes silicon oxide. The electrode region surface of the substrate is covered by the first mask layer. The second mask layer is located on the side of the first mask layer away from the substrate. The surface and side of the gate are also covered by the first mask layer and the second mask layer. The second mask layer may include silicon nitride.
[0150] In some structures, when the substrate is a silicon substrate, after trenches are opened in the electrode region of the substrate, silicon oxide will be formed on the inner wall of the trenches. Therefore, the silicon oxide on the inner wall of the trenches can be removed by epitaxial in-situ pre-cleaning process.
[0151] For example, a gas containing ammonia and hydrogen fluoride can be used to clean the inner wall of the trench, thereby removing the silica from the inner wall of the trench.
[0152] In addition, the portion of the first mask layer of silicon oxide near the trench will also be washed away, exposing the surface of the substrate near the trench.
[0153] Step S2: Form the first electrode of the P-type transistor within the trench. The first electrode includes boron. For example, the first electrode includes silicon, germanium, and boron.
[0154] When performing step S2, the process may include: forming a first sub-electrode layer in the trench; forming a second sub-electrode layer on the first sub-electrode layer, wherein the germanium content in the second sub-electrode layer is greater than the germanium content in the first sub-electrode layer, and the boron content in the second sub-electrode layer is greater than the boron content in the first sub-electrode layer.
[0155] The first sub-electrode layer acts as a buffer layer, allowing the second sub-electrode layer to better apply stress to the channel.
[0156] The first electrode is fabricated using an epitaxial growth process. The first electrode protrudes from the substrate surface, forming a protruding portion on the substrate surface.
[0157] Step S3: A barrier layer is formed on the first electrode, and at least a portion of the substrate surface and the area surrounding the first electrode is covered by the barrier layer.
[0158] When the substrate surface has a protrusion, the barrier layer covers the protrusion and extends from the peripheral side of the protrusion to the substrate surface, thus covering the substrate surface corresponding to the channel.
[0159] For example, the barrier layer is a pure silicon layer, or a layer structure including silicon and germanium.
[0160] Step S4: A first film layer is formed on the barrier layer. The first film layer includes boron, and the boron content in the first film layer is greater than the boron content in the first electrode. The barrier layer is used to suppress the diffusion of boron in the first film layer into the channel of the P-type transistor. For example, the first film layer includes silicon and boron.
[0161] When fabricating a P-type transistor in a semiconductor device using the method described in this application, although the area corresponding to the channel of the substrate will be exposed when cleaning the silicon oxide on the inner wall of the trench, the exposed area can be covered by adding a barrier layer to prevent the high boron content in the subsequent first film layer from diffusing into the channel.
[0162] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0163] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A P-type transistor includes a first electrode, a second electrode, a channel, and a gate. The first electrode, the second electrode, and the channel are located in the substrate. The channel is located between the first electrode and the second electrode. The gate is located on the channel. The first electrode includes boron. A first membrane layer is located on the first electrode, and the first membrane layer includes boron, wherein the boron content in the first membrane layer is greater than the boron content in the first electrode. A barrier layer is stacked between the first electrode and the first film layer, and the surface of the substrate includes a first region located around the first electrode, the first region being at least partially covered by the barrier layer. The barrier layer is used to suppress the diffusion of boron in the first film layer into the channel of the P-type transistor.
2. The semiconductor device according to claim 1, characterized in that, The first film layer and the first electrode also include silicon; The barrier layer comprises pure silicon; or; The barrier layer comprises silicon and boron; The boron content in the barrier layer is less than the boron content in the first film layer, and the silicon content in the barrier layer is greater than the silicon content in the first film layer; as well as, The boron content in the barrier layer is less than the boron content in the first electrode, and the silicon content in the barrier layer is greater than the silicon content in the first electrode.
3. The semiconductor device according to claim 1 or 2, characterized in that, The first electrode includes: an embedded portion located in the substrate, and a protruding portion protruding from the surface of the substrate, the first region surrounding the protruding portion; The peripheral side surface of the protruding portion and the surface facing away from the substrate are both covered by the barrier layer; The barrier layer located on the peripheral side of the protrusion extends into the first region and covers the first region.
4. The semiconductor device according to claim 3, characterized in that, The protruding portion is inclined in the direction away from the gate on its peripheral side near the gate.
5. The semiconductor device according to claim 3 or 4, characterized in that, The thickness of the barrier layer located in the first region is greater than the thickness of the barrier layer located on the first pole.
6. The semiconductor device according to any one of claims 1-5, characterized in that, The first membrane layer and the first region are separated by the barrier layer.
7. The semiconductor device according to any one of claims 1-6, characterized in that, The first electrode also includes silicon and germanium; The first electrode includes: a stacked first sub-electrode layer and a second sub-electrode layer, wherein the first sub-electrode layer is closer to the channel than the second sub-electrode layer; The germanium content in the second sub-electrode layer is greater than the germanium content in the first sub-electrode layer; and, The boron content in the second sub-electrode layer is greater than the boron content in the first sub-electrode layer.
8. The semiconductor device according to claim 7, characterized in that, The barrier layer comprises silicon and boron, wherein the boron content in the barrier layer is less than the boron content in the second sub-electrode layer, and the silicon content in the barrier layer is greater than the silicon content in the second sub-electrode layer.
9. The semiconductor device according to any one of claims 1-8, characterized in that, From the bottom surface to the top surface of the first pole, the radial dimension of the first pole first increases and then decreases.
10. The semiconductor device according to any one of claims 1-9, characterized in that, The semiconductor device further includes: a first gate sidewall and a second gate sidewall, wherein the first gate sidewall and the second gate sidewall are stacked sequentially on the peripheral side surface of the gate; Both the peripheral side surface of the first film layer and the peripheral side surface of the barrier layer are in contact with the second gate sidewall.
11. A semiconductor device packaging structure, characterized in that, include: The semiconductor device as described in any one of claims 1-10; A substrate on which the semiconductor device is disposed.
12. An electronic device, characterized in that, include: Circuit board; The semiconductor device packaging structure as described in claim 11; The semiconductor device packaging structure is disposed on the circuit board.
13. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A trench is formed in the electrode region of the substrate, the electrode region being used to form the first electrode of a P-type transistor; The first electrode of the P-type transistor is formed within the trench, and the first electrode comprises boron; A barrier layer is formed on the first electrode, and at least a portion of the substrate surface and the area surrounding the first electrode is covered by the barrier layer; A first film layer is formed on the barrier layer. The first film layer includes boron, and the boron content in the first film layer is greater than the boron content in the first electrode. The barrier layer is used to suppress the diffusion of boron in the first film layer into the channel of the P-type transistor.
14. The method for fabricating a semiconductor device according to claim 13, characterized in that, Before forming the trench in the electrode region of the substrate, the fabrication method further includes: A first mask layer and a second mask layer are formed. The first mask layer includes silicon oxide. The electrode region surface of the substrate is covered by the first mask layer. The second mask layer is located on the side of the first mask layer opposite to the substrate. After forming the trench in the electrode region of the substrate, the fabrication method further includes: The inner wall of the trench is cleaned, and the portion of the first mask layer near the trench is cleaned away, exposing the surface of the substrate near the trench.
15. The method for fabricating a semiconductor device according to claim 14, characterized in that, Cleaning the inner wall surface of the trench includes: The inner wall of the trench is cleaned with a gas containing ammonia and hydrogen fluoride, so that the silicon oxide on the inner wall of the trench is removed, as well as the silicon oxide of the first mask layer near the trench is removed.
16. The method for fabricating a semiconductor device according to any one of claims 13-15, characterized in that, The first electrode of the P-type transistor is formed within the trench, comprising: A first sub-electrode layer is formed within the trench; A second sub-electrode layer is formed on the first sub-electrode layer, wherein the germanium content in the second sub-electrode layer is greater than the germanium content in the first sub-electrode layer, and the boron content in the second sub-electrode layer is greater than the boron content in the first sub-electrode layer.