MOS device and preparation method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-03
- Publication Date
- 2026-03-13
AI Technical Summary
The uneven electric field distribution in existing MOS devices leads to insufficient breakdown voltage, which limits the optimization of device performance.
The design incorporates a gradient distribution of the cutoff ring structure. The cutoff rings closer to the active region and voltage divider region have deeper trenches and injection regions, while the cutoff rings farther from the voltage divider region have shallower trenches and injection regions. A dielectric layer is then placed over the trenches to form multiple cutoff rings, thereby optimizing the electric field distribution.
This achieves electric field homogenization, improves device breakdown voltage, enhances stability and reliability under high-voltage operating conditions, and reduces process complexity and switching losses.
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Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a MOS device and a method for fabricating the same. Background Technology
[0002] In high-voltage power electronic devices, silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) have become a more ideal choice for new energy vehicles and photovoltaic inverters due to their excellent voltage and heat resistance characteristics and significantly reduced energy loss. Their edge termination structure, especially the cutoff ring, is crucial for improving the device's breakdown voltage. However, the traditional single-depth and high-density cutoff ring structure leads to uneven electric field distribution, affecting termination efficiency; this "one-size-fits-all" design limits further optimization of device performance.
[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention
[0004] The main objective of this application is to provide a MOS device and its fabrication method to solve the problem of uneven electric field distribution in existing MOS devices.
[0005] To achieve the above objectives, according to one aspect of this application, a MOS device is provided, the MOS device comprising: an active region, a voltage divider region surrounding the active region, and a cutoff region surrounding the voltage divider region; the cutoff region comprising a plurality of cutoff rings spaced apart, each cutoff ring comprising a trench and an injection region located at the bottom of the trench; in any two of the plurality of cutoff rings, the depth of the trench closer to the voltage divider region is greater than the depth of the trench farther from the voltage divider region, and the depth of the injection region closer to the voltage divider region is greater than the depth of the injection region farther from the voltage divider region; the MOS device further comprising a dielectric layer, the dielectric layer at least covering the side surface and bottom surface of the trench.
[0006] In some embodiments of this application, in any two of the plurality of cutoff rings, the doping concentration of the implanted region closer to the voltage divider region is greater than the doping concentration of the implanted region farther from the voltage divider region.
[0007] In some embodiments of this application, in any two of the plurality of stop rings, the width of the groove closer to the pressure dividing region is greater than the width of the groove further away from the pressure dividing region.
[0008] In some embodiments of this application, each of the trenches has the same aspect ratio.
[0009] In some embodiments of this application, the aspect ratio of each trench is 1:1 to 5:1.
[0010] In some embodiments of this application, the plurality of stop rings include a first stop ring, a second stop ring, and a third stop ring arranged sequentially and gradually away from the pressure dividing region; the depth of the groove of the second stop ring is 1.2 to 3 times the depth of the groove of the third stop ring, and the depth of the injection region of the second stop ring is 1.1 to 1.5 times the depth of the injection region of the third stop ring; the depth of the groove of the first stop ring is 1.5 to 5 times the depth of the groove of the third stop ring, and the depth of the injection region of the first stop ring is 1.5 to 3 times the depth of the injection region of the third stop ring.
[0011] In some embodiments of this application, the doping concentration of the implantation region of the second cutoff ring is 10 to 100 times that of the implantation region of the third cutoff ring, and the doping concentration of the implantation region of the first cutoff ring is 10 to 100 times that of the implantation region of the third cutoff ring.
[0012] In some embodiments of this application, the dielectric layer material includes at least one of HfO2, Si3N4, TiO2, Al2O3, and ZrO2.
[0013] According to another aspect of this application, a method for fabricating a MOS device is provided. The method includes: forming a plurality of trenches within a cutoff region, the trenches being spaced apart, and in any two trenches, the trench closer to the voltage divider region has a greater depth than the trench further away from the voltage divider region; forming an injection region at the bottom of each trench to form a cutoff ring, and in any two injection regions, the injection region closer to the voltage divider region has a greater depth than the injection region further away from the voltage divider region; and forming a dielectric layer on the side surface and bottom surface of the trench.
[0014] In some embodiments of this application, the step of forming the plurality of trenches includes: forming a plurality of initial trenches of the same depth; sequentially exposing each of the initial trenches using a mask; and etching the plurality of initial trenches to form the plurality of trenches of different depths.
[0015] The beneficial effects of this application are as follows:
[0016] This application provides a MOS device and its fabrication method. The MOS device includes an active region, a voltage divider region surrounding the active region, and a cutoff region surrounding the voltage divider region. The cutoff region includes multiple cutoff rings spaced apart, each cutoff ring including a trench and an injection region located at the bottom of the trench. In any two cutoff rings, the depth of the trench closer to the voltage divider region is greater than the depth of the trench farther from the voltage divider region, and the depth of the injection region closer to the voltage divider region is greater than the depth of the injection region farther from the voltage divider region. The MOS device also includes a dielectric layer that at least covers the side surface and bottom surface of the trench. By making the cutoff ring closer to the active region and voltage divider region have deeper trenches and injection regions, this application can more effectively deplete and balance the high electric field intensity in this region, preventing electric field lines from becoming too concentrated in these critical areas, thereby avoiding breakdown caused by excessively high local electric field peaks. The cutoff ring farther from the voltage divider region, due to its naturally lower electric field intensity, uses shallower trenches and injection regions, which can reduce unnecessary capacitance effects and process complexity without affecting the uniformity of the electric field distribution. Furthermore, the gradient distribution cutoff ring design can more smoothly transition the electric field distribution, making the electric field uniform throughout the edge terminal region of the device. This helps to improve the actual breakdown voltage of the device, bringing it closer to the theoretical breakdown voltage limit of the substrate material (such as silicon carbide), thereby significantly improving the stability and reliability of the device under high voltage operating conditions. Attached Figure Description
[0017] One or more embodiments are illustrated by way of example with corresponding figures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings are not proportionally limited. To more clearly illustrate the technical solutions in the embodiments of this application or in conventional technology, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:
[0018] Figure 1 This is a schematic diagram of the partitioning of a MOS device according to an embodiment of this application;
[0019] Figure 2 This is a schematic diagram of the structure of a MOS device according to an embodiment of this application;
[0020] Figure 3 This is a schematic flowchart of a method for fabricating a MOS device according to an embodiment of this application;
[0021] Figures 4 to 9This is a schematic diagram of the fabrication process of a MOS device according to an embodiment of this application.
[0022] The above figures include the following reference numerals:
[0023] 1. Substrate; 2. Epitaxial layer; 3. Dielectric layer; 10. First cutoff ring; 11. First trench; 12. First implantation region; 20. Second cutoff ring; 21. Second trench; 22. Second implantation region; 30. Third cutoff ring; 31. Third trench; 32. Third implantation region; 41. First mask; 42. Second mask; 43. Third mask; 44. Fourth mask; 45. Fifth mask; 46. Sixth mask; 51. First initial trench; 52. Second initial trench; 53. Third initial trench. Detailed Implementation
[0024] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0025] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0026] When a component "includes" another component, unless otherwise stated, other components are not excluded, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is said to be "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or there can be another component present in between. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located in between.
[0027] The term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this text generally indicates that the preceding and following related objects have an "or" relationship.
[0028] The terms "first," "second," etc., are used to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. It should be understood that such terms can be used interchangeably where appropriate to describe embodiments of this application.
[0029] When an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element. Furthermore, in the specification and claims, terms such as "mounted," "connected," "joined," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.
[0030] The orientations or positional relationships indicated by terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "up," "down," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. Furthermore, in the accompanying drawings corresponding to the embodiments of this application, the thickness and area of the layers are enlarged for better understanding and ease of description.
[0031] Furthermore, the reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0032] The technical solutions in the examples of this application will be clearly and completely described below with reference to the accompanying drawings.
[0033] Figure 1 This is a schematic diagram of the partitioning of a MOS device according to an embodiment of this application, such as... Figure 1As shown, a MOS device includes an active region, a voltage divider region, and a cutoff region. The active region is the core of the device, responsible for switching and controlling the power. It contains the source, gate, drain, and corresponding doped regions. The voltage divider region surrounds the active region. By introducing additional potential through surface field plates or embedded voltage divider rings, it helps balance the electric field intensity at the edge of the active region, preventing premature breakdown due to excessive electric field concentration. The cutoff region surrounds the voltage divider region. By incorporating a series of cutoff rings and controlling their depth, concentration, and dosage, it optimizes the electric field distribution, improves the device's breakdown voltage, depletes carriers in high-field regions, smooths the electric field distribution, and prevents abrupt termination of the electric field at the device edge, thus preventing breakdown. MOS devices also include scribe lines surrounding the cutoff region, used to define the boundaries of individual devices during chip dicing and packaging.
[0034] Figure 2 This is a schematic diagram of the structure of a MOS device according to an embodiment of this application, with reference to... Figure 2 The MOS device includes a plurality of spaced-apart stop rings, each stop ring comprising a trench and an injection region at the bottom of the trench. In any two stop rings, the trench closer to the voltage divider region has a greater depth than the trench further away from the voltage divider region, and the injection region closer to the voltage divider region has a greater depth than the injection region further away from the voltage divider region. Furthermore, the MOS device includes a dielectric layer 3, which at least covers the side and bottom surfaces of the trenches in each stop ring.
[0035] By incorporating deeper trenches and injection regions into the cutoff ring closer to the active and voltage divider regions, the high electric field intensity in these areas can be more effectively depleted and balanced. This prevents excessive concentration of electric field lines in these critical regions, thus avoiding breakdown caused by excessively high local electric field peaks. Conversely, the cutoff ring further away from the voltage divider region, with its naturally lower electric field intensity, can utilize shallower trenches and injection regions. This reduces unnecessary capacitance effects and process complexity without affecting the uniformity of the electric field distribution. Furthermore, the gradient-distributed cutoff ring design allows for a smoother transition of the electric field distribution, resulting in a more uniform electric field across the entire device edge termination region. This helps improve the actual breakdown voltage of the device, bringing it closer to the theoretical breakdown voltage limit of the substrate material (e.g., silicon carbide), thereby significantly enhancing the stability and reliability of the device under high-voltage operating conditions.
[0036] In the embodiments of this application, the MOS device includes a substrate 1, an epitaxial layer 2, and a dielectric layer 3. The substrate 1 can be an N-type doped silicon carbide (SiC) substrate. The epitaxial layer 2 is located above the substrate 1 and serves as the main breakdown layer. By balancing the breakdown voltage and conductivity of the device, it increases the breakdown voltage while reducing energy loss, especially switching losses. The dielectric layer 3 fills the trenches of the cutoff ring and covers each injection region, which helps to improve the reverse breakdown voltage of the device, reduce switching losses under high-frequency operating conditions, and improve the operating efficiency of the device.
[0037] In some embodiments of this application, in any two of the plurality of cutoff rings, the doping concentration of the implanted region closer to the voltage divider region is greater than the doping concentration of the implanted region farther from the voltage divider region.
[0038] The high-doping concentration cutoff ring, located near the voltage divider region, helps create a stronger depletion region in the high electric field area. As the distance from the voltage divider region increases, the doping concentration gradually decreases, allowing the electric field lines to smoothly transition from the active region to the scribe line region. This avoids sudden interruptions or excessive concentration of the electric field lines, reducing the local electric field intensity and thus decreasing the risk of early breakdown. Furthermore, by employing a high doping concentration in the high electric field region, the electric field can be effectively controlled and balanced, resulting in a more uniform electric field distribution across the entire device edge termination structure and avoiding electric field peaks. This significantly improves the device's breakdown voltage.
[0039] In some embodiments of this application, in any two of the multiple cutoff rings, the width of the trench closer to the voltage divider region is greater than the width of the trench farther from the voltage divider region. In regions with high electric field strength (closer to the voltage divider region), the wider trench provides more space for charge depletion, helping to uniformly disperse electric field lines and prevent them from concentrating at specific points, thereby optimizing the electric field distribution at the device edge. In regions where the electric field strength gradually decreases (farther from the voltage divider region), using narrower trenches can reduce unnecessary material consumption and manufacturing costs while maintaining sufficient electric field control capability.
[0040] In some embodiments of this application, each trench has the same aspect ratio. A fixed trench ratio means that a standardized set of parameters can be used in the etching process, eliminating the need to adjust process conditions for trenches of different depths or widths. This simplifies the manufacturing process, reduces the complexity of controlling the photolithography and etching processes, thereby lowering manufacturing costs and improving process yield. When the aspect ratio is consistent, deviations during the etching process have a relatively small impact on device performance because the trench geometry remains consistent. Even with minor fluctuations in etching depth or width, the overall electric field distribution and device performance remain relatively stable, thus improving process tolerance.
[0041] In some embodiments of this application, each trench has the same aspect ratio, which is 1:1 to 5:1, for example, 1:1, 2:1, 3:1, 4:1, or 5:1. Setting the aspect ratio within the range of 1:1 to 5:1 allows the trench geometry to effectively guide electric field lines, ensuring a continuous and uniform electric field path from the active region to the voltage divider region and then to the scribe line. This helps to form a consistent and effective depletion region, thereby improving the electric field distribution, reducing electric field hotspots, increasing the device's breakdown voltage and operational stability, and reducing the stringent requirements for etching precision while maintaining effective electric field control. This lowers the difficulty of the manufacturing process and improves device yield and production efficiency.
[0042] like Figure 2 As shown, in some embodiments of this application, the cutoff region includes three cutoff rings, and each cutoff ring includes a groove and an injection region located at the bottom of the groove. The three cutoff rings are a first cutoff ring 10, a second cutoff ring 20, and a third cutoff ring 30 arranged sequentially away from the pressure dividing region. The first cutoff ring 10 includes a first groove 11 and a first injection region 12, the second cutoff ring 20 includes a second groove 21 and a second injection region 22, and the third cutoff ring 30 includes a third groove 31 and a third injection region 32.
[0043] In some embodiments of this application, the depth of the groove of the second stop ring 20 is 1.2 to 3 times the depth of the groove of the third stop ring 30, and the depth of the injection region of the second stop ring 20 is 1.1 to 1.5 times the depth of the injection region of the third stop ring 30; the depth of the groove of the first stop ring 10 is 1.5 to 5 times the depth of the groove of the third stop ring 30, and the depth of the injection region of the first stop ring 10 is 1.5 to 3 times the depth of the injection region of the third stop ring 30.
[0044] The trench depth is a key parameter determining the vertical junction depth of the N-type region. By deepening the trenches in specific areas and setting the depths of the aforementioned trenches within the specified ratio range, the stop-loop with deeper trenches can extend the vertical depletion region, enabling effective connection with the depletion region of adjacent stop-loops under lower voltage conditions. This design achieves early blocking and uniform distribution of the electric field, which is crucial for improving the breakdown voltage and operational stability of the device. Near the voltage divider ring with high electric field strength, the deep trench design provides stronger longitudinal depletion capability, effectively dispersing the high electric field and preventing excessive concentration of electric field lines in specific areas. This strengthens electric field control and prevents electric field distortion and potential breakdown risks.
[0045] In some embodiments of this application, the doping concentration of the implanted region of the second cutoff ring 20 is 10 to 100 times that of the implanted region of the third cutoff ring 30, and the doping concentration of the implanted region of the first cutoff ring 10 is 10 to 100 times that of the implanted region of the third cutoff ring 30.
[0046] In regions with significant electric field gradients, i.e., near the voltage divider rings, a high-concentration doping design is employed, and the doping concentration of each implantation region is set within the aforementioned proportional range, enabling each cutoff ring to possess excellent surface electric field carrying capacity. Through this strategy of dynamically adjusting the doping concentration, the embodiments of this application significantly reduce energy consumption during high-frequency operation while ensuring device withstand voltage performance, broadening the process tolerance range, reducing the need for precise process control, and thereby improving manufacturing yield and process stability.
[0047] In some embodiments of this application, the material of dielectric layer 3 includes at least one of HfO2, Si3N4, TiO2, Al2O3, and ZrO2. The high dielectric constant (K value) dielectric layer 3 described above can reduce the effective capacitance from the gate to the semiconductor surface, helping to reduce switching losses and improve the high-frequency performance of the device. Furthermore, the high-K dielectric layer can better control the charge within the channel, which is crucial for maintaining a stable threshold voltage and improving the charge mobility of the device. The selection of the dielectric layer 3 material can also optimize the electric field distribution, avoid electric field spikes, thereby reducing leakage current and improving the stability and safety of the device.
[0048] Based on the same concept, embodiments of this application also provide a method for fabricating a MOS device, the method being used to fabricate any of the aforementioned MOS devices. Figure 3 This is a schematic flowchart illustrating a method for fabricating a MOS device according to an embodiment of this application, as shown below. Figure 3 As shown, the fabrication method of the MOS device includes the following steps S1 to S3, wherein the MOS device includes an active region, a voltage divider region surrounding the active region, and a cutoff region surrounding the voltage divider region.
[0049] Step S1: Form multiple trenches in the cutoff area. The multiple trenches are spaced apart, and in any two trenches, the trench closer to the pressure dividing area has a greater depth than the trench further away from the pressure dividing area.
[0050] Step S2: An injection zone is formed at the bottom of each trench to form a cutoff ring. In any two injection zones among the multiple injection zones, the depth of the injection zone closer to the pressure dividing zone is greater than the depth of the injection zone farther from the pressure dividing zone.
[0051] Step S3: Form a dielectric layer on the side and bottom surfaces of the trench.
[0052] In the fabrication method provided by the embodiments of this application, the trenches and injection regions near the voltage divider region are deeper, which can provide a larger depletion width, more effectively deplete charge carriers, optimize the electric field distribution, and avoid electric field concentration. Using a shallower injection region in the region far from the voltage divider region can reduce charge accumulation, thereby reducing parasitic capacitance. The cutoff ring design with varying depth and concentration gradients is more tolerant of process fluctuations than a single depth and concentration cutoff ring, because cutoff rings of different depths and concentrations can compensate for each other. Even if there are some inaccuracies or fluctuations in the manufacturing process, the performance of the entire device can still remain within the expected range, thereby simplifying the process flow and improving production efficiency.
[0053] In some embodiments of this application, the step of forming multiple trenches (i.e., step S1) includes the following steps S101 and S102:
[0054] Step S101: Form multiple initial trenches of the same depth;
[0055] Step S102: Expose each initial trench sequentially using a mask, and etch multiple initial trenches to form multiple trenches of different depths.
[0056] In step S101, initial trenches of uniform depth are formed. This can be uniformly fabricated using standard etching processes, avoiding complex depth control of each trench in the initial stage. This simplifies the process and reduces costs. In step S102, each initial trench is sequentially etched using masking technology. This allows for precise control of the final depth of each trench, achieving depth differentiation and reducing the complexity of the etching process, further saving costs.
[0057] Figures 4 to 9 This is a schematic diagram of the fabrication process of a MOS device according to an embodiment of this application. Figures 4 to 9 The formation as shown in sequence is illustrated below. Figure 2 The intermediate structure of the MOS device formed in the fabrication process of the MOS device shown is referenced. Figures 4 to 9 A specific method for fabricating a MOS device includes the following steps S01 to S09:
[0058] Step S01: Provide substrate 1. For example, substrate 1 is an N-type silicon carbide substrate with a resistivity of 0.02±20%Ωcm.
[0059] Step S02: An epitaxial layer 2 is grown on substrate 1 using epitaxial growth technology. The portion of epitaxial layer 2 retained after subsequent steps can serve as a drift region, undertaking the main breakdown layer. Its doping concentration is 1E+15~1E1+16 cm⁻¹. -3The thickness can be set according to product requirements. For example, the thickness of the epitaxial layer 2 of a MOS device with a breakdown voltage requirement of 1200V is 9~11μm, and the thickness of the epitaxial layer 2 of a MOS device with a breakdown voltage requirement of 650V is 5~7μm.
[0060] Step S03: Form a first mask 41 on the epitaxial layer 2 and etch multiple initial trenches to form a shape as shown in the figure. Figure 4 The structure shown is illustrated. For example, etching is performed using F-based gas and argon (Ar) to a depth of 0.2~0.5μm, resulting in an initial trench with an aspect ratio of 1:1~5:1. Figure 4 The first initial groove 51, the second initial groove 52 and the third initial groove 53 are shown arranged sequentially along the pressure distribution region. The third initial groove 53 is the same as the third groove 31.
[0061] Step S04: Form a second mask 42 and etch the first initial trench 51 and the second initial trench 52. The second mask 42 exposes the first initial trench 51 and the second initial trench 52 to form as shown in the figure. Figure 5 As shown in the structure, the second initial trench 52 is transformed into the second trench 21 after this step. Exemplarily, the first initial trench 51 and the second initial trench 52 are etched using F-based gas and argon gas. The width and depth of the first initial trench 51 after this step are the same as those of the second trench 21. The depth ratio of the second trench 21 to the third trench 31 is 1.2:1 to 3:1, and the depth-to-width ratio of both the second trench 21 and the third trench 31 is 1:1 to 5:1.
[0062] Step S05: Form a third mask 43 and etch the first initial trench 51. The third mask 43 exposes the first initial trench 51 to form... Figure 6 The structure shown shows that the first initial trench 51 is formed into the first trench 11 after this step. For example, the first initial trench 51 is etched using F-based gas and argon gas to form the first trench 11. The depth ratio of the second trench 21 to the first trench 11 is 1.5:1 to 5:1, and the depth-to-width ratio of the second trench 21 and the first trench 11 is 1:1 to 5:1.
[0063] Step S06: Form a fourth mask 44 and perform ion implantation at the bottom of the third trench 31 to form a mask as shown in the figure. Figure 7 The third implantation region 32 shown has the same doping type as the epitaxial layer 2 as the implanted element. For example, the doping concentration of the third implantation region 32 is 1E+16~1E1+17 cm⁻¹. -3 The injection depth is 0.1~0.5μm.
[0064] Step S07: Form a fifth mask 45 and perform ion implantation at the bottom of the second trench 21 to form a mask as shown in the figure. Figure 8 The second implantation region 22 shown has the same doping type as the epitaxial layer 2. For example, the doping concentration of the second implantation region 22 is 1E+17~1E1+18 cm⁻¹. -3 The injection depth is 1.1 to 1.5 times the injection depth of the third injection zone 32.
[0065] Step S08: Form a sixth mask 46 and perform ion implantation at the bottom of the first trench 11 to form a mask as shown in the figure. Figure 9 The first implantation region 12 shown has the same doping type as the epitaxial layer 2 as the implanted element. For example, the doping concentration of the first implantation region 12 is 1E+18~1E1+19 cm⁻¹. -3 The injection depth is 1.5 to 3 times the injection depth of the third injection region 32. In this step, the sixth mask 46 can be the same as the third mask mentioned above, saving one mask and thus reducing costs.
[0066] Step S09: Remove the sixth mask 46 and form dielectric layer 3. Dielectric layer 3 covers the epitaxial layer and fills each trench, forming as shown in the figure. Figure 2 The structure shown is as follows. The dielectric layer 3 is formed of a dielectric material with a high dielectric constant, including but not limited to one or more of HfO2, Si3N4, TiO2, Al2O3, and ZrO2, with a thickness of 500 Å to 5000 Å.
[0067] The embodiments of this application can achieve trench etching of different depths and injection regions of different injection depths simply by changing the mask method. The process is simple and does not require completely independent process parameters for each depth of trench or injection region, which helps to simplify the manufacturing process and is suitable for mass production.
[0068] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0069] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A MOS device, characterized in that, include: An active region, a voltage-dividing region surrounding the active region, and a cutoff region surrounding the voltage-dividing region; The cutoff region includes a plurality of cutoff rings spaced apart, each cutoff ring including a groove and an injection area located at the bottom of the groove; In any two of the plurality of cutoff rings, the depth of the trench closer to the pressure dividing region is greater than the depth of the trench farther from the pressure dividing region, and the depth of the injection region closer to the pressure dividing region is greater than the depth of the injection region farther from the pressure dividing region. The MOS device further includes a dielectric layer that covers at least the side and bottom surfaces of the trench.
2. The MOS device according to claim 1, characterized in that, In any two of the plurality of cutoff rings, the doping concentration of the implanted region closer to the voltage divider region is greater than the doping concentration of the implanted region farther from the voltage divider region.
3. The MOS device according to claim 1, characterized in that, In any two of the plurality of stop rings, the width of the groove closer to the pressure dividing region is greater than the width of the groove further away from the pressure dividing region.
4. The MOS device according to claim 1, characterized in that, Each of the trenches has the same aspect ratio.
5. The MOS device according to claim 4, characterized in that, The depth-to-width ratio of each of the trenches is 1:1 to 5:
1.
6. The MOS device according to claim 1, characterized in that, The plurality of cutoff rings include a first cutoff ring, a second cutoff ring, and a third cutoff ring arranged sequentially and gradually away from the pressure dividing region; The depth of the groove of the second stop ring is 1.2 to 3 times the depth of the groove of the third stop ring, and the depth of the injection area of the second stop ring is 1.1 to 1.5 times the depth of the injection area of the third stop ring. The depth of the groove of the first stop ring is 1.5 to 5 times the depth of the groove of the third stop ring, and the depth of the injection area of the first stop ring is 1.5 to 3 times the depth of the injection area of the third stop ring.
7. The MOS device according to claim 6, characterized in that, The doping concentration of the implantation region of the second cutoff ring is 10 to 100 times that of the implantation region of the third cutoff ring, and the doping concentration of the implantation region of the first cutoff ring is 10 to 100 times that of the implantation region of the third cutoff ring.
8. The MOS device according to claim 1, characterized in that, The dielectric layer is made of at least one of HfO2, Si3N4, TiO2, Al2O3, and ZrO2.
9. A method for fabricating a MOS device, used to fabricate the MOS device according to any one of claims 1 to 8, characterized in that, The MOS device includes an active region, a voltage divider region surrounding the active region, and a cutoff region surrounding the voltage divider region; the fabrication method includes: Multiple grooves are formed in the cutoff area, and the multiple grooves are spaced apart. Among any two of the multiple grooves, the groove closer to the pressure dividing area has a greater depth than the groove further away from the pressure dividing area. An injection zone is formed at the bottom of each of the trenches to form a stop ring. In any two of the plurality of injection zones, the injection zone closer to the pressure dividing zone has a greater depth than the injection zone further away from the pressure dividing zone. A dielectric layer is formed on the side and bottom surfaces of the trench.
10. The method for fabricating a MOS device according to claim 9, characterized in that, The steps of forming the plurality of trenches include: Multiple initial trenches of the same depth are formed; Each initial trench is exposed sequentially using a mask, and the multiple initial trenches are etched to form multiple trenches of different depths.