Gallium nitride transistor assembly

Abstract

The invention provides a gallium nitride transistor assembly. The gallium nitride transistor assembly includes a semiconductor stack, a first transistor, a second transistor, a dielectric layer, an interconnect structure and a capacitor structure. The semiconductor stack has a first region and a second region. The first transistor is disposed on the first region of the semiconductor stack. The second transistor is disposed on the second region of the semiconductor stack. The dielectric layer is disposed on the first transistor and the second transistor. The interconnect structure is disposed on the semiconductor stack. The capacitor structure is disposed in the interconnect structure in the first region, wherein the capacitor structure is electrically connected between the drain of the first transistor and the gate of the second transistor. The capacitor structure includes a first electrode and a second electrode, wherein the first electrode and the second electrode are spaced apart from each other in a horizontal direction.

Description

Technical Field

[0001] This invention relates to a transistor assembly, and more particularly to a gallium nitride transistor assembly. Background Technology

[0002] Generally, transistors are susceptible to the Miller effect during switching, which can lead to channel mis-conversion. This can result in a large voltage being injected into the drain when the transistor is turned on, potentially damaging the device and affecting its reliability. To mitigate the Miller effect, a capacitor can be placed between the drain and gate of the transistor; however, this may increase the overall device area, hindering miniaturization. Summary of the Invention

[0003] This invention relates to a gallium nitride transistor component that can reduce component area and has good reliability.

[0004] According to an embodiment of the present invention, a gallium nitride transistor assembly includes a semiconductor stack, a first transistor, a second transistor, a dielectric layer, an interconnect structure, and a capacitor structure. The semiconductor stack has a first region and a second region. The first transistor is disposed on the first region of the semiconductor stack. The second transistor is disposed on the second region of the semiconductor stack. The dielectric layer is disposed on the first transistor and the second transistor. The interconnect structure is disposed on the semiconductor stack. The capacitor structure is disposed in the interconnect structure located in the first region, wherein the capacitor structure is electrically connected between the drain of the first transistor and the gate of the second transistor. The capacitor structure includes a first electrode and a second electrode, wherein the first electrode and the second electrode are horizontally separated from each other.

[0005] In a gallium nitride transistor assembly according to an embodiment of the present invention, the interconnect structure includes a first conductive layer disposed in a dielectric layer. The first conductive layer includes a first conductive portion, a second conductive portion, and a third conductive portion. The first conductive portion overlaps with the drain of the first transistor in a vertical direction. The second conductive portion is adjacent to the first conductive portion, wherein the first conductive portion and the second conductive portion are separated from each other in a horizontal direction. The third conductive portion overlaps with the gate and source of the first transistor in a vertical direction and is electrically connected to the source of the first transistor. The third conductive portion is separated from the first conductive portion and the second conductive portion in a horizontal direction, wherein the horizontal direction is perpendicular to the vertical direction. The first conductive portion constitutes the first electrode of a capacitor structure, and the second conductive portion constitutes the second electrode of a capacitor structure.

[0006] In a gallium nitride transistor assembly according to an embodiment of the present invention, the distance between the gate and drain of the first transistor is greater than the distance between the first electrode and the second electrode.

[0007] In a gallium nitride transistor assembly according to an embodiment of the present invention, the interconnect structure further includes a second conductive layer. The second conductive layer is disposed above the first conductive layer, and a dielectric layer vertically separates the first conductive layer and the second conductive layer. The second conductive layer includes a fourth conductive portion and a fifth conductive portion. The fourth conductive portion overlaps with the first conductive portion in the vertical direction, wherein the fourth conductive portion is physically and electrically connected to the first conductive portion of the first conductive layer through a first conductive via. The fifth conductive portion overlaps with the second conductive portion in the vertical direction. The capacitor structure also includes the fourth conductive portion and the fifth conductive portion.

[0008] In a gallium nitride transistor assembly according to an embodiment of the present invention, a fifth conductive portion in a second conductive layer is physically and electrically connected to a second conductive portion of a first conductive layer through a second conductive via.

[0009] In a gallium nitride transistor assembly according to an embodiment of the present invention, a first conductive portion of a first conductive layer is electrically connected to the drain of a first transistor, and a fifth conductive portion of a second conductive layer is electrically connected to the gate of a second transistor.

[0010] In a gallium nitride transistor assembly according to an embodiment of the present invention, the interconnect structure includes a second conductive layer. The second conductive layer is disposed on top of the dielectric layer. The second conductive layer includes a fourth conductive portion and a fifth conductive portion. The fourth conductive portion overlaps with the drain of the first transistor in the vertical direction. The fifth conductive portion is adjacent to the fourth conductive portion, wherein the fourth conductive portion and the fifth conductive portion are separated from each other in the horizontal direction, wherein the horizontal direction is perpendicular to the vertical direction. The fourth conductive portion constitutes the first electrode of the capacitor structure, and the fifth conductive portion constitutes the second electrode of the capacitor structure.

[0011] In a gallium nitride transistor assembly according to an embodiment of the present invention, the capacitor structure includes a plurality of capacitors stacked on a first region.

[0012] In a gallium nitride transistor assembly according to an embodiment of the present invention, the source, gate, and drain of a first transistor extend in a first direction, and the source, gate, and drain of a second transistor extend in a second direction, wherein the first direction is parallel or perpendicular to the second direction.

[0013] In a gallium nitride transistor assembly according to an embodiment of the present invention, the bottom surface of the capacitor structure is at least 1 μm away from the top surface of the semiconductor stack. Attached Figure Description

[0014] Figure 1 This is a cross-sectional schematic diagram of a gallium nitride transistor assembly according to an embodiment of the present invention;

[0015] Figure 2This is a schematic diagram of the layout of a gallium nitride transistor assembly according to an embodiment of the present invention;

[0016] Figure 3 This is a circuit diagram of a gallium nitride transistor assembly according to an embodiment of the present invention;

[0017] Figure 4 This is a cross-sectional schematic diagram of a gallium nitride transistor assembly according to another embodiment of the present invention;

[0018] Figure 5 This is a cross-sectional schematic diagram of a gallium nitride transistor assembly according to another embodiment of the present invention;

[0019] Figure 6 This is a layout schematic diagram of a gallium nitride transistor assembly according to another embodiment of the present invention;

[0020] Figure 7 This is a layout schematic diagram of a gallium nitride transistor assembly according to another embodiment of the present invention;

[0021] Figure 8 This is a schematic diagram of the layout of a gallium nitride transistor assembly according to another embodiment of the present invention. Detailed Implementation

[0022] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0023] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Throughout the specification, the same reference numerals denote the same components. It should be understood that when a component such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another component, it may be directly on or connected to the other component, or an intermediate component may also be present. Conversely, when a component is referred to as being "directly on" or "directly connected" to another component, no intermediate component is present. As used herein, "connection" can refer to a physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may refer to the presence of other components between the two components.

[0024] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, and / or portions should not be limited by these terms. These terms are used only to distinguish one component, part, region, layer, or portion from another. Therefore, “first component,” “part,” “region,” “layer,” or “portion” discussed below may be referred to as a second component, part, region, layer, or portion without departing from the teachings of this document.

[0025] Figure 1 This is a cross-sectional schematic diagram of a gallium nitride transistor assembly according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the layout of a gallium nitride transistor assembly according to an embodiment of the present invention. Figure 3 This is a circuit diagram of a gallium nitride transistor assembly according to an embodiment of the present invention. Figure 1 For example, it could be along Figure 2 A cross-sectional schematic diagram of one embodiment of lines A-A' and B-B'. Figure 1 The second conductive portion 162b is schematically represented by a dashed line to indicate its electrical connection with the gate G2 of the second transistor T2, and another dashed line is used to indicate its electrical connection with the gate G1 of the first transistor T1 and the drain D2 of the second transistor T2. For clarity, Figure 2 Some components (such as semiconductor stacks, doped semiconductor structures, conductive vias, dielectric layers, passivation layers, etc.) are omitted in the text. Please refer to the original document for further details. Figure 1 To understand.

[0026] Please refer to Figures 1 to 3 The gallium nitride transistor assembly 10 may include a semiconductor stack 100, a first transistor T1, a second transistor T2, a dielectric layer 140, and a capacitor structure C. The semiconductor stack 100 has a first region R1 and a second region R2. The first transistor T1 is disposed on the first region R1 of the semiconductor stack 100, and the second transistor T2 is disposed on the second region R2 of the substrate 100. The dielectric layer 140 is disposed on the first transistor T1 and the second transistor T2. An interconnect structure 160 is disposed on the semiconductor stack 100. The capacitor structure C is disposed in the interconnect structure 160 located in the first region R1. The capacitor structure C includes a first electrode E1 and a second electrode E2, wherein the first electrode E1 and the second electrode E2 are separated from each other in a horizontal direction (e.g., the x-direction). The horizontal direction may include, for example, the x-direction and the y-direction, wherein the x-direction and the y-direction are perpendicular.

[0027] In some embodiments, the semiconductor stack 100 may include a substrate 110, a first semiconductor layer 122, and a second semiconductor layer 124 stacked in sequence. The substrate 110 may include, for example, a silicon substrate, a silicon carbide substrate, a sapphire substrate, a silicon-on-insulator substrate, or other suitable semiconductor substrates, and the present invention is not limited thereto.

[0028] In some embodiments, the first transistor T1 and the second transistor T2 may be disposed on the second semiconductor layer 124, and the first semiconductor layer 122 and the second semiconductor layer 124 may be semiconductor materials with different energy bands, such that a two-dimensional electron gas can be generated near the interface between the first semiconductor layer 122 and the second semiconductor layer 124 to serve as a channel for the first transistor T1 and / or the second transistor T2. In some embodiments, the first semiconductor layer 122 may include gallium nitride (GaN), and the second semiconductor layer 124 may include aluminum gallium nitride (AlGaN), but the present invention is not limited thereto. In some embodiments, the first semiconductor layer 122 and the second semiconductor layer 124 may be sequentially formed on the substrate 110 by epitaxial processes or other growth processes. In some embodiments, both the first semiconductor layer 122 and the second semiconductor layer 124 are undoped semiconductor materials.

[0029] In some embodiments, both the first transistor T1 and the second transistor T2 are enhancement-mode high electron mobility transistors (EMBs). For example, the first transistor T1 may include a gate G1, a source S1, a drain D1, and a doped semiconductor structure 130 disposed on the second semiconductor layer 124 of the first region R1. The gate G1 is disposed between the source S1 and the drain D1, and the doped semiconductor structure 130 is disposed between the gate G1 and the second semiconductor layer 124. The second transistor T2 may include a gate G2, a source S2, a drain D2, and a doped semiconductor structure 132 disposed on the second semiconductor layer 124 of the second region R2. The gate G2 is disposed between the source S2 and the drain D2, and the doped semiconductor structure 132 is disposed between the gate G2 and the second semiconductor layer 124.

[0030] In some embodiments, the doped semiconductor structures 130 and 132 may include p-type gallium nitride or other suitable materials doped with p-type dopants. The p-type dopants may include, for example, boron, magnesium, or other suitable p-type dopants. In some embodiments, the gates G1 and G2 may include copper, gold, aluminum, nickel, titanium, titanium nitride, alloys thereof, combinations thereof, or other suitable conductive materials, and the invention is not limited thereto. In some embodiments, the source S1, drain D1, source S2, and drain D2 may include copper, gold, aluminum, nickel, titanium, alloys thereof, combinations thereof, or other suitable conductive materials, and the invention is not limited thereto.

[0031] In some embodiments, the first region R1 and the second region R2 can be separated by a trench T1, so that the first transistor T1 and the second transistor T2 can be located on independent platforms (i.e., the stack of the first semiconductor layer 122 and the second semiconductor layer 124). That is, the first region R1 can be referred to as the active region of the first transistor T1, and the second region R2 can be referred to as the active region of the second transistor T2. In other embodiments, the first region R1 and the second region R2 can be separated by providing an isolation structure, a well region, or other means; the present invention is not limited thereto.

[0032] In some embodiments, the trench TI may extend through the first semiconductor layer 122 and the second semiconductor layer 124 to expose the surface of the substrate 100, but the invention is not limited thereto. In some embodiments, the trench TI extends at least from the first semiconductor layer 122 beyond the interface between the first semiconductor layer 122 and the second semiconductor layer 124.

[0033] In some embodiments, dielectric layer 140 is disposed on second semiconductor layer 124 and covers first transistor T1 and second transistor T2. Dielectric layer 140 may also extend into trench T1. In some embodiments, dielectric layer 140 may be a single-layer or multi-layer structure. In some embodiments, the material of dielectric layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other suitable dielectric materials.

[0034] In some embodiments, the gallium nitride transistor assembly 10 further includes a passivation layer 150 disposed on the dielectric layer 140 to protect the structure beneath the passivation layer 150 from scratches, moisture, and contamination. In some embodiments, the passivation layer 150 may comprise polyimide or other suitable materials.

[0035] In some embodiments, the interconnect structure 160 may be located in the dielectric layer 140 and / or the passivation layer 150. The interconnect structure 160 may include a plurality of conductive layers (e.g., a first conductive layer 162 and a second conductive layer 164) and conductive vias (not shown) connecting the conductive layers. The conductive layers may provide horizontal conductive connections, and the conductive vias may provide vertical conductive connections (e.g., the z-direction, which is perpendicular to the top surface of the semiconductor stack 100).

[0036] exist Figure 1In this structure, a first conductive layer 162 is disposed within a dielectric layer 140. The first conductive layer 162 may include a first conductive portion 162a, a second conductive portion 162b, and a third conductive portion 162c. The first conductive portion 162a overlaps with the drain D1 of the first transistor T1 in the vertical direction (e.g., the z-direction). The second conductive portion 162b is adjacent to the first conductive portion 162a, and the first and second conductive portions 162b are separated from each other in the horizontal direction (e.g., the x-direction). The third conductive portion 162c overlaps with the gate G1 and source S1 of the first transistor T1 in the vertical direction (e.g., the z-direction) and is electrically connected to the source S1 of the first transistor T1. The third conductive portion 162c is separated from the first conductive portion 162a and the second conductive portion 162b in the horizontal direction (e.g., the x-direction), wherein the horizontal direction is perpendicular to the vertical direction. For example, the first conductive portion 162a, the second conductive portion 162b, and the third conductive portion 162c can be separated from each other by the dielectric layer 140.

[0037] In some embodiments, the first conductive portion 162a, the second conductive portion 162b, and the third conductive portion 162c are substantially at the same height and belong to the same conductive film layer. That is, the top surfaces of the first conductive portion 162a, the second conductive portion 162b, and the third conductive portion 162c are substantially coplanar, and the bottom surfaces of the first conductive portion 162a, the second conductive portion 162b, and the third conductive portion 162c are substantially coplanar.

[0038] In some embodiments, the first conductive portion 162a, the second conductive portion 162b, and the dielectric layer 140 between the first conductive portion 162a and the second conductive portion 162b can constitute a capacitor. That is, the first electrode E1 of the capacitor structure C can be formed by the first conductive portion 162a, and the second electrode E2 of the capacitor structure C can be formed by the second conductive portion 162b. Thus, the capacitor structure C can be part of the interconnect structure 160. In this way, the capacitor structure C can be disposed in the active region (i.e., the first region R1) of the first transistor T1 to effectively utilize space and reduce the overall area of ​​the gallium nitride transistor assembly 10.

[0039] In some embodiments, the bottom surface of capacitor structure C is at least 1 μm away from the top surface of semiconductor stack 100 (i.e., the top surface of second semiconductor layer 124). Figure 1 The distance (represented by h) is preferably greater than 1.5 μm to avoid the capacitor structure C affecting the current flowing through the second semiconductor layer 124 of the first transistor T1, thus affecting its electrical performance. Figure 1A conductive layer (first conductive layer) is schematically shown in dielectric layer 140, but is not intended to limit the invention. The number of conductive layers and their wiring can be adjusted according to actual needs. Furthermore, Figure 1 The diagram schematically shows the capacitor structure C located in the first conductive layer 162, but it is not intended to limit the invention. The capacitor structure C can be disposed in any conductive layer in the interconnect structure 160, but the bottom surface of the capacitor structure C must be at least 1 μm away from the top surface of the semiconductor stack 100.

[0040] Figure 1 The diagram schematically illustrates that capacitor structure C includes a single capacitor, but is not intended to limit the invention. In other embodiments, capacitor structure C may include multiple capacitors stacked in the dielectric layer 140 of the first region R1.

[0041] In some embodiments, the first conductive portion 162a (or the first electrode E1) can be electrically connected to the drain D1 of the first transistor T1 via a conductive via (not shown). The second conductive portion 162b (or the second electrode E2) can be connected via a suitable wiring design (e.g., Figure 2 (As shown) and is electrically connected to the gate G2 of the second transistor T2.

[0042] In some embodiments, the distance d1 between the gate G1 and the drain D1 of the first transistor T1 is greater than the distance d2 between the first conductive portion 162a (or the first electrode E1) and the second conductive portion 162b (or the second electrode E2). In some embodiments, the distance d2 may be between 0.1 μm and 10 μm.

[0043] In some embodiments, the third conductive portion 162c may be part of the source field plate FP to adjust the electric field strength between the gate G1 and the drain D1, thereby increasing the breakdown voltage of the first transistor T1. In some embodiments, the third conductive portion 162c may be electrically connected to the source S1 of the first transistor T1 through a conductive via.

[0044] In some embodiments, the source field plate FP may further include an extension 162d. The extension 162d is physically and electrically connected to the end of the third conductive portion 162c away from the source S1 and extends downward in a vertical direction (e.g., the z-direction). However, the invention is not limited thereto, and the shape and configuration of the source field plate FP may be adjusted according to actual needs.

[0045] In some embodiments, the interconnect structure 160 further includes a second conductive layer 164. The second conductive layer 164 is disposed on the first conductive layer 162 and the dielectric layer 140 separates the first conductive layer 162 and the second conductive layer 164 in a vertical direction (e.g., the z-direction).

[0046] In some embodiments, the topmost conductive layer in the interconnect structure 160 (i.e. Figure 1 The second conductive layer 164 can be disposed on the dielectric layer 140 and the first conductive layer 162, and the passivation layer 150 can cover the sidewall of the second conductive layer 164.

[0047] The passivation layer 150 may have multiple openings to expose a portion of the top surface of the second conductive layer 164. The portion of the second conductive layer 164 exposed above the passivation layer 150 can serve as a contact pad for external connections to the first transistor T1 and the second transistor T2. For example, the second conductive layer 164 may include contact pads 164a, 164b, and 164c. Contact pad 164a can be electrically connected to the first conductive portion 162a via a conductive via, thereby being electrically connected to the drain D1 of the first transistor T1. Contact pad 164b can be electrically connected to the third conductive portion 162c via a conductive via, thereby being electrically connected to the source S1 of the first transistor T1. Contact pad 164c can be electrically connected to the source S2 of the second transistor T2 via a conductive via.

[0048] In some embodiments, the materials of the first conductive layer 162 and the second conductive layer may include copper, gold, aluminum, nickel, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, combinations thereof, or other suitable conductive materials, and the present invention is not limited thereto.

[0049] In some embodiments, such as Figure 2 As shown, the first region R1 may include a plurality of first transistors T1 arranged in the x-direction and a plurality of capacitor structures C. Adjacent first transistors T1 may share a source S1 or a drain D2. In some embodiments, the semiconductor stack 100 may have two second regions R2 arranged in the x-direction, each second region R2 containing a second transistor T2. The two second regions R2 may be located on the same side of the first region R1. Adjacent second regions R2 may be connected by forming trenches (e.g., similar to...) between adjacent second regions R2. Figure 1 The trenches (TI), isolation structures, well areas, or other means will separate them from each other. It should be understood that... Figure 2 The layout of one embodiment of the gallium nitride transistor assembly 10 is shown only schematically and is not intended to limit the invention. The number and layout of the first region R1 and the second region R2 can be adjusted according to actual needs, and the number and layout of the first transistor T1 in the first region R1 and the number and layout of the second transistor T2 in the second region R2 can also be adjusted according to actual needs.

[0050] In some embodiments, viewed from a top-down perspective, such as Figure 2As shown, the source S1, gate G1, and drain D1 of the first transistor T1 extend in the y-direction and are arranged in the x-direction, while the source S2, gate G2, and drain D2 of the second transistor T2 extend in the y-direction and are arranged in the x-direction. In other words, the extension directions (i.e., the y-direction) of the source S1, gate G1, and drain D1 of the first transistor T1 are parallel to the extension directions (i.e., the y-direction) of the source S2, gate G2, and drain D2 of the second transistor T2.

[0051] In some embodiments, the second conductive layer 164 further includes a source connection portion 164d and a drain connection portion 164e. The source connection portion 164d may overlap with the source S1 of the first transistor T1 and the source S2 of the second transistor T2 in the vertical direction (i.e., the z-direction), and is electrically connected to the source S1 of the first transistor T1 and the source S2 of the second transistor T2. That is, the source S1 of the first transistor T1 may be electrically connected to the source S2 of the second transistor T2. In some embodiments, the source S1 of the first transistor T1 and the source S2 of the second transistor T2 may be grounded, but this is not a limitation of the invention. The drain connection portion 164e may overlap with the drain D1 of the first transistor T1 in the vertical direction (i.e., the z-direction), and is electrically connected to the drain D1 of the first transistor T1.

[0052] In some embodiments, the gallium nitride transistor assembly 10 further includes a gate connection layer G1c. For example, the gate connection layer G1c may include a line portion p1 and a pad portion p2. The line portion p1 may extend in the x-direction and be physically and electrically connected to the gates G1 of a plurality of first transistors T1, while the pad portions p2 may be disposed at both ends of the line portion p1. In some embodiments, the gate G1 may extend beyond the first region R1 in the y-direction to connect with the line portion p1. In some embodiments, the gate connection layer G1c and the gate G1 are located in the same film layer, but the present invention is not limited thereto.

[0053] In some embodiments, the gate connection layer G1c is also electrically connected to the drain D2 of the second transistor T2. For example, the drain D2 of the second transistor T2 may extend in the y-direction to a position corresponding to and overlapping with the line portion p1 of the gate connection layer G1c, and be electrically connected to the line portion p1 of the gate connection layer G1c through a conductive via (not shown), thereby being electrically connected to the gates G1 of multiple first transistors T1. That is, the gates G1 of different first transistors T1 may be connected to the drain D2 of the same second transistor T2.

[0054] In some embodiments, the gallium nitride transistor assembly 10 further includes a gate connection layer G2c. The gate connection layer G2c may extend in the x-direction and be physically and electrically connected to the gate G2. In some embodiments, the gate connection layer G2c and the gate G2 are located in the same film layer, but the present invention is not limited thereto.

[0055] In some embodiments, the gate connection layer G2c is also electrically connected to the second electrode E2 of the capacitor structure C. For example, the second electrode E2 of the capacitor structure C may extend in the y-direction beyond the first region R1 to a position corresponding to and overlapping with the gate connection layer G2c, and be electrically connected to the gate connection layer G2c through a conductive via (not shown), thereby being electrically connected to the gate G2 of the second transistor T2. In some embodiments, the second electrodes E2 of different capacitor structures C may be connected to the gate G2 of the same second transistor T2.

[0056] Because the capacitor structure C is electrically connected between the drain D1 of the first transistor T1 and the gate G2 of the second transistor T2, and the gate G1 of the first transistor T1 and the drain D2 of the second transistor T2 are electrically connected, the possibility of false turn-on due to the Miller effect in the gallium nitride transistor assembly 10 can be reduced, thereby improving reliability.

[0057] In detail, the circuit diagram of the gallium nitride transistor component 10 can be seen as follows: Figure 3 As shown, the drain D1 of the first transistor T1 is electrically connected to the capacitor structure C, the capacitor structure C is electrically connected to the gate G2 of the second transistor T2, and the drain D2 of the second transistor T2 is electrically connected to the gate G1 of the first transistor T1. Thus, when the gate G1 of the first transistor T1 is in the off state but the Miller effect causes the channel between the source S1 and drain D1 to conduct, the voltage input from the drain D1 will charge the capacitor structure C and apply a voltage to the gate G2 of the second transistor T2, causing the channel of the second transistor T2 to conduct. This results in a drop in the voltage at the drain D2 of the second transistor T2. Since the gate G1 of the first transistor T1 is electrically connected to the drain D2 of the second transistor T2, this reduces the voltage at the gate G1 of the first transistor T1, thus turning off the channel of the first transistor T1 and reducing the possibility of false turn-on due to the Miller effect in the gallium nitride transistor assembly 10.

[0058] The gallium nitride transistor assembly 10 of the present invention includes a first transistor T1, a second transistor T2 and a capacitor structure C electrically connected to each other. By setting the capacitor structure C in the active region (i.e., the first region R1) of the first transistor T1, space can be effectively utilized, reducing the overall area of ​​the gallium nitride transistor assembly 10 while maintaining good reliability.

[0059] Figure 4 This is a cross-sectional schematic diagram of a gallium nitride transistor assembly according to another embodiment of the present invention. It should be noted here that... Figure 4 The embodiments follow Figure 1The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here. Figure 4 The fifth conductive portion 164d is schematically represented by a dashed line to be electrically connected to the gate G2 of the second transistor T2, and the gate G1 of the first transistor T1 is represented by another dashed line to be electrically connected to the drain D2 of the second transistor T2.

[0060] Please refer to Figure 4 The gallium nitride transistor assembly 20 is generally similar to the gallium nitride transistor assembly 10. The difference between the gallium nitride transistor assembly 20 and the gallium nitride transistor assembly 10 is that the capacitor structure C' is located in the second conductive layer 164 of the interconnect structure 160, rather than the first conductive layer 162. In this embodiment, the second conductive layer 164 includes a fourth conductive portion 164a (also called a pad 164a) and a fifth conductive portion 164d. The fourth conductive portion 164a overlaps with the drain D1 of the first transistor T1 in the vertical direction (e.g., the z-direction). The fifth conductive portion 164d is adjacent to the fourth conductive portion 164a, wherein the fourth conductive portion 164a and the fifth conductive portion 164d are separated from each other in the horizontal direction (e.g., the x-direction).

[0061] In some embodiments, the fourth conductive portion 164a, the fifth conductive portion 164d, and the pads 164b and 164c are substantially at the same height and belong to the same conductive film layer. That is, the top surfaces of the fourth conductive portion 164a, the fifth conductive portion 164d, and the pads 164b and 164c are substantially coplanar, and the bottom surfaces of the fourth conductive portion 164a, the fifth conductive portion 164d, and the pads 164b and 164c are substantially coplanar.

[0062] In some embodiments, the fourth conductive portion 164a, the fifth conductive portion 164d, and the passivation layer between the fourth conductive portion 164a and the fifth conductive portion 164d can constitute a capacitor. That is, the first electrode E1 of the capacitor structure C' can be formed by the fourth conductive portion 164a, and the second electrode E2 of the capacitor structure C' can be formed by the fifth conductive portion 164d. Thus, the capacitor structure C' can be part of the interconnect structure 160. In this way, the capacitor structure C' can be disposed in the active region (i.e., the first region R1) of the first transistor T1 to effectively utilize space and reduce the overall area of ​​the gallium nitride transistor assembly 20.

[0063] In some embodiments, the fourth conductive portion 164a (or the first electrode E1) can be electrically connected to the drain D1 of the first transistor T1 through a conductive via and the first conductive portion 162a of the first conductive layer 162. In some embodiments, the fifth conductive portion 164d (or the second electrode E2) can be electrically connected to the gate G2 of the second transistor T2 through appropriate wiring design. The layout diagram of the gallium nitride transistor assembly 20 can be compared with... Figure 2 Similarly, for example, the second electrode E2 of capacitor structure C' can extend in the y-direction beyond the first region R1 to a position corresponding to and overlapping with the gate connection layer G2c, and be electrically connected to the gate connection layer G2c through a conductive via (not shown), thereby being electrically connected to the gate G2 of the second transistor T2. Figure 2 Similarly, except that in this embodiment, the second electrode E2 of the capacitor structure C' is located in the second conductive layer 164 instead of the first conductive layer 162.

[0064] In some embodiments, the passivation layer 150 may cover the sidewalls and top surface of the fifth conductive portion 164d.

[0065] Figure 5 This is a cross-sectional schematic diagram of a gallium nitride transistor assembly according to another embodiment of the present invention. It should be noted here that... Figure 5 The embodiments follow Figure 1 and Figure 4 The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here. Figure 5 The fifth conductive portion 164d is schematically represented by a dashed line to be electrically connected to the gate G2 of the second transistor T2, and the gate G1 of the first transistor T1 is represented by another dashed line to be electrically connected to the drain D2 of the second transistor T2.

[0066] Please refer to Figure 5 The gallium nitride transistor assembly 30 is generally similar to the gallium nitride transistor assembly 10. The difference between the gallium nitride transistor assembly 30 and the gallium nitride transistor assembly 10 is that the capacitor structure C” of the gallium nitride transistor assembly 30 includes multiple capacitors stacked on the first region R1 in a vertical direction (e.g., the z-direction). For example, the capacitor structure C” may include a capacitor C1 (similar to) formed by a first conductive portion 162a and a second conductive portion 162b of the first conductive layer 162 and a dielectric layer 140 located between the first conductive portion 162a and the second conductive portion 162b. Figure 1 The capacitor structure C) and the capacitor C2 (similar to) are composed of the fourth conductive portion 164a, the fifth conductive portion 164d of the second conductive layer 164 and the passivation layer 150 located between the fourth conductive portion 164a and the fifth conductive portion 164d. Figure 4 The capacitor structure C' may include a first conductive portion 162a and / or a fourth conductive portion 164a, and a second conductive portion E2 may include a second conductive portion 162b and / or a fifth conductive portion 164d. In other words, the capacitor structure C' may be part of the interconnect structure 160, allowing for efficient use of space and reducing the overall area of ​​the gallium nitride transistor assembly 30.

[0067] In some embodiments, the fourth conductive portion 164a in the second conductive layer 164 overlaps with the first conductive portion 162a of the first conductive layer 162 in the vertical direction (e.g., the z-direction) and is physically and electrically connected to the first conductive portion 162a of the first conductive layer 162 through the first conductive via v1. The fifth conductive portion 164d in the second conductive layer 164 overlaps with the second conductive portion 162b of the first conductive layer 162 in the vertical direction (e.g., the z-direction) and is physically and electrically connected to the second conductive portion 162b of the first conductive layer 162 through the second conductive via v2, such that capacitor C1 and capacitor C2 are connected in parallel.

[0068] In some embodiments, the first conductive portion 162a of the first conductive layer 162 is electrically connected to the drain D1 of the first transistor T1, and the fifth conductive portion 164d of the second conductive layer 164 is electrically connected to the gate G1 of the second transistor T2, thus forming a similar configuration. Figure 3 The circuit design shown.

[0069] Figure 6 This is a schematic layout diagram of a gallium nitride transistor assembly according to another embodiment of the present invention. It should be noted that... Figure 6 The embodiments follow Figure 2 The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0070] Please refer to Figure 6 Gallium nitride transistor component 40 and Figure 2 The difference in the embodiment is that the semiconductor stack 100 of the gallium nitride transistor assembly 40 has two second regions R2 arranged in the x direction and two first regions R1 arranged in the y direction. The two second regions R2 are located between the two first regions R1, such that the first transistor T1 located in different first regions R1 and the capacitor structure C can be electrically connected to the second transistor T2 in the same second region R2.

[0071] In some embodiments, the gate connection layer G1c of the gallium nitride transistor assembly 40 may include line portions p1, p3, p4, and pad portions p2. Line portions p1 and p3 may extend in the x-direction and are physically and electrically connected to the gates G1 of a plurality of first transistors T1 in two first regions R1, respectively. Line portion p3 may extend in the y-direction and is physically and electrically connected to line portions p1 and p3, while pad portions p2 may be disposed at both ends of line portion p3. In some embodiments, the gate G1 may extend beyond the first region R1 in the y-direction to connect to line portion p1 or line portion p3. In some embodiments, the gate connection layer G1c and the gate G1 are located in the same film layer, but the present invention is not limited thereto.

[0072] In some embodiments, the gate connection layer G1c is also electrically connected to the drain D2 of the second transistor T2. For example, the drain D2 of the second transistor T2 may extend in the y-direction to a position corresponding to the line portion p1 of the gate connection layer G1c and be electrically connected to the line portion p1 of the gate connection layer G1c through a conductive via (not shown), and may also extend in the y-direction to a position corresponding to the line portion p3 of the gate connection layer G1c and be electrically connected to the line portion p3 of the gate connection layer G1c through a conductive via (not shown), thereby being electrically connected to the gate G1 of a plurality of first transistors T1 in the two first regions R1. That is, the gate G1 of different first transistors T1 can be connected to the drain D2 of the same second transistor T2.

[0073] In some embodiments, the gate connection layer G2c of the gallium nitride transistor assembly 40 is electrically connected to the second electrode E2 of the capacitor structure C in the two first regions R1. For example, the second electrode E2 of different capacitor structures C can extend beyond the first region R1 in the y-direction to a position corresponding to the overlapping position of the gate connection layer G2c and be electrically connected to the gate connection layer G2c through a conductive via (not shown), thereby being electrically connected to the gate G2 of the second transistor T2. In some embodiments, the second electrode E2 of different capacitor structures C can be connected to the gate G2 of the same second transistor T2.

[0074] Figure 7 This is a schematic layout diagram of a gallium nitride transistor assembly according to another embodiment of the present invention. It should be noted that... Figure 6 The embodiments follow Figure 2 The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0075] Please refer to Figure 7 Gallium nitride transistor component 50 and Figure 2 The difference in the embodiments is that, viewed from a top-down direction, the source S1, gate G1, and drain D1 of the first transistor T1 in the first region R1 of the gallium nitride transistor assembly 50 extend in the y-direction and are arranged in the x-direction. The source S2, gate G2, and drain D2 of the second transistor T2 in the second region R2 extend in the x-direction and are arranged in the y-direction. That is, the source S1, gate G1, and drain D1 of the first transistor T1 and the source S2, gate G2, and drain D2 of the second transistor T2 extend in different directions. In some embodiments, the extension direction (i.e., the y-direction) of the source S1, gate G1, and drain D1 of the first transistor T1 is perpendicular to the extension direction (i.e., the x-direction) of the source S2, gate G2, and drain D2 of the second transistor T2.

[0076] In some embodiments, the drain D2 of the second transistor T2 may be parallel to the line portion p1 of the gate connection layer G1c and partially overlap in the vertical direction (e.g., the z direction).

[0077] Figure 8 This is a schematic layout diagram of a gallium nitride transistor assembly according to another embodiment of the present invention. It should be noted that... Figure 8 The embodiments follow Figure 6 The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0078] Please refer to Figure 8 Gallium nitride transistor component 60 and Figure 6 The difference in the embodiments is that, viewed from the top, the source S1, gate G1, and drain D1 of the first transistor T1 in the first region R1 of the gallium nitride transistor assembly 60 extend in the y-direction and are arranged in the x-direction. The source S2, gate G2, and drain D2 of the second transistor T2 in the second region R2 extend in the x-direction and are arranged in the y-direction. That is, the source S1, gate G1, and drain D1 of the first transistor T1 and the source S2, gate G2, and drain D2 of the second transistor T2 extend in different directions. In some embodiments, the extension direction (i.e., the y-direction) of the source S1, gate G1, and drain D1 of the first transistor T1 is perpendicular to the extension direction (i.e., the x-direction) of the source S2, gate G2, and drain D2 of the second transistor T2.

[0079] In some embodiments, the second region R2 may each include two second transistors T2 arranged in the y-direction. These two second transistors T2 may share a source S2, while their drains D2 may be respectively disposed on opposite sides of the source S2, and are parallel to and partially overlap with the line portions p1 and p3 of the gate connection layer G1c in the vertical direction (e.g., the z-direction). The gates G2 of the two second transistors T2 are respectively disposed between the source S2 and the corresponding drain D2.

[0080] Based on the above, the gallium nitride transistor assembly of the present invention includes a first transistor, a second transistor, and a capacitor structure that are electrically connected to each other. Since the capacitor structure is disposed in the active region of the first transistor, space can be effectively utilized, thereby reducing the overall area of ​​the gallium nitride transistor assembly while maintaining good reliability.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gallium nitride transistor assembly, characterized in that, include: A semiconductor stack having a first region and a second region; A first transistor is disposed on a first region of the semiconductor stack; The second transistor is disposed on the second region of the semiconductor stack; A dielectric layer is disposed on the first transistor and the second transistor; An interconnect structure is disposed on the semiconductor stack; as well as A capacitor structure is disposed in the interconnect structure located in the first region, wherein the capacitor structure is electrically connected between the drain of the first transistor and the gate of the second transistor. The capacitor structure includes a first electrode and a second electrode, wherein the first electrode and the second electrode are separated from each other in the horizontal direction.

2. The gallium nitride transistor assembly according to claim 1, characterized in that, The interconnect structure includes: A first conductive layer is disposed within the dielectric layer, wherein the first conductive layer comprises: The first conductive portion overlaps with the drain of the first transistor in the vertical direction; A second conductive portion, adjacent to the first conductive portion, wherein the first conductive portion and the second conductive portion are separated from each other in the horizontal direction; and The third conductive portion overlaps with the gate and source of the first transistor in the vertical direction and is electrically connected to the source of the first transistor. The third conductive portion is separated from the first and second conductive portions in the horizontal direction, wherein the horizontal direction is perpendicular to the vertical direction. The first conductive portion constitutes the first electrode of the capacitor structure, and the second conductive portion constitutes the second electrode of the capacitor structure.

3. The gallium nitride transistor assembly according to claim 1, characterized in that, The distance between the gate and the drain of the first transistor is greater than the distance between the first electrode and the second electrode.

4. The gallium nitride transistor assembly according to claim 2, characterized in that, The interconnect structure also includes: A second conductive layer is disposed on top of the first conductive layer, and the dielectric layer separates the first conductive layer and the second conductive layer in the vertical direction, wherein the second conductive layer comprises: A fourth conductive portion overlaps with the first conductive portion in the vertical direction, wherein the fourth conductive portion is physically and electrically connected to the first conductive portion of the first conductive layer through a first conductive via; and The fifth conductive portion overlaps with the second conductive portion in the vertical direction. The capacitor structure further includes the fourth conductive portion and the fifth conductive portion.

5. The gallium nitride transistor assembly according to claim 4, characterized in that, The fifth conductive portion in the second conductive layer is physically and electrically connected to the second conductive portion of the first conductive layer through a second conductive via.

6. The gallium nitride transistor assembly according to claim 4, characterized in that, The first conductive portion of the first conductive layer is electrically connected to the drain of the first transistor, and the fifth conductive portion of the second conductive layer is electrically connected to the gate of the second transistor.

7. The gallium nitride transistor assembly according to claim 1, characterized in that, The interconnect structure includes: A second conductive layer is disposed on the dielectric layer, wherein the second conductive layer comprises: The fourth conductive portion overlaps vertically with the drain of the first transistor; and A fifth conductive portion is adjacent to the fourth conductive portion, wherein the fourth conductive portion and the fifth conductive portion are separated from each other in the horizontal direction, wherein the horizontal direction is perpendicular to the vertical direction. The fourth conductive portion constitutes the first electrode of the capacitor structure, and the fifth conductive portion constitutes the second electrode of the capacitor structure.

8. The gallium nitride transistor assembly according to claim 1, characterized in that, The capacitor structure includes multiple capacitors stacked on top of the first region.

9. The gallium nitride transistor assembly according to claim 1, characterized in that, The source, gate, and drain of the first transistor extend in a first direction, and the source, gate, and drain of the second transistor extend in a second direction, wherein the first direction is parallel or perpendicular to the second direction.

10. The gallium nitride transistor assembly according to claim 1, characterized in that, The bottom surface of the capacitor structure is at least 1 μm away from the top surface of the semiconductor stack.

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