Semiconductor device and preparation method thereof
By forming grooves in the semiconductor devices in the peripheral circuit region and the core circuit region respectively and filling them with undoped epitaxial buffer layers and embedded epitaxial layers, the breakdown problem caused by inconsistent groove sizes is solved, and the reliability and electrical parameters of PMOS transistors are improved.
Patent Information
- Application Number
- CN202411194548.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-28
- Publication Date
- 2026-03-13
AI Technical Summary
In existing semiconductor devices, the PMOS transistors in the peripheral circuit region and the core circuit region have inconsistent groove sizes due to the synchronous fabrication of the embedded germanium-silicon epitaxial layer. This results in low breakdown voltage and high threshold voltage for the PMOS transistors in the peripheral circuit region, affecting reliability and electrical parameters.
A first groove and a second groove are formed in the peripheral circuit region and the core circuit region, respectively, and an undoped epitaxial buffer layer is covered on their inner walls. The first embedded and second embedded epitaxial layers are filled respectively. The ion doping concentration of the lightly doped region is adjusted to control the threshold voltage difference. The effective distance between the embedded epitaxial layer and the gate structure is increased by the undoped epitaxial buffer layer.
The breakdown voltage of the PMOS transistor in the peripheral circuit area has been increased to meet the reliability requirements under high operating voltage, the short-channel effect has been improved, and the electrical parameters have been ensured to meet the standards.
Smart Images
Figure CN121665669A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] Existing semiconductor devices typically divide the substrate into different regions according to different functions. For example, the substrate is divided into a core circuit region and a peripheral circuit region. Both the core circuit region and the peripheral circuit region usually include transistors and corresponding circuits that control the transistors. Because the core circuit region and the peripheral circuit region have different functional requirements, the parameters of the transistors formed are not the same.
[0003] To meet the demands of high drive speeds, current PMOS transistors typically employ embedded silicon germanium (eSiGe) technology. This involves selectively epitaxially forming an embedded silicon germanium layer in the source and drain regions of the PMOS transistor to increase channel stress and enhance carrier mobility. Some semiconductor devices require the turn-on speed of the PMOS transistor in the peripheral circuit region to be lower than that in the core circuit region. This means the threshold voltage of the peripheral circuit region's PMOS transistor must be higher than that of the core circuit region's PMOS transistor. In actual manufacturing, the threshold voltage can be adjusted by regulating the ion doping concentration in the lightly doped region. Therefore, the ion doping concentration in the lightly doped region of the peripheral circuit region will be lower than that in the lightly doped region of the core circuit region. However, the ion doping concentration affects the etching rate. The higher the ion doping concentration, the slower the etching rate. Currently, the embedded germanium-silicon epitaxial layers in the peripheral circuit region and the core circuit region are fabricated simultaneously. This results in the size of the groove in the peripheral circuit region being larger than the size of the groove in the core circuit region when etching the lightly doped region and the substrate to form a groove to accommodate the embedded germanium-silicon epitaxial layer. This makes the effective distance between the embedded germanium-silicon epitaxial layer in the peripheral circuit region and the gate structure smaller, resulting in a lower breakdown voltage of the PMOS transistor in the peripheral circuit region, while the threshold voltage of the PMOS transistor in the peripheral circuit region is higher. Therefore, it is prone to breakdown and has low reliability. Figure 1 VBD test pattern of the embedded germanium-silicon epitaxial layer in the existing peripheral circuit area, such as Figure 1 As shown, due to the small effective distance between the embedded germanium-silicon epitaxial layer and the gate structure in the peripheral circuit area, the embedded germanium-silicon epitaxial layer and the gate structure are easily broken down, which cannot meet the reliability requirements under higher operating voltages.
[0004] Furthermore, since the embedded germanium-silicon epitaxial layers in the peripheral circuit region and the core circuit region are grown synchronously, the difference in the size and density of the grooves in the peripheral circuit region and the core circuit region will cause asynchrony during the epitaxial growth process. When the grooves in the core circuit region are filled, the grooves in the peripheral circuit region may not be filled, resulting in the electrical parameters of the PMOS transistors in the peripheral circuit region not meeting the standards. Summary of the Invention
[0005] The purpose of this invention is to provide a semiconductor device and its fabrication method to solve the problems of low reliability in existing semiconductor devices.
[0006] To achieve the above objectives, the present invention provides a semiconductor device comprising:
[0007] A substrate having a peripheral circuit region and a core circuit region;
[0008] The first groove and the second groove extend from the surface of the substrate into the substrate and are located in the peripheral circuit area and the core circuit area, respectively.
[0009] An undoped epitaxial buffer layer covers the inner wall of the first groove;
[0010] A first embedded epitaxial layer and a second embedded epitaxial layer respectively fill the first groove and the second groove; and,
[0011] A first gate structure and a second gate structure, wherein the first gate structure is located on the substrate between two adjacent first grooves, and the second gate structure is located on the substrate between two adjacent second grooves.
[0012] Optionally, the first gate structure and the first embedded epitaxial layers on both sides constitute a first transistor, and the second gate structure and the second embedded epitaxial layers on both sides constitute a second transistor, wherein the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.
[0013] Optionally, the substrates on both sides of the first gate structure have a first lightly doped region, the first groove extends downward after passing through the first lightly doped region, the substrates on both sides of the second gate structure have a second lightly doped region, the second groove extends downward after passing through the second lightly doped region, and the ion doping concentration of the first lightly doped region is lower than the ion doping concentration of the second lightly doped region.
[0014] Optionally, the top of both the first embedded epitaxial layer and the top of the second embedded epitaxial layer are not lower than the surface of the substrate.
[0015] Optionally, the maximum lateral width of the first groove is greater than the maximum lateral width of the second groove.
[0016] Optionally, the material of the undoped epitaxial buffer layer is at least one of silicon, germanium, silicon carbide, or germanium-silicon; and / or, the thickness of the undoped epitaxial buffer layer is 3 nm to 10 nm.
[0017] Optionally, the material of the undoped epitaxial buffer layer includes silicon carbide, and the carbon concentration in the undoped epitaxial buffer layer gradually increases from bottom to top; and / or, the material of the undoped epitaxial buffer layer includes germanium silicon, and the germanium concentration in the undoped epitaxial buffer layer gradually increases from bottom to top.
[0018] This invention also provides a method for fabricating a semiconductor device, comprising:
[0019] A substrate is provided, wherein the substrate has a peripheral circuit region and a core circuit region;
[0020] A first gate structure and a second gate structure are formed on the substrate, wherein the first gate structure is located on the peripheral circuit region and the second gate structure is located on the core circuit region;
[0021] The substrates on both sides of the first gate structure are etched to form a first groove;
[0022] An undoped epitaxial buffer layer is formed on the inner wall of the first groove;
[0023] A first embedded epitaxial layer is formed within the first groove;
[0024] The substrate on both sides of the second gate structure is etched to form a second groove; and,
[0025] A second embedded epitaxial layer is formed within the second groove.
[0026] Optionally, the second groove and the second embedded epitaxial layer are formed after the first groove, the undoped epitaxial buffer layer and the first embedded epitaxial layer are formed; or, the first groove, the undoped epitaxial buffer layer and the first embedded epitaxial layer are formed after the second groove and the second embedded epitaxial layer are formed.
[0027] Optionally, after forming the first gate structure and the second gate structure, ion implantation is performed on the substrates on both sides of the first gate structure and the second gate structure to form a first lightly doped region in the substrates on both sides of the first gate structure and a second lightly doped region in the substrates on both sides of the second gate structure, wherein the ion doping concentration of the first lightly doped region is lower than the ion doping concentration of the second lightly doped region.
[0028] Optionally, after the first embedded epitaxial layer is formed in the first groove, the top of the first embedded epitaxial layer is not lower than the surface of the substrate; and / or, after the second embedded epitaxial layer is formed in the second groove, the top of the second embedded epitaxial layer is not lower than the surface of the substrate.
[0029] Optionally, the maximum lateral width of the first groove is greater than the maximum lateral width of the second groove.
[0030] Optionally, the step of etching the substrate on both sides of the first gate structure to form the first groove includes:
[0031] The substrates on both sides of the first gate structure are etched using a first dry etching process to form the first groove having a first initial shape;
[0032] The substrate is further etched along the first groove using a first wet etching process to form the first groove having a first final shape;
[0033] And / or, the step of etching the substrate on both sides of the second gate structure to form the second groove includes:
[0034] The substrates on both sides of the second gate structure are etched using a second dry etching process to form the second groove having a second initial shape;
[0035] The substrate is further etched along the second groove using a second wet etching process to form the second groove having a second final shape.
[0036] Optionally, before etching the substrate on both sides of the first gate structure using the first dry etching process, the core circuit area is covered with a first photoresist layer, and before continuing to etch the substrate along the first groove using the first wet etching process, the first photoresist layer is removed; and / or,
[0037] Before etching the substrates on both sides of the second gate structure using the second dry etching process, the peripheral circuit area is covered with a second photoresist layer, and the second photoresist layer is removed before continuing to etch the substrate along the second groove using the second wet etching process.
[0038] Optionally, the first initial shape is U-shaped; and / or, the second initial shape is bowl-shaped.
[0039] Optionally, after forming the first gate structure and the second gate structure, a sacrificial layer is formed on the substrate, the sacrificial layer conformally covering the substrate, the sidewalls and top of the first gate structure, and the sidewalls and top of the second gate structure;
[0040] Before etching the substrates on both sides of the first gate structure, the sacrificial layers on both sides of the first gate structure are opened; and,
[0041] Before etching the substrates on both sides of the second gate structure, the sacrificial layers on both sides of the second gate structure are opened.
[0042] Optionally, after forming the first embedded epitaxial layer, a first capping layer and a first protective layer are formed on the first embedded epitaxial layer in sequence, and a fourth protective layer is formed that conformally covers the substrate, the first protective layer, the sacrificial layer, and the sidewalls and top of the first gate structure and the second gate structure.
[0043] After forming the second embedded epitaxial layer, a second capping layer is formed on the second embedded epitaxial layer, and a second protective layer is formed on the second capping layer;
[0044] After the first and second protective layers are formed, a portion of the thickness of the sacrificial layer and the fourth protective layer are removed; and,
[0045] Remove the remaining thickness of the first protective layer, the second protective layer, and the sacrificial layer.
[0046] In the semiconductor device provided by the present invention, the substrate has a peripheral circuit region and a core circuit region; a first groove and a second groove extend from the surface of the substrate into the substrate and are located in the peripheral circuit region and the core circuit region, respectively; an undoped epitaxial buffer layer covers the inner wall of the first groove; a first embedded epitaxial layer and a second embedded epitaxial layer fill the first groove and the second groove, respectively; a first gate structure is located on the substrate between two adjacent first grooves, and a second gate structure is located on the substrate between two adjacent second grooves. In this invention, the undoped epitaxial buffer layer can increase the effective distance between the first embedded epitaxial layer and the first gate structure, improving the problem of easy breakdown between the first embedded epitaxial layer and the first gate structure due to the large first groove, and meeting the reliability requirements of the transistor in the peripheral circuit region at higher operating voltages. Moreover, the thickness of the undoped epitaxial buffer layer is relatively thin, which will not have too much impact on the device performance. This invention will not affect the size of the lightly doped region in the peripheral circuit region, thus achieving an improvement in breakdown voltage with minimal modifications. At the same time, the undoped epitaxial buffer layer can also prevent doped ions in the first embedded epitaxial layer from diffusing into the channel, improving the short-channel effect. Furthermore, the undoped epitaxial buffer layer can also serve as a buffer layer between the substrate and the first embedded epitaxial layer, improving dislocation defects in the first embedded epitaxial layer.
[0047] Accordingly, the present invention also provides a method for fabricating a semiconductor device, wherein the first groove and the first embedded epitaxial layer in the peripheral circuit region are fabricated separately from the second groove and the second embedded epitaxial layer in the core circuit region. This allows the undoped epitaxial buffer layer to be formed separately in the first groove. At the same time, it can also improve the problem of inconsistent growth heights of the first embedded epitaxial layer and the second embedded epitaxial layer caused by the inconsistency in size between the first groove and the second groove. After separate fabrication, the first embedded epitaxial layer can fill the first groove, and the first embedded epitaxial layer can also fill the second groove. The electrical parameters of the transistors in the peripheral circuit region and the core circuit region can both meet the standards. Attached Figure Description
[0048] Figure 1 VBD test pattern of the embedded germanium-silicon epitaxial layer in the existing peripheral circuit area;
[0049] Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;
[0050] Figures 3 to 15 The diagram shows the corresponding structural steps of the semiconductor device fabrication method provided in the embodiments of the present invention. Figure 15 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;
[0051] The attached figures are labeled as follows:
[0052] 100 - Substrate; STI - Trench isolation structure; 210 - First gate structure; 220 - Second gate structure; 201 - Gate oxide layer; 202 - Gate electrode layer; 203 - Gate masking layer; 204 - First sub-sidewall; 205 - Second sub-sidewall; 206 - Third sub-sidewall; 207 - Fourth sub-sidewall; 301 - Third protective layer; 401 - Mask layer; 510 - First trench; 520 - Second trench; 511 - First embedded epitaxial layer; 512 - Undoped epitaxial buffer layer; 521 - Second embedded epitaxial layer; 610 - First capping layer; 611 - First protective layer; 612 - Fourth protective layer; 620 - Second capping layer; 621 - Second protective layer; 701 - First photoresist layer; 702 - Second photoresist layer. Detailed Implementation
[0053] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0054] Figure 15 This is a schematic diagram of the semiconductor device provided in this embodiment. Figure 15 As shown, the semiconductor device includes a substrate 100, which can be made of silicon, silicon-on-insulator (SiI), germanium, silicon-germanium (SIG), or germanium-on-insulator (IGIA), among other semiconductor substrates. A trench isolation structure (STI) is formed in the substrate 100, extending from the substrate 100 into its interior, and is used to define active regions within the substrate 100. Two adjacent active regions are isolated by the trench isolation structure (STI). The substrate 100 also has a peripheral circuit region (PIO) and a core circuit region (Pcore), which are also isolated by the trench isolation structure (STI).
[0055] In this embodiment, the top of the trench isolation structure STI is higher than the surface of the substrate 100. The material of the trench isolation structure STI is silicon oxide, but it should not be limited to this. In other embodiments, the trench isolation structure STI can also be other dielectric materials, such as high-k dielectrics such as metal oxides.
[0056] The substrate 100 has a plurality of first gate structures 210 and a plurality of second gate structures 220. The first gate structures 210 are spaced apart on the peripheral circuit region PIO, and the second gate structures 220 are spaced apart on the core circuit region Pcore. The first gate structures 210 and the second gate structures 220 have the same structure. Specifically, both the first gate structure 210 and the second gate structure 220 include a gate oxide layer 201, a gate electrode layer 202, a gate shielding layer 203, a first sidewall, and a second sidewall. The gate oxide layer 201, the gate electrode layer 202, and the gate shielding layer 203 are all patterned films, and the gate oxide layer 201, the gate electrode layer 202, and the gate shielding layer 203 are stacked sequentially from bottom to top. The first sidewall covers the sidewalls of the gate oxide layer 201, the gate electrode layer 202, and the gate shielding layer 203, and the second sidewall covers the first sidewall.
[0057] In this embodiment, the material of the gate oxide layer 201 can be a dielectric material such as silicon oxynitride or silicon oxide, the material of the gate electrode layer 202 can typically be a conductive material such as polycrystalline silicon or metal, and the material of the gate shielding layer 203 can typically be a dielectric material such as silicon nitride.
[0058] The first and second sidewalls are typically stacked structures made of dielectric materials such as silicon oxide and silicon nitride. For example, in this embodiment, the first sidewall includes a first sub-sidewall 204 and a second sub-sidewall 205. The first sub-sidewall 204 covers the sidewalls of the gate oxide layer 201, the gate electrode layer 202, and the gate shielding layer 203, while the second sub-sidewall 205 covers the first sub-sidewall 204. The third sub-sidewall 206 covers the first sidewall (specifically, it covers the second sub-sidewall 205), and the fourth sub-sidewall 207 covers the third sub-sidewall 206. Furthermore, the materials of the first sub-sidewall 204 and the third sub-sidewall 206 are typically dielectric materials such as silicon oxide, while the materials of the second sub-sidewall 205 and the fourth sub-sidewall 207 can be dielectric materials such as silicon nitride.
[0059] Furthermore, the substrate 100 also includes a first lightly doped drain (LDD), a first doped pocket region, a second lightly doped region, and a second doped pocket region. The first lightly doped region and the first doped pocket region are both located within the peripheral circuit region PIO, with the first lightly doped region located on both sides of the first gate structure 210, and the first doped pocket region surrounding the channel side of the corresponding first lightly doped region. The second lightly doped region and the second doped pocket region are both located within the core circuit region Pcore, with the second lightly doped region located on both sides of the second gate structure 220, and the second doped pocket region surrounding the channel side of the corresponding second lightly doped region. The first lightly doped region and the second lightly doped region can improve the short-channel effect of the transistor, and the shallow junction formed between the first lightly doped region, the second lightly doped region, and the corresponding channel helps reduce leakage current. The first doped pocket region and the second doped pocket region narrow the depletion region below the first gate structure 210 and the second gate structure 220, respectively, alleviating the short-channel effect and further reducing leakage current.
[0060] The types of dopant ions in the first lightly doped region and the second lightly doped region are consistent with the types of transistors formed by the peripheral circuit region PIO and the core circuit region Pcore, respectively. The types of dopant ions in the first doped pocket region and the second doped pocket region are opposite to the types of transistors formed by the peripheral circuit region PIO and the core circuit region Pcore, respectively. In this embodiment, the type of transistor formed by the peripheral circuit region PIO and the core circuit region Pcore is a PMOS transistor. The dopant ions in the first lightly doped region and the second lightly doped region are one or more P-type ions selected from B, Ga, or In. The dopant ions in the first doped pocket region and the second doped pocket region are one or more N-type ions selected from P, As, or Sb.
[0061] The substrate 100 has a first groove 510 and a second groove 520, both extending from the surface of the substrate 100 into the substrate 100. Specifically, the first groove 510 is located within the peripheral circuit region PIO, extending downwards from the surface of the substrate 100 after passing through the first lightly doped region; the second groove 520 is located within the core circuit region Pcore, extending downwards from the surface of the substrate 100 after passing through the second lightly doped region.
[0062] In this embodiment, the final shape of the first groove 510 and the second groove 520 is diamond-shaped, which is the “∑” shape recognized in the industry. However, it should not be limited to this. In some embodiments, the shape of the first groove 510 and the second groove 520 can also be other shapes, such as rectangle, inverted trapezoid, U-shape, etc.
[0063] Furthermore, in this embodiment, the maximum lateral width of the first groove 510 is greater than the maximum lateral width of the second groove 520, and the depth of the first groove 510 is also greater than the depth of the second groove 520.
[0064] The first recess 510 has an undoped epitaxial buffer layer 512, which conformally covers the inner wall of the first recess 510. The first recess 510 also has a first embedded epitaxial layer 511, which is located on the undoped epitaxial buffer layer 512 and fills the first recess 510. The second recess 520 has a second embedded epitaxial layer 521, which fills the second recess 520. The first embedded epitaxial layers 511 on both sides of the first gate structure 210 are source / drain doped, and the second embedded epitaxial layers 521 on both sides of the second gate structure 220 are also source / drain doped. As can be imagined, the first gate structure 210 and the first embedded epitaxial layers 511 on both sides constitute the first transistor, with the first gate structure 210 serving as the gate of the first transistor and the first embedded epitaxial layers 511 on both sides serving as the source and drain of the first transistor, respectively; the second gate structure 220 and the second embedded epitaxial layers 521 on both sides constitute the second transistor, with the second gate structure 220 serving as the gate of the second transistor and the second embedded epitaxial layers 521 on both sides serving as the source and drain of the second transistor, respectively.
[0065] Furthermore, in this embodiment, both the first transistor and the second transistor are PMOS transistors, and the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor, thereby making the turn-on speed of the first transistor lower than that of the second transistor. Since adjusting the ion doping concentration of the first lightly doped region can adjust the threshold voltage of the first transistor, and adjusting the ion doping concentration of the second lightly doped region can adjust the threshold voltage of the second transistor, controlling the ion doping concentration of the first lightly doped region to be lower than that of the second lightly doped region can make the threshold voltage of the first transistor greater than that of the second transistor.
[0066] It is understandable that, since the threshold voltage of the first transistor is high, the first transistor needs to operate at a high voltage. The size of the first groove 510 is large, so the effective distance D1 between the first groove 510 and the first gate structure 210 is also large. If the first embedded epitaxial layer 511 is directly used to fill the first groove 510, the effective distance between the first embedded epitaxial layer 511 and the first gate structure 210 will also be D1, resulting in a low breakdown voltage between the first embedded epitaxial layer 511 and the first gate structure 210, making it easy to be broken down.
[0067] In this embodiment, the inner wall of the first groove 510 is covered by the undoped epitaxial buffer layer 512, and the first embedded epitaxial layer 511 is located on the undoped epitaxial buffer layer 512. The effective distance between the first embedded epitaxial layer 511 and the first gate structure 210 is D2, where D2 > D1. Therefore, the undoped epitaxial buffer layer 512 can increase the effective distance between the first embedded epitaxial layer 511 and the first gate structure 210, improving the problem of easy breakdown between the first embedded epitaxial layer 511 and the first gate structure 210 due to the large size of the first groove 510, and meeting the reliability requirements of the first transistor at higher operating voltages. Furthermore, the thickness of the undoped epitaxial buffer layer 512 is relatively thin (the thickness of the undoped epitaxial buffer layer 512 can be 3nm to 10nm), so it will not have too much impact on device performance. This embodiment does not require changing the size of the first groove 510, and will not affect the size of the first lightly doped region, thus achieving an increase in breakdown voltage with minimal modifications. Meanwhile, the undoped epitaxial buffer layer 512 can also prevent doped ions in the first embedded epitaxial layer 511 from diffusing into the channel, thus improving the short-channel effect. Furthermore, the undoped epitaxial buffer layer 512 can also serve as a buffer layer between the substrate 100 and the first embedded epitaxial layer 511, improving dislocation defects in the first embedded epitaxial layer 511.
[0068] Optionally, the material of the embedded epitaxial layer 511 may be germanium silicon, and the material of the undoped epitaxial buffer layer 512 may be at least one of silicon, germanium, silicon carbide or germanium silicon.
[0069] In this embodiment, both the embedded epitaxial layer 511 and the undoped epitaxial buffer layer 512 are made of germanium-silicon. The germanium concentration in the embedded epitaxial layer 511 gradually increases from bottom to top (germanium concentration is 30% to 50%). The undoped epitaxial buffer layer 512 is a single-layer structure, and the germanium concentration in the undoped epitaxial buffer layer 512 gradually increases from bottom to top (germanium concentration is 10% to 30%). In this way, the undoped epitaxial buffer layer 512 can better solve the problems of lattice mismatch and thermal expansion mismatch between the substrate 100 and the first embedded epitaxial layer 511, and reduce dislocation defects in the first embedded epitaxial layer 511.
[0070] Of course, in some embodiments, the material of the undoped epitaxial buffer layer 512 can also be silicon carbide, and the carbon concentration in the undoped epitaxial buffer layer 512 gradually increases from bottom to top, which can also achieve similar technical effects as in this embodiment.
[0071] It is understood that the undoped epitaxial buffer layer 512 may also be a stack of multiple film layers. For example, the undoped epitaxial buffer layer 512 may be a bilayer structure, with the first layer being silicon carbide and the second layer being germanium silicon, but this should not be the limitation.
[0072] Furthermore, the top of both the first embedded epitaxial layer 511 and the top of the second embedded epitaxial layer 521 are not lower than the surface of the substrate 100, thereby avoiding the problem that the electrical parameters of the first transistor or the second transistor would not meet the standards due to the first embedded epitaxial layer 511 failing to fill the first groove 510 or the second embedded epitaxial layer 521 failing to fill the second groove 520. In this embodiment, the top of both the first embedded epitaxial layer 511 and the top of the second embedded epitaxial layer 521 are flush with the surface of the substrate 100.
[0073] Please continue reading. Figure 15The first embedded epitaxial layer 511 also has a first capping layer 610, which covers the corresponding first embedded epitaxial layer 511. The first capping layer 610 can protect the first embedded epitaxial layer 511 and can be converted into a metal silicide layer to serve as the contact metal of the first embedded epitaxial layer 511. Similarly, the second embedded epitaxial layer 521 also has a second capping layer 620, which covers the corresponding second embedded epitaxial layer 521. The second capping layer 620 can protect the second embedded epitaxial layer 521 and can be converted into a metal silicide layer to serve as the contact metal of the second embedded epitaxial layer 521.
[0074] In this embodiment, the materials of the first capping layer 610 and the second capping layer 620 can be silicon, and boron doping can be introduced to increase the carrier concentration.
[0075] Based on this, this embodiment also provides a method for fabricating the semiconductor device. Figure 2 This is a flowchart illustrating the fabrication method of the semiconductor device provided in this embodiment. Figure 2 As shown, the method for fabricating the semiconductor device includes:
[0076] Step S100: Provide a substrate having a peripheral circuit region and a core circuit region;
[0077] Step S200: A first gate structure and a second gate structure are formed on the substrate, wherein the first gate structure is located on the peripheral circuit region and the second gate structure is located on the core circuit region;
[0078] Step S300: Etch the substrate on both sides of the first gate structure to form a first groove;
[0079] Step S400: Form an undoped epitaxial buffer layer on the inner wall of the first groove;
[0080] Step S500: Form a first embedded epitaxial layer within the first groove;
[0081] Step S600: Etch the substrate on both sides of the second gate structure to form a second groove; and,
[0082] Step S700: Form a second embedded epitaxial layer in the second groove.
[0083] Figures 3 to 15 This is a schematic diagram of the structure corresponding to the steps of the semiconductor device fabrication method provided in this embodiment. Next, we will combine... Figures 3 to 15 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.
[0084] like Figure 3 As shown, in step S100, the substrate 100 is provided, and a trench isolation structure STI is formed in the substrate 100. The trench isolation structure STI extends from the surface of the substrate 100 into the substrate 100, and is used to isolate two adjacent active regions and to isolate the peripheral circuit region PIO and the core circuit region Pcore. The top of the trench isolation structure STI is higher than the surface of the substrate 100, but this is not a limitation.
[0085] The method for forming the trench isolation structure STI can be, for example, forming a mask layer on the substrate 100. Figure 3 (Not shown in the image), then the mask layer and a portion of the substrate 100 are etched to form an isolation trench. An isolation material is then filled into the isolation trench, and planarization is performed to remove the isolation material from the mask layer. The mask layer is then removed. The isolation material within the isolation trench constitutes the trench isolation structure (STI). After removing the mask layer, the top of the trench isolation structure STI will be higher than the surface of the substrate 100. The thickness of the trench isolation structure STI extending beyond the surface of the substrate 100 is the thickness of the mask layer.
[0086] Please continue reading. Figure 3 In step S200, a plurality of first gate structures 210 and a plurality of second gate structures 220 are formed on the substrate 100. The first gate structures 210 are located on the peripheral circuit region PIO, and the second gate structures 220 are located on the core circuit region Pcore. The first gate structures 210 and the second gate structures 220 have the same structure and are fabricated simultaneously.
[0087] The steps of forming the first gate structure 210 and the second gate structure 220 may include: depositing a gate oxide material layer, a gate electrode material layer, and a gate shielding material layer all over the substrate 100. Figure 3 (Not shown in the image), then the gate masking material layer, the gate electrode material layer, and the gate oxide material layer are etched until the substrate 100 is exposed. The remaining gate oxide material layer, gate electrode material layer, and gate masking material layer constitute the gate oxide layer 201, the gate electrode layer 202, and the gate masking layer 203, respectively. The gate oxide layer 201, the gate electrode layer 202, and the gate masking layer 203 are stacked sequentially to form several gate stack structures. A portion of the gate stack structures is located on the peripheral circuit region PIO, and another portion is located on the core circuit region Pcore. The first sub-sidewall material layer and the second sub-sidewall material layer are deposited all over the substrate 100. Figure 3(Not shown in the image), the first sub-sidewall material layer and the second sub-sidewall material layer conformally cover the substrate and the sidewalls of the gate stack structure. Then, the second sub-sidewall material layer and the first sub-sidewall material layer are etched to remove the second sub-sidewall material layer and the first sub-sidewall material layer on the substrate 100 and the top of the gate stack structure. The second sub-sidewall material layer and the first sub-sidewall material layer on the sidewalls of the gate stack structure are retained to form the first sub-sidewall 204 and the second sub-sidewall 205. The first sub-sidewall 204 and the second sub-sidewall 205 constitute the first sidewall.
[0088] Please continue reading. Figure 3 Ion implantation is performed on the substrates 100 on both sides of the first gate structure 210 and the substrates 100 on both sides of the second gate structure 220 to form a first lightly doped region and a first doped pocket region in the substrates 100 on both sides of the first gate structure 210, and a second lightly doped region and a second doped pocket region in the substrates 100 on both sides of the second gate structure 220. The first doped pocket region surrounds the corresponding first lightly doped region on the side near the channel, and the second doped pocket region surrounds the corresponding second lightly doped region on the side near the channel.
[0089] In this embodiment, a first transistor with a high threshold voltage needs to be formed in the peripheral circuit region PIO, and a second transistor with a high threshold voltage needs to be formed in the core circuit region Pcore. Therefore, the ion doping concentration of the first lightly doped region can be lower than the ion doping concentration of the second lightly doped region.
[0090] like Figure 4 As shown, in step S300, a third protective layer 301 and a mask layer 401 are sequentially formed on the substrate 100. The third protective layer 301 and the mask layer 401 are stacked sequentially and conformally cover the substrate 100, the sidewalls and top of the first gate structure 210, and the sidewalls and top of the second gate structure 220. The third protective layer 301 and the mask layer 401 together constitute a sacrificial layer.
[0091] In this embodiment, the third protective layer 301 and the mask layer 401 are formed using atomic layer deposition (ALD) technology. However, this should be limited to the above, and other deposition processes may also be used to form the third protective layer 301 and the mask layer 401.
[0092] Furthermore, the material of the third protective layer 301 can be silicon oxide or silicon oxynitride, and the thickness of the third protective layer 301 is preferably 3nm to 5nm. The material of the mask layer 401 can be silicon nitride, and the thickness of the mask layer 401 is preferably 100nm to 150nm.
[0093] like Figure 5 As shown, a first photoresist layer 701 is formed on the core circuit region Pcore. The first photoresist layer 701 specifically covers the mask layer 401 on the core circuit region Pcore, thereby completely covering the core circuit region Pcore with the first photoresist layer 701.
[0094] Please continue reading. Figure 5 The mask layer 401 and the third protective layer 301 on the peripheral circuit region PIO are etched to remove the mask layer 401 and the third protective layer 301 on both sides of the first gate structure 210, thereby opening the mask layer 401 and the third protective layer 301 on both sides of the first gate structure 210 (opening the sacrificial layer) and exposing the substrate 100 on both sides of the first gate structure 210. In this step, since the first photoresist layer 701 covers the core circuit region Pcore, the mask layer 401 and the third protective layer 301 on the core circuit region Pcore will not be opened.
[0095] Next, the substrate 100 on both sides of the first gate structure 210 is etched using a first dry etching process to form the first groove 510 with a first initial shape, which is U-shaped. It should be noted that the first dry etching process first etches the first lightly doped region until it penetrates the first lightly doped region, and then continues etching downwards on the substrate 100 until the first groove 510 is formed. Therefore, the first groove 510 extends downwards from the surface of the substrate 100, beyond the first lightly doped region, and continues to extend downwards into the interior of the substrate 100.
[0096] like Figure 6As shown, after removing the first photoresist layer 701, the substrate 100 on both sides of the first gate structure 210 is further etched using a first wet etching process. The etchant from the first wet etching process flows into the first groove 510, continuing to etch the substrate 100 within the first groove 510. Because the etchant in the wet etching process is selective for crystal orientation, the shape and size of the first groove 510 will change after etching, forming the first groove 510 with a first final shape. In this embodiment, the etchant used in the wet etching process on the substrate 100 is tetramethylammonium hydroxide (TMAN). This etchant... <111> The etching rate of the crystal orientation is lower than that of other crystal orientations. After etching is completed, the first final shape is diamond-shaped.
[0097] It should be noted that the initial shape is U-shaped. The effective distance between the first groove 510 and the first gate structure 210 in the U-shape is larger than that in other shapes (such as bowl-shaped) (it can be about 1nm to 2nm larger). Therefore, after forming the diamond-shaped first groove 510, the effective distance between the diamond-shaped first groove 510 and the first gate structure 210 is also larger, thereby increasing the breakdown voltage between the subsequently formed first embedded epitaxial layer 511 and the first gate structure 210, and thus improving the reliability of the device.
[0098] In some embodiments, the first initial shape is not limited to a U-shape, but can also be a bowl shape, a saucer shape, a rectangle or an inverted trapezoid, etc. The shape of the first final shape is not limited to a diamond shape, but can also be designed as a rectangle, an inverted trapezoid, a U-shape, etc., as needed.
[0099] In some embodiments, the etchant in the first wet etching process may also be potassium hydroxide (KOH).
[0100] It should be noted that when the mask layer 401 and the third protective layer 301 on both sides of the first gate structure 210 are etched to open the substrate 100, and when the substrate 100 is etched to form the first groove 510, the mask layer 401 and the third protective layer 301 on the top of the first gate structure 210 are also removed. It is conceivable that the remaining mask layer 401 and the third protective layer 301 may only be located on the sidewalls of the first gate structure 210.
[0101] Furthermore, in this embodiment, the photomask used in the step of redesigning the substrate 100 on both sides of the first gate structure 210 can be replaced by an existing photomask, which can save costs and does not change the size of the first groove 510.
[0102] like Figure 7As shown, in step S400, an undoped epitaxial buffer layer 512 is formed on the inner wall of the first groove 510 using a selective epitaxy process. The undoped epitaxial buffer layer 512 conformally covers the inner wall of the first groove 510, thereby occupying a certain space within the first groove 510. Since the second groove 520 has not yet been formed, the undoped epitaxial buffer layer 512 can be formed solely within the first groove 510.
[0103] In some embodiments, the thickness of the undoped epitaxial buffer layer 512 can be 3 nm to 10 nm.
[0104] like Figure 8 As shown, in step S500, a first embedded epitaxial layer 511 is formed in the first groove 510 (i.e., on the undoped epitaxial buffer layer 512) using a selective epitaxial growth process. The first embedded epitaxial layer 511 can fill the first groove 510. At this time, the undoped epitaxial buffer layer 512 can serve as a buffer layer between the substrate 100 and the first embedded epitaxial layer 511, which can improve dislocation defects in the first embedded epitaxial layer 511.
[0105] It is understood that the undoped epitaxial buffer layer 512 can increase the effective distance between the first embedded epitaxial layer 511 and the first gate structure 210, improving the problem of easy breakdown between the first embedded epitaxial layer 511 and the first gate structure 210 caused by the large size of the first groove 510, and meeting the reliability requirements of the first transistor at higher operating voltages. Furthermore, the thickness of the undoped epitaxial buffer layer 512 is relatively thin, so it will not have a significant impact on device performance. This embodiment does not require changing the size of the first groove 510, and will not affect the size of the first lightly doped region, thus achieving an increase in breakdown voltage with minimal modifications. Simultaneously, the undoped epitaxial buffer layer 512 can also prevent doped ions in the first embedded epitaxial layer 511 from diffusing into the channel, improving the short-channel effect.
[0106] Furthermore, the selective epitaxial growth process can be any one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).
[0107] like Figure 9As shown, a first capping layer 610 is formed on the first embedded epitaxial layer 511. The first capping layer 610 covers the first embedded epitaxial layer 511 and can be subsequently converted into a metal silicide layer as the contact metal of the first embedded epitaxial layer 511.
[0108] Please continue reading. Figure 9 A first protective layer 611 is formed on the first capping layer 610, covering the first capping layer 610. Next, a fourth protective layer 612 is formed on the substrate 100, conformally covering the substrate 100, the first protective layer 611, the sacrificial layer (specifically, the mask layer 401 within the sacrificial layer), and the tops of the first gate structure 210 and the second gate structure 220. That is, the fourth protective layer 612 completely covers the structures on the peripheral circuit region PIO and the core circuit region Pcore. The first protective layer 611 and the fourth protective layer 612 together act as a mask layer, protecting the first capping layer 610, the sacrificial layer, the first gate structure 210, the second gate structure 220, and the core circuit region Pcore of the substrate 100 during subsequent processes. The first protective layer 611 can be made of silicon oxide, which can be formed using a thermal oxidation process. The fourth protective layer 612 can be made of silicon nitride, which can be formed using processes such as atomic layer deposition.
[0109] like Figure 10 As shown, in step S600, a second photoresist layer 702 is formed on the peripheral circuit region PIO. The second photoresist layer 702 specifically covers the fourth protective layer 612 on the peripheral circuit region PIO, thereby completely covering the structure on the peripheral circuit region PIO with the second photoresist layer 702.
[0110] Please continue reading. Figure 10 The fourth protective layer 612, the mask layer 401, and the third protective layer 301 on the core circuit region Pcore are etched to remove the fourth protective layer 612, the mask layer 401, and the third protective layer 301 on both sides of the second gate structure 220, thereby opening the fourth protective layer 612, the mask layer 401, and the third protective layer 301 on both sides of the second gate structure 220 (opening the sacrificial layer) and exposing the substrate 100 on both sides of the second gate structure 220. In this step, since the second photoresist layer 702 covers the peripheral circuit region PIO, the structure on the peripheral circuit region PIO will not be damaged.
[0111] Next, a second dry etching process is used to etch the substrate 100 on both sides of the second gate structure 220 to form the second groove 520 with a second initial shape, which is bowl-shaped. It should be noted that the second dry etching process first etches the second lightly doped region until it penetrates the second lightly doped region, and then continues etching downwards on the substrate 100 until the second groove 520 is formed. Therefore, the second groove 520 extends downwards from the surface of the substrate 100, beyond the second lightly doped region, and continues to extend downwards into the interior of the substrate 100.
[0112] like Figure 11 As shown, after removing the second photoresist layer 702, a second wet etching process is used to continue etching the substrate 100 on both sides of the second gate structure 220. The etchant of the second wet etching process flows into the second groove 520, continuing to etch the substrate 100 within the second groove 520. Because the etchant in the wet etching process is selective for crystal orientation, the shape and size of the second groove 520 will change after etching, forming the second groove 520 with a second final shape. In this embodiment, the etchant used in the wet etching process on the substrate 100 is tetramethylammonium hydroxide (TMAN). This etchant... <111> The etching rate of the crystal orientation is lower than that of other crystal orientations. After etching is completed, the second final shape is diamond-shaped.
[0113] It should be noted that the second initial shape is bowl-shaped. The effective distance between the second groove 520 and the corresponding channel in the bowl shape is smaller than that in other shapes (such as bowl shape). Therefore, after forming the diamond-shaped second groove 520, the effective distance between the diamond-shaped second groove 520 and the corresponding channel is also smaller, thereby effectively increasing the stress. Although it will also reduce the breakdown voltage between the subsequently formed second embedded epitaxial layer 521 and the second gate structure 220, since the threshold voltage of the second transistor is designed to be low, reducing the breakdown voltage between the second embedded epitaxial layer 521 and the second gate structure 220 will not have too much impact on the reliability of the device.
[0114] In some embodiments, the second initial shape is not limited to a bowl shape, but can also be a U-shape, a saucer shape, a rectangle or an inverted trapezoid, etc. The shape of the second final shape is not limited to a diamond shape, but can also be designed as a rectangle, an inverted trapezoid, a U-shape, etc., as needed.
[0115] In some embodiments, the etchant in the second wet etching process may also be potassium hydroxide (KOH).
[0116] It should be noted that when the fourth protective layer 612, the mask layer 401, and the third protective layer 301 on both sides of the second gate structure 220 are etched to expose the substrate 100, and when the substrate 100 is etched to form the second groove 520, the fourth protective layer 612, the mask layer 401, and the third protective layer 301 on the top of the second gate structure 220 are also removed. It is conceivable that the remaining fourth protective layer 612, the mask layer 401, and the third protective layer 301 may only be located on the sidewalls of the second gate structure 220.
[0117] Furthermore, in this embodiment, the photomask used in the step of etching the substrate 100 on both sides of the second gate structure 220 does not need to be redesigned; an existing photomask can be used directly (that is, the same photomask used in the step of etching the substrate 100 on both sides of the first gate structure 210), which can save costs and does not change the size of the second groove 520. After etching is completed, the maximum lateral width of the first groove 510 will also be greater than the maximum lateral width of the second groove 520.
[0118] like Figure 12 As shown, in step S700, the second embedded epitaxial layer 521 is formed in the second groove 520 by selective epitaxial growth process, and the second embedded epitaxial layer 521 can fill the second groove 520.
[0119] It is understandable that the first embedded epitaxial layer 511 and the second embedded epitaxial layer 521 are fabricated separately. This improves the problem of inconsistent growth heights of the first embedded epitaxial layer 511 and the second embedded epitaxial layer 521 caused by the inconsistent sizes of the first groove 510 and the second groove 520. After being fabricated separately, the first embedded epitaxial layer 511 can fill the first groove 510 (the top of the first embedded epitaxial layer 511 will not be lower than the surface of the substrate 100), and the second embedded epitaxial layer 521 can also fill the second groove 520 (the top of the second embedded epitaxial layer 521 will not be lower than the surface of the substrate 100). The electrical parameters of the first transistor and the second transistor can both meet the standards.
[0120] like Figure 13 As shown, a second capping layer 620 is formed on the second embedded epitaxial layer 521. The second capping layer 620 covers the second embedded epitaxial layer 521 and can be subsequently converted into a metal silicide layer as the contact metal of the second embedded epitaxial layer 521.
[0121] Please continue reading. Figure 13A second protective layer 621 is formed on the second capping layer 620, covering the second capping layer 620 and thus protecting it. The second protective layer 621 can be formed using processes such as thermal oxidation. The material of the second protective layer 621 can be silicon oxide.
[0122] Since the structure on the core circuit region Pcore needs to be etched and wet-cleaned after the first protective layer 611 is formed, the total thickness of the first protective layer 611 and the fourth protective layer 612 can be appropriately thicker, so as to better protect the peripheral circuit region PIO and part of the core circuit region Pcore, and effectively avoid damage to the first capping layer 610, the first gate structure 210 and the second gate structure 220. After the second protective layer 621 is formed, there are fewer subsequent processes, so the second protective layer 621 can be relatively thin.
[0123] It should be noted that in this embodiment, the first groove 510, the undoped epitaxial buffer layer 512, and the first embedded epitaxial layer 511 are formed first, followed by the formation of the second groove 520 and the second embedded epitaxial layer 521. In some embodiments, the second groove 520 and the second embedded epitaxial layer 521 may be formed first, followed by the formation of the first groove 510, the undoped epitaxial buffer layer 512, and the first embedded epitaxial layer 511.
[0124] like Figure 14 As shown, the mask layer 401 is stripped using phosphoric acid. In this step, the fourth protective layer 612 is also stripped simultaneously, which is equivalent to removing part of the thickness of the sacrificial layer and the fourth protective layer 612. Then, the third protective layer 301 is removed using hydrofluoric acid. In this step, the first protective layer 611 and the second protective layer 621 are also removed, which is equivalent to removing the remaining thickness of the first protective layer 611, the second protective layer 621, and the sacrificial layer.
[0125] like Figure 15 As shown, a second sidewall is then formed on the first sidewall, covering the first sidewall. In this embodiment, the second sidewall includes a third sub-sidewall 206 and a fourth sub-sidewall 207, whereby the third sub-sidewall 206 covers the first sidewall and the fourth sub-sidewall 207 covers the third sub-sidewall 206. The method for forming the second sidewall is similar to the method for forming the first sidewall, and will not be described in detail here.
[0126] Subsequently, source and drain electrodes can be formed by source and drain doping in the first embedded epitaxial layer 511 and the second embedded epitaxial layer 521.
[0127] In summary, in the semiconductor device provided in the embodiments of the present invention, the substrate has a peripheral circuit region and a core circuit region; a first groove and a second groove extend from the surface of the substrate into the substrate and are located in the peripheral circuit region and the core circuit region, respectively; an undoped epitaxial buffer layer covers the inner wall of the first groove; a first embedded epitaxial layer and a second embedded epitaxial layer fill the first groove and the second groove, respectively; a first gate structure is located on the substrate between two adjacent first grooves, and a second gate structure is located on the substrate between two adjacent second grooves. In this invention, the undoped epitaxial buffer layer can increase the effective distance between the first embedded epitaxial layer and the first gate structure, improving the problem of easy breakdown between the first embedded epitaxial layer and the first gate structure due to the large first groove, and meeting the reliability requirements of the transistor in the peripheral circuit region at higher operating voltages. Moreover, the thickness of the undoped epitaxial buffer layer is relatively thin, which will not have too much impact on the device performance. This invention will not affect the size of the lightly doped region in the peripheral circuit region, thus achieving an improvement in breakdown voltage with minimal modifications. At the same time, the undoped epitaxial buffer layer can also prevent doped ions in the first embedded epitaxial layer from diffusing into the channel, improving the short-channel effect. Furthermore, the undoped epitaxial buffer layer can also serve as a buffer layer between the substrate and the first embedded epitaxial layer, improving dislocation defects in the first embedded epitaxial layer.
[0128] Accordingly, this invention also provides a method for fabricating a semiconductor device, wherein the first groove and the first embedded epitaxial layer in the peripheral circuit region are fabricated separately from the second groove and the second embedded epitaxial layer in the core circuit region. This allows the undoped epitaxial buffer layer to be formed separately in the first groove. Simultaneously, it improves the problem of inconsistent growth heights of the first and second embedded epitaxial layers caused by the inconsistent sizes of the first and second grooves. After separate fabrication, the first embedded epitaxial layer can fill both the first and second grooves, and the electrical parameters of the transistors in both the peripheral circuit region and the core circuit region can meet the requirements.
[0129] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0130] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.
[0131] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.
[0132] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.
Claims
1. A semiconductor device, characterized in that, include: A substrate having a peripheral circuit region and a core circuit region; The first groove and the second groove extend from the surface of the substrate into the substrate and are located in the peripheral circuit area and the core circuit area, respectively. An undoped epitaxial buffer layer covers the inner wall of the first groove; A first embedded epitaxial layer and a second embedded epitaxial layer respectively fill the first groove and the second groove; and, A first gate structure and a second gate structure, wherein the first gate structure is located on the substrate between two adjacent first grooves, and the second gate structure is located on the substrate between two adjacent second grooves.
2. The semiconductor device as claimed in claim 1, characterized in that, The first gate structure and the first embedded epitaxial layers on both sides constitute a first transistor, and the second gate structure and the second embedded epitaxial layers on both sides constitute a second transistor. The threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.
3. The semiconductor device as described in claim 2, characterized in that, The substrates on both sides of the first gate structure have a first lightly doped region, and the first groove extends downward after passing through the first lightly doped region. The substrates on both sides of the second gate structure have a second lightly doped region, and the second groove extends downward after passing through the second lightly doped region. The ion doping concentration of the first lightly doped region is lower than that of the second lightly doped region.
4. The semiconductor device as claimed in claim 1, characterized in that, The top of the first embedded epitaxial layer and the top of the second embedded epitaxial layer are both not lower than the surface of the substrate.
5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The maximum lateral width of the first groove is greater than the maximum lateral width of the second groove.
6. The semiconductor device according to any one of claims 1 to 4, characterized in that, The material of the undoped epitaxial buffer layer is at least one of silicon, germanium, silicon carbide, or germanium-silicon; and / or, the thickness of the undoped epitaxial buffer layer is 3 nm to 10 nm.
7. The semiconductor device according to any one of claims 1 to 4, characterized in that, The material of the undoped epitaxial buffer layer includes silicon carbide, and the carbon concentration in the undoped epitaxial buffer layer gradually increases from bottom to top; and / or, the material of the undoped epitaxial buffer layer includes germanium silicon, and the germanium concentration in the undoped epitaxial buffer layer gradually increases from bottom to top.
8. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, wherein the substrate has a peripheral circuit region and a core circuit region; A first gate structure and a second gate structure are formed on the substrate, wherein the first gate structure is located on the peripheral circuit region and the second gate structure is located on the core circuit region; The substrates on both sides of the first gate structure are etched to form a first groove; An undoped epitaxial buffer layer is formed on the inner wall of the first groove; A first embedded epitaxial layer is formed within the first groove; The substrate on both sides of the second gate structure is etched to form a second groove; and, A second embedded epitaxial layer is formed within the second groove.
9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After forming the first groove, the undoped epitaxial buffer layer, and the first embedded epitaxial layer, the second groove and the second embedded epitaxial layer are then formed; or, after forming the second groove and the second embedded epitaxial layer, the first groove, the undoped epitaxial buffer layer, and the first embedded epitaxial layer are then formed.
10. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After forming the first gate structure and the second gate structure, ion implantation is performed on the substrates on both sides of the first gate structure and the second gate structure to form a first lightly doped region in the substrates on both sides of the first gate structure and a second lightly doped region in the substrates on both sides of the second gate structure. The ion doping concentration of the first lightly doped region is lower than that of the second lightly doped region.
11. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After the first embedded epitaxial layer is formed in the first groove, the top of the first embedded epitaxial layer is not lower than the surface of the substrate; and / or, after the second embedded epitaxial layer is formed in the second groove, the top of the second embedded epitaxial layer is not lower than the surface of the substrate.
12. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The maximum lateral width of the first groove is greater than the maximum lateral width of the second groove.
13. The method for fabricating a semiconductor device according to any one of claims 8 to 12, characterized in that, The step of etching the substrates on both sides of the first gate structure to form the first groove includes: The substrates on both sides of the first gate structure are etched using a first dry etching process to form the first groove having a first initial shape; The substrate is further etched along the first groove using a first wet etching process to form the first groove having a first final shape; And / or, the step of etching the substrate on both sides of the second gate structure to form the second groove includes: The substrates on both sides of the second gate structure are etched using a second dry etching process to form the second groove having a second initial shape; The substrate is further etched along the second groove using a second wet etching process to form the second groove having a second final shape.
14. The method for fabricating a semiconductor device as described in claim 13, characterized in that, Before etching the substrates on both sides of the first gate structure using the first dry etching process, the core circuit area is covered with a first photoresist layer, and before continuing to etch the substrate along the first groove using the first wet etching process, the first photoresist layer is removed; and / or, Before etching the substrates on both sides of the second gate structure using the second dry etching process, the peripheral circuit area is covered with a second photoresist layer, and the second photoresist layer is removed before continuing to etch the substrate along the second groove using the second wet etching process.
15. The method for fabricating a semiconductor device as described in claim 13, characterized in that, The first initial shape is U-shaped; and / or the second initial shape is bowl-shaped.
16. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After forming the first gate structure and the second gate structure, a sacrificial layer is formed on the substrate, the sacrificial layer conformally covering the substrate, the sidewalls and top of the first gate structure and the sidewalls and top of the second gate structure; Before etching the substrates on both sides of the first gate structure, the sacrificial layers on both sides of the first gate structure are opened; and, Before etching the substrates on both sides of the second gate structure, the sacrificial layers on both sides of the second gate structure are opened.
17. The method for fabricating a semiconductor device as described in claim 16, characterized in that, After forming the first embedded epitaxial layer, a first capping layer and a first protective layer are formed on the first embedded epitaxial layer in sequence, and a fourth protective layer is formed that conformally covers the substrate, the first protective layer, the sacrificial layer, and the sidewalls and top of the first gate structure and the second gate structure. After forming the second embedded epitaxial layer, a second capping layer is formed on the second embedded epitaxial layer, and a second protective layer is formed on the second capping layer; After the first protective layer and the second protective layer are both formed, a portion of the thickness of the sacrificial layer and the fourth protective layer are removed; and, Remove the remaining thickness of the first protective layer, the second protective layer, and the sacrificial layer.