MOS device and manufacturing method thereof
By setting a double-sided interconnect structure on both sides of the substrate of the MOS device, the parasitic effects and warpage caused by the increase in the length of the metal interconnects are solved, thereby achieving performance improvement and increased integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2026-03-13
AI Technical Summary
As device integration increases, the length of metal interconnects increases, leading to significant parasitic effects and severe substrate warping, which cannot meet the demands for improved device performance and higher integration.
A double-sided interconnect structure is adopted. By setting a first back-end interconnect layer and a second back-end interconnect layer on both sides of the substrate, the length of the interconnect line is shortened, and warping is avoided by stress balancing of the two interconnect layers.
It effectively improves parasitic effects, enhances device performance, increases interconnect integration density, avoids substrate warpage, and meets the needs of improved device performance and higher integration.
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Figure CN121665675A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the semiconductor field, and in particular to a MOS device and a method for manufacturing the same. Background Technology
[0002] When fabricating MOS devices using CMOS (Complementary Metal Oxide Semiconductor) technology, the MOS devices and their related structures are fabricated within a substrate, and a multilayer back-end interconnect structure is fabricated on the front side of the substrate to achieve the connection between MOS devices and the connection between MOS devices and external signals.
[0003] As device integration density increases, the back-end interconnect structures on the substrate surface become increasingly complex. The number of metal interconnect layers increases, and the length of the metal interconnects connecting to the device ends becomes longer, leading to more pronounced parasitic effects and resulting in decreased device performance, failing to meet the demands for improved device performance and higher integration density. Simultaneously, with the increase in metal interconnect layers, the thickness of the front-side film on the substrate increases, leading to increased stress on the substrate and problems such as substrate warping.
[0004] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention
[0005] The purpose of this application is to provide a MOS device and a method for manufacturing the same, which reduces the parasitic effects of the back-end interconnect structure, enabling the back-end interconnect structure to meet the requirements of improved device performance and increased integration, while avoiding substrate warping.
[0006] To address the aforementioned technical problems, this application provides a MOS device, comprising:
[0007] Substrate;
[0008] The source and drain regions are located in the substrate;
[0009] The gate is located on one side of the first surface of the substrate;
[0010] The first back-end interconnect layer is located on one side of the first surface of the substrate and is electrically connected to the gate, the source region and the drain region through a first conductive structure;
[0011] The second back-end interconnect layer is located on one side of the second surface of the substrate and is electrically connected to the source region and the drain region through a second conductive structure.
[0012] Optionally, it also includes:
[0013] A control layer and a first insulating dielectric layer are located on the second surface of the substrate;
[0014] In the direction perpendicular to the substrate, the control layer at least located on one side of the source epitaxial structure in the source region has a lateral groove, and / or, the control layer at least located on one side of the drain epitaxial structure in the drain region has a lateral groove.
[0015] The first insulating dielectric layer is located in the transverse groove.
[0016] Optionally, it also includes:
[0017] A second insulating dielectric layer located on the second surface of the substrate;
[0018] In the source region, the end face of the source epitaxial structure near the second surface of the substrate is flush with or protrudes from the surface of the second insulating dielectric layer away from the substrate; and / or, in the drain region, the end face of the drain epitaxial structure near the second surface of the substrate is flush with or protrudes from the surface of the second insulating dielectric layer away from the substrate.
[0019] Optionally, it also includes: a shallow isolation trench structure;
[0020] The substrate includes a first MOS transistor region and a second MOS transistor region, and the shallow isolation trench structure is located between the first MOS transistor region and the second MOS transistor region.
[0021] Optionally, it also includes:
[0022] A barrier layer is located on the outer surface of the source epitaxial structure and the drain epitaxial structure in the second MOS transistor region;
[0023] The source epitaxial structure and the drain epitaxial structure are embedded in the substrate, with the source epitaxial structure located in the source region and the drain epitaxial structure located in the drain region.
[0024] Optionally, it also includes:
[0025] A silicide layer is located between the source epitaxial structure and the contact hole, and / or between the drain epitaxial structure and the contact hole;
[0026] The first conductive structure includes the contact hole, the source epitaxial structure and the drain epitaxial structure are embedded in the substrate, the source epitaxial structure is located in the source region, and the drain epitaxial structure is located in the drain region.
[0027] This application also provides a method for manufacturing a MOS device, comprising:
[0028] A device prefabrication structure is obtained; the device prefabrication structure includes a substrate, a source region, a drain region, a gate, and a first back-channel interconnect layer, wherein the source region and the drain region are located in the substrate, the gate is located on the side of the first surface of the substrate, and the first back-channel interconnect layer is electrically connected to the gate, the source region, and the drain region through a first conductive structure;
[0029] A dielectric layer is fabricated on the first back-end interconnect layer;
[0030] The device prefabrication structure is bonded to the carrier through the dielectric layer;
[0031] Thin the substrate at its second surface;
[0032] A second conductive structure electrically connected to the source region and the drain region is fabricated on one side of the second surface of the substrate;
[0033] A second back-end interconnect layer electrically connected to the second conductive structure is fabricated on the second conductive structure.
[0034] Optionally, obtaining the device prefabricated structure includes:
[0035] A gate dielectric layer is deposited on the first surface of the substrate;
[0036] A gate electrode is fabricated on the gate dielectric layer;
[0037] The substrate is etched to form source region trenches and drain region trenches;
[0038] The source region and the drain region are fabricated in the source region groove and the drain region groove;
[0039] A first conductive structure electrically connected to the source region, the drain region, and the gate is formed on one side of the first surface of the substrate;
[0040] A first back-end interconnect layer electrically connected to the first conductive structure is formed on the upper surface of the first conductive structure.
[0041] Optionally, before obtaining the device prefabrication structure, the process also includes:
[0042] A control layer is fabricated on the first surface of the first substrate unit layer;
[0043] A second substrate unit layer is fabricated on the surface of the control layer opposite to the first substrate unit layer; the first substrate unit layer and the second substrate unit layer serve as the substrate.
[0044] After etching the substrate to form source and drain region trenches, the process further includes:
[0045] The control layer is etched within the source region groove and the drain region groove to form a lateral groove in the control layer; wherein, in the direction perpendicular to the substrate, the lateral groove is located at least on one side of the source region groove, and / or, the lateral groove is located at least on one side of the drain region groove;
[0046] A first insulating dielectric layer is filled into the transverse groove.
[0047] Optionally, before obtaining the device prefabrication structure, the process also includes:
[0048] A second insulating dielectric layer is fabricated on the first surface of the first substrate unit layer;
[0049] A second substrate unit layer is fabricated on the surface of the second insulating dielectric layer that is opposite to the first substrate unit layer; the first substrate unit layer and the second substrate unit layer serve as the substrate.
[0050] Accordingly, thinning the substrate on the second surface of the substrate includes:
[0051] The first substrate unit layer is removed from the second surface of the first substrate unit layer until the second insulating dielectric layer is removed.
[0052] This application provides a MOS device comprising: a substrate; a source region and a drain region located in the substrate; a gate located on one side of a first surface of the substrate; a first back-channel interconnect layer located on one side of the first surface of the substrate and electrically connected to the gate, the source region and the drain region through a first conductive structure; and a second back-channel interconnect layer located on one side of a second surface of the substrate and electrically connected to the source region and the drain region through a second conductive structure.
[0053] As can be seen, the MOS device in this application includes a substrate, a source region, a drain region, a gate, a first back-channel interconnect layer, and a second back-channel interconnect layer, which are located on opposite sides of the substrate. By setting a double-sided interconnect structure with the first and second back-channel interconnect layers, the length of the interconnects can be shortened, effectively improving parasitic effects and enhancing the performance of the MOS device. Simultaneously, the interconnect integration density can be increased, meeting the demands for improved device performance and higher integration. Furthermore, since there are back-channel interconnect structures on both sides of the substrate, the stresses generated by the first and second back-channel interconnect layers on the substrate can cancel each other out and balance each other, avoiding problems such as substrate warping caused by stress from a single back-channel interconnect layer.
[0054] In addition, this application also provides a manufacturing method having the above-mentioned advantages. Attached Figure Description
[0055] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0056] Figure 1 A schematic diagram of the structure of a MOS device provided in an embodiment of this application. Figure 1 ;
[0057] Figure 2 A schematic diagram of the structure of a MOS device provided in an embodiment of this application. Figure 2 ;
[0058] Figure 3 This is a comparative schematic diagram of a MOS device provided in an embodiment of this application and a MOS device in the prior art when the contact hole is offset;
[0059] Figure 4(a) is a partial enlarged view of the first insulating dielectric layer in a MOS device provided in an embodiment of this application;
[0060] Figure 4(b) is a partial enlarged view of the first insulating dielectric layer in another MOS device provided in the embodiment of this application;
[0061] Figure 5 A schematic diagram of the structure of a MOS device provided in an embodiment of this application. Figure 3 ;
[0062] Figure 6 A schematic diagram of the structure of a MOS device provided in this application embodiment is shown in Figure 4.
[0063] Figure 7 A schematic diagram of the structure of a MOS device provided in an embodiment of this application. Figure 5 ;
[0064] Figure 8 A flowchart illustrating a method for manufacturing a MOS device according to an embodiment of this application;
[0065] Figures 9 to 17 A manufacturing process flow diagram of a MOS device provided in an embodiment of this application;
[0066] Figures 18 to 32 A manufacturing process flow diagram of another MOS device provided in an embodiment of this application;
[0067] In the figure, 1. Substrate, 2. Gate, 3. Second back-channel interconnect layer, 4. First back-channel interconnect layer, 5. Source epitaxial structure, 6. Drain epitaxial structure, 7. Gate dielectric layer, 8. Control layer, 9. Contact hole, 10. Metal layer, 11. First dielectric layer, 12. Second dielectric layer, 13. First insulating dielectric layer, 14. Third dielectric layer, 15. Fourth dielectric layer, 16. Shallow isolation trench structure, 17. Barrier layer, 18. Silicate layer, 19. Substrate to be removed, 20. Shallow doped silicon epitaxial layer, 21. SiGe layer, 22. Bonding dielectric layer, 23. Carrier, 24. Source region trench, 25. Drain region trench, 26. Lateral trench, 27. First substrate unit layer, 28. Second substrate unit layer, 29. Second insulating dielectric layer. Detailed Implementation
[0068] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0069] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.
[0070] As described in the background section, existing MOS devices only have a back-channel interconnect layer on the front side of the substrate. As the integration density of devices increases, the single-sided back-channel interconnect layer is increasingly unable to meet the performance requirements of the devices. Furthermore, the length of the interconnect lines in the back-channel interconnect layer is getting longer and longer, the number of interconnect layers is increasing, the parasitic effects are becoming more and more obvious, and it can also cause substrate warping.
[0071] In view of this, this application provides a MOS device, please refer to... Figure 1 ,include:
[0072] Substrate 1;
[0073] The source and drain regions are located in the substrate 1;
[0074] Gate 2 is located on the side of the first surface of the substrate 1;
[0075] The first back-end interconnect layer 4 is located on one side of the first surface of the substrate 1 and is electrically connected to the gate 2, the source region and the drain region through a first conductive structure;
[0076] The second back-end interconnect layer 3 is located on the side of the second surface of the substrate 1 and is electrically connected to the source region and the drain region through a second conductive structure.
[0077] Substrate 1 can be a silicon substrate 1.
[0078] In this embodiment, the MOS device can be a planar CMOS device.
[0079] The substrate 1 may include a first MOS transistor region A and a second MOS transistor region B. The first MOS transistor region A and the second MOS transistor region B respectively include a source region, a drain region, and a gate 2. The first back-channel interconnect layer 4 and the second back-channel interconnect layer 3 are both located in the first MOS transistor region A and the second MOS transistor region B.
[0080] Of the first MOS transistor region A and the second MOS transistor region B, one can be a PMOS transistor region and the other can be an NMOS transistor region.
[0081] The source region includes a source electrode, which includes a source epitaxial structure 5. The drain region includes a drain electrode, which includes a drain epitaxial structure 6. The gate 2 is located between the source epitaxial structure 5 and the drain epitaxial structure 6.
[0082] The source epitaxial structure 5 and the drain epitaxial structure 6 can be hexagonal (i.e., Sigma shape), rectangular, or fin-shaped, etc. The source epitaxial structure 5 and the drain epitaxial structure 6 are located inside the substrate 1, and in the direction perpendicular to the substrate 1, the two ends of the source epitaxial structure 5 and the drain epitaxial structure 6 protrude from the first surface and the second surface of the substrate 1, respectively.
[0083] For the PMOS transistor region, the source epitaxial structure 5 and the drain epitaxial structure 6 can be germanium silicon (SiGe), and for the NMOS transistor region, the source epitaxial structure 5 and the drain epitaxial structure 6 can be phosphorus-doped silicon (Si:P).
[0084] It should be noted that a gate dielectric layer 7 may also be distributed between the first surface of the substrate 1 and the gate 2, with the gate 2 located on the surface of the gate dielectric layer 7 facing away from the first surface of the substrate 1. The gate dielectric layer 7 is used for electrical insulation between the gate 2 and the substrate 1, and the material of the gate dielectric layer 7 includes, but is not limited to, any one of silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.
[0085] The first back-end interconnect layer 4 includes multiple layers of metal interconnects and contact holes 9 connecting the metal interconnects. For specific structures, please refer to relevant technologies, which will not be described in detail here.
[0086] The first conductive structure may include a contact hole 9 and a metal layer 10. The gate 2, the source epitaxial structure 5 and the drain epitaxial structure 6 are each connected to a contact hole 9 (CT). Each contact hole 9 is connected to a metal layer 10. The metal layer 10 is connected to the first back-end interconnect layer 4.
[0087] The second back-end interconnect layer 3 includes multiple layers of metal wires and contact holes 9 for connecting the metal wires. The specific number of metal wire layers is not limited in this embodiment and depends on the situation.
[0088] Metal interconnects need to avoid component structures on the device. For example, if there are already a lot of component structures on the first surface of substrate 1 and the metal interconnects in the first back-end interconnect layer 4 are relatively long, the metal interconnects can be moved to the second surface of substrate 1. Since there are fewer component structures on the second surface, the length of the metal interconnects can be shortened, thereby effectively improving parasitic effects.
[0089] The second conductive structure may include a contact hole 9 and a metal layer 10. The source epitaxial structure 5 and the drain epitaxial structure 6 are respectively connected to a contact hole 9. Each contact hole 9 is connected to a metal layer 10. The metal layer 10 is electrically connected to the second back-end interconnect layer 3.
[0090] The contact hole 9 is filled with metal, which can be copper or other materials. The metal layer 10 can be made of copper, aluminum, etc.
[0091] The gate 2 is led out only from the first surface of the substrate 1, and the contact hole 9 connecting the source and drain of the device can be led out from the first surface and the second surface respectively.
[0092] Between the gate dielectric layer 7 and the first back-channel interconnect layer 4, there are also stacked first dielectric layer 11 and second dielectric layer 12, the second dielectric layer 12 is located around the metal layer 10, and the first dielectric layer 11 is located around the contact hole 9 and the gate 2.
[0093] Between the substrate 1 and the second back-end interconnect layer 3, there are also stacked third dielectric layer 14 and fourth dielectric layer 15, the fourth dielectric layer 15 is located around the metal layer 10, and the third dielectric layer 14 is located around the contact hole 9.
[0094] The material of the first dielectric layer 11 includes, but is not limited to, any one of silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.
[0095] The material of the second dielectric layer 12 includes, but is not limited to, any one of silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.
[0096] The material of the third dielectric layer 14 includes, but is not limited to, any one of silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.
[0097] The material of the fourth dielectric layer 15 includes, but is not limited to, any one of silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.
[0098] In this embodiment, the MOS device includes a substrate 1, a source region, a drain region, a gate 2, a first back-channel interconnect layer 4, and a second back-channel interconnect layer 3, which are located on opposite sides of the substrate 1. By setting a double-sided interconnect structure with the first back-channel interconnect layer 4 and the second back-channel interconnect layer 3, the interconnect integration density can be increased to meet the performance requirements of the device. Furthermore, the length of the interconnect lines can be shortened, effectively improving parasitic effects and enhancing the performance of the MOS device. Moreover, since there are back-channel interconnect structures on both sides of the substrate 1, the stresses generated by the first back-channel interconnect layer 4 and the second back-channel interconnect layer 3 on the substrate 1 can cancel each other out and balance each other, avoiding problems such as substrate 1 warping caused by stress from a single back-channel interconnect layer.
[0099] Based on the above embodiments, in one embodiment of this application, please refer to... Figures 2 to 3 MOS devices may also include:
[0100] The control layer 8 and the first insulating dielectric layer 13 are located on the second surface of the substrate 1;
[0101] In the direction perpendicular to the substrate 1, the control layer 8 at least located on one side of the source epitaxial structure 5 in the source region has a lateral groove, and / or, the control layer 8 at least located on one side of the drain epitaxial structure 6 in the drain region has a lateral groove.
[0102] The first insulating dielectric layer 13 is located in the transverse groove.
[0103] In the source region, the end face of the source epitaxial structure 5 near the second surface of the substrate 1 is flush with or protrudes from the first insulating dielectric layer 13 and away from the surface of the substrate 1; and / or, the end face of the drain epitaxial structure 6 near the second surface of the substrate 1 is flush with or protrudes from the first insulating dielectric layer 13 and away from the surface of the substrate 1, so as to ensure that the contact hole 9 in the second conductive structure is in contact with the source epitaxial structure 5 and the drain epitaxial structure 6 to achieve electrical connection.
[0104] The function of the control layer 8 is to precisely control the thickness of the substrate 1 during the thinning process of the substrate 1 in the manufacturing process of the MOS device.
[0105] The greater the difference in etching rates between the control layer 8 and the substrate 1, the better. For example, the material of the control layer 8 can be germanium silicon or germanium.
[0106] As one possible implementation, the thickness of the control layer 8 can range from 3nm to 100nm. The control layer 8 is relatively thin, which makes the MOS device thinner and can also reduce the manufacturing cost of the MOS device.
[0107] For example, the thickness of the control layer 8 can be 3nm, 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc.
[0108] A first insulating dielectric layer 13 is provided on one side (left or right) or both sides (left and right) of the source epitaxial structure 5, and a first insulating dielectric layer 13 is provided on one side (left or right) or both sides (left and right) of the drain epitaxial structure 6. When the contact hole 9 in the second conductive structure connects the source epitaxial structure 5 and the drain epitaxial structure 6, if the contact hole 9 is misaligned, the first insulating dielectric layer 13 can play a protective role, avoiding short circuits between the contact hole 9 and the channel region, etc. At the same time, it can also reduce the alignment accuracy between the contact hole 9 and the source epitaxial structure 5 and the drain epitaxial structure 6, and reduce the alignment difficulty.
[0109] As one possible implementation, a first insulating dielectric layer 13 is provided on both sides of the source epitaxial structure 5 and both sides of the drain epitaxial structure 6. When the contact hole 9 is aligned, the contact hole 9 is offset to the left and right sides by a certain amount, which further reduces the difficulty of alignment.
[0110] The material of the first insulating dielectric layer 13 includes, but is not limited to, any one of silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.
[0111] The transverse groove is formed by extending away from the source epitaxial structure 5 along the direction parallel to the second surface of the substrate 1 from the contact point with the source epitaxial structure 5, and by extending away from the drain epitaxial structure 6 along the direction parallel to the second surface of the substrate 1 from the contact point with the drain epitaxial structure 6.
[0112] It should be noted that the size of the transverse groove is not limited in this embodiment and can be set by the user.
[0113] As one possible implementation, the length of the transverse groove can range from 3nm to 100nm, which reduces the alignment accuracy of the contact hole 9 while reducing the manufacturing difficulty of the transverse groove.
[0114] For example, the length of the transverse groove (the dimension in the direction parallel to the second surface of the substrate 1) can be 3nm, 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc.
[0115] The length of the first insulating dielectric layer 13 can range from 3 nm to 100 nm. For example, the length of the first insulating dielectric layer 13 (the dimension in the direction parallel to the second surface of the substrate 1) can be 3 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc.
[0116] As one possible implementation, the length of the first insulating dielectric layer 13 can be equal to the length of the transverse groove, that is, the first insulating dielectric layer 13 fills the transverse groove, such as... Figure 2 As shown. However, this embodiment does not limit this. In other possible embodiments of this application, the length of the first insulating dielectric layer 13 can be less than the length of the transverse groove, that is, there is a certain gap between the first insulating dielectric layer 13 and the source epitaxial structure 5, and between the first insulating dielectric layer 13 and the drain epitaxial structure 6, so as to reduce the manufacturing difficulty of the first insulating dielectric layer 13.
[0117] In one embodiment of this application, the first insulating dielectric layer 13 includes a first insulating dielectric unit layer 131 and a second insulating dielectric unit layer 132 stacked in the direction perpendicular to the first surface of the substrate 1, as shown in FIG4(a).
[0118] It should be noted that this application does not limit the relationship between the thickness of the first insulating dielectric layer 13 (the dimension in the direction perpendicular to the second surface of the substrate 1) and the thickness of the control layer 8 (the dimension in the direction perpendicular to the second surface of the substrate 1).
[0119] As one possible implementation, the thickness of the first insulating dielectric layer 13 is equal to the thickness of the control layer 8, such as... Figure 2 , Figure 3 As shown in Figure 4(a).
[0120] As another possible implementation, the thickness of the first insulating dielectric layer 13 is less than the thickness of the control layer 8, and the surface of the first insulating dielectric layer 13 facing away from the substrate 1 and the surface of the control layer 8 facing away from the substrate 1 are on the same horizontal plane, so that the contact hole 9 contacts the first insulating dielectric layer 13 when it is offset. That is, there can be a part of the control layer 8 between the first insulating dielectric layer 13 and the substrate 1, as shown in Figure 4(b).
[0121] Based on the above embodiments, in one embodiment of this application, please refer to... Figure 5 MOS devices may also include:
[0122] The second insulating dielectric layer 29 is located on the second surface of the substrate 1;
[0123] In the source region, the end face of the source epitaxial structure 5 near the second surface of the substrate 1 is flush with or protrudes from the second insulating dielectric layer 29 and away from the surface of the substrate 1; and / or, in the drain region, the end face of the drain epitaxial structure 6 near the second surface of the substrate 1 is flush with or protrudes from the second insulating dielectric layer 29 and away from the surface of the substrate 1.
[0124] In this embodiment, by providing a second insulating dielectric layer 29 on the second surface of the substrate 1, when the contact hole 9 in the second conductive structure connects the source epitaxial structure 5 and the drain epitaxial structure 6, if the contact hole 9 is misaligned, the second insulating dielectric layer 29 can play a protective role, avoiding short circuits between the contact hole 9 and the channel region. At the same time, it can also reduce the alignment accuracy between the contact hole 9 and the source epitaxial structure 5 and the drain epitaxial structure 6, and reduce the alignment difficulty.
[0125] The thickness of the second insulating dielectric layer 29 can range from 3nm to 100nm. The thickness of the second insulating dielectric layer 29 is relatively thin, which makes the MOS device thinner and can also reduce the manufacturing cost of the MOS device.
[0126] For example, the thickness of the second insulating dielectric layer 29 can be 3nm, 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc.
[0127] The material of the second insulating dielectric layer 29 includes, but is not limited to, any one of silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.
[0128] To ensure that the contact hole 9 in the second conductive structure contacts the source epitaxial structure 5 and the drain epitaxial structure 6 to achieve electrical connection, the end face of the source epitaxial structure 5 near the second surface of the substrate 1 can be flush with the surface of the second insulating dielectric layer 29 away from the substrate 1, or protrude from the surface of the second insulating dielectric layer 29 away from the substrate 1; the end face of the drain epitaxial structure 6 near the second surface of the substrate 1 can be flush with the surface of the second insulating dielectric layer 29 away from the substrate 1, or protrude from the surface of the second insulating dielectric layer 29 away from the substrate 1.
[0129] Please refer to Figure 6 and Figure 7 Based on the above embodiments, in one embodiment of this application, the MOS device may further include:
[0130] Shallow isolation trench structure 16;
[0131] The substrate 1 includes a first MOS transistor region and a second MOS transistor region, and the shallow isolation trench structure 16 is located between the first MOS transistor region and the second MOS transistor region.
[0132] The shallow isolation trench structure 16 provides physical and electrical isolation between the first MOS transistor region A and the second MOS transistor region B, preventing mutual interference between the first MOS transistor region A and the second MOS transistor region B.
[0133] Please refer to Figure 1 , Figure 2 , Figure 6 and Figure 7 Based on the above embodiments, in one embodiment of this application, the MOS device may further include:
[0134] Barrier layer 17 is located on the outer surface of source epitaxial structure 5 and drain epitaxial structure 6 in the second MOS transistor region;
[0135] The source epitaxial structure 5 and the drain epitaxial structure 6 are embedded in the substrate 1, with the source epitaxial structure 5 located in the source region and the drain epitaxial structure 6 located in the drain region.
[0136] The second MOS transistor region B is an NMOS transistor region. The source epitaxial structure 5 and the drain epitaxial structure 6 can be phosphorus-doped silicon. By setting the barrier layer 17, damage to the source epitaxial structure 5 and the drain epitaxial structure 6 of the NMOS transistor region can be prevented in the relevant process of thinning the substrate 1 from the second surface of the substrate 1 using wet method.
[0137] The material of the barrier layer 17 can be germanium-silicon.
[0138] Please refer to Figure 1 , Figure 2 , Figure 6 and Figure 7 Based on the above embodiments, in one embodiment of this application, the MOS device may further include:
[0139] A silicide layer 18 is located between the source epitaxial structure 5 and the contact hole 9, and / or between the drain epitaxial structure 6 and the contact hole 9;
[0140] The first conductive structure includes the contact hole 9, the source epitaxial structure 5 and the drain epitaxial structure 6 are embedded in the substrate 1, the source epitaxial structure 5 is located in the source region, and the drain epitaxial structure 6 is located in the drain region.
[0141] The silicide layer 18 can be made of metal silicides, such as nickel silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), etc.
[0142] The silicide layer 18 can reduce the resistance between the contact hole 9 and the substrate 1, thereby improving the performance of the semiconductor device; it can provide good ohmic contact, ensuring that the current can flow smoothly from the metal layer 10 to the source and drain regions in the substrate 1; it can improve the electrical reliability at the contact hole 9 and reduce device failure due to poor contact; at the same time, it can also reduce the parasitic capacitance of the source and drain regions, thereby improving the frequency response of the device.
[0143] This application also provides a method for manufacturing a MOS device, please refer to... Figure 8 The method may include:
[0144] Step S101: Obtain the device prefabricated structure;
[0145] The device prefabrication structure includes a substrate, a source region, a drain region, a gate, and a first back-end interconnect layer. The source region and the drain region are located in the substrate, and the gate is located on one side of the first surface of the substrate. The first back-end interconnect layer is electrically connected to the gate, the source region, and the drain region through a first conductive structure.
[0146] It should be noted that the device prefabrication structure also includes a gate dielectric layer, a first dielectric layer and a second dielectric layer. The gate dielectric layer is located between the gate and the first surface of the substrate. The first dielectric layer and the second dielectric layer are stacked between the gate dielectric layer and the first back-end interconnect layer. The second dielectric layer is located around the metal layer, and the first dielectric layer is located around the contact hole and the gate.
[0147] Step S102: Fabricate a dielectric layer on the first back-end interconnect layer.
[0148] The function of the dielectric layer is to bond the device prefabrication structure to the carrier so as to create a second back-end interconnect layer on the second surface of the substrate.
[0149] In this embodiment, the dielectric layer is not limited and can be set by the user.
[0150] The dielectric layer can be any one of silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.
[0151] A dielectric layer is deposited on the first back-end interconnect layer, and then the surface of the dielectric layer is polished and planarized to facilitate subsequent bonding processes.
[0152] Step S103: Bond the device prefabricated structure to the carrier through the dielectric layer.
[0153] It should be noted that, prior to bonding, a process of grinding and removing the edges of the silicon wafer using the TRIM process may also be included.
[0154] Step S104: Thin the substrate on the second surface of the substrate.
[0155] It should be noted that the method of thinning the substrate is not limited in this embodiment and can be selected at your own discretion.
[0156] As one possible implementation method, wet etching can be used to thin the substrate. The thickness of the thinned substrate can be set as needed, and no specific limitation is made here. The etching solution used in the wet etching process can be an alkaline solution, such as sodium hydroxide solution.
[0157] When the substrate is thinned, the source epitaxial structure and the drain epitaxial structure can be exposed.
[0158] Step S105: Fabricate a second conductive structure that is electrically connected to the source region and the drain region on the side where the second surface of the substrate is located.
[0159] The second conductive structure includes a contact hole and a metal layer. The fabrication process includes: depositing a third dielectric layer on the second surface of the substrate, then photolithographically forming a through hole on the third dielectric layer, depositing metal in the through hole and performing CMP (Chemical Mechanical Polishing) to metallize the through hole and form a contact hole; then depositing a fourth dielectric layer on the third dielectric layer, then photolithographically forming a through hole on the fourth dielectric layer, and depositing metal in the through hole to form a metal layer connected to the contact hole.
[0160] It should be noted that after the second back-end interconnect layer is fabricated, the fabrication of pads (PADs) may also be included. The specific process will not be described in detail in this embodiment.
[0161] Step S106: Fabricate a second back-end interconnect layer that is electrically connected to the second conductive structure on the second conductive structure.
[0162] The MOS device fabricated in this embodiment includes a substrate, a source region, a drain region, a gate, a first back-channel interconnect layer, and a second back-channel interconnect layer, which are located on opposite sides of the substrate. By setting a double-sided interconnect structure with the first and second back-channel interconnect layers, the interconnect integration density can be increased to meet the performance requirements of the device. Furthermore, the length of the interconnect lines can be shortened, effectively improving parasitic effects and enhancing the performance of the MOS device. Moreover, since there are back-channel interconnect structures on both sides of the substrate, the stresses generated by the first and second back-channel interconnect layers on the substrate can cancel each other out and balance each other, avoiding substrate warping and other problems caused by stress from a single back-channel interconnect layer.
[0163] Based on the above embodiments, in one embodiment of this application, obtaining the device prefabricated structure includes:
[0164] Step S1011: Deposit a gate dielectric layer on the first surface of the substrate.
[0165] The material of the first dielectric layer includes, but is not limited to, any one of silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.
[0166] Step S1012: Fabricate a gate on the gate dielectric layer.
[0167] The gate fabrication process may include: depositing a gate film on a gate dielectric layer, performing photolithography and etching on the gate film to form a via in the gate film, fabricating the gate in the via, and then removing the remaining gate film.
[0168] Step S1013: Etch the substrate to form source region trenches and drain region trenches.
[0169] Step S1014: Fabricate the source region and the drain region in the source region groove and the drain region groove.
[0170] For ease of explanation, steps S1013 and S1014 will be explained together.
[0171] The substrate may include a first MOS transistor region and a second MOS transistor region. The first MOS transistor region and the second MOS transistor region respectively include a source region and a drain region. During fabrication, the source region and drain region of the first MOS transistor region can be fabricated first, then the first MOS transistor region can be protected, and then the source region and drain region of the second MOS transistor region can be fabricated.
[0172] Of the first MOS transistor region and the second MOS transistor region, one can be a PMOS transistor region and the other can be an NMOS transistor region.
[0173] The fabrication process of the source and drain epitaxial structures in the PMOS transistor region can include: etching the substrate using dry etching to form trenches for the source and drain regions; processing the trenches using wet etching to form Sigma-shaped grooves; and then epitaxially growing a SiGe layer to form the source and drain epitaxial structures.
[0174] The fabrication process of the source and drain epitaxial structures of the NMOS transistor region may include: etching the substrate using dry etching to form trenches for the source and drain regions; processing the trenches using wet etching to form Sigma-shaped grooves; epitaxially layering a barrier layer inside and outside the Sigma-shaped grooves; and then epitaxially forming phosphorus-doped silicon in the Sigma-shaped grooves to form the source and drain epitaxial structures.
[0175] Step S1015: A first conductive structure electrically connected to the source region, the drain region and the gate is formed on one side of the first surface of the substrate.
[0176] The first conductive structure includes a contact hole and a metal layer. The fabrication process includes: depositing a first dielectric layer on the gate, then photolithographically forming a through hole on the first dielectric layer, depositing metal in the through hole and performing CMP polishing to metallize the through hole and form a contact hole; then depositing a second dielectric layer on the first dielectric layer, then photolithographically forming a through hole on the second dielectric layer, and depositing metal in the through hole to form a metal layer connected to the contact hole.
[0177] Step S1016: Fabricate a first back-end interconnect layer electrically connected to the first conductive structure on the upper surface of the first conductive structure.
[0178] The specific manufacturing process of the first back-end interconnect layer can be found in relevant technologies, and will not be elaborated here.
[0179] Based on any of the above embodiments, in one embodiment of this application, before depositing the gate dielectric layer on the first surface of the substrate, the following may be included:
[0180] A shallow isolation trench structure is fabricated between the first MOS transistor region and the second MOS transistor region on the substrate.
[0181] The shallow isolation trench structure provides physical and electrical isolation between the first MOS transistor region and the second MOS transistor region, preventing mutual interference between the first MOS transistor region and the second MOS transistor region.
[0182] Based on any of the above embodiments, in one embodiment of this application, before depositing the gate dielectric layer on the first surface of the substrate, the following may be included:
[0183] A first epitaxial layer is grown on the substrate to be removed, wherein the doping concentration of the first epitaxial layer is different from that of the substrate to be removed;
[0184] A second epitaxial layer is grown on the first epitaxial layer, wherein the second epitaxial layer and the first epitaxial layer are of different types.
[0185] The substrate is grown on the second epitaxial layer;
[0186] Accordingly, thinning the substrate on the second surface of the substrate includes:
[0187] The substrate to be removed is removed by grinding.
[0188] Remove the first epitaxial layer;
[0189] Remove the second epitaxial layer;
[0190] Remove a portion of the substrate.
[0191] The first epitaxial layer can be a doped silicon epitaxial layer, and the greater the difference in doping concentration between it and the silicon substrate, the better, so that the thickness of the substrate to be removed can be accurately controlled when removing the substrate.
[0192] The thickness of the substrate to be removed can range from 10 micrometers to 200 micrometers. In this embodiment, a grinding method is used to remove the substrate, which can improve the removal speed of the substrate and thus improve the fabrication efficiency of semiconductor devices.
[0193] The second epitaxial layer can be a germanium-silicon layer or a germanium layer. Since it is a different type of epitaxial layer from the first epitaxial layer, the removal rate is different, and the removal thickness can be accurately controlled.
[0194] The removal methods for the first epitaxial layer and the second epitaxial layer can be wet removal or CMP polishing, and this embodiment does not limit the method.
[0195] In this embodiment, a layer-by-layer gradual removal method is adopted when thinning the substrate, which has good process stability and can improve the yield of the device.
[0196] As one possible implementation, the removal of the substrate can be performed in two steps: first, the substrate is thinned using wet etching or CMP processes, stopping at the STI (Surface Mount Technology); then, the substrate is removed using wet etching with an alkaline solution until the source and drain epitaxial structures are exposed. Gradually thinning the substrate in a progressive manner can improve device yield, and this thinning process has good stability.
[0197] In one embodiment of this application, only a first epitaxial layer or a second epitaxial layer may be epitaxially grown on the substrate to be removed, and then the substrate may continue to grow.
[0198] Based on any of the above embodiments, in one embodiment of this application, the method for manufacturing a MOS device may further include, before obtaining the device prefabrication structure:
[0199] A control layer is fabricated on the first surface of the first substrate unit layer;
[0200] A second substrate unit layer is fabricated on the surface of the control layer opposite to the first substrate unit layer; the first substrate unit layer and the second substrate unit layer serve as the substrate.
[0201] After etching the substrate to form source and drain region trenches, the process further includes:
[0202] The control layer is etched within the source region groove and the drain region groove to form a lateral groove in the control layer; wherein, in the direction perpendicular to the substrate, the lateral groove is located at least on one side of the source region groove, and / or, the lateral groove is located at least on one side of the drain region groove;
[0203] A first insulating dielectric layer is filled into the transverse groove.
[0204] In this embodiment, the source region groove and the drain region groove extend from the first substrate unit layer to the second substrate unit layer.
[0205] The transverse grooves can be fabricated using either wet etching or dry etching; no specific method is specified in this embodiment.
[0206] When the first insulating dielectric layer is deposited in the transverse groove, the insulating dielectric material begins to adhere on the upper and lower surfaces of the transverse groove to form the first insulating dielectric unit layer and the second insulating dielectric unit layer, respectively. The thickness of the first insulating dielectric unit layer and the second insulating dielectric unit layer is equal, that is, only half the depth of the transverse groove (the dimension in the direction perpendicular to the second surface of the substrate) of the film layer needs to be grown.
[0207] It should be noted that during the deposition of the first insulating dielectric layer, a first insulating dielectric layer is also formed in the source region trench and the drain region trench, as well as on the gate dielectric layer. It is also necessary to remove the first insulating dielectric layer in the source region trench and the drain region trench, as well as on the gate dielectric layer, and retain the first insulating dielectric layer in the lateral trench.
[0208] As one possible implementation, the first insulating dielectric layer in the source region trench and drain region trench, as well as on the gate dielectric layer, can be removed using isotropic etching.
[0209] When removing the first insulating dielectric layer inside the source region groove and drain region groove, as well as on the gate dielectric layer, a portion of the first insulating dielectric layer at the opening of the transverse groove can also be removed, so that there is a certain gap between the first insulating dielectric layer inside the transverse groove and the subsequently fabricated source epitaxial structure and drain epitaxial structure.
[0210] The first and second substrate unit layers can be silicon. The greater the difference in etching rates between the control layer and the substrate, the better. For example, the material of the control layer can be germanium-silicon or germanium.
[0211] In the second conductive structure, when the contact hole connects the source epitaxial structure and the drain epitaxial structure, if the contact hole is misaligned, the first insulating dielectric layer can play a protective role, avoiding short circuits between the contact hole and the channel region. At the same time, it can also reduce the alignment accuracy between the contact hole and the source epitaxial structure and the drain epitaxial structure, reducing the alignment difficulty.
[0212] In this embodiment, when thinning the substrate, the second substrate unit layer is removed. Since the control layer and the second substrate unit layer have significantly different properties, the thinning can be accurately stopped at the control layer, thereby achieving precise control of the substrate thinning thickness.
[0213] In one embodiment of this application, when creating a transverse groove in the etch control layer, the entire control layer can be etched away, and then an insulating dielectric layer can be filled in the area where the control layer was removed.
[0214] Based on any of the above embodiments, in one embodiment of this application, the method for manufacturing a MOS device may further include, before obtaining the device prefabrication structure:
[0215] A second insulating dielectric layer is fabricated on the first surface of the first substrate unit layer;
[0216] A second substrate unit layer is fabricated on the surface of the second insulating dielectric layer that is opposite to the first substrate unit layer; the first substrate unit layer and the second substrate unit layer serve as the substrate.
[0217] Accordingly, thinning the substrate on the second surface of the substrate includes:
[0218] The first substrate unit layer is removed from the second surface of the first substrate unit layer until the second insulating dielectric layer is removed.
[0219] The material of the second insulating dielectric layer includes, but is not limited to, any one of silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.
[0220] When the contact hole in the second conductive structure connects the source epitaxial structure and the drain epitaxial structure, if the contact hole is misaligned, the second insulating dielectric layer can play a protective role, avoiding short circuits between the contact hole and the channel region. At the same time, it can also reduce the alignment accuracy between the contact hole and the source epitaxial structure and the drain epitaxial structure, reducing the alignment difficulty.
[0221] The fabrication method of the MOS device in this application will be described below with reference to a specific embodiment.
[0222] Example 1
[0223] Step 1, please refer to Figure 9 On the substrate 19 to be removed, shallowly doped silicon epitaxial layers 20 with different doping concentrations are epitaxially formed, and SiGe layer 21 is formed, which is then epitaxially formed as the silicon layer of substrate 1 for forming surface devices. On the first surface of substrate 1, a shallow trench isolation (STI) structure is first formed, followed by the formation of gate dielectric layer 7, gate 2, source epitaxial structure 5, drain epitaxial structure 6, contact hole 9, metal layer 10, and first back-end interconnect layer. Finally, a bonding dielectric layer 22 is deposited on one side of the first surface of substrate 1, and polished and planarized by CMP to facilitate subsequent bonding processes.
[0224] Step 2, please refer to Figure 10The edges of the substrate 1 are removed by grinding using the TRIM process, and then one side of the first surface of the silicon wafer is bonded to a carrier 23 by the bonding dielectric layer 22.
[0225] Step 3, please refer to Figure 11 The substrate 19 to be removed is removed by grinding until the lightly doped silicon epitaxial layer 20 is reached, and then the surface is ground and smoothed by CMP.
[0226] Step 4, please refer to Figure 12 The shallowly doped silicon epitaxial layer 20 is removed by wet or CMP process and stopped on the SiGe layer 21.
[0227] Step 5, please refer to Figure 13 The SiGe layer 21 is removed by wet or CMP process;
[0228] Step 6, please refer to Figure 14 The substrate 1 is removed by a wet process (alkaline solution) to expose the source epitaxial structure 5 and the drain epitaxial structure 6.
[0229] Step 7, please refer to Figure 15 The third dielectric layer 14 was deposited and planarized using CMP.
[0230] Step 8, please refer to Figure 16 In the third dielectric layer 14, a via is formed by photolithography etching to connect the source epitaxial structure 5 and the drain epitaxial structure 6. Then, metal is deposited and CMP is performed to metallize the via and form a contact hole 9. A fourth dielectric layer 15 is deposited on the third dielectric layer 14, and a metal layer 10 connecting the contact hole 9 is formed by photolithography etching in the fourth dielectric layer 15.
[0231] Step 9, please refer to Figure 17 and Figure 6 A second back-end interconnect layer 3 and a pad structure are fabricated on the fourth dielectric layer 15. Then, the bonding dielectric layer 22 and the carrier 23 are removed to obtain a planar MOS device.
[0232] Example 2
[0233] Step 1, please refer to Figure 18On the substrate 19 to be removed, shallowly doped silicon epitaxial layers 20 with different doping concentrations are epitaxially formed, and then a first substrate unit layer 27, a control layer 8, and a second substrate unit layer 28 are epitaxially formed in sequence to form surface devices; on the first surface of the second substrate unit layer 28, a shallow trench isolation (STI) structure is first formed, and then a gate dielectric layer 7 and a gate 2 are formed; a source region trench 24 and a drain region trench 25 are etched in the first MOS transistor region, and the bottom of the source region trench 24 and the drain region trench 25 are located in the first substrate unit layer 27;
[0234] Step 2, please refer to Figure 19 In the source region groove 24 and the drain region groove 25, a portion of the control layer 8 is etched away laterally using wet etching or dry etching to form a lateral groove 26.
[0235] Step 3, please refer to Figure 20 Deposit insulating dielectric material to fill the transverse groove 26 to form the first insulating dielectric layer 13;
[0236] Step 4, please refer to Figure 21 Isotropic etching is used to remove the bottom and sidewalls of the planes of the source region groove 24 and the drain region groove 25, as well as the first insulating dielectric layer 13 located on the gate dielectric layer 7.
[0237] Step 5, please refer to Figure 22 Epitaxial material is grown in the source region groove 24 and the drain region groove 25 of the first MOS transistor region to form source epitaxial structure 5 and drain epitaxial structure 6.
[0238] Step 6, please refer to Figure 23 In the second MOS transistor region, source region groove 24 and drain region groove 25 are etched and the process of steps 2 to 4 is repeated. Then, a barrier layer 17 is formed in the source region groove 24 and drain region groove 25. Then, step 5 is repeated to form source epitaxial structure 5 and drain epitaxial structure 6.
[0239] Step 7, please refer to Figure 24 A first dielectric layer 11 is deposited on one side of the first surface of substrate 1 and a contact hole 9 is formed. A second dielectric layer 12 is deposited and a metal layer 10 is formed. Then a first back-end interconnect layer is formed. Finally, a bonding dielectric layer 22 is deposited on one side of the first surface of substrate 1 and polished and planarized by CMP to facilitate subsequent bonding processes.
[0240] Step 8, please refer to Figure 25 The edges of the substrate 1 are removed by grinding using the TRIM process, and then one side of the first surface of the silicon wafer is bonded to a carrier 23 by the bonding dielectric layer 22.
[0241] Step 9, please refer to Figure 26 The substrate 19 to be removed is removed by grinding until the lightly doped silicon epitaxial layer 20 is reached, and then the surface is ground and smoothed by CMP.
[0242] Step 10, please refer to Figure 27 The shallowly doped silicon epitaxial layer 20 is removed by wet or CMP process;
[0243] Step 11, please refer to Figure 28 The first substrate unit layer 27 is thinned using a wet process or CMP process and then placed on the STI.
[0244] Step 12, please refer to Figure 29 The second substrate unit layer 28 is bonded using a wet process (alkaline solution).
[0245] Removed to expose the source epitaxial structure 5 and the drain epitaxial structure 6, and stopped on the control layer 8 and the first insulating dielectric layer 13;
[0246] Step 13, please refer to Figure 30 The third dielectric layer 14 was deposited and planarized using CMP.
[0247] Step 14, please refer to Figure 31 In the third dielectric layer 14, a via is formed by photolithography etching to connect the source epitaxial structure 5 and the drain epitaxial structure 6. Then, metal is deposited and CMP is performed to metallize the via and form a contact hole 9. A fourth dielectric layer 15 is deposited on the third dielectric layer 14, and a metal layer 10 connecting the contact hole 9 is formed by photolithography etching in the fourth dielectric layer 15.
[0248] Step 15, please refer to Figure 32 and Figure 7 A second back-end interconnect layer 3 and a pad structure are fabricated on the fourth dielectric layer 15, and then the bonding dielectric layer 22 and the carrier 23 are removed to obtain a planar MOS device.
[0249] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0250] The MOS device and its manufacturing method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the solution and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.
Claims
1. A MOS device, characterized in that, include: Substrate; The source and drain regions are located in the substrate; The gate is located on one side of the first surface of the substrate; The first back-end interconnect layer is located on one side of the first surface of the substrate and is electrically connected to the gate, the source region and the drain region through a first conductive structure; The second back-end interconnect layer is located on one side of the second surface of the substrate and is electrically connected to the source region and the drain region through a second conductive structure.
2. The MOS device as described in claim 1, characterized in that, Also includes: A control layer and a first insulating dielectric layer are located on the second surface of the substrate; In the direction perpendicular to the substrate, the control layer at least located on one side of the source epitaxial structure in the source region has a lateral groove, and / or, the control layer at least located on one side of the drain epitaxial structure in the drain region has a lateral groove. The first insulating dielectric layer is located in the transverse groove.
3. The MOS device as described in claim 1, characterized in that, Also includes: A second insulating dielectric layer located on the second surface of the substrate; In the source region, the end face of the source epitaxial structure near the second surface of the substrate is flush with or protrudes from the surface of the second insulating dielectric layer away from the substrate; and / or, in the drain region, the end face of the drain epitaxial structure near the second surface of the substrate is flush with or protrudes from the surface of the second insulating dielectric layer away from the substrate.
4. The MOS device as described in claim 1, characterized in that, Also includes: Shallow isolation trench structure; The substrate includes a first MOS transistor region and a second MOS transistor region, and the shallow isolation trench structure is located between the first MOS transistor region and the second MOS transistor region.
5. The MOS device as described in claim 4, characterized in that, Also includes: A barrier layer is located on the outer surface of the source epitaxial structure and the drain epitaxial structure in the second MOS transistor region; The source epitaxial structure and the drain epitaxial structure are embedded in the substrate, with the source epitaxial structure located in the source region and the drain epitaxial structure located in the drain region.
6. The MOS device according to any one of claims 1 to 5, characterized in that, Also includes: A silicide layer is located between the source epitaxial structure and the contact hole, and / or between the drain epitaxial structure and the contact hole; The first conductive structure includes the contact hole, the source epitaxial structure and the drain epitaxial structure are embedded in the substrate, the source epitaxial structure is located in the source region, and the drain epitaxial structure is located in the drain region.
7. A method for manufacturing a MOS device, characterized in that, include: A device prefabrication structure is obtained; the device prefabrication structure includes a substrate, a source region, a drain region, a gate, and a first back-channel interconnect layer, wherein the source region and the drain region are located in the substrate, the gate is located on the side of the first surface of the substrate, and the first back-channel interconnect layer is electrically connected to the gate, the source region, and the drain region through a first conductive structure; A dielectric layer is fabricated on the first back-end interconnect layer; The device prefabrication structure is bonded to the carrier through the dielectric layer; Thin the substrate at its second surface; A second conductive structure electrically connected to the source region and the drain region is fabricated on one side of the second surface of the substrate; A second back-end interconnect layer electrically connected to the second conductive structure is fabricated on the second conductive structure.
8. The method for manufacturing a MOS device as described in claim 7, characterized in that, Obtaining the device prefabrication structure includes: A gate dielectric layer is deposited on the first surface of the substrate; A gate electrode is fabricated on the gate dielectric layer; The substrate is etched to form source region trenches and drain region trenches; The source region and the drain region are fabricated in the source region groove and the drain region groove; A first conductive structure electrically connected to the source region, the drain region, and the gate is formed on one side of the first surface of the substrate; A first back-end interconnect layer electrically connected to the first conductive structure is formed on the upper surface of the first conductive structure.
9. The method for manufacturing a MOS device as described in claim 8, characterized in that, Before obtaining the device prefabrication structure, the following steps are also included: A control layer is fabricated on the first surface of the first substrate unit layer; A second substrate unit layer is fabricated on the surface of the control layer opposite to the first substrate unit layer; the first substrate unit layer and the second substrate unit layer serve as the substrate. After etching the substrate to form source and drain region trenches, the process further includes: The control layer is etched within the source region groove and the drain region groove to form a lateral groove in the control layer; wherein, in the direction perpendicular to the substrate, the lateral groove is located at least on one side of the source region groove, and / or, the lateral groove is located at least on one side of the drain region groove; A first insulating dielectric layer is filled into the transverse groove.
10. The method for manufacturing a MOS device as described in claim 8, characterized in that, Before obtaining the device prefabrication structure, the following steps are also included: A second insulating dielectric layer is fabricated on the first surface of the first substrate unit layer; A second substrate unit layer is fabricated on the surface of the second insulating dielectric layer that is opposite to the first substrate unit layer; the first substrate unit layer and the second substrate unit layer serve as the substrate. Accordingly, thinning the substrate on the second surface of the substrate includes: The first substrate unit layer is removed from the second surface of the first substrate unit layer until the second insulating dielectric layer is removed.