Isolation pattern module, manufacturing method thereof and construction method of isolation pattern
By employing electronic design automation systems and standard component splicing and combining methods in very large integrated circuits to form isolated pattern modules, the problem of standardization that is difficult to solve in traditional manual methods is solved, thereby improving process accuracy and design flexibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2026-03-13
AI Technical Summary
Traditional manual methods for forming isolation patterns are difficult to standardize in very large integrated circuits, affecting the process accuracy and margin of well isolation elements.
Using electronic design automation software, standard components are used as pattern units and spliced together by an EDA system to form an isolation pattern module, including first and second sub-isolation patterns, which define and overlap closed regions in a semiconductor substrate to form an isolation structure.
It improves the precision and margin of integrated circuit manufacturing processes, reduces manual operations, and increases the flexibility and variability of designs.
Smart Images
Figure CN121665686A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a system and method for functional design, synthesis verification, and physical design (including placement, routing, layout, design rule checking, etc.) of Very Large-Scale Integration (VLSI), and particularly to a method, isolation pattern, and isolation pattern module for implementing well region isolation in a semiconductor substrate during semiconductor manufacturing. Background Technology
[0002] In recent years, with the increasing miniaturization of the critical-dimensional (CD) dimensions of semiconductor circuit elements in very large integrated circuits, photolithography has become one of the most crucial steps in semiconductor manufacturing. Among these steps, the accuracy of the photomask pattern plays a particularly important role.
[0003] Taking semiconductor fabrication processes that form well-isolated devices in semiconductor substrates as an example, the traditional approach is to manually outline the desired isolation area to form an isolation pattern, which is then combined with a deep-doped well in the underlying semiconductor substrate to surround the area to achieve the intended isolation effect. However, as the patterns of very large-scale integrated circuits become increasingly complex, forming isolation patterns manually using traditional methods is not only difficult to standardize, but may also affect the process accuracy and margin (process window) of the well-isolated devices.
[0004] Therefore, there is a need to provide an advanced isolation pattern module and its manufacturing method, as well as an isolation pattern construction method, to solve the problems faced by known technologies. Summary of the Invention
[0005] One embodiment of this specification discloses an isolation pattern module, including a first isolation pattern and a second isolation pattern. The first isolation pattern includes a plurality of pattern units, each pattern unit having a pitch boundary to define a closed region. A second photomask pattern corresponds to the pitch boundary of each pattern unit and overlaps with the closed region.
[0006] Another embodiment of this specification discloses a method for manufacturing an isolation pattern module, comprising the following steps: First, constructing multiple pattern units, each pattern unit having a line width boundary. Next, splicing these pattern units to form a first sub-isolation pattern, defining a closed region by the line width boundary of each pattern unit; and constructing a second sub-isolation pattern based on this closed region, overlapping the closed region.
[0007] Another embodiment of this specification discloses a method for constructing an isolation pattern, comprising the following steps: First, creating multiple pattern units. Next, adding the multiple pattern units to an electronic design automation system using multiple instructions. Then, combining these pattern units to construct a first sub-isolation pattern and defining a closed region. A second sub-isolation pattern is then constructed based on the closed region, overlapping the closed region.
[0008] Based on the above embodiments, this specification provides an isolation pattern module, its manufacturing method, and a method for constructing the isolation pattern. It employs Electronic Design Automation (EDA) software to construct at least one pattern cell based on the process linewidth (pitch), each pattern cell containing a linewidth boundary. Multiple pattern cells are then assembled to form a first sub-isolation pattern, wherein the linewidth boundaries of adjacent pattern cells are connected to define a closed region. A second sub-isolation pattern is then formed based on this closed region, overlapping with the closed region, thereby constituting an isolation pattern module.
[0009] By employing at least one pre-designed standard cell as the patterning unit, and combining it with an Electronic Design Automation (EDA) system, multiple standard cells can be more efficiently constructed into at least one sub-isolation pattern. These sub-isolation patterns can then be combined into an isolation pattern module to form isolation elements in a semiconductor substrate. This approach offers advantages such as reduced manual intervention, increased design flexibility and variability, and improved precision and margin in integrated circuit manufacturing processes.
[0010] In one embodiment of this specification, the isolation pattern module includes a first sub-isolation pattern and a second sub-isolation pattern. A first well region corresponding to the first sub-isolation pattern can be formed in the semiconductor substrate, defining a closed circuit region. A second well region corresponding to the second sub-isolation pattern is formed below the first well region, so that the second well region overlaps with the closed circuit region, thereby forming an isolation structure. Attached Figure Description
[0011] To provide a better understanding of the above and other aspects of this specification, specific embodiments are described below in conjunction with the accompanying drawings:
[0012] Figure 1A This is a schematic diagram illustrating the steps of a method for manufacturing an isolation pattern module according to an embodiment of this specification;
[0013] Figure 1BAccording to one embodiment of this specification, a method of using Figure 1A A schematic diagram illustrating the method steps for forming an isolation structure in a semiconductor substrate using the isolation pattern module;
[0014] Figure 2 It is a drawing of the structure Figure 1A The flowchart of the method for creating sub-isolation patterns in the isolation pattern module;
[0015] Figure 3 This is a schematic diagram illustrating another isolation pattern module according to another embodiment of this specification;
[0016] Figure 4 This is a schematic diagram illustrating yet another isolation pattern module according to yet another embodiment of this specification; and
[0017] Figure 5 This is a schematic diagram illustrating another isolation pattern module according to yet another embodiment of this specification.
[0018] [Symbol Explanation]
[0019] 10: Integrated Circuits
[0020] 100: Isolation Pattern Module
[0021] 101: First Sub-Isolation Pattern
[0022] 101a: Pattern unit
[0023] 101p: Line width boundary
[0024] 102: Second Sub-Isolation Pattern
[0025] 103: Enclosed Area
[0026] 110: Semiconductor substrate
[0027] 111A: Circuit Area
[0028] 120: Isolation Structure
[0029] 121: First Trap Zone
[0030] 122: Second Well Region
[0031] 300: Isolation Pattern Module
[0032] 301: First Sub-Isolation Pattern
[0033] 302: Second Sub-Isolation Pattern
[0034] 303: Closed Area
[0035] 400: Isolation Pattern Module
[0036] 401a, 401b, 401c, 401d, 401e, 401f, 401g, 401h: Patterning Units
[0037] 401ap, 401bp, 401cp, 401dp, 401ep, 401fp, 401gp, 401hp: Linewidth boundaries; 403: Closed region
[0038] 501: Third Isolation Pattern
[0039] 501a, 501b, 501c, 501d, 501e, 501f, 501g, 501h: Patterned Units
[0040] C1: Tangent
[0041] C2: Tangent
[0042] S21: Create multiple pattern units 101a.
[0043] S22: Use multiple instructions to add multiple pattern units 101a to the electronic design automation system.
[0044] S23: The line width boundaries 101p of these pattern units 101a are spliced and combined to construct the first sub-isolation pattern 101 in a rectangular closed loop.
[0045] S24: Based on the defined splicing boundary of the first sub-isolation pattern 101, construct a rectangular second sub-isolation pattern 102, so that the second sub-isolation pattern 102 overlaps with the closed region 103. Detailed Implementation
[0046] Please refer to Figure 1A , Figure 1A This specification illustrates a method for fabricating an isolation pattern module 100 according to one embodiment. The isolation pattern module 100 includes a first sub-isolation pattern 101 and a second sub-isolation pattern 102. Each first sub-isolation pattern 101 includes multiple different pattern units 101a, each pattern unit 101a having a linewidth boundary 101p. By combining and splicing the linewidth boundaries 101p of the multiple different pattern units 101a, a rectangular closed region 103 can be defined. The second sub-isolation pattern 102 corresponds to the linewidth boundary 101p of each different pattern unit 101a and overlaps with the closed region 103. In one embodiment of this specification, the linewidth boundary 101p may be the boundary of the metal line process spacing of the semiconductor element in the integrated circuit 10.
[0047] Please refer to Figure 2 , Figure 2This specification illustrates a flowchart of a method for constructing a sub-isolation pattern of an isolation pattern module 100, according to an embodiment of the present specification. The method for constructing the isolation pattern (including a first sub-isolation pattern 101 and a second sub-isolation pattern 102) of the isolation pattern module 100 includes the following steps:
[0048] First (refer to step S21), multiple different pattern units 101a are created. In this embodiment, the different pattern units 101a may be multiple pattern units 101a of the same size but different in arrangement position, direction, angle or method.
[0049] Next (referring to step S22), multiple different pattern units 101a are imported into the Electronic Design Automation (EDA) system using multiple instructions. Then (referring to step S23), the linewidth boundaries 101p of these different pattern units 101a are spliced together to construct a first sub-isolation pattern 101 in a closed loop (e.g., a rectangular closed loop), thereby defining a closed region 103. Then, referring to step S24, a second sub-isolation pattern 102 (e.g., rectangular in shape) is constructed based on the splicing boundaries defining the first sub-isolation pattern 101, such that the second sub-isolation pattern 102 overlaps with the closed region 103.
[0050] Please refer to the following: Figure 1B The sub-isolation patterns (including the first sub-isolation pattern 101 and the second sub-isolation pattern 102) of the isolation pattern module 100 are transferred to a photoresist layer (not shown) located above the semiconductor substrate 110. Using the patterned photoresist layer (not shown) as a mask, a first well region 121 corresponding to the first sub-isolation pattern 101 and a second well region 122 corresponding to the second sub-isolation pattern 102 are formed in the semiconductor substrate 110 by an ion implantation process. The first well region 121 defines a closed circuit region 111A in the semiconductor substrate 110; and the second well region 122 overlaps with the closed circuit region 111A to form an isolation structure 120.
[0051] For example, please refer to Figure 1B (1) Diagram and Figure 1B (2) In this embodiment, the second well region 122 is a deep N-well region located below the first well region 121 and having n-type electrical properties. The second well region 122 overlaps with the circuit region 111A and is connected to the first well region 121, forming a circuit region 111A surrounded by an isolation structure. (e.g.) Figure 1B(As illustrated). It is worth noting that in the embodiments of this specification, the order of the ion implantation processes used to form the first well region 121 and the second well region 122 is not limited, and those skilled in the art can arrange them arbitrarily according to process requirements.
[0052] Subsequently, through a series of downstream processes, such as forming multiple semiconductor elements (not shown) and metal line processes above circuit area 111A, and forming interconnect structures (not shown) above circuit area 111A, the fabrication of integrated circuit 10 is finally completed.
[0053] However, the shape of the photomask pattern (e.g., the first photomask pattern 101 and the second photomask pattern 102) of the photomask module 100 is not limited to rectangles. For example, please refer to... Figure 3 , Figure 3 This is a schematic diagram illustrating another isolation pattern module 300 according to another embodiment of this specification. The first sub-isolation pattern 301 of the isolation pattern module 300 can be a polygonal (e.g., cross-shaped) closed loop pattern composed of multiple pattern units 101a arranged in different ways. In this embodiment, the line width boundaries of multiple pattern units 101a arranged in different ways are spliced together to construct the closed cross-shaped first sub-isolation pattern 301, thereby defining the closed region 303. Then, based on the splicing boundaries defining the first sub-isolation pattern 301, a cross-shaped second sub-isolation pattern 302 is constructed, and the second sub-isolation pattern 302 overlaps with the closed region 303.
[0054] In other embodiments, the isolation pattern module 400 may include multiple pattern units of different sizes and shapes, such as eight patterned units 401a, 401b, 401c, 401d, 401e, 401f, 401g, and 401h. Please refer to... Figure 4 , Figure 4 This is a schematic diagram illustrating yet another isolation pattern module 400 according to another embodiment of this specification. Each patterning unit 401a, 401b, 401c, 401d, 401e, 401f, 401g, and 401h has the same linewidth boundaries 401ap, 401bp, 401cp, 401dp, 401ep, 401fp, 401gp, and 401hp. Designers can construct photomask patterns by selecting different types and / or numbers of patterning units 401a, 401b, 401c, 401d, 401e, 401f, 401g, and 401h.
[0055] For example, in this embodiment, patterned units 401a, 401b, 401c, and 401d can be respectively arranged at the top, bottom, left, and right corners of a plane. Multiple patterned units 401e are arranged between patterned units 401a and 401b; multiple patterned units 401f are arranged between patterned units 401c and 401d; multiple patterned units 401g are arranged between patterned units 401a and 401c; and multiple patterned units 401h are arranged between patterned units 401b and 401d. By splicing together the linewidth boundaries 401ap, 401bp, 401cp, 301dp, 401ep, 401fp, 401gp, and 401hp of two adjacent patterned units (e.g., two adjacent patterned units 401a, 401b, 401c, 401d, 401e, 401f, 401gp, and 401hp), a closed rectangular ring-shaped first sub-isolation pattern 401 is constructed. This defines a closed region 403. Then, based on the splicing boundaries defining the first sub-isolation pattern 401, a rectangular second sub-isolation pattern 402 is constructed, overlapping the closed region 403.
[0056] Please refer to Figure 5 , Figure 5 This is a schematic diagram illustrating another isolation pattern module 500 according to yet another embodiment of this specification. The structure of the isolation pattern module 500 is similar to that of the isolation pattern module 400, except that the isolation pattern module 500 additionally (optionally) includes eight additional patterning units 501a, 501b, 501c, 501d, 501e, 501f, 501g, and 501h, corresponding to one of the patterning units 401a, 401b, 401c, 401d, 401e, 401f, 401g, and 401h, respectively. Furthermore, each patterned unit 501a, 501b, 501c, 501d, 501e, 501f, 501g, or 501h is connected to the outer side of its corresponding 401a, 401b, 401c, 401d, 401e, 401f, 401g, or 401h, away from the closed region 403. Consequently, a third sub-isolation pattern 501 is formed outside the first sub-isolation pattern 401.
[0057] According to the above embodiments, this specification provides an isolation pattern module, its manufacturing method, and a method for constructing the isolation pattern. It employs electronic design automation software to construct at least one pattern unit based on the process linewidth, each pattern unit containing a linewidth boundary. Multiple pattern units are then assembled to form a first sub-isolation pattern, wherein the linewidth edges of adjacent pattern units are connected to define a closed region. Based on this closed region, a second sub-isolation pattern is formed that overlaps with the closed region, thereby constituting an isolation pattern module.
[0058] By employing at least one pre-designed standard cell as the patterning unit, and combining it with an electronic design automation (EDA) system, multiple standard components can be constructed into at least one sub-isolation pattern more efficiently. These sub-isolation patterns can then be combined into an isolation pattern module to form an isolation structure (isolation element) in a semiconductor substrate. This approach offers advantages such as reduced manual operations, increased design flexibility and variability, and improved precision and margin in integrated circuit manufacturing processes.
[0059] In one embodiment of this specification, the isolation pattern module described above includes a first sub-isolation pattern and a second sub-isolation pattern. A first well region corresponding to the first sub-isolation pattern can be formed in the semiconductor substrate, and a closed circuit region can be defined. A second well region corresponding to the second photomask pattern is formed below the first well region, so that the second well region overlaps with the closed circuit region, thereby forming an isolation structure.
[0060] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.
Claims
1. An isolation pattern module, comprising: The first sub-isolation pattern comprises multiple pattern units, each of which has a pitch boundary to define a closed region; as well as The second sub-isolation pattern corresponds to the linewidth boundary of each of the multiple pattern units and overlaps with the closed area.
2. The isolation pattern module as claimed in claim 1, wherein the linewidth boundary is constructed by the process linewidth (pitch) of the semiconductor element.
3. The isolation pattern module as claimed in claim 2, wherein the semiconductor element comprises: Isolation structures include: A first well region is formed in a semiconductor substrate and corresponds to the first sub-isolation pattern, and a circuit region is defined in the semiconductor substrate corresponding to the closed region; A second well region is formed in the semiconductor substrate, located below the first well region, corresponding to the second sub-isolation pattern, and overlapping the circuit region; and The integrated circuit is located within this circuit region.
4. The isolation pattern module of claim 1, wherein the integrated circuit comprises digital circuitry, analog circuitry, or a combination thereof.
5. The isolation pattern module of claim 1, wherein each of the plurality of pattern units comprises: The first sub-pattern unit is adjacent to the enclosed area; as well as The second sub-pattern unit is connected to and located on the side of the first sub-pattern unit away from the closed area.
6. The isolation pattern module as claimed in claim 1, wherein the closed region comprises a polygon.
7. The isolation pattern module as claimed in claim 6, wherein the plurality of pattern units include at least one first shape pattern unit and at least one second shape pattern unit, and the polygon is formed by the at least one first shape pattern unit and the at least one second shape pattern unit.
8. A method for manufacturing an isolation pattern module, comprising: Construct multiple pattern units to have line width boundaries; The multiple pattern units are spliced together to form a first sub-isolation pattern, and a closed area is defined by the line width boundary of each of the multiple pattern units; as well as A second sub-isolation pattern is constructed based on the closed area, overlapping with the closed area.
9. The method for manufacturing an isolation pattern module as claimed in claim 8, wherein the step of constructing the first sub-isolation pattern and the second sub-isolation pattern includes using Electronic Design Automation (EDA) software.
10. A method for constructing an isolation pattern, comprising: Create multiple pattern units; Use multiple instructions to add these multiple pattern units to the electronic design automation system; The multiple pattern units are combined to construct the first sub-isolation pattern and define the closed region; as well as A second sub-isolation pattern is constructed based on the closed area, overlapping with the closed area.