Image sensor forming method and image sensor

Abstract

The invention provides an image sensor forming method, which comprises the following steps of: forming at least two vertical transfer transistors corresponding to each pixel unit of an image sensor, and etching a semiconductor substrate on the outer sides of the two vertical transfer transistors of the same pixel unit of the image sensor, and a semiconductor substrate outside the floating diffusion region adjacent to the vertical transfer transistor to reduce the capacitance of the floating diffusion region and the capacitance of the vertical transfer transistor. According to the scheme, the total capacitance of the floating diffusion region of the image sensor is reduced, the conversion gain is larger, and then a better signal-to-noise ratio is obtained; and two vertical transfer transistors are arranged at the edge of the pixel unit, and an isolation structure is designed, so that the problems of pixel white points, charge crosstalk between pixels and the like are reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an image sensor forming method and an image sensor. Background Technology

[0002] With the rapid development of image sensors, their applications are becoming increasingly widespread, and the performance requirements for image sensors are constantly rising, especially in terms of pixel density, image quality, response speed, and power consumption control. Currently, while the size of sensor pixels is getting smaller, the capacitance of the floating diffusion region is getting higher, resulting in a lower conversion gain (CG) and a deterioration in the signal-to-noise ratio of the image sensor.

[0003] Compared to traditional planar transistors, FinFETs, due to their three-dimensional structure, occupy a smaller area and offer better channel control. This can effectively improve the performance of image sensor transistors, enhancing signal amplification efficiency and signal-to-noise ratio, enabling image sensors to provide clear, high-quality images even in low-light environments. However, in current three-dimensional transistor structures, the gate and the gate oxide capacitance on the side furthest from the channel are parasitic capacitances. To further optimize the signal-to-noise ratio, an effective method is needed to reduce this capacitance and further improve conversion gain.

[0004] On the other hand, the shrinking size of image sensors makes it more difficult to design the isolation structure between the photodiode region and the surrounding functional transistor region. When using ion implantation for electrical isolation, the exposure size is getting smaller and smaller, which brings greater challenges to the photolithography process. Summary of the Invention

[0005] The purpose of this invention is to provide an image sensor forming method, comprising: At least two vertical transfer transistors are formed for each pixel unit of the image sensor. The semiconductor substrate outside the two vertical transfer transistors of the same pixel unit of the image sensor, as well as the semiconductor substrate outside the floating diffusion region adjacent to the vertical transfer transistors, are etched to reduce the capacitance of the floating diffusion region and the capacitance of the vertical transfer transistors.

[0006] Furthermore, at least one of the at least two vertical transfer transistors is an elongated strip with an aspect ratio of not less than 1.2, in order to improve the control capability of the vertical transfer transistor.

[0007] Furthermore, the two elongated vertical transfer transistors are arranged along the longer edges of the two adjacent edges of the pixel unit to reduce charge crosstalk and dark current of the photodiode.

[0008] Furthermore, it also includes: A doped region of the same doping type as the floating diffusion region is provided between the at least two vertical transfer transistors of a pixel unit and near the floating diffusion region to connect the floating diffusion region to the photodiode of the pixel unit.

[0009] Furthermore, before forming the isolation structure of the pixel region, the process includes: According to the preset photolithography pattern, the semiconductor substrate is etched to form a first trench and a second trench, which are used to form the gates of the vertical transfer transistor and the fin functional transistor, respectively. The semiconductor substrate between the second trenches is used to form the channel region of the fin functional transistor.

[0010] Furthermore, the finned functional transistor includes at least a source follower transistor.

[0011] Furthermore, after forming the first trench and the second trench, and before forming the isolation structure of the pixel region, the method further includes: A gate oxide layer is formed on the surface of the first trench and the second trench; Deposit polycrystalline semiconductors to form polycrystalline layers; The polycrystalline layer is etched to form the gates of the vertical transfer transistor and the finned transistor.

[0012] Furthermore, it also includes: When forming an isolation structure for a pixel region between the vertical transfer transistors of adjacent pixel units, an isolation structure for other devices in the pixel unit region is also formed simultaneously.

[0013] Furthermore, it also includes: The gate portion of the two vertical transfer transistors near the floating diffusion region is over-etched to more than 100 angstroms below the surface of the active region to reduce the electric field strength between the vertical transfer transistors and the floating diffusion region.

[0014] Furthermore, it also includes: The gate length of the fin-type functional transistor is less than the length of the second trench. The polycrystalline layer in the second trench, which is close to the source and drain regions of the fin-type functional transistor and extends beyond the gate of the fin-type functional transistor by a preset length, is over-etched to a depth of more than 100 angstroms below the surface of the active region to reduce the noise of the fin-type functional transistor.

[0015] Furthermore, when etching the vertical transfer transistor substrate outside the transmission regions of the two vertical transfer transistors of the same pixel unit of the image sensor, and the semiconductor substrate adjacent to the vertical transfer transistor and near the outside of the floating diffusion region, the method further includes: Simultaneously, the substrate on the side of the finned transistor gate away from the channel, and / or part of the polycrystalline layer, are etched to reduce the parasitic capacitance of the finned transistor gate.

[0016] Furthermore, the isolation structure forming the pixel region includes: A first dielectric layer is formed on the surface of the image sensor; According to the preset photolithography pattern, photoresist is applied to the surface of the image sensor. The photoresist on the isolation area is removed by exposure and development, and the third trench is etched. The oxidized and exposed polycrystalline layer forms a second dielectric layer to weaken the sharp corners in the third trench and reduce the overflow of dopants in the polycrystalline layer in subsequent processes; A medium is deposited on the surface of the third trench to form a first sidewall layer, and ion implantation is performed on the fin functional transistor; The deposition medium material forms a second sidewall layer, creating an isolation structure for the pixel region.

[0017] Furthermore, the dielectric material used in forming the second sidewall layer includes one or more combinations of oxides, nitrides, antireflective materials, SOC materials, and SOG materials.

[0018] Furthermore, after forming the second sidewall layer, the method further includes: Anisotropic etching is performed on the second sidewall layer to form the sidewall structure surrounding the gate of the vertical transfer transistor and the fin functional transistor, while the interior of the third trench is etched back to the surface of the active region.

[0019] Furthermore, after forming the second sidewall layer, the method further includes: Ion implantation is performed on the floating diffusion region, and pinning implantation is performed on the photodiode region.

[0020] The present invention also provides an image sensor formed using the image sensor forming method described above.

[0021] This invention proposes a method for forming a high-performance image sensor through the above-described scheme. On the one hand, the total capacitance of the floating diffusion region of the image sensor is reduced, resulting in a higher conversion gain and thus a better signal-to-noise ratio. On the other hand, by placing two vertical transfer transistors at the edge of the pixel unit and designing an isolation structure, problems such as pixel white spots and inter-pixel charge crosstalk are reduced. Therefore, this invention helps to achieve higher performance while continuously improving the integration of image sensors. Attached Figure Description

[0022] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0023] Figure 1 This is a cross-sectional view of an image sensor structure in one embodiment of the present invention; Figures 2-8 This is a schematic diagram of the structure in the image sensor formation method according to an embodiment of the present invention.

[0024] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0025] The present invention provides an image sensor forming method, specifically, forming at least two vertical transfer transistors (VTGs) for each pixel unit of the image sensor, wherein the semiconductor substrate 100 outside the two vertical transfer transistors (VTGs) of the same pixel unit of the image sensor, and the semiconductor substrate 100 outside the floating diffusion region (FD) adjacent to the vertical transfer transistors (VTGs) are etched to reduce the capacitance of the floating diffusion region (FD) and the capacitance of the vertical transfer transistors (VTGs).

[0026] Preferably, to improve the control capability of the vertical transfer transistor (VTG), in one embodiment, at least one of the at least two VTGs is an elongated shape with an aspect ratio of not less than 1.2, resulting in a larger gate oxide area and improved control capability over the readout channel. Furthermore, to further reduce charge crosstalk and dark current in the photodiode, the longer side of the two elongated VTGs can be arranged along two adjacent edges of the pixel unit, such as... Figure 1 As shown.

[0027] Furthermore, in an optional embodiment, a doped region of the same doping type as the floating diffusion region (FD) may be provided between the at least two vertical transfer transistors (VTGs) of a pixel unit, near the floating diffusion region (FD), to connect the floating diffusion region (FD) to the photodiode of the pixel unit. For example, in a preferred embodiment, the floating diffusion region (FD) is made of an N-type doped semiconductor material, and the region connecting the floating diffusion region (FD) and the photodiode is also N-type doped.

[0028] Furthermore, before forming the isolation structure of the pixel region, the following steps can be performed: Step S1: According to the preset photolithography pattern, the semiconductor substrate 100 is etched to simultaneously form the first trench 110 and the second trench 120. Optionally, a hard mask layer 200 can be formed on the surface of the semiconductor substrate 100 before etching, such as... Figure 2 As shown. The first trench 110 and the second trench 120 are used to form the gates of the vertical transfer transistor (VTG) and the FinFET, respectively, wherein the semiconductor substrate 100 between the second trenches 120 is used to form the channel region of the FinFET. Preferably, the FinFET includes one or more combinations of a source follower transistor (SF), a row select transistor (SEL), a reset transistor (RST), and one or more conversion gain control transistors (DCG).

[0029] In an optional implementation, after forming the first trench 110 and the second trench 120 in step S1, and before forming the isolation structure of the pixel region, the following steps may also be performed: Step S21: Form a gate oxide layer 130 on the surface of the first trench 110 and the second trench 120, such as Figure 5 As shown; Step S22: Deposit a polycrystalline semiconductor and perform element doping implantation to form a polycrystalline layer 140, such as... Figure 6 As shown; Step S23: Etch the polycrystalline layer 140, and simultaneously form the gates of the vertical transfer transistor (VTG) and the finned transistor (FinFET), as shown below. Figure 8 As shown.

[0030] In an optional embodiment, when etching the semiconductor substrate 100 outside the transmission regions of the two vertical transfer transistors (VTGs) of the same pixel unit of the image sensor, and the semiconductor substrate 100 adjacent to the vertical transfer transistors (VTGs) and near the outside of the floating diffusion region (FD), the substrate on the side of the FinFET gate away from the channel and / or part of the polycrystalline layer 140 may be etched simultaneously to reduce the gate parasitic capacitance of the FinFET.

[0031] Further, in an optional embodiment, during the formation of the image sensor, when forming an isolation structure A1 for the pixel region between the vertical transfer transistors (VTGs) of adjacent pixel units, an isolation structure A2 is simultaneously formed between photodiodes and / or between transistors of each pixel unit and / or between transistors and the semiconductor substrate and / or between transistors and the dielectric layer, as shown. Figure 8 As shown.

[0032] In an optional implementation, after forming the gate of the vertical transfer transistor (VTG), the gate of the two vertical transfer transistors (VTG) near the floating diffusion region (FD) can be over-etched to more than 100 angstroms below the surface of the active region, thereby reducing the electric field strength between the vertical transfer transistor (VTG) and the floating diffusion region. The gates of the two vertical transfer transistors (VTG) corresponding to the same photodiode are electrically connected through a polycrystalline semiconductor above the active region.

[0033] In an optional embodiment, the gate length of the FinFET is less than the length of the second trench 120, and the polycrystalline layer 140 in the second trench 120, which is close to the source and drain regions of the FinFET and extends beyond the gate of the FinFET by a predetermined length, is over-etched to more than 100 angstroms below the surface of the active region to reduce the noise of the FinFET.

[0034] In an optional implementation, the following steps may be used when forming the isolation structure of the pixel region: Step S31: Form a first dielectric layer 300 on the surface of the image sensor, such as... Figure 6 As shown; Step S32: According to the preset photolithography pattern, photoresist is applied to the surface of the image sensor. The photoresist on the isolation area is removed by exposure and development, and the third trench 310 is etched. Figure 7 As shown; Step S33: The exposed polycrystalline layer 140 is oxidized to form a second dielectric layer 320 to weaken the sharp corners 311 within the third trench 310 and reduce the overflow of dopant elements from the polycrystalline layer 140 in subsequent processes, such as... Figure 7 As shown; Step S34: Deposit a dielectric on the surface of the third trench 310 to form a first sidewall layer 330, and perform ion implantation on the fin-type functional transistor (FinFET); Step S35: A second sidewall layer 340 is formed by depositing a medium material, thereby forming an isolation structure for the pixel region, such as... Figure 8 As shown.

[0035] Preferably, in step S35, the dielectric material used to form the second sidewall layer 340 can be one or more combinations of oxides, nitrides, antireflective materials, SOC materials, and SOG materials.

[0036] In an optional implementation, after forming the second sidewall layer 340 in step S35, the method further includes: Step S36: Perform anisotropic etching on the second sidewall layer 340 to form the sidewall structure around the gate of the vertical transfer transistor (VTG) and the fin functional transistor (FinFET), while simultaneously etching back into the interior of the third trench 310 to the surface of the active region.

[0037] Alternatively, after forming the second sidewall layer 340 in step S35, the method further includes: Step S37: Ion implantation is performed on the floating diffusion region (FD) and the photodiode region is pinned.

[0038] The present invention also provides an image sensor formed using the image sensor forming method described above.

[0039] In one specific embodiment of this solution, a pixel array comprises multiple pixel units, each pixel array containing a FinFET (Fin Field Transistor), such as a readout-related source follower (SF). Each pixel unit has two vertical transfer transistors (VTGs), placed parallel to each other at the boundary of the pixel unit to reduce dark current. The VTGs of adjacent sub-pixels within the same pixel array are separated by trench isolation structures. Similarly, trench isolation structures are formed between the functional transistor region and the photodiode region, the functional transistor region and the ground region, and the photodiode region and the ground region. Specifically, the FinFET and VTG can be formed by simultaneously etching the semiconductor substrate. After gate etching, during the process of forming the trench isolation structure by etching the silicon substrate, a portion of the polycrystalline semiconductor of the gates of the FinFET and VTG is also etched away. For source follower transistors (SF), etching away the polysilicon on the side of the FinFET trench away from the channel can reduce the transistor's parasitic capacitance, thereby improving conversion gain (CG) and optimizing signal-to-noise ratio. For vertical transfer transistors (VTG), etching away the silicon on the side of the dual vertical transfer transistor (VTG) away from the transmission region near the floating diffusion region (FD) can reduce the capacitance between the VTG and the FD, thereby improving conversion gain and optimizing signal-to-noise ratio. In addition, the VTG is elongated, with a larger gate oxide area, improving the control capability of the readout channel. The gate polysilicon portion of the dual vertical transfer transistor (VTG) near the FD is etched below the active region to reduce the electric field between the VTG and the FD. The silicon between the two VTGs between adjacent sub-pixels is etched away to reduce signal crosstalk, and the gate polysilicon on the side away from the transmission channel is partially etched to reduce the parasitic capacitance of the VTG. This solution utilizes a simple process to manufacture a high-performance image sensor.

[0040] In one specific embodiment of the present invention, an image sensor structure protected by the present invention can be formed through the following process.

[0041] Step S100: Provide a semiconductor substrate 100, for example, a silicon substrate may be used. After forming the photodiode region necessary for the image sensor, a pad oxide layer (not shown) is deposited on the semiconductor substrate 100; Step S200: Etching the semiconductor substrate 100 to form VTG trenches and FinFET trenches. Preferably, as shown in... Figure 2As shown, a hard mask layer 200 can be prepared according to a preset photolithography pattern. The hard mask at the corresponding position is opened using photolithography, and the semiconductor substrate 100 is etched. At the same time, a first trench 110 and a second trench 120 are formed. The first trench 110 is used to form a VTG, and the second trench 120 is used to form a FinFET transistor. The substrate between the two second trenches 120 is a channel region designed for FinFET devices. Step S300: The surfaces of the first trench 110 and the second trench 120 are oxidized to form an oxide layer 131, which removes the damage generated on the trench surface during the etching process and protects the trenches from damage in subsequent processes, such as... Figure 3 As shown; Step S400: Remove the hard mask layer 200, then remove the pad oxide layer and the oxide layer 131 on the trench surface, as shown. Figure 4 As shown; Step S500: Forming a gate oxide layer 130 for transistors including VTG, FinFET devices, etc. Figure 5 As shown. Preferably, gate oxide layers of different thicknesses can be formed through photolithography selection and multi-step etching and deposition processes; Step S600: Deposit a polycrystalline semiconductor material, such as polycrystalline silicon, to form a polycrystalline layer 140 as the gate material for all transistors, and oxidize the surface of the polycrystalline layer to form an oxide layer 300, followed by doping implantation, such as... Figure 6 As shown; Step S700: The doped polycrystalline layer 140 is etched using a photomask to form the gate of each transistor. Then, an etching process is performed to etch the polycrystalline layer in the trench below the surface of the active region. The gates of two VTG transistors corresponding to the same photodiode are connected through the polycrystalline layer above the active region. Figure 7 As shown; Step S800: Re-oxidize the gate of each transistor, forming an oxide layer 320 on the gate surface to encapsulate the gate, such as... Figure 7 As shown; Step S900: Using a photomask, an isolation structure trench is etched in the pixel area to form an isolation trench region A1 in the pixel area. The polysilicon portion of the transistor gate is covered by shallow trench photoresist. During the etching process to form the isolation structure trench, the polysilicon layer in the transistor that is not covered by the photoresist is also etched. At the junction of the first trench 110 or the second trench 120 and the isolation structure trench, a sharp corner 311 with a surface covered by a polysilicon layer is formed. Figure 7 As shown; Step S1000: After etching, the polycrystalline layer is oxidized a second time to weaken the sharp corners in the trench and reduce the spillover of polycrystalline semiconductor doping elements in subsequent processes. Step S1100: Perform P-type ion implantation on the surface of the trench and the surface of the photodiode using a photomask; Step S1200: Deposit and form the first sidewall oxide layer 330 and fill the isolation structure trench, then perform FinFET transistor lightly doped drain (LDD) ion implantation using a photomask. Step S1300: Deposit a dielectric material, such as silicon oxide, silicon nitride, etc., to form a second sidewall 340, such as... Figure 8 As shown in the diagram, during filling, the isolation structure trenches in the pixel area are also filled with silicon oxide and silicon nitride. Due to the sharp corner structure 311 present at the junction of the first trench 110, the second trench 120, and the isolation structure trench, the trenches can be filled quickly. After filling, the step height within the trenches is effectively controlled. For applications requiring even lower step heights, a filling material with better flowability, such as BARC or SOC / SOG materials, can be used to flatten the surface and then etch it back to further improve flatness. Step S1400: Anisotropic etching is performed on the sidewalls to form the sidewall structure around the polysilicon gate of each transistor, while the inner surface of the shallow trench is etched back to a position close to the active region. Step S1500: After the second sidewall 340 is formed, lightly doped drain ions are implanted into the floating diffusion region (FD), and P-type pinning is performed on the second surface of the photodiode region; in order to avoid ion implantation below the isolation region between the two vertical transfer transistors causing punch-through between the two adjacent photodiodes, the ion implantation in the floating diffusion region is not completed synchronously in step S1200. Step S1600: Perform source / drain redoping implantation, form silicide by photolithography in selected regions, and then form metal plugs.

[0042] The above process is one embodiment of a portion of the process used to form the image sensor in this invention.

[0043] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for forming an image sensor, characterized in that, include: At least two vertical transfer transistors are formed for each pixel unit of the image sensor. The semiconductor substrate outside the two vertical transfer transistors of the same pixel unit of the image sensor, as well as the semiconductor substrate outside the floating diffusion region adjacent to the vertical transfer transistors, are etched to reduce the capacitance of the floating diffusion region and the capacitance of the vertical transfer transistors.

2. The image sensor forming method as described in claim 1, characterized in that, At least one of the at least two vertical transfer transistors is an elongated strip with an aspect ratio of not less than 1.2, in order to improve the control capability of the vertical transfer transistor.

3. The image sensor forming method as described in claim 2, characterized in that, The two elongated vertical transfer transistors are arranged along the longer edges of the two adjacent edges of the pixel unit to reduce charge crosstalk and dark current of the photodiode.

4. The image sensor forming method as described in claim 1, characterized in that, Also includes: A doped region of the same doping type as the floating diffusion region is provided between the at least two vertical transfer transistors of a pixel unit and near the floating diffusion region to connect the floating diffusion region to the photodiode of the pixel unit.

5. The image sensor forming method as described in claim 1, characterized in that, Before forming the isolation structure of the pixel region, the following is included: According to the preset photolithography pattern, the semiconductor substrate is etched to form a first trench and a second trench, which are used to form the gates of the vertical transfer transistor and the fin functional transistor, respectively. The semiconductor substrate between the second trenches is used to form the channel region of the fin functional transistor.

6. The image sensor forming method as described in claim 5, characterized in that, The finned functional transistor includes at least a source follower transistor.

7. The image sensor forming method as described in claim 5, characterized in that, After forming the first trench and the second trench and before forming the isolation structure of the pixel region, the method further includes: A gate oxide layer is formed on the surface of the first trench and the second trench; Deposit polycrystalline semiconductors to form polycrystalline layers; The polycrystalline layer is etched to form the gates of the vertical transfer transistor and the finned transistor.

8. The image sensor forming method as described in claim 1, characterized in that, Also includes: When forming an isolation structure for a pixel region between the vertical transfer transistors of adjacent pixel units, an isolation structure for other devices in the pixel unit region is also formed simultaneously.

9. The image sensor forming method as described in claim 7, characterized in that, Also includes: The gate portion of the two vertical transfer transistors near the floating diffusion region is over-etched to more than 100 angstroms below the surface of the active region to reduce the electric field strength between the vertical transfer transistors and the floating diffusion region.

10. The image sensor forming method as described in claim 7, characterized in that, Also includes: The gate length of the fin-type functional transistor is less than the length of the second trench. The polycrystalline layer in the second trench, which is close to the source and drain regions of the fin-type functional transistor and extends beyond the gate of the fin-type functional transistor by a preset length, is over-etched to a depth of more than 100 angstroms below the surface of the active region to reduce the noise of the fin-type functional transistor.

11. The image sensor forming method as described in claim 7, characterized in that, When etching the vertical transfer transistor substrate outside the transmission regions of the two vertical transfer transistors of the same pixel unit of the image sensor, and the semiconductor substrate adjacent to the vertical transfer transistors and close to the outside of the floating diffusion region, the method further includes: Simultaneously, the substrate on the side of the finned transistor gate away from the channel, and / or part of the polycrystalline layer, are etched to reduce the parasitic capacitance of the finned transistor gate.

12. The image sensor forming method as described in claim 7, characterized in that, The isolation structure forming the pixel region includes: A first dielectric layer is formed on the surface of the image sensor; Cover the photoresist on the surface of the image sensor according to a preset lithography pattern, remove the photoresist on the isolation region through exposure and development, and etch to form a third trench; Oxidize the exposed polycrystalline layer to form a second dielectric layer to weaken the sharp corners in the third trench and reduce the overflow of doping elements in the polycrystalline layer in subsequent processes; Deposit a dielectric on the surface of the third trench to form a first sidewall layer, and perform ion implantation on the fin-type functional transistor; Deposit a dielectric material to form a second sidewall layer to form an isolation structure for the pixel region.

13. The image sensor forming method as described in claim 12, characterized in that, The dielectric material used when forming the second sidewall layer includes one or a combination of oxides, nitrides, anti-reflection materials, SOC materials, and SOG materials.

14. The image sensor forming method as described in claim 12, characterized in that, After forming the second sidewall layer, it further includes: Perform anisotropic etching on the second sidewall layer to form sidewall structures around the gates of the vertical transfer transistor and the fin-type functional transistor, and at the same time back-etch the inside of the third trench to the active region surface range.

15. The image sensor forming method as described in claim 13, characterized in that, After forming the second sidewall layer, it further includes: Perform ion implantation on the floating diffusion region and perform pinning implantation on the photodiode region.

16. An image sensor, characterized in that, It is formed by using the image sensor forming method as described in claims 1 to 15.

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