Selective contact area buried solar cell and back contact structure thereof

Abstract

The invention is suitable for the technical field of solar cells, and provides a selective contact area buried solar cell and a back contact structure thereof, the back contact structure comprises grooves arranged on the back of a silicon substrate at intervals; the first conductive regions and the second conductive regions are alternately arranged, the first conductive regions are arranged in the grooves, the second conductive regions are arranged outside the grooves, each first conductive region comprises a first dielectric layer and a first doped region which are sequentially arranged, and each second conductive region comprises a second doped region; the second dielectric layer is arranged between the first conductive region and the second conductive region, and the number of the second dielectric layer is at least one; and a conductive layer disposed on the first conductive region and the second conductive region. According to the back contact structure provided by the invention, the problems of high control requirement on the width of the groove and poor passivation effect in the prior art are solved.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, and particularly relates to a selective contact area buried solar cell and its back contact structure. Background Technology

[0002] In crystalline silicon solar cells, the efficiency loss of the cell can be divided into two aspects: electrical loss and optical loss. The important components of electrical loss are recombination loss and resistance loss caused by metal-semiconductor contact, while the important component of optical loss is the shading of the metal grid lines on the light-receiving surface.

[0003] Passivated metal contact structures exhibit significant electrical performance, simultaneously achieving low contact resistivity and low surface recombination. This structure consists of an ultrathin tunneling oxide layer and an N-type or P-type doped polycrystalline silicon layer. Since the absorption of light by the doped polycrystalline silicon layer is 'parasitic', meaning it contributes nothing to the photocurrent, passivated metal contact structures are primarily used on the back of the cell, completely eliminating the obstruction of the metal grid lines on the front surface. Solar radiation received on the solar cell generates electrons and holes, which migrate to the doped polycrystalline silicon layers, creating a voltage difference between them. Solar cells can be constructed using either the aforementioned passivated metal contact structure or a diffusion structure.

[0004] Currently, passivated metal contact structures and diffusion structures are deposited directly on the back side of a silicon wafer. However, when they are connected without any obstruction, leakage and other defects can occur. Therefore, to solve the problem caused by this lack of obstruction, a very narrow trench is created between the passivated metal contact structure and the diffusion structure to separate them, thereby preventing leakage and reducing the open-circuit voltage of the battery. However, existing trenches are fabricated using laser drilling or wet etching. In these cases, the trench width is only tens of micrometers, requiring strict width control, making fabrication difficult and often resulting in the use of only a single dielectric layer for passivation. However, passivation with a single dielectric layer has poor passivation effect and produces poor internal back reflection. Summary of the Invention

[0005] The purpose of this invention is to provide a back contact structure for solar cells, which aims to solve the problems of high requirements for trench width control and poor passivation effect in existing technologies.

[0006] The present invention is implemented as follows: a back contact structure for a solar cell includes: Grooves spaced apart on the back side of the silicon substrate; Alternating first conductive region and second conductive region, the first conductive region is disposed inside the groove and the second conductive region is disposed outside the groove, the first conductive region includes a first dielectric layer and a first doped region disposed sequentially, and the second conductive region includes a second doped region; The total thickness of the first dielectric layer and the first doped region is less than the depth of the groove, and the second doped region is a boss outside the groove, and the second doped region covers all or part of the boss. A second dielectric layer is disposed between the first conductive region and the second conductive region, wherein the second dielectric layer is at least one layer; and A conductive layer is disposed on the first conductive region and the second conductive region.

[0007] Furthermore, the first doped region is a P-type doped region, and the second doped region is an N-type doped layer; or The first doped region is an N-type doped region, and the second doped region is a P-type doped layer.

[0008] Furthermore, the width of the P-type doped region is greater than the width of the N-type doped region.

[0009] Furthermore, the first doped region includes doped polycrystalline silicon, doped silicon carbide, or doped amorphous silicon.

[0010] Furthermore, the first dielectric layer is one or more combinations of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer.

[0011] Furthermore, the second dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer. Furthermore, the second dielectric layer covers the area between the first conductive region and the second conductive region, or extends to cover the first conductive region and / or the second conductive region.

[0012] Furthermore, the back side of the silicon substrate located between the first conductive region and the second conductive region has a rough textured structure.

[0013] Furthermore, the width of the P-type doped region is 300-600 μm, or the width of the N-type doped region is 100-500 μm.

[0014] Furthermore, the depth of each groove is 0.01-10 μm, and the horizontal distance between the first conductive area and the second conductive area is greater than 0 and less than or equal to 500 μm.

[0015] Furthermore, the first dielectric layer covers the first doped region or extends to cover the region between the first doped region and the second doped region.

[0016] Furthermore, the groove is arc-shaped, trapezoidal, or square.

[0017] Furthermore, the junction depth of the second doped region is 0.01-1 μm, the sheet resistance is 10-500 ohm / sqr, and the surface concentration is 1E18-1E21 cm⁻¹. -3 .

[0018] Furthermore, the thickness of the first dielectric layer is 1-20 nm, and the total thickness of the first conductive region is greater than 20 nm.

[0019] Furthermore, the doped silicon carbide includes doped hydrogenated silicon carbide.

[0020] Furthermore, the first dielectric layer is a tunneling oxide layer and an intrinsic silicon carbide layer.

[0021] Furthermore, the tunneling oxide layer consists of one or more layers of silicon oxide or aluminum oxide.

[0022] Furthermore, the intrinsic silicon carbide layer in the first dielectric layer includes an intrinsic hydrogenated silicon carbide layer.

[0023] Furthermore, the second dielectric layer is an aluminum oxide layer and an intrinsic silicon carbide layer, or a silicon oxide layer and an intrinsic silicon carbide layer, and the thickness of the second dielectric layer is greater than 25 nm.

[0024] Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer is greater than 10 nm.

[0025] Furthermore, the intrinsic silicon carbide layer in the second dielectric layer is composed of at least one first intrinsic silicon carbide film with different refractive indices.

[0026] Furthermore, the refractive index of each layer of the first intrinsic silicon carbide film decreases sequentially from the back side of the silicon substrate outwards.

[0027] Furthermore, the outer layer of the second dielectric layer is also provided with a magnesium fluoride layer.

[0028] Furthermore, the conductive layer is a TCO transparent conductive film and / or a metal electrode.

[0029] Furthermore, the metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-coated copper electrode, or a silver-coated copper electrode.

[0030] Furthermore, the copper electrode is an electroplated copper electrode prepared by an electroplating process or a copper electrode prepared by physical vapor deposition.

[0031] Another embodiment of the present invention aims to provide a selectively contacted buried solar cell, comprising: silicon substrate; A back contact structure as described above is disposed on the back side of a silicon substrate; and A third dielectric layer disposed on the front side of a silicon substrate.

[0032] Furthermore, the third dielectric layer is one or more combinations of aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer and silicon oxide layer.

[0033] Furthermore, the third dielectric layer is a silicon oxide layer and an intrinsic silicon carbide layer, or an aluminum oxide layer and an intrinsic silicon carbide layer, and the thickness of the third dielectric layer is greater than 50 nm.

[0034] Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer is greater than 10 nm.

[0035] Furthermore, the intrinsic silicon carbide layer in the third dielectric layer is composed of at least one second intrinsic silicon carbide film with different refractive indices.

[0036] Furthermore, the refractive index of each layer of the second intrinsic silicon carbide film decreases sequentially from the front side of the silicon substrate outwards.

[0037] Furthermore, the outer layer of the third dielectric layer is also provided with a magnesium fluoride layer.

[0038] Furthermore, an electric field layer or floating junction is provided between the front side of the silicon substrate and the third dielectric layer.

[0039] Another objective of this invention is to provide a battery assembly comprising the selective contact area buried solar cells described above.

[0040] Another objective of this invention is to provide a photovoltaic system comprising the battery module as described above.

[0041] The back contact structure provided in this invention involves creating grooves on the back side of a silicon substrate at intervals, and alternately placing a first conductive region inside or outside one of the grooves and a second conductive region in the other. This allows the first and second conductive regions to be isolated through a portion of the grooves or a portion of the protrusions outside the grooves. The grooves have more lenient width control requirements than existing trenches, and are easier to fabricate. Furthermore, the grooves allow the first dielectric layer to contact both the bottom and sidewalls of the groove when the first conductive region is located within it, thus facilitating the transport of charge carriers generated on the silicon substrate. The carriers are separated and selectively collected in the corresponding first doped region through the first dielectric layer on the sidewall of the trench. This not only reduces leakage current but also enables selective transport of carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of carriers in the bottom and sidewalls of the trench. Since there is at least one second dielectric layer, the back side of the silicon substrate is passivated through at least one second dielectric layer, resulting in better passivation and improved internal back reflection. This solves the existing problems of high requirements for trench width control and poor passivation effect. Attached Figure Description

[0042] Figures 1 to 13 This is a schematic diagram of the structure of a selective contact area buried solar cell in various embodiments of the present invention; Figure 14 This is a flowchart of a selective contact area buried solar cell manufacturing method provided in another embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0044] In this invention, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0045] This invention involves creating grooves on the back side of a silicon substrate at intervals, and alternately placing a first conductive region inside or outside one of the grooves and a second conductive region in the other. This allows the first and second conductive regions to be isolated through a portion of the groove or a portion of the protrusion outside the groove. The grooves offer more lenient width control requirements than existing trenches, and are easier to fabricate. Furthermore, the grooves allow the first dielectric layer of the first conductive region to contact both the bottom and sidewalls of the groove when it is located within the groove. Therefore, charge carriers generated on the silicon substrate can easily pass through the sidewalls of the groove. The first dielectric layer on the substrate is separated and selectively collected into the corresponding first doped region, which not only reduces leakage current but also enables selective transport of charge carriers in both the longitudinal and lateral directions. This facilitates multi-dimensional collection of charge carriers in the bottom and sidewalls of the trench. Since there is at least one second dielectric layer, the back side of the silicon substrate is passivated through at least one second dielectric layer, resulting in better passivation and improved internal back reflection. This solves the existing problems of high requirements for trench width control and poor passivation effect.

[0046] Example 1 The first embodiment of the present invention provides a back contact structure for a solar cell. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown. Refer to... Figures 1-13 As shown, the back contact structure of the solar cell provided in this embodiment of the invention includes: Grooves spaced apart on the back side of the silicon substrate 10; The first conductive region 20 and the second conductive region 30 are alternately arranged, one of which is located inside the groove and the other is located outside the groove. The first conductive region 20 includes a first dielectric layer 21 and a first doped region 22 arranged in sequence, and the second conductive region 30 includes a second doped region. A second dielectric layer 40 is disposed between the first conductive region 20 and the second conductive region 30. The second dielectric layer 40 is at least one layer and its refractive index decreases sequentially from the back side of the silicon substrate 10 outwards. Conductive layers 50 are disposed on the first conductive region 20 and the second conductive region 30.

[0047] In one embodiment of the present invention, the silicon substrate 10 has a front side facing the sun during normal operation and a back side opposite to the front side, with the front side being the light-receiving surface; the back side is located on the opposite side of the silicon substrate 10 relative to the front side, that is, the aforementioned front side and back side are located on different sides of the silicon substrate 10 and are opposite sides. In this embodiment, the silicon substrate 10 is an N-type silicon wafer. It is understood that in other embodiments, the silicon substrate 10 may also be other types of silicon wafers. The back side of the silicon substrate 10 is provided with grooves spaced apart. The grooves can be formed by laser etching or by a combination of mask (such as hard mask, silicon oxide mask, silicon nitride mask, and photoresist mask) and wet / dry etching. In this case, due to the grooves spaced apart on the back side of the silicon substrate 10, the area between two adjacent grooves of the silicon substrate 10 is generally in the shape of a protrusion. Therefore, the pattern on the back side of the silicon substrate 10 generally presents a pattern formed by the alternating arrangement of grooves and protrusions.

[0048] Furthermore, in one embodiment of the present invention, such as Figure 1 As shown, it can be configured such that the first conductive region 20 is located inside the groove, while the second conductive region 30 is located outside the groove; or as shown... Figure 2 As shown, the first conductive region 20 is located outside the groove, and the second conductive region 30 is located inside the groove. Furthermore, the first doped region 22 and the second doped region have opposite conductivity types; if the first doped region 22 is a P-type doped region, then the second doped region is an N-type doped layer; or if the first doped region 22 is an N-type doped region, then the second doped region is a P-type doped layer.

[0049] Furthermore, in one embodiment of the present invention, the first dielectric layer 21 covers the first doped region 22, or extends to cover the region between the first doped region 22 and the second doped region. Wherein, when the first conductive region 20 is disposed within the groove, if the first dielectric layer 21 only covers the first doped region 22, its reference... Figure 1 As shown, at this time, its first dielectric layer 21 is connected to the bottom wall and side wall of the groove; if the first dielectric layer 21 also extends to cover the area between the first doped region 22 and the second doped region, refer to Figure 3 As shown. When the first conductive region 20 is located outside the groove, if the first dielectric layer 21 only covers the first doped region 22, its reference... Figure 2 As shown; if the first dielectric layer 21 further extends to cover the region between the first doped region 22 and the second doped region, refer to Figure 4 As shown.

[0050] The first dielectric layer 21 is located between the silicon substrate 10 and the first doped region 22, serving as a tunneling structure. The first dielectric layer 21 and the first doped region 22 connected to and covered by it together form a passivation contact structure. This passivation contact structure provides good surface passivation for the back side of the silicon substrate 10. Generally, the first dielectric layer 21 has a sufficiently thin thickness, allowing one type of charge carrier to selectively transport itself via tunneling, while another type of charge carrier is difficult to tunnel through the first dielectric layer 21 due to the potential barrier and the field effect of the doped region. Therefore, the first dielectric layer 21 allows one type of charge carrier to tunnel into the first doped region 22 while blocking the passage of the other type of charge carrier, causing recombination. This significantly reduces interface recombination, resulting in higher open-circuit voltage and short-circuit current in the solar cell, thereby increasing photoelectric conversion efficiency. Furthermore, as... Figures 1 to 13 As shown, the surface of the silicon substrate 10 in contact with the first dielectric layer 21 forms a plurality of internal diffusion regions corresponding to the first doped regions 22. It should be noted that, in a preferred embodiment of the present invention, the first conductive region 20 is preferably disposed in the groove. In this case, the first dielectric layer 21 can contact both the bottom wall and the side wall of the groove. Therefore, the charge carriers generated on the silicon substrate 10 can be easily separated by the first dielectric layer 21 on the side wall of the groove and selectively collected into the corresponding first doped regions 22, which is beneficial for the multi-dimensional collection of charge carriers in the bottom wall and side wall of the groove.

[0051] Furthermore, in one embodiment of the present invention, the first dielectric layer 21 is preferably one or a combination of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer. As some examples of the present invention, the first dielectric layer 21 may be a tunneling oxide layer of a single material, a combination of a tunneling oxide layer and an intrinsic amorphous silicon layer of multiple materials, or a combination of multiple intrinsic amorphous silicon layers of a single material with different refractive indices. It is understood that the specific structural arrangement of the first dielectric layer 21 includes, but is not limited to, the above-listed methods. The first dielectric layer 21 is configured accordingly according to actual usage needs, and no specific limitation is made here.

[0052] In a preferred embodiment of the present invention, the first dielectric layer 21 is preferably a tunneling oxide layer and an intrinsic silicon carbide layer, wherein the tunneling oxide layer and the intrinsic silicon carbide layer are arranged sequentially from the silicon substrate 10 outwards, with the tunneling oxide layer in contact with the back side of the silicon substrate 10 and the intrinsic silicon carbide layer in contact with the first doped region 22. Further, the tunneling oxide layer is preferably composed of one or more layers of silicon oxide and aluminum oxide; therefore, the first dielectric layer 21 can also be a combination of silicon oxide and aluminum oxide layers in the tunneling oxide layer. The intrinsic silicon carbide layer in the first dielectric layer 21 includes an intrinsic hydrogenated silicon carbide layer. In this case, the tunneling oxide layer and the intrinsic silicon carbide layer reduce the interface state density between the silicon substrate 10 and the first doped region 22 and the second doped region through chemical passivation. For example, hydrogen in the intrinsic hydrogenated silicon carbide layer enters the silicon substrate 10 under the action of diffusion mechanism and thermal effect, which neutralizes the dangling bonds on the back side of the silicon substrate 10, passivates the defects on the back side of the silicon substrate 10, and thus transfers the energy band in the bandgap to the valence band or conduction band, thereby increasing the probability of charge carriers entering the first doped region 22 through the first dielectric layer 21.

[0053] Generally, as specific examples of the present invention, in practical use, the first dielectric layer 21 preferably adopts a 1-2 nm silicon oxide layer and a 2-5 nm intrinsic silicon carbide layer. Compared with using only a silicon oxide layer as the tunneling structure, the intrinsic silicon carbide layer can also provide an additional hydrogen passivation effect, increasing the fabrication process window of the tunneling structure without affecting the tunneling effect. Of course, a 1-2 nm silicon oxide layer, or a 1 nm silicon oxide layer and a 1 nm aluminum oxide layer, or two or more intrinsic amorphous silicon layers with different refractive indices can also be used directly. It is understood that the specific structural arrangement of the first dielectric layer 21 includes, but is not limited to, the specific examples listed above. In addition, the first dielectric layer 21 can also be an intrinsic microcrystalline silicon layer, an intrinsic microcrystalline silicon oxide layer, an intrinsic amorphous silicon oxide layer, etc. Among them, such as Figures 1-13 As shown, it only shows the first dielectric layer 21 as a single layer. It can be understood that the specific structure of the first dielectric layer 21 is set according to actual needs and is not completely in accordance with the attached drawings of the specification.

[0054] Furthermore, in one embodiment of the present invention, the first doped region 22 preferably includes doped polycrystalline silicon, doped silicon carbide, or doped amorphous silicon; wherein, doped silicon carbide may include doped hydrogenated silicon carbide, specifically by adding hydrogen gas during silicon carbide deposition. It should be noted that when the first dielectric layer 21 is the aforementioned silicon oxide layer and intrinsic silicon carbide layer, the first doped region 22 is specifically doped silicon carbide. When the first dielectric layer 21 is the aforementioned silicon oxide layer or other combinations, the first doped region 22 may be doped polycrystalline silicon, etc. When the first dielectric layer 21 is the aforementioned intrinsic amorphous silicon layer, the first doped region 22 is specifically doped amorphous silicon.

[0055] Furthermore, in one embodiment of the present invention, the first conductive region 20, which is composed of the first dielectric layer 21 and the first doped region 22, is disposed in or outside the groove by means of deposition or the like. At this time, the thickness of the first dielectric layer 21 is 1-20 nm, and the thickness of the first conductive region 20 is greater than 20 nm, that is, the total thickness of the first dielectric layer 21 and the first doped region 22 is greater than 20 nm.

[0056] Furthermore, in one embodiment of the present invention, the second conductive region 30 includes a second doped region, which is a doped layer. It should be noted that this doped layer differs from the first conductive region 20 grown by methods such as deposition in a trench. The doped layer is a diffusion structure formed on the silicon substrate 10 by incorporating different types of diffusion sources. Therefore, the doped layer is not grown; rather, it is partially diffused onto the silicon substrate 10 to become a doped layer. The junction depth of this second doped region is 0.01-1 μm, the sheet resistance is 10-500 ohm / sqr, and the surface concentration is 1E18-1E21 cm⁻¹. -3 Meanwhile, the second doped region can be a P-type doped layer or an N-type doped layer. It can be set as a second doped region with the opposite conductivity type according to the specific conductivity type of the first doped region 22. The P-type doped layer is formed by diffusion of boron, aluminum, gallium, etc., and the N-type doped layer is formed by diffusion of nitrogen, phosphorus, arsenic, etc. In this case, the N-type doped layer is an N+ layer relative to the silicon substrate 10, which is specifically an N-type silicon wafer, that is, its doped layer is formed by local heavy doping.

[0057] Furthermore, in one embodiment of the present invention, the distance between the first conductive region 20 and the second conductive region 30 is 0-500um, that is, the first conductive region 20 and the second conductive region 30 can be adjacent or have a certain distance in the horizontal direction. In other words, the first conductive region 20 or the second conductive region 30 disposed on the protrusion outside the groove can be disposed on part or all of the protrusion.

[0058] When the first conductive region 20 is disposed on the protrusion outside the groove, and the second conductive region 30 is disposed inside the groove, since the first conductive region 20 is deposited and grown on the protrusion, while the second conductive region 30 disposed inside the groove is formed by doping the silicon substrate 10 at the bottom of the groove, the height difference between the groove and the protrusion allows for the isolation of the first conductive region 20 and the second conductive region 30. In this case, the first conductive region 20 can be disposed on part or all of the protrusion. (Refer to...) Figure 2 , Figure 4 and Figure 5 As shown, it can be configured according to actual usage needs.

[0059] When the first conductive area 20 is disposed within the groove and the second conductive area 30 is disposed on the protrusion outside the groove, the second conductive area 30 can be disposed on a portion of the protrusion, so that it will not connect with the first conductive area 20 within the groove. Figure 1 As shown; when the second conductive area 30 is disposed on the entire area of ​​the boss, the depth of the groove is greater than the thickness of the first conductive area 20 and the junction depth of the second conductive area 30, so that the first conductive area 20 and the second conductive area 30 are not connected.

[0060] Furthermore, in one embodiment of the present invention, the depth of each groove is set to 0.01-10 μm. Therefore, when the first conductive region 20 is disposed within the groove, the total thickness of the first conductive region 20 can be greater than, less than, or equal to the depth of the groove. That is, the first conductive region 20 can be deposited only within the groove or extend beyond it. It should be noted that, in one embodiment of the present invention, such as... Figure 6 As shown, the second conductive region 30 is disposed on a portion of the protrusion, and the first dielectric layer 21 extends to cover the area between the first doped region 22 and the second doped region. The thickness of the first conductive region 20 is greater than the depth of the groove. At this time, the first doped region 22 can also extend to a portion of the protrusion and is not connected to the second doped region. At this time, the first dielectric layer 21 and the first doped region 22 disposed on the protrusion also form a passivated contact structure and are connected to the first dielectric layer 21 and the first doped region 22 in the groove, thereby increasing the contact area of ​​the first dielectric layer 21 through which charge carriers selectively pass.

[0061] It should also be noted that, in one embodiment of the present invention, such as Figure 7As shown, the second conductive region 30 is disposed in the groove. When the silicon substrate 10 in the groove is diffused by a diffusion source to form the second doped region, it may also diffuse to form a second doped region on the sidewall of the groove, so that the second doped region extends to a portion of the region between the grooves. Therefore, in one embodiment of the present invention, the first doped region 22 and / or the second doped region can extend to a portion of the region between the grooves. That is, the first doped region 22 can extend out of the groove to a portion of the region between the grooves; or the second doped region can extend from the sidewall of the groove to a portion of the region between the grooves; or the first doped region 22 can extend out of the groove to a portion of the region between the grooves, while the second doped region extends from the sidewall of the groove to a portion of the region between the grooves.

[0062] It should be noted that when the first doped region 22 is a P-type doped region, the width of the P-type doped region is 300-600 μm; when the first doped region 22 is an N-type doped region, the width of the N-type doped region is 100-500 μm. Furthermore, the width of the P-type doped region is greater than the width of the N-type doped region. That is, when the first conductive region 20 is disposed within the groove, the width of the groove is as described above; and when the first conductive region 20 is disposed on the protrusion, the width of the protrusion is at least greater than described above, so that the first conductive region 20 is partially or entirely disposed on the protrusion. As can be seen from the above, the width of the groove is more relaxed than the tens of micrometers width control requirements of existing trenches, and the fabrication is easier than the fabrication of existing trenches. As a preferred embodiment of the present invention, the width of the P-type doped region is preferably 500 μm; the width of the N-type doped region is preferably 300 μm; and the distance between the first conductive region 20 and the second conductive region 30 is preferably 100 μm.

[0063] Furthermore, in one embodiment of the present invention, the second dielectric layer 40 covers the region between the first conductive region 20 and the second conductive region 30, or extends to cover the first conductive region 20 and / or the second conductive region 30. That is to say, referring to... Figure 8 and Figure 9 As shown, the second dielectric layer 40 can cover only the area between the first doped region 22 and the second doped region. Correspondingly, the conductive layer 50 covers the first doped region 22 and its entire back surface for electrical connection. (Refer to...) Figure 1 and Figure 2As shown, the second dielectric layer 40 can also extend to cover the first doped region 22 and / or the second doped region. In this case, the conductive layer 50 covers the remaining back sides of the first doped region 22 and the second doped region that are not covered by the second dielectric layer 40, forming electrical connections with the first doped region 22 and the second doped region, respectively. Of course, the second dielectric layer 40 can also completely cover the entire back side of the back contact structure during the fabrication process. In this case, when fabricating the conductive layer 50, the conductive layer 50 is inserted through the second dielectric layer 40 by means of perforation or the like to form electrical connections with the first doped region 22 and the second doped region, respectively.

[0064] Furthermore, in one embodiment of the present invention, the second dielectric layer 40 is preferably one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer. The second dielectric layer 40 serves a passivation function, and is configured as at least one layer with the refractive index of each layer decreasing sequentially from the silicon substrate 10 outwards. This allows the layers closer to the silicon substrate 10 to provide passivation, while the layers further away from the silicon substrate 10 provide anti-reflection, thereby enhancing the anti-reflection effect and increasing the absorption and utilization of light by the silicon substrate 10, thus increasing the short-circuit current density. In addition, the second dielectric layer 40 can also be a doped silicon layer (such as a doped microcrystalline silicon layer, a doped amorphous silicon layer, or a doped polycrystalline silicon layer), a doped silicon carbide layer (such as a doped polycrystalline silicon carbide layer), or a doped silicon oxide layer (such as a doped polycrystalline silicon oxide or a doped amorphous silicon oxide). Furthermore, each layer of the second dielectric layer 40 with a different structure may be composed of multiple layers of films with different refractive indices, and the refractive indices of each layer are arranged in a manner that decreases sequentially from the silicon substrate 10 outwards, as described above. For example, the silicon oxide layer in the second dielectric layer 40 may be composed of multiple layers of silicon oxide films with a refractive index that decreases sequentially from the silicon substrate 10 outwards.

[0065] Based on the above, as some specific examples of the present invention, for example, its second dielectric layer 40 can be a three-layer structure composed of a silicon oxide layer / alumina layer, an intrinsic silicon carbide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / alumina layer in the inner first layer is greater than 0.5 nm, the thickness of the intrinsic silicon carbide layer in the second layer is greater than 1 nm, and the thickness of the silicon nitride layer / silicon oxynitride layer in the outer third layer is greater than 50 nm.

[0066] As some specific examples of the present invention, for example, its second dielectric layer 40 can also be a two-layer structure composed of an aluminum oxide layer and a silicon nitride layer / silicon oxynitride layer, in which case the thickness of the aluminum oxide layer in the inner first layer is greater than 1 nm; and the thickness of the silicon nitride layer / silicon oxynitride layer in the outer second layer is greater than 50 nm.

[0067] As some specific examples of the present invention, for example, its second dielectric layer 40 can also be a three-layer structure composed of a silicon oxide layer / alumina layer, a doped polycrystalline silicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / alumina layer in the inner first layer is 0.5-3nm, the thickness of the doped polycrystalline silicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer in the second layer is 20-100nm, and the thickness of the silicon nitride layer / silicon oxynitride layer in the outer third layer is greater than 50nm.

[0068] As some specific examples of the present invention, for example, its second dielectric layer 40 can also be a three-layer structure composed of an intrinsic amorphous silicon layer, a doped amorphous silicon layer / doped amorphous silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the intrinsic amorphous silicon layer in the inner first layer is 2-10 nm, the thickness of the doped amorphous silicon layer / doped amorphous silicon oxide layer in the second layer is 2-50 nm, and the thickness of the silicon nitride layer / silicon oxynitride layer in the outer third layer is greater than 50 nm.

[0069] As some specific examples of the present invention, for example, its second dielectric layer 40 can also be a three-layer structure composed of a silicon oxide layer / alumina layer, an intrinsic silicon carbide layer / doped amorphous silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / alumina layer in the inner first layer is 0.5-3nm, the thickness of the intrinsic silicon carbide layer / doped amorphous silicon oxide layer in the second layer is 10-50nm, and the thickness of the silicon nitride layer / silicon oxynitride layer in the outer third layer is greater than 50nm.

[0070] It is understood that the specific structural arrangement of the second dielectric layer 40 includes, but is not limited to, the specific examples listed above. In a preferred embodiment of the invention, refer to... Figure 1 and Figure 2 As shown, the second dielectric layer 40 preferably has a two-layer structure of an alumina layer and an intrinsic silicon carbide layer, or a two-layer structure of a silicon oxide layer and an intrinsic silicon carbide layer. In this case, the overall thickness of the second dielectric layer 40 is greater than 25 nm, while it is typically 70-80 nm during normal production. In this case, the intrinsic silicon carbide layer not only provides hydrogen passivation, but also, compared to intrinsic amorphous silicon layers and doped polycrystalline silicon layers, reduces parasitic light absorption due to its large optical band gap and small absorption coefficient. Furthermore, the thickness of the alumina layer or silicon oxide layer in the second dielectric layer 40 is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer 40 is greater than 10 nm. It should be noted that in the multilayer structures indicated in the embodiments of the present invention, the arrangement order is from the silicon substrate 10 outwards. For example, when the second dielectric layer 40 is an alumina layer and an intrinsic silicon carbide layer, the alumina layer is closer to the silicon substrate 10, while the intrinsic silicon carbide layer is closer to the outside. It should also be noted that in the accompanying drawings, as shown... Figures 1-13As shown, it only illustrates that the second dielectric layer 40 has a two-layer structure. It is understood that the second dielectric layer 40 can also have other layers, and its specific structure is set according to actual needs, and is not entirely consistent with the accompanying drawings. It should also be noted that the various drawings of this invention are only used to describe the specific structural distribution in the back contact structure, but do not represent the actual dimensions of each structure. For example, the thickness of the first dielectric layer 21 mentioned above is 1-20 nm, and the thickness of the second dielectric layer 40 is greater than 25 nm. The drawings do not completely correspond to the specific actual dimensions in this embodiment; the dimensions should be based on the specific parameters provided in this embodiment.

[0071] Furthermore, the intrinsic silicon carbide layer in the second dielectric layer 40 is composed of at least one first intrinsic silicon carbide film with different refractive indices. The refractive index of each first intrinsic silicon carbide film decreases sequentially from the back side of the silicon substrate 10 outwards. Optionally, the refractive indices of the aforementioned materials can generally be selected as follows: 3.88 for monocrystalline silicon; 3.5-4.2 for amorphous silicon; 3.93 for polycrystalline silicon; 2-3.88 for silicon carbide; 1.9-3.88 for silicon nitride; 1.45-3.88 for silicon oxynitride; 1.45 for silicon oxide; and 1.63 for aluminum oxide. It is understood that the refractive indices of the aforementioned materials can also be set to other values ​​according to actual application needs, and no specific limitations are made here.

[0072] Furthermore, in one embodiment of the present invention, the outer layer of the second dielectric layer 40 is further provided with a magnesium fluoride layer. That is, based on one or more combinations of the selected aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer, and silicon oxide layer for the second dielectric layer 40, a magnesium fluoride layer may also be provided on the outer layer of the second dielectric layer 40. The refractive index of the magnesium fluoride layer is required to be the lowest, generally set to 1.4, and it is used to enhance the optical function of anti-reflection.

[0073] Furthermore, in one embodiment of the present invention, the conductive layer 50 is a TCO transparent conductive film and / or a metal electrode. The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-plated copper electrode, or a silver-plated copper electrode. Further, the copper electrode is electroplated copper prepared by an electroplating process or a copper electrode prepared by physical vapor deposition. The electroplated copper uses nickel, chromium, titanium, or tungsten electrodes as its seed layer or protective layer.

[0074] Furthermore, in one embodiment of the invention, the groove is arc-shaped, trapezoidal, or square. For example... Figure 1 and Figure 2 As shown, in one specific embodiment, the groove is square. (As illustrated...) Figure 10As shown, in another specific embodiment, the groove for the first conductive region 20 is arc-shaped. For example... Figure 11 As shown, in another specific embodiment, the groove for the first conductive region 20 is trapezoidal. It can be understood that the second conductive region 30 can also be disposed within the arc-shaped or trapezoidal groove. Preferably, the groove is arc-shaped or trapezoidal, as this improves the light reflection effect of the inner wall of the groove. Furthermore, when the first conductive region 20 is disposed within the groove, it increases the surface area of ​​the first dielectric layer 21, which serves as the tunneling structure, in contact with the silicon substrate 10. Of course, since a square groove simplifies the actual manufacturing process, the shape of the groove can be set according to actual usage requirements, and no specific limitation is made here.

[0075] It should be noted that in other embodiments of the present invention, when the first conductive region 20 is disposed within the groove, there is a possibility that the first dielectric layer 21 is connected to the bottom wall of the groove, and the second dielectric layer 40 is also connected to the side wall of the groove. This is mainly because when a mask is used to cover the groove area, the silicon in part of the silicon substrate 10 next to the first doped region 22 will be etched during subsequent mask removal, thereby expanding the width of the groove. When the second dielectric layer 40 is subsequently deposited, it will be deposited into the empty area, thus connecting the second dielectric layer 40 to the side wall of the groove. Alternatively, when preparing an arc-shaped groove (such as an elliptical groove), it may be impossible to deposit the first dielectric layer 21 and the first doped region 22 onto the inner wall of the arc-shaped groove along its long axis. Therefore, when depositing the second dielectric layer 40, it may fill the empty area, causing the second dielectric layer 40 to connect with the sidewall of the arc-shaped groove. Alternatively, it may be impossible to deposit the second dielectric layer 40 into the empty area, resulting in a gap between the sidewall of the arc-shaped groove and the first dielectric layer 21 and the first doped region 22. It should be noted that, in this embodiment of the invention, the first dielectric layer 21 is preferably directly connected to the sidewall of the groove in the back contact structure. This allows the first dielectric layer 21 disposed on the sidewall of the groove to selectively collect charge carriers in multiple dimensions.

[0076] Furthermore, in one embodiment of the present invention, referring to Figure 12 and Figure 13 As shown, when the first conductive region 20 or the second conductive region 30 is disposed on a portion of the protrusion outside the groove, the back side of the silicon substrate 10 located between the first conductive region 20 and the second conductive region 30 has a rough texture structure 60. This rough texture structure 60 is typically formed by texturing, which can be an irregular hemispherical texture formed by acid texturing, a pyramidal texture formed by alkaline texturing, or a pyramidal texture formed first by alkaline texturing followed by acid texturing to smooth the pyramid apex.

[0077] Testing showed that the experimental group of batteries prepared using the back contact structure provided in this embodiment of the invention exhibited a significantly improved conversion efficiency of approximately 25.6% compared to the control group batteries prepared using existing trench methods, with a substantial increase in reliability. The electrical performance results are shown in Table 1 below. Table 1 Among them, the beneficial effects of the embodiments of the present invention compared with the prior art are as follows: 1. By setting grooves at intervals on the back side of the silicon substrate, and alternately setting a first conductive region on one side of the groove and a second conductive region on the other side, the first and second conductive regions can be blocked by part of the groove or part of the protrusion outside the groove. The width control requirements of the grooves are more relaxed than those of existing trenches, and the fabrication is easier than that of existing trenches.

[0078] 2. Due to the design of the groove, when the first conductive region is located in the groove, its first dielectric layer can contact both the bottom wall and the side wall of the groove. Therefore, the charge carriers generated on the silicon substrate can be easily separated through the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region. This not only reduces the leakage current but also enables selective transport of charge carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of charge carriers in the bottom wall and side wall of the groove.

[0079] 3. Since the second dielectric layer is set to at least one layer, the back side of the silicon substrate is passivated by at least one second dielectric layer and the first dielectric layer, resulting in a better passivation effect. Furthermore, by controlling the refractive index of each layer to decrease sequentially from the silicon substrate outward, the reflection of long-wavelength light on the inner back side of the silicon substrate can be improved, thereby increasing the short-circuit current density.

[0080] 4. Because the grooves have a certain depth, the hard mask only directly contacts the protrusion between the two grooves, so that the hard mask will not directly contact the bottom of the groove, reducing impurity contamination. Therefore, it can play a certain role in protecting the silicon substrate on the bottom wall of the groove. There is no need to worry about the hard mask causing damage to the silicon substrate. The damage caused by the hard mask contacting the protrusion surface of the silicon substrate can also be removed by the subsequent texturing process.

[0081] 5. In the process of selectively depositing the first doped region using a hard mask, since there are silicon substrate bump structures of a certain width between each groove for isolation, the alignment requirement of the hard mask does not need to be very precise when depositing the groove region under the cover of the hard mask. A moderate amount of deviation can be allowed, which makes the alignment of the hard mask simpler and reduces the difficulty of the process.

[0082] 6. In the prior art, due to the limitations of width and depth in the trench area, the chemical solution cannot fully wet the bottom of the trench for chemical wet texturing due to the hydrophobicity of water and silicon wafer. However, in this embodiment, due to the grooves provided and the opposite back surface of the silicon substrate between adjacent grooves being protrusions, it is easier to achieve texturing to obtain a rough texture structure than the existing trench structure. Furthermore, by texturing the protrusions on the back surface of the silicon substrate, the reflection of light on the inner back surface of the silicon substrate is increased, thereby increasing the light absorption rate of the silicon substrate.

[0083] Example 2 The second embodiment of the present invention provides a selectively contacted buried solar cell. For ease of explanation, only the parts relevant to the embodiments of the present invention are shown. Refer to... Figures 1-13 As shown, the selective contact area buried solar cell provided in this embodiment of the invention includes: Silicon substrate 10; The back contact structure described in the aforementioned embodiment is disposed on the back side of the silicon substrate 10; and A third dielectric layer 70 is disposed on the front side of the silicon substrate 10.

[0084] Furthermore, in one embodiment of the present invention, the second dielectric layer 40 and the third dielectric layer 70 can be fabricated on both sides of the silicon substrate 10 using the same process. In this case, the third dielectric layer 70 can have the same structure as the second dielectric layer 40 in the aforementioned embodiment. Therefore, referring to the aforementioned embodiments, the third dielectric layer 70 can also preferably be one or a combination of an alumina layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0085] As some examples of the present invention, the third dielectric layer 70 may also be a three-layer structure composed of a silicon oxide layer / alumina layer and a doped polycrystalline silicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer and silicon nitride layer / silicon oxynitride layer, or a three-layer structure composed of an intrinsic amorphous silicon layer and a doped amorphous silicon layer / doped amorphous silicon oxide layer and silicon nitride layer / silicon oxynitride layer, or a three-layer structure composed of a silicon oxide layer / alumina layer and an intrinsic silicon carbide layer / doped amorphous silicon oxide layer and silicon nitride layer / silicon oxynitride layer.

[0086] Furthermore, in a preferred embodiment of the present invention, referring to Figure 1As shown, the third dielectric layer 70 is preferably a two-layer structure consisting of a silicon oxide layer and an intrinsic silicon carbide layer, or a two-layer structure consisting of an aluminum oxide layer and an intrinsic silicon carbide layer, with a thickness greater than 50 nm. Specifically, the thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer 70 is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer 70 is greater than 10 nm. In this case, the intrinsic silicon carbide layer not only provides hydrogen passivation, but also, compared to intrinsic amorphous silicon layers and doped polycrystalline silicon layers, has a large optical band gap and a small absorption coefficient, thus reducing parasitic light absorption. Furthermore, the intrinsic silicon carbide layer in the third dielectric layer 70 is composed of at least one second intrinsic silicon carbide film with different refractive indices. The refractive index of each second intrinsic silicon carbide film decreases sequentially from the front side of the silicon substrate 10 outwards. Furthermore, in one embodiment of the present invention, a magnesium fluoride layer is also provided on the outer layer of the third dielectric layer 70. The outermost magnesium fluoride layer has the lowest refractive index requirement, typically set to 1.4, which is used to enhance the optical function of anti-reflection.

[0087] Of course, the third dielectric layer 70 may also have a different structural arrangement than the second dielectric layer 40 in the aforementioned embodiments. The structure of each film layer of the second dielectric layer 40 and the third dielectric layer 70 may be set according to the actual use needs, and no specific limitation is made here.

[0088] Furthermore, in one embodiment of the present invention, an electric field layer or a floating junction is provided between the front side of the silicon substrate 10 and the third dielectric layer 70. Specifically, the silicon substrate 10 is subjected to phosphorus diffusion to obtain the electric field layer or to boron diffusion to obtain the floating junction. In this case, the electric field layer or floating junction serves as the front surface electric field (FSF) of the selective contact region buried solar cell.

[0089] In this embodiment, by creating grooves at intervals on the back side of the silicon substrate, and alternately placing a first conductive region inside and outside one of the grooves and a second conductive region in the other, the first and second conductive regions are effectively blocked by a portion of the groove or a portion of the protrusion outside the groove. The grooves have more lenient width control requirements than existing trenches, and their fabrication is easier. Furthermore, due to the grooves, when the first conductive region is placed within a groove, its first dielectric layer can contact both the bottom and sidewalls of the groove. Therefore, charge carriers generated on the silicon substrate can easily pass through the groove sidewalls. The first dielectric layer on the wall is separated and selectively collected into the corresponding first doped region, which can reduce leakage current and achieve selective transport of charge carriers in both the longitudinal and lateral directions. This is beneficial for multi-dimensional collection of charge carriers in the bottom and side walls of the trench. Since there is at least one second dielectric layer, the back side of the silicon substrate is passivated through at least one second dielectric layer, which brings better passivation effect and improves internal back reflection. This solves the existing problems of high requirements for trench width control and poor passivation effect.

[0090] Example 3 The third embodiment of the present invention provides a method for fabricating a selectively contacted buried solar cell. For ease of explanation, only the parts related to the embodiments of the present invention are shown. Refer to... Figure 14 As shown, the selective contact area buried solar cell fabrication method provided in this embodiment of the invention is used to prepare the selective contact area buried solar cell as described in the foregoing embodiments. Specifically, the method includes: Step S11: A plurality of grooves spaced apart are formed on the back side of the silicon substrate; Prior to step S11, a pretreatment of the silicon substrate should also be performed. The aforementioned pretreatment includes cleaning the silicon substrate and removing the damaged layer. Specifically, it includes: (1) RCA standard cleaning to remove particles and organic matter from the surface of the silicon substrate; (2) After cleaning the silicon substrate, it is placed in a 2-5% KOH alkaline solution (potassium hydroxide) or TMAH solution (tetramethylammonium hydroxide, i.e., developer) at a temperature of 50-80℃ for 1-5 minutes to remove the surface damage layer caused by the slicing process. (3) Use HCl to pickle the surface of the silicon substrate to neutralize the alkaline solution remaining on the surface of the silicon substrate and remove the residual metal impurities on the surface of the silicon wafer; (4) The silicon substrate is cleaned with HF solution to remove the silicon dioxide layer on the surface of the silicon wafer and form Si-H passivation bonds with the dangling bonds on the surface of the silicon substrate. Finally, it is dried with nitrogen for later use.

[0091] Furthermore, after the silicon substrate has been pretreated, the trenches can be created using the following methods: Method 1: Directly groove the desired area on the back side of the silicon substrate using a laser to remove localized silicon crystals, forming the required grooves. Method 2: Perform thermal oxidation on the silicon substrate to form a layer of silicon oxide on the entire surface. Remove the silicon oxide from the front and back sides of the substrate using laser grooving, followed by wet etching and removal of the silicon oxide with acid (such as HF) to form the desired grooves. Method 3: Deposit a layer of silicon nitride on the back side of the silicon substrate using PECVD. Remove the silicon nitride from the back side using laser grooving, followed by wet etching and removal of the silicon nitride to form the desired grooves. Method 4: Deposit silicon nitride on the back of a silicon substrate or thermally oxidize the silicon substrate to form silicon oxide, then deposit a photoresist mask on the back, develop the developing area by patterning the screen and exposing it, remove the developing area by wet etching with a developer, remove the silicon nitride / silicon oxide in the developing area by acid (such as HF), and then remove the photoresist mask and silicon nitride / silicon oxide by wet etching to form the desired groove; Method 5: Print patterned paste on the back of a silicon substrate as a mask, then remove the paste by wet etching to form the desired groove.

[0092] In this embodiment of the invention, the second method described above is preferably used for creating the grooves. In this second method, the thermal oxidation process specifically includes: dry oxygen oxidation / water vapor oxidation / wet oxygen oxidation (i.e., dry oxygen + water vapor) in a quartz tube. The specific reactants are oxygen and / or high-purity water vapor. The reaction pressure is 50-1000 mbar, the reaction temperature is 900-1200℃, and the resulting silicon oxide thickness is greater than 10 nm. The laser grooving process for removing silicon oxide specifically includes: using a laser with a wavelength of 532 nm, a laser power of 10-60 W, a laser frequency of ≤250 to 1500 kHz, and a laser pulse width of 3-50 ns to remove the silicon oxide. The wet etching process uses an alkaline solution and isoacetone. The alkaline solution is KOH or TMAH, with a concentration of 1-5% and an isoacetone content of 1-10%. The reaction temperature is 60-85℃, and the reaction time is 10-30 min. The acid solution used in the step of removing silicon oxide is HF, with a concentration of 1-5%, a reaction temperature of room temperature, and a reaction time of 3-10 min.

[0093] Specifically, after creating the grooves using the second method described above, the depth of each groove is 0.01-10 μm. The grooves can be arc-shaped, trapezoidal, or square. In contrast, existing technologies using laser drilling or wet etching for groove fabrication require strict width control and are difficult to manufacture. The groove fabrication method in this embodiment is easier than existing methods and does not have the stringent width control requirements of existing methods.

[0094] Step S21: A first conductive region and a second conductive region are alternately prepared on a silicon substrate. One of the first conductive region and the second conductive region is disposed in a groove, and the other is disposed outside the groove. The first conductive region includes a first dielectric layer and a first doped region disposed sequentially, and the second conductive region includes a second doped region. Prior to step S21, the specific production process may include texturing the front side of the silicon substrate. In this embodiment, front-side texturing mainly employs alkaline etching, where the alkaline solution reacts with the silicon substrate to generate a water-soluble compound, simultaneously forming a pyramid-shaped textured surface. Due to the presence of this textured surface, after the incident light undergoes its first reflection, it does not directly enter the air. Instead, it encounters adjacent textured surfaces and undergoes a second or even third reflection before entering the air. This allows for multiple uses of the incident light, thereby reducing the front-side reflectivity. When the back side of the silicon substrate also requires a rough textured structure, both the front and back sides can be texturized simultaneously. Conversely, when the back side of the silicon substrate does not require a rough textured structure, a silicon nitride protective layer can be deposited on the back side first, followed by front-side texturing. The silicon nitride protective layer on the back side can then be removed using a laser, thus avoiding texturing the back side of the silicon substrate.

[0095] The alternating fabrication of the first and second conductive regions on the silicon substrate is achieved through the following steps: A first dielectric layer and a first doped region having a first conductivity type are sequentially prepared inside or outside the groove; A second doped region with a second conductivity type is prepared outside or inside the corresponding groove, wherein the first conductivity type is opposite to the second conductivity type.

[0096] It should be noted that the first conductive region and the second conductive region are respectively located at different positions inside and outside the groove. When the first conductive region, which is specifically the first dielectric layer and the first doped region, is located inside the groove, the second conductive region, which is specifically the second doped region, is located outside the groove; conversely, when the first dielectric layer and the first doped region are located outside the groove, the second doped region is located inside the groove. Furthermore, the conductivity types of the first doped region and the second doped region are opposite. If the first doped region is a P-type doped region, the second doped region corresponds to an N-type doped layer; conversely, if the first doped region is an N-type doped region, the second doped region corresponds to a P-type doped layer.

[0097] Since the steps of preparing the alternating first and second conductive regions cannot be performed simultaneously through the process flow, the first conductive region must be prepared first, followed by the second conductive region; or the second conductive region must be prepared first, followed by the first conductive region. Accordingly, the order in which the first and second conductive regions are prepared is determined based on the convenience of the actual process flow and is not specifically limited here. Preferably, in this embodiment, the first conductive region is prepared first inside or outside the groove, and then the second conductive region is prepared inside or outside the corresponding groove.

[0098] Furthermore, the above-mentioned sequential preparation of the first dielectric layer and the first doped region with the first conductivity type inside or outside the groove specifically involves first preparing the first dielectric layer inside or outside the groove, and then preparing the first doped region with the first conductivity type on the first dielectric layer by either in-situ deposition or non-in-situ deposition.

[0099] Specifically, the first dielectric layer is prepared by means of high-temperature oxidation process or deposition process, and the type of the first dielectric layer is set according to the specific deposition process. No specific limitation is made here. At this time, the first dielectric layer is one or more of the following: tunneling oxide layer, intrinsic silicon carbide layer, and intrinsic amorphous silicon layer, and the thickness of the first dielectric layer is 1-20nm.

[0100] Specifically, in one embodiment of the present invention, when the first doped region is prepared by in-situ deposition, the step of preparing the first doped region on the first dielectric layer includes: Deposit doped amorphous silicon or doped amorphous silicon carbide of a first conductivity type on the first dielectric layer; High-temperature crystallization treatment is performed to transform doped amorphous silicon or doped amorphous silicon carbide into doped polycrystalline silicon or doped silicon carbide, thereby obtaining a first doped region having a first conductivity type.

[0101] In one possible implementation, a first conductive region is disposed inside / outside the groove, and the first doped region within this first conductive region is a P-type doped region. When depositing the P-type doped region in situ, the unwanted protrusions / grooves outside the groove are masked using a masking method. P-type amorphous silicon / P-type amorphous silicon carbide is then deposited in situ inside / outside the groove. The temperature is then raised to 700-1000°C using direct high-temperature or laser heating, causing the P-type amorphous silicon / P-type amorphous silicon carbide inside / outside the groove to transform into P-type polycrystalline silicon / P-type silicon carbide under high-temperature crystallization treatment, thus obtaining the P-type doped region, i.e., the first doped region with the first conductivity type. The mask can be a hard mask, a silicon nitride mask, a silicon oxide mask, or a photoresist mask.

[0102] Specifically, in one embodiment of the present invention, when the first doped region is prepared by non-in-situ deposition, the step of preparing the first doped region on the first dielectric layer includes: Intrinsic amorphous silicon or intrinsic silicon carbide is deposited on the first dielectric layer; Doping intrinsic amorphous silicon or intrinsic silicon carbide with a first conductivity type; High-temperature crystallization treatment is performed to transform intrinsic amorphous silicon or intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide, thereby obtaining a first doped region having a first conductivity type.

[0103] Specifically, the steps of doping intrinsic amorphous silicon or intrinsic silicon carbide with a first conductivity type include: Implanting ions of the first conductivity type onto intrinsic amorphous silicon or intrinsic silicon carbide; or Deposit a doping source of the first conductivity type onto intrinsic amorphous silicon or intrinsic silicon carbide; or Doping is performed by introducing a source gas of the first conductivity type into intrinsic amorphous silicon or intrinsic silicon carbide.

[0104] In one possible implementation, specifically, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited on the first dielectric layer, and then doped by implanting ions of a first conductivity type into the intrinsic amorphous silicon or intrinsic silicon carbide (when the first doped region is a P-type doped region, P-type ions containing elements such as boron, aluminum, and gallium are implanted; and when the first doped region is an N-type doped region, N-type ions containing elements such as nitrogen, phosphorus, and arsenic are implanted); or doped by depositing a dopant source of the first conductivity type on the intrinsic amorphous silicon or intrinsic silicon carbide using a mask method (when the first doped region is a P-type doped region, a P-type dopant source containing boron, aluminum, gallium, etc. (such as borosilicate glass) is deposited to form P-type amorphous silicon / P-type silicon carbide; and when the first doped region is an N-type doped region, an N-type dopant source containing nitrogen, phosphorus, arsenic, etc. (such as phosphosilicate glass) is deposited). (1) Doping is performed to form N-type amorphous silicon / N-type silicon carbide; or doping is performed by introducing a source gas of the first conductivity type into intrinsic amorphous silicon or intrinsic silicon carbide through a mask method (e.g., when the first doping region is a P-type doping region, a P-type source gas containing elements such as boron, aluminum, gallium, etc. (e.g., borane gas or a carrier gas carrying boron trichloride or boron tribromide) is introduced to form P-type amorphous silicon / P-type silicon carbide; when the first doping region is an N-type doping region, an N-type source gas containing elements such as nitrogen, phosphorus, arsenic, etc. (e.g., phosphine gas or a carrier gas carrying phosphorus oxychloride) is introduced to form N-type amorphous silicon / N-type silicon carbide). After doping, high-temperature crystallization treatment is performed to transform the intrinsic amorphous silicon or intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide to obtain a first doped region with the first conductivity type. Since intrinsic amorphous silicon or intrinsic silicon carbide may be deposited on the sides and front of the silicon substrate, a wet etching process is required after high-temperature crystallization to remove the plating. It should also be noted that after depositing a dopant source of the first conductivity type, performing doping, and high-temperature crystallization, the dopant source needs to be removed using methods such as lasers.

[0105] Specifically, in another embodiment of the present invention, when the first doped region is prepared by non-in-situ deposition, the step of preparing the first doped region on the first dielectric layer further includes: Intrinsic amorphous silicon or intrinsic silicon carbide is deposited on the first dielectric layer; Intrinsic amorphous silicon or intrinsic silicon carbide is diffused with a first conductivity type to transform the intrinsic amorphous silicon or intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide, thereby obtaining a first doped region having a first conductivity type.

[0106] It should be noted that during the preparation of the first doped region, due to the need for a high-temperature crystallization process, the relatively thin first dielectric layer will be partially broken. At this time, during the high-temperature diffusion process, it will adhere to the broken part of the first dielectric layer and the back side of the silicon substrate, so that multiple internal diffusion regions corresponding to the first doped region are formed on the surface where the silicon substrate and the first dielectric layer are in contact.

[0107] Furthermore, the step of preparing a second doped region with a second conductivity type outside or inside the corresponding groove includes: A source gas corresponding to the second conductivity type is introduced into the corresponding groove outside or inside the groove to perform thermal diffusion and form a second doped region with the second conductivity type; or Deposit or spin-coat a doping source corresponding to the second conductivity type outside or inside the corresponding groove, and then thermally diffuse to form a second doped region with the second conductivity type; or Ions corresponding to the second conductivity type are injected outside or inside the corresponding groove and thermally diffused to form a second doped region with the second conductivity type.

[0108] Specifically, when the second doped region is a P-type doped layer, its specific fabrication process includes: Method 1: Introducing a source gas containing elements such as boron, aluminum, and gallium (such as borane gas or a carrier gas carrying boron trichloride or boron tribromide) for thermal diffusion to form a P-type doped layer; Method 2: Depositing a doped source containing elements such as boron, aluminum, and gallium (such as borosilicate glass) for thermal diffusion to form a P-type doped layer; Method 3: Fabricating an aluminum electrode on top of the doped layer, and then forming an aluminum-doped P-type doped layer through a high-temperature process; Method 4: Spin-coating a doped source containing elements such as boron, aluminum, and gallium (such as boron tribromide) for thermal diffusion to form a P-type doped layer; Method 5: Implanting ions containing elements such as boron, aluminum, and gallium, and then forming a P-type doped layer through high-temperature diffusion.

[0109] When the second doped region is an N-type doped layer, the specific fabrication process is as follows: Method 1: Introduce a source gas containing elements such as nitrogen, phosphorus, and arsenic (e.g., phosphine gas or a carrier gas carrying phosphorus oxychloride) for thermal diffusion to form an N-type doped layer; Method 2: Deposit a dopant source containing elements such as nitrogen, phosphorus, and arsenic (e.g., phosphosilicate glass) for thermal diffusion to form an N-type doped layer; Method 3: Spin-coat a dopant source containing elements such as nitrogen, phosphorus, and arsenic (e.g., phosphorus oxychloride) for thermal diffusion to form an N-type doped layer; Method 4: Implant ions containing elements such as nitrogen, phosphorus, and arsenic, and then diffuse them at high temperature to form an N-type doped layer. It should be noted that after the thermal diffusion of the deposited dopant source, it is necessary to remove the dopant source using methods such as lasers.

[0110] Step S31: Prepare a second dielectric layer and a third dielectric layer on the back and front sides of the silicon substrate, respectively; Prior to step S41, the process may further include texturing the back side of the silicon substrate at the location between the first conductive region and the second conductive region to obtain a rough textured structure. The specific texturing process can be referred to the above description.

[0111] Specifically, during the fabrication of the second and third dielectric layers on the back and front sides of the silicon substrate, the fabrication process is based on the specific composition of the second and third dielectric layers, without specific limitations. Correspondingly, the second and third dielectric layers can be one or more combinations of aluminum oxide, silicon nitride, silicon oxynitride, intrinsic silicon carbide, intrinsic amorphous silicon, and silicon oxide. Furthermore, when the second and third dielectric layers are configured as a multilayer structure, the refractive index of each layer decreases sequentially from the silicon substrate outwards, and the outermost layer may also contain a magnesium fluoride layer with the lowest required refractive index.

[0112] Simultaneously, before fabricating the third dielectric layer on the front side of the silicon substrate, an electric field layer or a floating junction can be fabricated first. Specifically, the electric field layer is obtained by phosphorus diffusion on the silicon substrate, or a floating junction is obtained by boron diffusion. At this time, the electric field layer or floating junction serves as the front surface electric field (FSF) of the selective contact area buried solar cell.

[0113] Step S51: Prepare a conductive layer on the first conductive region and the second conductive region.

[0114] Specifically, when the second dielectric layer only covers the area between the first doped region and the second doped region in the silicon substrate, the conductive layer covers the entire back side of the first doped region and the second doped region for electrical connection; when the second dielectric layer extends to cover the first doped region and the second doped region, the conductive layer covers the remaining back side of the first doped region and the second doped region that is not covered by the second dielectric layer for electrical connection; when the second dielectric layer covers the entire back side of the silicon substrate, the conductive layer is electrically connected to the first doped region and the second doped region by means of through-holes or the like, so that a first electrode is formed in the first doped region and a second electrode is formed in the second doped region.

[0115] Among them, the beneficial effects of the embodiments of the present invention compared with the prior art are as follows: 1. By setting grooves at intervals on the back side of the silicon substrate, and alternately setting a first conductive region on one side of the groove and a second conductive region on the other side, the first and second conductive regions can be blocked by part of the groove or part of the protrusion outside the groove. The width control requirements of the grooves are more relaxed than those of existing trenches, and the fabrication is easier than that of existing trenches.

[0116] 2. Due to the design of the groove, when the first conductive region is located in the groove, its first dielectric layer can contact both the bottom wall and the side wall of the groove. Therefore, the charge carriers generated on the silicon substrate can be easily separated through the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region. This not only reduces the leakage current but also enables selective transport of charge carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of charge carriers in the bottom wall and side wall of the groove.

[0117] 3. Since the second dielectric layer is set to at least one layer, the back side of the silicon substrate is passivated by at least one second dielectric layer and the first dielectric layer, resulting in a better passivation effect. Furthermore, by controlling the refractive index of each layer to decrease sequentially from the silicon substrate outward, the reflection of long-wavelength light on the inner back side of the silicon substrate can be improved, thereby increasing the short-circuit current density.

[0118] 4. Because the grooves have a certain depth, the hard mask only directly contacts the protrusion between the two grooves, so that the hard mask will not directly contact the bottom of the groove, reducing impurity contamination. Therefore, it can play a certain role in protecting the silicon substrate on the bottom wall of the groove. There is no need to worry about the hard mask causing damage to the silicon substrate. The damage caused by the hard mask contacting the protrusion surface of the silicon substrate can also be removed by the subsequent texturing process.

[0119] 5. In the process of selectively depositing the first doped region using a hard mask, since there are silicon substrate bump structures of a certain width between each groove for isolation, the alignment requirement of the hard mask does not need to be very precise when depositing the groove region under the cover of the hard mask. A moderate amount of deviation can be allowed, which makes the alignment of the hard mask simpler and reduces the difficulty of the process.

[0120] 6. In the prior art, due to the limitations of width and depth in the trench area, the chemical solution cannot fully wet the bottom of the trench for chemical wet texturing due to the hydrophobicity of water and silicon wafer. However, in this embodiment, due to the grooves provided and the opposite back surface of the silicon substrate between adjacent grooves being protrusions, it is easier to achieve texturing to obtain a rough texture structure than the existing trench structure. Furthermore, by texturing the protrusions on the back surface of the silicon substrate, the reflection of light on the inner back surface of the silicon substrate is increased, thereby increasing the light absorption rate of the silicon substrate.

[0121] Example 4 The fourth embodiment of the present invention also provides a battery assembly, which includes the selective contact area buried solar cell described in the foregoing embodiments.

[0122] In this embodiment, the battery assembly uses selectively contacted buried solar cells with grooves spaced apart on the back side of a silicon substrate. A first conductive region is alternately positioned inside or outside one of the grooves, and a second conductive region is positioned in the other. This allows the first and second conductive regions to be isolated through the grooves or protrusions outside the grooves. The grooves have more lenient width control requirements than existing trenches, and their fabrication is easier. Furthermore, due to the grooves, when the first conductive region is located within the groove, its first dielectric layer can contact both the bottom and sidewalls of the groove. Therefore, the resulting... Charge carriers can also be easily separated through the first dielectric layer on the sidewall of the trench and selectively collected into the corresponding first doped region, which can reduce leakage current and achieve selective transport of charge carriers in both the longitudinal and lateral directions. This is beneficial for multi-dimensional collection of charge carriers in the bottom and sidewalls of the trench. Since there is at least one second dielectric layer, the back side of the silicon substrate can achieve multi-layer passivation through at least one second dielectric layer, thereby bringing better passivation effect and improving internal back reflection. This solves the existing problems of high requirements for trench width control and poor passivation effect.

[0123] Example 5 The fifth embodiment of the present invention also provides a photovoltaic system, including the battery module as described in the foregoing embodiments.

[0124] In this embodiment of the photovoltaic system, the selective contact area of ​​the buried solar cell in the battery module is provided with grooves spaced apart on the back side of the silicon substrate. A first conductive region is alternately provided in one of the grooves and a second conductive region in the other. This allows the first and second conductive regions to be isolated through a portion of the groove or a portion of the protrusion outside the groove. The width control requirements of the grooves are more relaxed than those of existing trenches, and their fabrication is easier. Simultaneously, due to the groove arrangement, when the first conductive region is located within the groove, its first dielectric layer can contact both the bottom and sidewalls of the groove. Therefore, the photovoltaic system produced on the silicon substrate... The generated charge carriers can also be easily separated through the first dielectric layer on the sidewall of the trench and selectively collected into the corresponding first doped region. This enables both a reduction in leakage current and selective transport of charge carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of charge carriers in the bottom and sidewalls of the trench. Since there is at least one second dielectric layer, the back side of the silicon substrate is passivated through at least one second dielectric layer, resulting in better passivation and improved internal back reflection. This solves the existing problems of high requirements for trench width control and poor passivation effect.

[0125] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A back contact structure for a solar cell, characterized in that, include: Grooves spaced apart on the back side of the silicon substrate; Alternating first conductive region and second conductive region, the first conductive region is disposed inside the groove and the second conductive region is disposed outside the groove, the first conductive region includes a first dielectric layer and a first doped region disposed sequentially, and the second conductive region includes a second doped region; The total thickness of the first dielectric layer and the first doped region is less than the depth of the groove, and the second doped region is a boss outside the groove, and the second doped region covers all or part of the boss. A second dielectric layer is disposed between the first conductive region and the second conductive region, wherein the second dielectric layer is at least one layer. and A conductive layer is disposed on the first conductive region and the second conductive region.

2. The back contact structure as described in claim 1, characterized in that, The first doped region is a P-type doped region, and the second doped region is an N-type doped layer; or The first doped region is an N-type doped region, and the second doped region is a P-type doped layer.

3. The back contact structure as described in claim 2, characterized in that, The width of the P-type doped region is greater than the width of the N-type doped region.

4. The back contact structure as described in claim 1, characterized in that, The first doped region includes doped polycrystalline silicon, doped silicon carbide, or doped amorphous silicon.

5. The back contact structure as described in claim 1, characterized in that, The first dielectric layer is one or more combinations of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer.

6. The back contact structure as described in claim 1, characterized in that, The second dielectric layer is one or more combinations of aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer and silicon oxide layer.

7. The back contact structure as described in claim 1, characterized in that, The back side of the silicon substrate located between the first conductive region and the second conductive region has a rough textured structure.

8. The back contact structure as described in claim 2, characterized in that, The width of the P-type doped region is 300-600 μm, or the width of the N-type doped region is 100-500 μm.

9. The back contact structure as described in claim 1, characterized in that, The depth of each groove is 0.01-10 μm, and the horizontal distance between the first conductive area and the second conductive area is greater than 0 and less than or equal to 500 μm.

10. The back contact structure as described in claim 1, characterized in that, The first dielectric layer covers the first doped region.

11. The back contact structure as described in claim 1, characterized in that, The groove can be arc-shaped, trapezoidal, or square.

12. The back contact structure as described in claim 1, characterized in that, The junction depth of the second doped region is 0.01-1 μm, the sheet resistance is 10-500 ohm / sqr, and the surface concentration is 1E18-1E21 cm⁻¹. -3 .

13. The back contact structure as described in claim 1, characterized in that, The thickness of the first dielectric layer is 1-20 nm, and the total thickness of the first conductive region is greater than 20 nm.

14. The back contact structure as described in claim 4, characterized in that, The doped silicon carbide includes doped hydrogenated silicon carbide.

15. The back contact structure as described in claim 5, characterized in that, The first dielectric layer is a tunneling oxide layer and an intrinsic silicon carbide layer.

16. The back contact structure as described in claim 5 or 15, characterized in that, The tunneling oxide layer consists of one or more layers of silicon oxide or aluminum oxide.

17. The back contact structure as described in claim 5 or 15, characterized in that, The intrinsic silicon carbide layer in the first dielectric layer includes an intrinsic hydrogenated silicon carbide layer.

18. The back contact structure as described in claim 6, characterized in that, The second dielectric layer is an aluminum oxide layer and an intrinsic silicon carbide layer, or a silicon oxide layer and an intrinsic silicon carbide layer, and the thickness of the second dielectric layer is greater than 25 nm.

19. The back contact structure as described in claim 18, characterized in that, The thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer is greater than 10 nm.

20. The back contact structure as described in claim 6 or 18, characterized in that, The intrinsic silicon carbide layer in the second dielectric layer is composed of at least one first intrinsic silicon carbide film with different refractive indices.

21. The back contact structure as described in claim 20, characterized in that, The refractive index of the first intrinsic silicon carbide film in each layer decreases sequentially from the back side of the silicon substrate outwards.

22. The back contact structure as described in claim 6, characterized in that, The outer layer of the second dielectric layer is also provided with a magnesium fluoride layer.

23. The back contact structure as described in claim 1, characterized in that, The conductive layer is a TCO transparent conductive film and / or a metal electrode.

24. The back contact structure as described in claim 23, characterized in that, The metal electrodes include silver electrodes, copper electrodes, aluminum electrodes, tin-coated copper electrodes, or silver-coated copper electrodes.

25. The back contact structure as described in claim 24, characterized in that, The copper electrode is prepared by electroplating or by physical vapor deposition.

26. A selectively contacted buried solar cell, characterized in that, include: silicon substrate; A back contact structure as described in any one of claims 1-25, disposed on the back side of a silicon substrate; and A third dielectric layer disposed on the front side of a silicon substrate.

27. The selective contact area buried solar cell as described in claim 26, characterized in that, The third dielectric layer is one or more combinations of aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer and silicon oxide layer.

28. The selective contact area buried solar cell as described in claim 27, characterized in that, The third dielectric layer is a silicon oxide layer and an intrinsic silicon carbide layer, or an aluminum oxide layer and an intrinsic silicon carbide layer, and the thickness of the third dielectric layer is greater than 50 nm.

29. The selective contact area buried solar cell as described in claim 28, characterized in that, The thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer is greater than 10 nm.

30. The selective contact area buried solar cell as described in claim 27 or 28, characterized in that, The intrinsic silicon carbide layer in the third dielectric layer consists of at least one second intrinsic silicon carbide film with different refractive indices.

31. The selective contact area buried solar cell as described in claim 30, characterized in that, The refractive index of each layer of the second intrinsic silicon carbide film decreases sequentially from the front side of the silicon substrate outwards.

32. The selective contact area buried solar cell as described in claim 26, characterized in that, The outer layer of the third dielectric layer is also provided with a magnesium fluoride layer.

33. The selective contact area buried solar cell as described in claim 26, characterized in that, An electric field layer or floating junction is also provided between the front side of the silicon substrate and the third dielectric layer.

34. A battery assembly, characterized in that, The battery assembly includes a selective contact area buried solar cell as described in any one of claims 26-33.

35. A photovoltaic system, characterized in that, The photovoltaic system includes the battery module as described in claim 34.

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