Light-emitting pixel particle, display panel, electronic equipment and preparation method of light-emitting pixel particle

Abstract

The invention provides a light-emitting pixel particle, a display panel, electronic equipment and a preparation method of the light-emitting pixel particle. The light-emitting pixel particle comprises a substrate, a light-emitting diode chip, a thin film transistor, a first type of conductive holes, a second type of conductive holes and a first metal interconnection layer. The thin film transistor is arranged on the side, away from the substrate, of the light-emitting diode chip. The light emitting diode chip comprises a first electrode; the thin film transistor includes a first thin film transistor including a first pole. The length of the first type of conductive holes in the first direction is larger than that of the second type of conductive holes in the first direction, and the first direction is perpendicular to the substrate. The first electrode is electrically connected with the first metal interconnection layer through a first conductive hole, the first electrode is electrically connected with the first metal interconnection layer through a second conductive hole, the first conductive hole is a first type of conductive hole, and the second conductive hole is a second type of conductive hole. The electric connection in the light-emitting pixel particles has good precision degree and high reliability, and the miniaturization degree of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of electronic device technology, and in particular to a light-emitting pixel, a display panel, an electronic device, and a method for preparing the light-emitting pixel. Background Technology

[0002] With the development of light-emitting diode (LED) chips, they are gradually becoming smaller. Currently, LED chips include mini-LEDs and micro-LEDs. Mini-LEDs typically refer to chips with a size between 50μm and 300μm, while micro-LEDs typically refer to chips with a size less than 50μm.

[0003] In LED chip display or lighting systems, LED chips require connection to driving devices to control their operation. For example, in one technical solution, the driving device is a thin-film transistor (TFT). Specifically, the TFT can independently control the switching and grayscale of each LED chip; this driving mode is active matrix (AM). This active matrix driving mode can meet complex display design requirements such as large size and a large number of pixels. In one technical solution, the active matrix driving mode display panel includes two substrates. One substrate contains TFT devices and / or other active driving devices to form a driving substrate, while the other substrate contains LED chip devices to form a display substrate. The driving substrate and the display substrate are then bonded together by transfer bonding, i.e., the LED chips and TFTs are connected by bonding to form a display module. In another technical solution, the active matrix driving mode display panel includes a driving substrate. LED chips are then transferred to the driving substrate, and the LED chips are bonded to the TFTs.

[0004] In the process of bonding the driving substrate and the display substrate, bonding is inevitably required to connect the light-emitting diode chip and the thin-film transistor. This results in a large number of bonding points in the display panel, leading to lower connection reliability. Furthermore, the fabrication process is complex, requiring more equipment and resulting in higher costs. Summary of the Invention

[0005] This application provides a light-emitting pixel, a display panel, an electronic device, and a method for manufacturing the light-emitting pixel. The internal electrical connection performance of the light-emitting pixel is relatively precise and reliable, and the area occupied by the light-emitting pixel on the display panel is also small, which is beneficial to improving the integration of the display panel.

[0006] In a first aspect, this application provides a light-emitting pixel. The light-emitting pixel includes a substrate, a light-emitting diode (LED) chip, a thin-film transistor (TFT), multiple conductive vias, and a first metal interconnect layer. The LED chip is disposed on the substrate, and the TFT is disposed on the side of the LED chip facing away from the substrate. The TFT and the LED chip are stacked in a direction away from the substrate. A buffer layer is disposed between the LED chip and the TFT to isolate them. The LED chip includes a first electrode and a second electrode; the TFT includes a first TFT, which includes a first electrode, which can be a source or a drain. The conductive vias include a first type of conductive via and a second type of conductive via. The length of the first type of conductive via along a first direction is greater than the length of the second type of conductive via along the first direction, and the first direction is perpendicular to the substrate. The depth of the first type of conductive via is greater than the depth of the second type of conductive via. The first metal interconnect layer is located on the side of the first TFT facing away from the LED chip. This eliminates the need to fabricate the first metal interconnect layer before fabricating the TFT, thereby improving the quality of the TFT, enhancing the reliability of the electrical connection structure within the light-emitting pixel, and increasing product yield. The first electrode is electrically connected to the first metal interconnect layer through a first conductive via, and the first pole is electrically connected to the first metal interconnect layer through a second conductive via, thus electrically connecting the first pole to the first electrode. The first conductive via is a type 1 conductive via, and the second conductive via is a type 2 conductive via. The light-emitting diode chip and the thin-film transistor are electrically connected through conductive vias and the metal interconnect layer, exhibiting good precision and high reliability, which is beneficial for improving the miniaturization and connection reliability of the display panel. Furthermore, since no additional connection points are required, the area occupied by the light-emitting pixels on the display panel is also smaller, which is beneficial for improving the integration of the display panel.

[0007] The first conductive hole described above is a first type of conductive hole, and the second conductive hole is a second type of conductive hole. The connection between the thin-film transistor and the light-emitting diode chip is achieved through two structures at different distances along a first direction, connected by first and second conductive holes of different depths. Since both the first and second conductive holes extend in a straight line, their orthogonal projections onto the substrate occupy a relatively small area, which is beneficial for improving the integration density of the light-emitting pixels.

[0008] The conductive holes in the light-emitting pixels of this application include a metal structure and a hole structure. The metal structure is located inside the hole structure to form the conductive holes. The metal structure of the first type of conductive holes is an integrally formed structure, which is beneficial to improving the strength and electrical connection effect of the metal structure inside the first type of conductive holes.

[0009] In the specific technical solution, the aforementioned first type of conductive via includes a first conductive via portion and a second conductive via portion, which are arranged along the direction toward the substrate, with the first conductive via portion above the second conductive via portion. The first conductive via portion includes a first end facing away from the substrate, and the orthographic projection of the second conductive via portion onto the substrate is completely within the orthographic projection of the first end onto the substrate. The metal structure within the first and second conductive via portions is relatively continuous, improving the electrical connection reliability of the first conductive via. Furthermore, it is advantageous to simultaneously fabricate the metal structure within the first and second conductive via portions using a single process.

[0010] In the first type of conductive hole described above, the inner diameters of the first and second conductive hole portions increase sequentially away from the substrate, and the inner diameters of the second type of conductive hole also increase sequentially away from the substrate. The inner walls of the conductive holes are sloped to facilitate metal adhesion and improve structural stability.

[0011] The first and second conductive hole portions of the aforementioned first type of conductive hole form a stepped shape. Specifically, the diameter D1 of the end of the first conductive hole portion facing the second conductive hole portion and the diameter D2 of the second conductive hole portion facing the first conductive hole portion satisfy: D1 > D2. The diameter of the bottom end of the first conductive hole portion is larger than the diameter of the top end of the second conductive hole portion, thus forming a step between the first and second conductive hole portions. This facilitates the attachment of the metal structure within the second conductive hole portion, improving the reliability of the first type of conductive hole. Furthermore, during the fabrication of the first type of conductive hole, it is advantageous to fabricate the hole structure of the second conductive hole portion on the bottom wall of the hole structure of the first conductive hole portion, resulting in a more continuous metal structure on the inner wall of the first conductive hole portion.

[0012] In one technical solution, the length of the second conductive hole portion along the first direction is the same as the length of the second type of conductive hole along the first direction. This facilitates the fabrication of the second conductive hole portion and the second type of conductive hole in a single process, thereby simplifying the fabrication process of the light-emitting pixel.

[0013] Specifically, the end of the conductive via facing the substrate is connected to a conductive structure, which includes a groove. At least part of the metal structure within the conductive via is located within the groove. The large contact area between the metal structure within the conductive via and the connected conductive structure improves the reliability of the connection between them, thereby enhancing signal transmission performance.

[0014] To control the light-emitting pixels, each pixel may further include a first power connector, which can be connected to a power line. The second electrode and the first power connector are electrically connected via a third conductive hole, which is a type of conductive hole. This connects the LED chip to the power line, thereby connecting the light-emitting pixels to the power line.

[0015] Similarly, the light-emitting pixel may also include a second power connection piece, which can be connected to another power line. The first thin-film transistor also includes a second electrode, which can be either a source or a drain. For example, the first electrode is the source and the second electrode is the drain; or, the first electrode is the drain and the second electrode is the source. The second electrode of the first thin-film transistor and the second power connection piece are electrically connected through a fourth conductive via, which is a type of second conductive via. This enables the connection of the first thin-film transistor to another power line, thereby enabling the connection of the light-emitting pixel to the other power line.

[0016] In this application's technical solution, the light-emitting pixel may include at least two thin-film transistors (TFTs). Besides a first TFT, the TFT also includes a second TFT, which has a third electrode, either as a source or a drain. The first TFT further includes a first active region and a first gate. The first and second electrodes are located in the first active region, and the first gate is located on the side of the first active region facing away from the substrate. The third electrode and the first gate are electrically connected through a fifth conductive via, which is a type of second conductive via. In this embodiment, the two TFTs are a switching transistor and a driving transistor, respectively, to improve the stability of the light-emitting pixel.

[0017] In the technical solution of this application, the orthographic projection of the thin-film transistor on the substrate and the orthographic projection of the light-emitting diode chip on the substrate at least partially overlap. This is beneficial for reducing the area occupied by the light-emitting pixels on the substrate of the display panel, improving the miniaturization of the light-emitting pixels, and increasing the integration of the display panel.

[0018] Furthermore, the orthographic projection of the thin-film transistors onto the substrate lies entirely within the orthographic projection of the light-emitting diode (LED) chip onto the substrate. Since all thin-film transistors are positioned above the LED chip, there is no need to fabricate thin-film transistors outside the area of ​​the LED chip on the substrate. This reduces the area occupied by the orthographic projection of the light-emitting pixels on the substrate, thus improving the integration density of the light-emitting pixels and the overall integration density of the display panel with these light-emitting pixels.

[0019] The above-mentioned thin-film transistor's orthogonal projection onto the substrate can be understood as the total orthogonal projection of the source, drain, and gate onto the substrate.

[0020] The orthographic projection of the first conductive hole onto the substrate lies entirely within the orthographic projection of the LED chip onto the substrate, and the orthographic projection of the second conductive hole onto the substrate also lies entirely within the orthographic projection of the LED chip onto the substrate. The conductive holes that interconnect the LED chip and the thin-film transistor do not occupy additional area, which is beneficial for improving the integration density of the light-emitting pixels and thus the integration density of the display panel with the aforementioned light-emitting pixels.

[0021] In one technical solution, the first electrode of the aforementioned light-emitting diode (LED) chip is the anode. This facilitates the connection between the LED chip and the thin-film transistor (TFT), simplifies the setup of the interconnect structure between the LED chip and the TFT, reduces the size of the light-emitting pixel, and improves the integration density of the light-emitting pixel.

[0022] To protect the LED chip, a buffer layer is placed between the LED chip and the thin-film transistor, covering the top and peripheral surfaces of the LED chip. This protects the LED chip from both the top and sides, extending its lifespan.

[0023] Furthermore, the aforementioned light-emitting pixel also includes a first dielectric layer and a second dielectric layer. The first and second dielectric layers are arranged in a direction away from the substrate. The first thin-film transistor includes a first active region and a first gate, with the first active region located in the first dielectric layer and the first gate located in the second dielectric layer. The first dielectric layer includes a first groove, within which at least a portion of the structure of the light-emitting diode chip is located. The second dielectric layer includes a second groove, within which at least a portion of the structure of the light-emitting diode chip is located. In addition to being located on top of the light-emitting diode chip, the first and second dielectric layers used to fabricate the thin-film transistor may also be located at least in a portion of the peripheral region of the light-emitting diode chip. This protects the light-emitting diode chip and improves the structural reliability of the light-emitting pixel.

[0024] Secondly, this application also provides a display panel. The display panel includes a substrate and a plurality of light-emitting pixels of any of the types described in the first aspect, with the plurality of light-emitting pixels arranged on the substrate. The substrate serves as a carrier for the light-emitting pixels, used to support and fix the light-emitting pixels. In fabricating this display panel, individual light-emitting pixels are first fabricated, and then each individual light-emitting pixel is fixed to the substrate according to a certain rule to form the display panel. This approach facilitates the arrangement of light-emitting pixels according to requirements, and there are no restrictions on the arrangement of the light-emitting pixels during fabrication. The light-emitting pixels in this approach occupy a smaller area in the display panel, resulting in a higher integration density of the display panel.

[0025] Thirdly, this application also provides a display panel. The display panel includes a plurality of light-emitting pixels of any of the types provided in the first aspect, and the substrates of the plurality of light-emitting pixels are of a single integrated structure. In this solution, the display panel is directly fabricated on the single integrated substrate while the light-emitting pixels are being fabricated. The display panel exhibits good integrity and eliminates the need for peeling and transferring of the light-emitting pixels, thus simplifying the fabrication process. The light-emitting pixels in this solution occupy a smaller area on the display panel, resulting in a higher integration density.

[0026] Fourthly, this application also provides an electronic device. The electronic device includes a housing and a display panel as described in the second or third aspect above, the display panel being mounted on the housing. In this solution, the light-emitting pixels occupy a smaller area on the display panel, resulting in a higher integration density of the display panel, thereby improving the performance of the electronic device.

[0027] Fifthly, this application also provides a method for fabricating light-emitting pixel particles. The method includes: fabricating a light-emitting diode (LED) chip on a substrate surface, the LED chip including a first electrode and a second electrode; fabricating a buffer layer on the surface of the LED chip; fabricating a thin-film transistor (TFT) on the surface of the buffer layer, the TFT including a first TFT and a first electrode; fabricating conductive vias, the conductive vias including a first conductive via and a second conductive via, the first conductive via being electrically connected to the first electrode, and the second conductive via being electrically connected to the first electrode; and fabricating a metal interconnect layer connecting the first conductive via and the second conductive via. The light-emitting pixel particles fabricated using this method have more precise and reliable internal electrical connections, and the light-emitting pixel particles occupy a smaller area on the display panel, which is beneficial for improving the integration of the display panel.

[0028] In the specific technical solution, the above-mentioned preparation of conductive holes includes: preparing a first hole portion; preparing a second hole portion and a second type of hole, preparing the second hole portion at the bottom of the first hole portion, and connecting the first hole portion and the second hole portion to form a first type of hole; preparing a metal structure within the first type of hole and the second type of hole to form a first type of conductive hole and a second type of conductive hole, wherein the first conductive hole is a first type of conductive hole and the second conductive hole is a second type of conductive hole. This technical solution can prepare a metal structure within first type of holes and second type of holes of different depths to form conductive holes in a single process. This simplifies the preparation process of conductive holes and simplifies the preparation process of light-emitting pixel particles.

[0029] In one technical solution, the above-mentioned preparation of the conductive hole further includes: the diameter D1' of the end of the first hole facing the second hole and the diameter D2' of the second hole facing the first hole satisfying: D1' > D2'. The diameter of the bottom end of the first hole is larger than the diameter of the top end of the second hole, forming a step between the first and second holes. When fabricating a metal structure within the first type of hole, the step can support the metal structure, thereby facilitating the attachment of the metal structure to the second hole and improving the reliability of the first type of conductive hole. Furthermore, during the fabrication process, the larger bottom wall area of ​​the first hole facilitates the fabrication of the hole structure of the second hole on the bottom wall of the first hole, making it less likely to damage the sidewalls of the first hole, resulting in a more continuous metal structure on the inner wall of the first conductive hole.

[0030] The above-mentioned preparation of the second hole and the second type of hole specifically includes: the second hole and the second type of hole extending to the conductive structure, such that the conductive structure includes a groove. In addition to being attached to the inner wall of the conductive hole, the metal structure is also attached to the groove of the conductive structure. The large contact area between the metal structure within the conductive hole and the connected conductive structure is beneficial for improving the reliability of the connection between the metal structure within the conductive hole and the conductive structure, thereby improving signal transmission performance. Attached Figure Description

[0031] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0032] Figure 2 This is a partial structural diagram of a display panel provided in an embodiment of this application;

[0033] Figure 3 A schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of a display panel structure in one embodiment of this application;

[0035] Figure 5 This is a schematic diagram of a display panel structure in one embodiment of this application;

[0036] Figure 6 This is a schematic diagram of a display panel structure in one embodiment of this application;

[0037] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0038] Figure 8 This is a schematic diagram of the structure of a light-emitting pixel in an embodiment of this application;

[0039] Figure 9 This is a schematic diagram of one structure of the light-emitting pixel in the comparative example;

[0040] Figure 10 This is a schematic diagram of the structure of a light-emitting pixel in an embodiment of this application;

[0041] Figure 11 This is a schematic diagram of the structure of a light-emitting pixel in an embodiment of this application;

[0042] Figure 12 This is a schematic diagram of the structure of a light-emitting pixel in an embodiment of this application;

[0043] Figure 13 This is a schematic diagram of the structure of a light-emitting pixel in an embodiment of this application;

[0044] Figure 14 This is a schematic diagram of the structure of a light-emitting pixel in an embodiment of this application;

[0045] Figure 15 This is a schematic diagram of a fabrication process for light-emitting pixel particles in an embodiment of this application;

[0046] Figure 16 This is a schematic diagram of a fabrication process for light-emitting pixel particles in an embodiment of this application.

[0047] Figure label:

[0048] 1-Display panel; 11-Substrate;

[0049] 12 - Light-emitting pixel; 121 - Substrate;

[0050] 122 - Light-emitting diode chip; 1221 - First electrode;

[0051] 1222 - Second electrode; 1223 - First active layer;

[0052] 1224 - First semiconductor doped layer; 1225 - Second semiconductor doped layer;

[0053] 123 - Thin-film transistor; 123a - First thin-film transistor;

[0054] 1231 - First pole; 1232 - Second pole;

[0055] 1233 - First gate; 1234 - First active region;

[0056] 123b - Second thin-film transistor; 1235 - Third electrode;

[0057] 1236 - Fourth electrode; 1237 - Second gate electrode;

[0058] 124 - Conductive hole; 1241 - First conductive hole;

[0059] 1242 - Second conductive hole; 1243 - First conductive hole portion;

[0060] 1244 - Second conductive hole; 1245 - Third conductive hole;

[0061] 1246 - Fourth conductive hole; 1247 - Fifth conductive hole;

[0062] 1248 - Sixth conductive hole; 1249 - First pit;

[0063] 125 - Metal interconnect layer; 1251 - First metal interconnect layer;

[0064] 1252 - Second metal interconnect layer; 1253 - Third metal interconnect layer;

[0065] 1254 - Second pit; 126 - Buffer layer;

[0066] 127 - Other interconnect layers; 128 - Contaminated area;

[0067] 13-First dielectric layer; 14-Second dielectric layer;

[0068] 15 - Groove; 16 - Flat layer;

[0069] 17-First power connector; 18-Second power connector;

[0070] 19 - Data cable; 2 - Housing;

[0071] 110 - Gate drive circuit; 200 - Timing controller;

[0072] 300 - System controller; 400 - Source driver chip;

[0073] X - First direction. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0075] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise.

[0076] References to “an embodiment” or “a specific embodiment” as used in this specification mean that one or more embodiments of this application include a particular feature, structure, or characteristic described in connection with that embodiment. The terms “comprising,” “including,” “having,” and variations thereof mean “including, but not limited to,” unless otherwise specifically emphasized.

[0077] The terms "coaxial," "coincident," and "identical" (e.g., identical length, identical depth, etc.) mentioned in the embodiments of this application are all relative to the current technological level, rather than absolute and strict mathematical definitions. For example, there may be certain deviations between two coaxial parts and between two parts with the same dimensions. For instance, the descriptions in this application such as "the hole axis of the first conductive hole coincides with the hole axis of the second conductive hole" and "the first conductive hole and the second conductive hole are coaxial" refer to the fact that the first and second conductive holes are coaxially arranged during the design. However, during the actual manufacturing process, due to the influence of manufacturing tolerances, there may be a certain deviation between the hole axis of the first conductive hole and the hole axis of the second conductive hole. For example, the deviation could be 10% of the diameter of the first conductive hole. As another example, the statement that the length of the second conductive hole along the first direction is the same as the length of the second type of conductive hole along the first direction mainly means that the first and second conductive holes can be completed in the same step during hole preparation. Depending on the actual technological level, the deviation between the length of the second conductive hole along the first direction and the length of the second type of conductive hole along the first direction can actually be 10% of the length of the second type of conductive hole along the first direction.

[0078] To facilitate understanding of the light-emitting pixel, display panel, electronic device, and method for preparing the light-emitting pixel provided in the embodiments of this application, the application scenarios are introduced below.

[0079] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. (Reference) Figure 1 As shown, the electronic device provided in this application can be a terminal device with a display screen. Specifically, the terminal device can be a mobile phone, monitor, television, head-up display (HUD) system, personal computer, computer, etc. The electronic device can also be a wearable device with a display screen. Specifically, the wearable device can be a watch, wristband, or near-eye display (NED) device, such as virtual reality (VR) glasses, VR headsets, or augmented reality (AR) glasses, AR headsets, etc. Users can wear NED devices to play games, read, watch movies (or TV series), participate in virtual meetings, participate in video education, or video shopping, etc.

[0080] Specifically, the aforementioned electronic device may include a display panel 1 and a housing 2. The display panel 1 is used to display images, and the housing 2 is used to support the display panel 1. For example, when the electronic device is AR glasses or VR glasses, the housing 2 may be temples and a frame, wherein the frame may be connected between two temples, and the display panel 1 is fixed to the frame. As another example, when the head-mounted display device is an AR helmet or VR helmet, the housing 2 may be a helmet shell. When the electronic device is a mobile phone, the housing 2 may be the phone's outer casing, and the housing 2 may include a mid-frame and a back cover, wherein the back cover may be fixed to one side of the mid-frame, and the display panel 1 is fixed to the other side of the mid-frame opposite the back cover.

[0081] In addition, the image displayed on the display panel 1 can be an image projected onto the display panel 1 by a terminal device (such as a mobile phone, tablet computer, etc.), or it can be an image formed by the display panel 1.

[0082] There are various choices for the material of the housing 2 of the above-mentioned electronic device. For example, the housing 2 can be a housing 2 made of metal or a housing 2 made of plastic, etc. This application does not limit this.

[0083] Figure 2 This is a partial structural diagram of a display panel provided in an embodiment of this application, such as... Figure 2 As shown in the embodiment of this application, the display panel 1 may include a substrate 11 and N light-emitting pixels 12. The N light-emitting pixels 12 are disposed on the substrate 11. Specifically, the N light-emitting pixels 12 are arranged in an array, and each light-emitting pixel 12 can function as an independent light-emitting device, emitting light of different colors such as red (R), green (G), and blue (B), enabling the display module to achieve image display functionality. For example, the N light-emitting pixels 12 can be arranged in H rows × K columns, where N equals H multiplied by K, and both H and K are positive integers. This arrangement allows the display panel 1 of the same area to accommodate as many light-emitting pixels 12 as possible, thereby helping to improve the maximum resolution of the display panel 1. Furthermore, the cross-sectional shape of the light-emitting pixels 12 is not limited, for example... Figure 2 The image shows the case where the cross-section of the light-emitting pixel 12 is rectangular.

[0084] Figure 3 This is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application, referred to... Figure 3 As shown, in this embodiment, the cross-sectional shape of the light-emitting pixel 12 can also be designed as circular. Of course, in this embodiment, the cross-sectional shape of the light-emitting pixel 12 is not limited to [specific shape]. Figure 2 or Figure 3The shapes shown can also be triangles, rhombuses, ellipses, or other regular or irregular shapes, and can be designed according to the specific type of electronic device. This application does not impose any restrictions on this.

[0085] Figure 4 This is a schematic diagram of a display panel structure in an embodiment of this application, such as... Figure 4 As shown, in one embodiment, the display panel 1 provided in this application includes a substrate 11 and a plurality of light-emitting pixels 12, with the plurality of light-emitting pixels 12 arranged on the substrate 11. The substrate 11 serves as a carrier for the light-emitting pixels 12, used to support and fix the light-emitting pixels 12. In one embodiment, when preparing the display panel 1, individual light-emitting pixels 12 are first prepared, and then each individual light-emitting pixel 12 is fixed to the substrate 11 according to a certain rule to form the display panel 1. This embodiment facilitates the arrangement of the light-emitting pixels 12 according to requirements, and there are no restrictions on the arrangement of the light-emitting pixels 12 during preparation.

[0086] Figure 5 This is a schematic diagram of a display panel structure in an embodiment of this application, such as... Figure 5 As shown, in one embodiment, the light-emitting pixel 12 provided in this application includes a substrate 121, and a light-emitting diode chip 122 (LED) and a thin-film transistor 123 (TFT) located on the substrate 121. The LED chip 122 and the TFT 123 are arranged sequentially in a direction away from the substrate 121. The display panel 1 provided in this application includes a plurality of light-emitting pixels 12, and the substrate 121 of the plurality of light-emitting pixels 12 is an integral structure. In this embodiment, the display panel 1 is directly formed on the integral substrate 121 while the light-emitting pixel 12 is being prepared. In this embodiment, the display panel 1 has good integrity and does not require the peeling and transfer of the light-emitting pixel 12, which helps to simplify the preparation process of the display panel 1. In this embodiment, the integral substrate 121 can be used as the substrate 11 of the display panel 1.

[0087] Figure 6 This is a schematic diagram of a display panel structure in an embodiment of this application, such as... Figure 6 As shown, in one embodiment, the light-emitting diode chip 122 includes a first electrode 1221 and a second electrode 1222. The second electrode 1222 of the light-emitting diode chip 122 of the plurality of light-emitting pixels 12 of the display panel 1 is an integral structure, thereby simplifying the fabrication process of the light-emitting diode chip 122. In one embodiment, the doped semiconductor layer connecting the light-emitting diode chip 122 of the plurality of light-emitting pixels 12 to the second electrode 1222 can also be an integral structure.

[0088] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. (Refer to...) Figure 7 The electronic device includes a display panel 1, a timing controller 200, a system controller 300, and a source driver chip 400. Exemplarily, the display panel 1 includes a display area AA and a non-display area BB. The display area AA includes a plurality of light-emitting pixels 12, each of which includes multiple light-emitting pixels of different colors (spx). For example, the light-emitting pixels 12 may include red, green, and blue light-emitting pixels, allowing for color mixing to achieve a color display. Alternatively, the light-emitting pixels 12 may also include red, green, blue, and white light-emitting pixels, allowing for color mixing to achieve a color display. Of course, in practical applications, the light-emitting colors of the light-emitting pixels 12 can be designed and determined according to the actual application environment, and are not limited here. Furthermore, the arrangement order and method of the various light-emitting pixels 12 are not limited in this application.

[0089] The display area AA also includes multiple gate lines GAa, GAb, GAc, and multiple data lines DA. Each row of luminous pixels 12 connects to one gate line GAa, one gate line GAb, and one gate line GAc, while each column of luminous pixels 12 connects to one data line. Alternatively, each row of luminous pixels 12 can connect to two gate lines GAa, two gate lines Gab, and two gate lines GAc, and each column of luminous pixels 12 can connect to two data lines. In practical applications, the number of gate lines GAa, Gab, and GAc connected to each row of luminous pixels 12, and the number of data lines connected to each column of luminous pixels 12, can be determined according to the needs of the specific application scenario and are not limited here. Figure 7 This is merely one possible embodiment.

[0090] The non-display area BB includes gate driving circuits 110a, 110b, and 110c. Gate driving circuit 110a is connected to multiple gate lines GAa, and sends a first gate scan signal to each gate line GAa. Gate driving circuit 110b is connected to multiple gate lines GAb, and sends a second gate scan signal to each gate line GAb. Gate driving circuit 110c is connected to multiple gate lines GAc, and sends a third gate scan signal to each gate line GAc. Additionally, the non-display area BB may also include other functional circuits, such as electrostatic discharge (ESD) circuits.

[0091] The source driver chip 400 is bonded to the non-display area BB via a chip-on-film (COF) thin film. Furthermore, the source driver chip is connected to the data line DA via the COF, inputting a data voltage to the data line DA. For example, multiple source driver chips 400 can be configured, with different source driver chips 400 connected to different data lines. Figure 7 This example uses two source driver chips (400) as an illustration. In practical applications, the number of source driver chips can be determined based on the resolution of the display panel 1 and the data output channels of the source driver chips. For example, for a display panel 1 with a resolution of 3840*2160, the number of data lines in the display panel 1 can be 3840*3. If one source driver chip has 1920 data output channels, then the display panel 1 needs to be equipped with 6 (i.e., 3840*3 / 1920) source driver chips.

[0092] The system controller 300 is connected to the timing controller 200, which in turn is connected to the gate drive circuits 110a-110c and the source drive chip 400. In operation, the system controller 300 acquires the grayscale information of the image to be displayed in each display frame (this grayscale information includes a digital signal carrying a corresponding grayscale value for each luminous pixel 12 in the display panel 1), processes the grayscale information, and then sends it to the timing controller 200. Upon receiving the grayscale information, the timing controller 200 sends control signals (such as frame trigger signals and clock control signals) to the gate drive circuits 110a-110c and processes the grayscale information before sending it to the source drive chip 400. The gate drive circuits 110a-110c input first to third gate scan signals to the gate lines GAa-110c according to the received control signals. The source driver chip 400 receives display grayscale information, converts the received grayscale information into an analog signal, and inputs the actual data voltage to the data line DA to write the data voltage into the light-emitting pixel 12, thereby enabling the display panel 1 to display an image. Additionally, the system controller 300 can be a field-programmable gate array (FPGA), a central processing unit (CPU), a general-purpose processor, a digital signal processing unit (DSP), an application-specific integrated circuit (ASIC), a system-on-chip (SOC), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The aforementioned system controller can also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0093] Figure 8 This is a schematic diagram of the structure of a light-emitting pixel in an embodiment of this application, such as... Figure 8As shown, in one embodiment, the light-emitting pixel 12 provided in this application includes a substrate 121, a light-emitting diode chip 122, a thin-film transistor 123, a plurality of conductive holes 124, and a metal interconnect layer 125. The light-emitting diode chip 122 is disposed on the substrate 121, and the thin-film transistor 123 is disposed on the side of the light-emitting diode chip 122 facing away from the substrate 121, that is, the thin-film transistor 123 and the light-emitting diode chip 122 are stacked in a direction away from the substrate 121. A buffer layer 126 is provided between the light-emitting diode chip 122 and the thin-film transistor 123 to isolate the light-emitting diode chip 122 from the thin-film transistor 123.

[0094] The aforementioned light-emitting diode chip 122 includes a first electrode 1221 and a second electrode 1222. The thin-film transistor 123 includes a first thin-film transistor 123a, which includes a first electrode 1231, a second electrode 1232, and a first gate 1233.

[0095] Specifically, the conductive holes 124 in the light-emitting pixel 12 provided in this application include a first type of conductive hole and a second type of conductive hole. The length of the first type of conductive hole along the first direction X is greater than the length of the second type of conductive hole along the first direction X. The first direction X is perpendicular to the plane where the substrate 121 is located. Specifically, the first direction X can also be understood as the thickness direction of the light-emitting pixel 12. In simpler terms, the depth of the first type of conductive hole is greater than the depth of the second type of conductive hole; the first type of conductive hole can be called a deep hole, and the second type of conductive hole can be called a shallow hole.

[0096] The metal interconnect layer 125 includes a first metal interconnect layer 1251, which is located on the side of the first electrode 1231 facing away from the substrate 121. The first electrode 1221 is electrically connected to the first metal interconnect layer 1251 through a first conductive via 1241, and the first electrode 1231 is electrically connected to the first metal interconnect layer 1251 through a second conductive via 1242, thus electrically connecting the first electrode 1231 to the first electrode 1221. Specifically, one end of the first conductive via 1241 is connected to the first metal interconnect layer 1251, and the other end is connected to the first electrode 1221. One end of the second conductive via 1242 is connected to the first metal interconnect layer 1251, and the other end is connected to the first electrode 1231. In this embodiment, the light-emitting diode chip 122 and the thin-film transistor 123 are electrically connected through the conductive via 124 and the metal interconnect layer 125, which has good precision and high reliability, and is beneficial to improving the miniaturization and connection reliability of the display panel 1. Furthermore, since no additional connection points are required, the area occupied by the light-emitting pixel 12 on the display panel 1 is also smaller, which is beneficial to improving the integration of the display panel 1.

[0097] In this embodiment, the first conductive hole 1241 is a first type of conductive hole, and the second conductive hole 1242 is a second type of conductive hole. In this embodiment, the connection between the thin-film transistor 123 and the light-emitting diode chip 122 is achieved through the conductive hole 124, and two structures with different distances along the first direction X are connected through the first conductive hole 1241 and the second conductive hole 1242 with different depths.

[0098] In this embodiment, the metal interconnect layer 125 is located on the side of the first thin film transistor 123a away from the light-emitting diode chip 122, and the first metal interconnect layer 1251 and the first electrode 1221 are directly electrically connected through the first conductive hole 1241. One end of the first conductive hole 1241 is connected to the first metal interconnect layer 1251, and the other end is connected to the first electrode 1221. Therefore, it is not necessary to prepare other interconnect layers between the first metal interconnect layer 1251 and the first electrode 1221. Figure 9 This is a schematic diagram of the structure of a light-emitting pixel in the comparative example, such as... Figure 9 As shown in one comparative example, two conductive vias and other interconnect layers 127 are further provided between the first electrode 1221 and the first metal interconnect layer 1251. These other interconnect layers 127 connect the two metal interconnect layers. The other interconnect layers 127 are on the same layer as the active region of the thin-film transistor 123, or the other interconnect layers 127 are located between the active region of the thin-film transistor and the first electrode 1221. In the comparative example, after laser crystallization of the semiconductor layer of the thin-film transistor 123, an active region is formed. During the laser crystallization process, the high temperature generated by the laser may damage the metal structures such as the other interconnect layers 127, causing the metal to volatilize into metal particles. These metal particles may contaminate the active region of the thin-film transistor, forming a contaminated region 128, affecting the quality of the thin-film transistor. Furthermore, they may damage the metal structures such as the other interconnect layers 127, reducing the reliability of the electrical connection structure within the light-emitting pixel and potentially causing it to fail, thus reducing product yield. In this application, the aforementioned other interconnect layers 127 are not required, thereby improving the quality of the thin-film transistor and the reliability of the electrical connection structure within the light-emitting pixel, thus improving product yield.

[0099] In this application, the semiconductor process of the light-emitting pixel can be completed first, followed by the metallization process, thereby improving the quality of the light-emitting pixel and the product yield.

[0100] The first conductive hole 1241 has a hole axis, meaning it extends along a first direction X, and is a conductive hole 124 extending in a straight line. The second conductive hole 1242 has a hole axis, meaning it extends along the first direction X, and is also a conductive hole 124 extending in a straight line. Therefore, the areas occupied by the orthogonal projections of the first conductive hole 1241 and the second conductive hole 1242 onto the substrate 121 are both relatively small, which is beneficial for improving the integration density of the light-emitting pixel 12.

[0101] In one embodiment, the orthographic projection of the first conductive hole 1241 onto the substrate 121 is entirely within the orthographic projection of the light-emitting diode chip 122 onto the substrate 121, and the orthographic projection of the second conductive hole 1242 onto the substrate 121 is also entirely within the orthographic projection of the light-emitting diode chip 122 onto the substrate 121. In this embodiment, the conductive hole 124 that interconnects the light-emitting diode chip 122 and the thin-film transistor 123 does not occupy additional area, which is beneficial to improving the integration density of the light-emitting pixels and thus the integration density of the display panel with the aforementioned light-emitting pixels.

[0102] In this application, the conductive hole 124 includes a hole structure and a metal structure. The metal structure is located within the hole structure. The hole structure supports the metal structure, and the metal structure transmits electrical signals, enabling the conductive hole to conduct electricity. In optional embodiments, the metal structure can be a metal layer attached to the inner wall, i.e., the bottom, of the hole structure; or, the metal structure can be a metal pillar filling the hole structure; or, the metal structure can be located within the hole structure, with a recess in the upper region. In short, the metal structure within the hole structure can have various optional forms, and this application does not limit these, as long as the electrical connection between the conductive structures at both ends of the conductive hole can be achieved.

[0103] For the first type of conductive hole, although the depth of the first type of conductive hole is relatively large, the metal structure inside the first type of conductive hole is a one-piece molded structure, which is beneficial to improving the strength and electrical connection effect of the metal structure inside the first type of conductive hole.

[0104] The aforementioned first type of conductive via includes a first conductive via portion 1243 and a second conductive via portion 1244. The first conductive via portion 1243 and the second conductive via portion 1244 are arranged along a direction toward the substrate 121, with the second conductive via portion 1244 closer to the substrate 121 than the first conductive via portion 1243. With the direction of the substrate 121 as downward, the first conductive via portion 1243 is above the second conductive via portion 1244. Of the two ends of the first conductive via portion 1243 along the first direction X, the end facing away from the substrate 121 is the first end, and the end facing the substrate 121 is the second end. The orthographic projection of the second conductive via portion 1244 onto the substrate 121 lies entirely within the orthographic projection of the first end onto the substrate 121. This design makes the metal structure within the first conductive via portion 1243 and the second conductive via portion 1244 more continuous, improving the electrical connection reliability of the first type of conductive via. Furthermore, it facilitates the simultaneous fabrication of the metal structure within the first conductive via portion 1243 and the second type of conductive via in a single process.

[0105] In one embodiment, the orthographic projection of the second conductive hole portion 1244 onto the substrate 121 lies entirely within the orthographic projection of the second end onto the substrate 121. This design further enhances the continuity of the metal structures within the first conductive hole portion 1243 and the second conductive hole portion 1244, improving the electrical connection reliability of the first type of conductive hole. It also facilitates the simultaneous fabrication of metal structures within the first conductive hole portion 1243 and the second type of conductive hole using a single process.

[0106] Provided the process meets the requirements, the hole axis of the first conductive hole portion 1243 and the hole axis of the second conductive hole portion 1244 coincide. Specifically, the first conductive hole portion 1243 and the second conductive hole portion 1244 are coaxially arranged, and the hole axis of the first conductive hole portion 1243, the hole axis of the second conductive hole portion 1244, and the hole axis of the corresponding first type of conductive hole are coaxial.

[0107] In this embodiment, the hole structure of the first conductive hole portion 1243 can be prepared first, followed by the hole structure of the second conductive hole portion 1244 and the hole structure of the second type of conductive hole. Then, metal structures are simultaneously prepared within the hole structures of the first and second types of conductive holes to form conductive holes of both types. The fabrication process of the light-emitting pixel 12 in this scheme is also relatively simple, which helps to reduce the fabrication cost of the light-emitting pixel 12.

[0108] In this embodiment, the second conductive hole 1242 connected to the first electrode 1231 is located on the side of the first electrode 1231 away from the substrate 121. It will not affect the preparation of the first active layer 1223 where the first electrode 1231 is located, and will not damage the first active layer 1223. This is beneficial to improving the yield of the light-emitting pixel 12.

[0109] In one specific embodiment, the first metal interconnect layer and the first electrode are electrically connected only through a first conductive via, without requiring any other additional structures. This simplifies the electrical connection structure between the first metal interconnect layer and the first electrode, improving the product yield and reliability of the light-emitting pixel.

[0110] Specifically, in the aforementioned first type of conductive hole, the inner diameters of the first conductive hole portion 1243 and the second conductive hole portion 1244 increase sequentially in the direction away from the substrate 121. Therefore, viewed in cross-section, the first conductive hole portion 1243 and the second conductive hole portion 1244 are trapezoidal sections. Similarly, the inner diameters of the aforementioned second type of conductive holes increase sequentially in the direction away from the substrate 121. Therefore, viewed in cross-section, the second type of conductive holes are trapezoidal sections. In this embodiment, the inner walls of the first type of conductive holes and the second type of conductive holes each form a certain slope, which facilitates metal adhesion to the inner walls of the first type of conductive holes and the second type of conductive holes, and helps to improve the structural stability of the first type of conductive holes and the second type of conductive holes.

[0111] It is understood that the thin-film transistor 123 mentioned in the embodiments of this application includes a source, a drain, and a gate. The first electrode 1231 of the first thin-film transistor 123a can be the source and the second electrode 1232 can be the drain; or, the first electrode 1231 can be the drain and the second electrode 1232 can be the source. The orthogonal projection of the thin-film transistor 123 onto the substrate 121 can be understood as the total orthogonal projection of the source, drain, and gate onto the substrate 121.

[0112] In one embodiment, the orthographic projection of the thin-film transistor 123 onto the substrate 121 and the orthographic projection of the light-emitting diode chip 122 onto the substrate 121 at least partially overlap, which helps to reduce the area occupied by the light-emitting pixel 12 on the substrate 11 of the display panel 1, and helps to improve the miniaturization of the light-emitting pixel 12 and improve the integration of the display panel 1.

[0113] Please continue to refer to this. Figure 8 In this embodiment, the orthographic projection of the thin-film transistor 123 onto the substrate 121 can be completely located within the orthographic projection of the light-emitting diode chip 122 onto the substrate 121. Specifically, the orthographic projection of the source of the thin-film transistor 123 onto the substrate 121 is completely located within the orthographic projection of the light-emitting diode chip 122 onto the substrate 121, the orthographic projection of the drain onto the substrate 121 is completely located within the orthographic projection of the light-emitting diode chip 122 onto the substrate 121, and the orthographic projection of the gate onto the substrate 121 is completely located within the orthographic projection of the light-emitting diode chip 122 onto the substrate 121. In some embodiments, the light-emitting pixel 12 includes at least two thin-film transistors 123, then the orthographic projection of each thin-film transistor 123 onto the substrate 121 is completely located within the orthographic projection of the light-emitting diode chip 122 onto the substrate 121. Specifically, the source of each thin-film transistor 123 is projected onto the substrate 121 in a manner that is entirely within the projection of the light-emitting diode chip 122 onto the substrate 121; the drain is projected onto the substrate 121 in a manner that is entirely within the projection of the light-emitting diode chip 122 onto the substrate 121; and the gate is projected onto the substrate 121 in a manner that is entirely within the projection of the light-emitting diode chip 122 onto the substrate 121. In this embodiment, the thin-film transistors 123 are all disposed above the light-emitting diode chip 122, eliminating the need to fabricate thin-film transistors 123 in areas other than the light-emitting diode chip 122 on the substrate 121. This reduces the area occupied by the projection of the light-emitting pixel 12 onto the substrate 121, thereby improving the integration density of the light-emitting pixel 12 and the overall integration density of the display panel 1 with the aforementioned light-emitting pixel 12.

[0114] Please continue to refer to this. Figure 8In this embodiment, the substrate 121 can be any one of sapphire substrate 121, single-crystal silicon substrate 121, silicon carbide substrate 121, aluminum nitride substrate 121, gallium nitride substrate 121, or quartz substrate 121. In one specific embodiment, the substrate 121 can be selected as sapphire substrate 121.

[0115] The light-emitting diode chip 122 disposed on the substrate 121 may include a first electrode 1221, a first semiconductor doped layer 1224, a first active layer 1223, a second semiconductor doped layer 1225, and a second electrode 1222. The specific types of the first electrode 1221 and the second electrode 1222 can be varied; for example, the first electrode 1221 may be a cathode and the second electrode 1222 anode, or the first electrode 1221 may be an anode and the second electrode 1222 a cathode.

[0116] Taking the first electrode 1221 as the anode and the second electrode 1222 as the cathode as an example.

[0117] The second semiconductor doped layer 1225 is an N-type semiconductor doped layer, that is, a second semiconductor doped layer 1225 doped with N-type material. The light-emitting diode chip 122 in this application may include one or more N-type semiconductor doped layers. The specific material selection for the aforementioned N-type semiconductor doped layer is varied; for example, it may be N-type doped gallium nitride (n-GaN), or it may be a composite layer of u-GaN and n-GaN, or a composite layer of aluminum nitride (AlN) and n-GaN. Specifically, the N-type semiconductor layer may be doped with silicon (Si), and the Si content is 0.5*10⁻⁶. 19 / cm 3 ~5*10 19 / cm 3 .

[0118] The first active layer 1223 is a multiple quantum well (MQW) layer, which may include a single-layer structure or a multi-layer structure. For example, the first active layer 1223 may be a series of overlapping gallium nitride (InGaN) and gallium nitride (GaN) layers, which may include a ten-layer structure. The InGaN mentioned above is In-doped GaN, and the In to Ga ratio is 0.05 to 0.95.

[0119] The aforementioned first semiconductor doped layer 1224 is a P-type semiconductor doped layer, that is, a first semiconductor doped layer 1224 doped with P-type material. The light-emitting diode chip 122 in this application may include one or more P-type semiconductor doped layers. The P-type semiconductor doped layer may be P-type doped GaN, and may further be doped with magnesium (Mg), with a Mg content of 0.2*10⁻⁶. 17 / cm3 ~8*10 17 / cm 3 .

[0120] The first electrode 1221 is the anode, and it is in contact with the P-type semiconductor doped layer. The first electrode 1221 can be a single-layer structure or a multi-layer structure, such as nickel (Ni) / silver (Ag) / titanium (Ti), Ni / Al / Ti, Ni / Pt / Au, ITO, or IZO, etc.

[0121] The buffer layer 126 is disposed on the light-emitting diode chip 122. The material of the buffer layer 126 can be a single layer of silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide, or it can be a multilayer film stack. In one embodiment, the buffer layer 126 can be a stack of aluminum oxide and silicon oxide, wherein the thickness of the aluminum oxide is 1 nm to 100 nm, and the thickness of the silicon oxide is 100 nm to 2000 nm. In a specific embodiment, the thickness of the aluminum oxide is 10 nm, the thickness of the silicon oxide is 1000 nm, and the silicon oxide is stacked on top of the aluminum oxide.

[0122] Specifically, the buffer layer 126 covers the top and peripheral surfaces of the LED chip 122. This protects the LED chip 122 from its top and side surfaces, thus extending its lifespan.

[0123] A thin-film transistor 123 is formed on the buffer layer 126. The thin-film transistor 123 includes an active region and a gate, with the source and drain on either side of the active region, respectively. The light-emitting pixel 12 in this application includes a first dielectric layer 13 and a second dielectric layer 14, which are arranged in a direction away from the substrate 121. The active region is located in the first dielectric layer 13, and the gate is located in the second dielectric layer 14. For example, the first thin-film transistor 123a includes a first active region 1234 and a first gate 1233, with the first active region 1234 located in the first dielectric layer 13 and the first gate 1233 located in the second dielectric layer 14.

[0124] The aforementioned active region is located above the buffer layer 126 and is used to form the active channel of the thin-film transistor 123. The material of the active region may include polycrystalline silicon, monocrystalline silicon, metal oxide semiconductor, two-dimensional sulfide semiconductor, or carbon-based semiconductor. For example, in a specific embodiment, the material of the active region is selected as low-temperature polycrystalline silicon.

[0125] The first dielectric layer 13 can also be referred to as a gate insulating layer, used to form a gate dielectric layer; the first dielectric layer 13 is located above the buffer layer 126, and the first dielectric layer 13 covers the active region, which can also be understood as the active region being located within the first dielectric layer 13. The material of the first dielectric layer 13 is an insulating layer material. In specific embodiments, the first dielectric layer 13 can be a single-layer structure or a multi-layer structure. For example, the first dielectric layer 13 can be a single-layer silicon nitride layer, silicon oxide layer, silicon oxynitride layer, or aluminum oxide layer, or the first dielectric layer 13 can also be a multi-layer structure of multilayer film stacking, specifically a stacked structure of at least two of the above-mentioned silicon nitride layer, silicon oxide layer, silicon oxynitride layer, or aluminum oxide layer; in this embodiment, the first dielectric layer 13 can be formed by the stacking of silicon oxide layer and silicon nitride layer, wherein the thickness of silicon oxide layer is 1nm to 200nm, and the thickness of silicon nitride layer is 1nm to 200nm. Specifically, the thickness of the silicon oxide layer can be 70nm, the thickness of the silicon nitride layer can be 20nm, and the silicon nitride layer can be stacked on top of the silicon oxide.

[0126] The gate electrode is disposed on the first dielectric layer 13 and is located between the source and drain. Specifically, the gate electrode can be a metallic material, such as Mo, Ti, or MoTi. In this embodiment, the gate electrode can be Ti.

[0127] The second dielectric layer 14 is located above the gate and is used to cover the gate. The material of the second dielectric layer 14 is an insulating layer material. In specific embodiments, the second dielectric layer 14 can be a single-layer structure or a multi-layer structure. For example, the second dielectric layer 14 can be a single-layer silicon nitride layer, silicon oxide layer, silicon oxynitride layer, or aluminum oxide layer. Alternatively, the second dielectric layer 14 can also be a multi-layer structure of multilayer film stacks, specifically a stacked structure of at least two of the aforementioned silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide layers. In this embodiment, the second dielectric layer 14 can be formed by stacking silicon oxide and silicon nitride layers, wherein the thickness of the silicon oxide layer is 1nm to 400nm, and the thickness of the silicon nitride layer is 1nm to 400nm. Specifically, the thickness of the silicon oxide layer can be 300nm, the thickness of the silicon nitride layer can be 300nm, and the silicon nitride is stacked on top of the silicon oxide.

[0128] The metal interconnect layer 125 is located above the second dielectric layer 14. Specifically, the metal interconnect layer 125 includes multiple structures for connection to the gate, source, and drain. For example, the metal interconnect layer 125 can be a metal material, specifically a multilayer metal stack structure, such as Mo / Al / Mo, Ti / Al / Ti, Mo / AlNb / Mo, Ti / AlNb / Ti, Mo / Cu / Mo, Ti / Cu / Ti, Ti / Cu / IZO, MoTi / Al / MoTi, MoTi / AlNb / MoTi, Ni / Al / Ti, or Cr / Al / Ti. In this embodiment, it can specifically be Ti / Al / Ti, Mo / Al / Mo, or Cr / Al / Ti.

[0129] A planarization layer 16 may be included above the second dielectric layer 14. This planarization layer 16 is located above the metal interconnect layer 125 and can be used for wiring. The planarization layer 16 can be an organic or inorganic material. Specifically, the organic material can be an organic insulating material such as acrylate, polyimide, or epoxy resin. The inorganic material can be silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or aluminum oxide. It can be a single-layer structure or a multi-layer stacked structure. The wiring material is Mo / Cu / Mo, Ti / Cu / Ti, Ti / Cu / IZO, Ti / Cu / ITO, Ni / Ag / Ti, Ni / Ag / ITO, Ni / Pt / Au, Mo / Al / Mo, or Ti / Al / Ti. In this embodiment, it can specifically be Ti / Al / Ti, Ni / Ag / ITO, or Ti / Cu / ITO.

[0130] In a specific embodiment, the first type of conductive hole penetrates the second dielectric layer 14, the first dielectric layer 13, and the buffer layer 126, while the second type of conductive hole penetrates the first dielectric layer 13 and the second dielectric layer 14.

[0131] Figure 10 This is a schematic diagram of one structure of the light-emitting pixel in an embodiment of this application. Please refer to it. Figure 10The first conductive hole portion 1243 and the second conductive hole portion 1244 of the aforementioned first type of conductive hole form a stepped shape. Specifically, the diameter D1 of the end of the first conductive hole portion 1243 facing the second conductive hole portion 1244 and the diameter D2 of the second conductive hole portion 1244 facing the first conductive hole portion 1243 satisfy: D1 > D2. That is, the diameter of the bottom end of the first conductive hole portion 1243 is larger than the diameter of the top end of the second conductive hole portion 1244, so that a step is formed between the first conductive hole portion 1243 and the second conductive hole portion 1244. When fabricating a metal structure in the first type of conductive hole, the aforementioned step can be used to support the metal structure, thereby facilitating the attachment of the metal structure to the second conductive hole portion 1244 and improving the reliability of the first type of conductive hole. Furthermore, during the fabrication of the first type of conductive hole, the hole structure of the first conductive hole portion 1243 can be fabricated first. The bottom wall area of ​​the hole structure of the first conductive hole portion 1243 is relatively large, which is beneficial for the subsequent fabrication of the hole structure of the second conductive hole portion 1244 on the bottom wall of the hole structure of the first conductive hole portion 1243. It is less likely to damage the side wall of the first conductive hole portion 1243, making the metal structure of the inner wall of the first conductive hole portion 1243 more continuous.

[0132] In one embodiment, the length of the second conductive hole portion 1244 along the first direction X is the same as the length of the second type of conductive hole along the first direction X. That is, the depth of the first conductive hole portion 1243 is the same as the depth of the second type of conductive hole. This facilitates the fabrication of the second conductive hole portion 1244 and the second type of conductive hole in a single process, thereby simplifying the fabrication process of the light-emitting pixel 12.

[0133] Figure 11 This is a schematic diagram of one structure of the light-emitting pixel in an embodiment of this application. Please refer to it. Figure 11 In the actual structure, because the metal structures within the first type of conductive hole and the second type of conductive hole are fabricated in a single process, and the depth of the first type of conductive hole is greater than the depth of the second type of conductive hole, the metal structure within the first type of conductive hole may contain a first pit 1249. For example... Figure 11 In the illustrated embodiment, during the fabrication of the metal interconnect layer 125, the structure of the metal interconnect layer 125 may at least partially fill the first recess of the first type of conductive via. Specifically, the depth of the first recess 1249 can be selected from various options. The depth of the first recess 1249 may be less than or equal to the depth of the first conductive via portion 1243; the depth of the first recess 1249 may also be greater than the depth of the first conductive via portion 1243, meaning the first recess extends into the first conductive via portion 1243. It is understood that the first recess 1249 is specifically filled with structures such as the metal interconnect layer 125, and is not a cavity.

[0134] Figure 12 This is a schematic diagram of one structure of the light-emitting pixel in an embodiment of this application. Please refer to it. Figure 12 In one embodiment, the metal structure within the conductive hole 124 and the metal interconnect layer 125 may be fabricated simultaneously, which may result in a second recess 1254 in the metal interconnect layer 125. It is understood that the first recess 1249 is specifically filled with structures such as the metal interconnect layer 125, and the second recess 1254 is also filled with structures such as insulating materials, and is not a cavity.

[0135] Figure 13 This is a schematic diagram of one structure of the light-emitting pixel in an embodiment of this application. Please refer to it. Figure 13 To improve the connection between the conductive hole 124 and the conductive structure, an over-etching process is typically performed during the fabrication of the conductive hole 124, forming a groove 15 in the conductive structure at the bottom of the conductive hole 124. When fabricating the metal structure within the conductive hole 124, the metal structure is attached not only to the inner wall of the conductive hole 124 but also to the groove 15 of the conductive structure. Specifically, from a product structure perspective, the end of the conductive hole 124 facing the substrate 121 is connected to the conductive structure, which includes the groove 15, and at least part of the metal structure within the conductive hole 124 is located within the groove 15. In this embodiment, the contact area between the metal structure within the conductive hole 124 and the connected conductive structure is relatively large, which is beneficial for improving the reliability of the connection between the metal structure within the conductive hole 124 and the conductive structure, thereby improving signal transmission performance.

[0136] Figure 14 This is a schematic diagram of the structure of a light-emitting pixel in an embodiment of this application, such as... Figure 14 As shown, to achieve control over the light-emitting pixel 12, the light-emitting pixel 12 in this embodiment further includes a first power connection piece 17 and a planarization layer 16. The first power connection piece 17 is located in the planarization layer 16 and can be a trace within the planarization layer 16. The second electrode 1222 of the aforementioned light-emitting diode chip 122 and the first power connection piece 17 are electrically connected through a third conductive hole 1245, which is a first type of conductive hole. In a specific embodiment, the aforementioned third conductive hole 1245 can serve as the second electrode 1222, that is, the third conductive hole 1245 is reused as the second electrode 1222.

[0137] In addition, please continue to refer to Figure 14The aforementioned light-emitting pixel 12 further includes a second power connection piece 18, and the first thin-film transistor 123a further includes a second electrode 1232. The second electrode 1232 and the second power connection piece 18 are electrically connected through a fourth conductive hole 1246, which is a type of second conductive hole. Specifically, the aforementioned metal interconnect layer 125 further includes a second metal interconnect layer 1252. The second electrode 1232 is connected to the second metal interconnect layer 1252 through the fourth conductive hole 1246, and the second power connection piece 18 is connected to the second metal interconnect layer 1252, thereby realizing the electrical connection between the second power connection piece 18 and the second electrode 1232.

[0138] Please continue to refer to this. Figure 14 In this embodiment, the thin-film transistor 123 of the light-emitting pixel 12 further includes a second thin-film transistor 123b. The second thin-film transistor 123b includes a third electrode 1235, a fourth electrode 1236, and a second gate 1237. Specifically, the third electrode 1235 can be the source and the fourth electrode 1236 the drain, or vice versa. The third electrode 1235 is electrically connected to the first gate 1233 through a fifth conductive hole 1247, which is a second type of conductive hole. Specifically, the metal interconnect layer 125 further includes a third metal interconnect layer 1253. The third electrode 1235 is connected to the third metal interconnect layer 1253 through the fifth conductive hole 1247, and the third metal interconnect layer 1253 is connected to the first gate 1233 through a sixth conductive hole 1248, thereby achieving electrical connection between the third electrode 1235 and the first gate 1233. In this embodiment, the two thin-film transistors 123 are a switching transistor and a driving transistor, respectively, to improve the stability of the light-emitting pixel.

[0139] In one specific embodiment, the fourth terminal 1236 of the second thin-film transistor 123b is electrically connected to a data line 19 located on the planarization layer 16. The data line 19 controls the switching of the first gate 1233 of the first thin-film transistor 123a.

[0140] In a specific embodiment, the voltage connected to the first power connector 17 is a ground voltage or a low-level voltage, and the voltage connected to the second power connector 18 is a high-level voltage.

[0141] In this embodiment, the first dielectric layer 13 includes a first groove, and at least a portion of the structure of the light-emitting diode chip 122 is located within the first groove. The second dielectric layer 14 includes a second groove, and at least a portion of the structure of the light-emitting diode chip 122 is located within the second groove. In this embodiment, the first dielectric layer 13 and the second dielectric layer 14 used to fabricate the thin-film transistor 123 may be located not only on top of the light-emitting diode chip 122, but also at least in a portion of the peripheral area of ​​the light-emitting diode chip 122. This protects the light-emitting diode chip 122 and improves the structural reliability of the light-emitting pixel 12.

[0142] Based on the same inventive concept, this application also provides a method for preparing light-emitting pixel particles, which is used to prepare the light-emitting pixel particles provided in this application. Figure 15 As shown, the preparation method includes:

[0143] Step S101: A light-emitting diode chip 122 is fabricated on the surface of a substrate 121. The light-emitting diode chip 122 includes a first electrode 1221 and a second electrode 1222 arranged along the direction toward the substrate 121.

[0144] The substrate 121 can be any one of sapphire substrate 121, single-crystal silicon substrate 121, silicon carbide substrate 121, aluminum nitride substrate 121, gallium nitride substrate 121, or quartz substrate 121. In one specific embodiment, the substrate 121 can be selected as sapphire substrate 121.

[0145] In one specific embodiment, the aforementioned light-emitting diode chip 122 may include a second electrode 1222, a second semiconductor doped layer 1225, a first active layer 1223, a first semiconductor doped layer 1224, and a first electrode 1221. The first electrode 1221 is a cathode, and the second electrode 1222 is an anode, or vice versa. Taking the first electrode 1221 as the anode and the second electrode 1222 as the cathode as an example.

[0146] The second semiconductor doped layer 1225 is an N-type semiconductor doped layer, that is, a second semiconductor doped layer 1225 doped with N-type material. The light-emitting diode chip 122 in this application may include one or more N-type semiconductor doped layers. The specific material selection for the aforementioned N-type semiconductor doped layer is varied; for example, it may be N-type doped gallium nitride (n-GaN), or it may be a composite layer of u-GaN and n-GaN, or a composite layer of aluminum nitride (AlN) and n-GaN. Specifically, the N-type semiconductor layer may be doped with Si, and the Si content is 0.5 to 5*10⁻⁶. 19 / cm 3 .

[0147] The first active layer 1223 is a multiple quantum well (MQW) layer, which may include a single-layer structure or a multi-layer structure. For example, the first active layer 1223 may be a series of overlapping gallium nitride (InGaN) and gallium nitride (GaN) layers, which may include a ten-layer structure. The InGaN mentioned above is In-doped GaN, and the In to Ga ratio is 0.05 to 0.95.

[0148] The aforementioned first semiconductor doped layer 1224 is a P-type semiconductor doped layer, that is, a first semiconductor doped layer 1224 doped with P-type material. The light-emitting diode chip 122 in this application may include one or more P-type semiconductor doped layers. The P-type semiconductor doped layer may be P-type doped GaN, and may further be doped with magnesium (Mg), with a Mg content of 0.2–8 × 10⁻⁶. 17 / cm 3 .

[0149] The first electrode 1221 is the anode, and it is in contact with the p-type semiconductor doped layer. The first electrode can be a single-layer or multi-layer structure, such as nickel (Ni) / silver (Ag) / titanium (Ti), Ni / Al / Ti, Ni / Pt / Au, ITO, or IZO, etc.

[0150] In step S101, multiple light-emitting pixel particles can be simultaneously fabricated on the substrate 121. Each light-emitting pixel particle includes a light-emitting diode chip 122, thus multiple light-emitting diode chips 122 can be fabricated simultaneously on the substrate 121. Specifically, the various layers of the light-emitting diode chip 122 can be fabricated sequentially on the substrate 121 first, and then trenches can be etched to separate the multiple light-emitting diode chips 122, that is, trenches can be etched between any two adjacent light-emitting diode chips 122.

[0151] Step S102: Prepare a buffer layer 126 on the surface of the light-emitting diode chip 122;

[0152] The buffer layer 126 is disposed on the light-emitting diode chip 122 device to separate the light-emitting diode chip 122 and the thin-film transistor 123. Specifically, the buffer layer 126 can be formed by deposition. The material of the buffer layer 126 can be a single layer of silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide, or it can be a multilayer stack. In one embodiment, the buffer layer 126 can be a stack of aluminum oxide and silicon oxide, wherein the thickness of the aluminum oxide is 1nm to 100nm and the thickness of the silicon oxide is 100nm to 2000nm. In a specific embodiment, the thickness of the aluminum oxide is 10nm and the thickness of the silicon oxide is 1000nm, with the silicon oxide stacked on top of the aluminum oxide. Specifically, the buffer layer 126 covers the top and peripheral surfaces of the light-emitting diode chip 122. This protects the light-emitting diode chip 122 from its top and side surfaces, improving its lifespan.

[0153] Step S103: A thin film transistor 123 is fabricated on the surface of the buffer layer 126. The thin film transistor 123 includes a first thin film transistor 123a, and the first thin film transistor 123a includes a first electrode 1231.

[0154] The above-mentioned thin-film transistor 123 and the light-emitting diode chip 122 are at least partially overlapped on the substrate 121, which is beneficial to reduce the area occupied by the light-emitting pixel 12 on the substrate 11 of the display panel 1, and to improve the miniaturization of the light-emitting pixel 12 and the integration of the display panel 1.

[0155] The thin-film transistor 123 includes an active region and a gate, with the source and drain located on opposite sides of the active region. The light-emitting pixel 12 in this application includes a first dielectric layer 13 and a second dielectric layer 14, which are arranged in a direction away from the substrate 121. The active region is located in the first dielectric layer 13, and the gate is located in the second dielectric layer 14. For example, the first thin-film transistor 123a includes a first active region 1234 and a first gate 1233, with the first active region 1234 located in the first dielectric layer 13 and the first gate 1233 located in the second dielectric layer 14.

[0156] In the specific preparation method, this step includes:

[0157] A semiconductor layer is formed on the surface of the buffer layer 126. Specifically, it can be formed by depositing amorphous silicon (A-Si) followed by laser crystallization to create a polycrystalline silicon layer as the semiconductor layer. Specifically, an ultra-narrow continuous wave laser can be used to crystallize the amorphous silicon (A-Si). Then, etching and other processes are used to form the active region. This active region is used to form the active channel of the thin-film transistor 123. The material of the semiconductor layer can include polycrystalline silicon, single-crystal silicon, metal oxide semiconductor, two-dimensional sulfide semiconductor, or carbon-based semiconductor. For example, in one specific embodiment, the material of the semiconductor layer is low-temperature polycrystalline silicon.

[0158] A first dielectric layer 13 is deposited to form the active region. This first dielectric layer 13 covers the active region and can also be understood as a semiconductor layer located within the first dielectric layer 13. The first dielectric layer 13 can also be called a gate insulating layer and is used to form a gate dielectric layer. The material of the first dielectric layer 13 is an insulating layer material. In specific embodiments, the first dielectric layer 13 can be a single-layer structure or a multi-layer structure. For example, the first dielectric layer 13 can be a single-layer silicon nitride layer, silicon oxide layer, silicon oxynitride layer, or aluminum oxide layer. Alternatively, the first dielectric layer 13 can also be a multi-layer structure of multilayer film stacks, specifically a stacked structure of at least two of the aforementioned silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide layers. In this embodiment, the first dielectric layer 13 can be formed by a stack of silicon oxide and silicon nitride layers, wherein the thickness of the silicon oxide layer is 1 nm to 200 nm, and the thickness of the silicon nitride layer is 1 nm to 200 nm. Specifically, the thickness of the silicon oxide layer can be 70 nm, the thickness of the silicon nitride layer can be 20 nm, and the silicon nitride layer can be stacked on top of the silicon oxide layer.

[0159] A gate layer is then deposited and etched to form the gate. This gate is located above the first dielectric layer 13 and between the source and drain. The gate can be a metallic material, such as Mo, Ti, or MoTi. In this embodiment, the gate can be Ti.

[0160] A second dielectric layer 14 is then deposited, which is located above the gate and covers it. The material of the second dielectric layer 14 is an insulating layer. In specific embodiments, the second dielectric layer 14 can be a single-layer structure or a multi-layer structure. For example, the second dielectric layer 14 can be a single-layer silicon nitride layer, silicon oxide layer, silicon oxynitride layer, or aluminum oxide layer. Alternatively, the second dielectric layer 14 can be a multi-layer structure of stacked films, specifically a stacked structure of at least two of the aforementioned silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide layers. In this embodiment, the second dielectric layer 14 can be formed by stacking silicon oxide and silicon nitride layers, wherein the thickness of the silicon oxide layer is 1 nm to 400 nm, and the thickness of the silicon nitride layer is 1 nm to 400 nm. Specifically, the thickness of the silicon oxide layer can be 300 nm, the thickness of the silicon nitride layer can be 300 nm, and the silicon nitride layer can be stacked on top of the silicon oxide layer. When the second dielectric layer 14 is a multi-layer structure, it can be formed by multiple deposition processes.

[0161] Step S104: Prepare conductive hole 124. The prepared conductive hole 124 includes a first conductive hole 1241 and a second conductive hole 1242. The first conductive hole 1241 is electrically connected to the first electrode 1221, and the second conductive hole 1242 is electrically connected to the first electrode 1231.

[0162] Specifically, the end of the first conductive hole 1241 facing the substrate 121 is electrically connected to the first electrode 1221, and the end of the second conductive hole 1242 facing the substrate 121 is electrically connected to the second electrode 1232.

[0163] Figure 16 This is a schematic diagram illustrating one fabrication process of the light-emitting pixel in an embodiment of this application. Please refer to it. Figure 16 Step S104 may specifically include the following steps:

[0164] Step S1041: Prepare the first hole;

[0165] The first hole can be prepared by methods such as laser drilling or mechanical drilling, and the first hole has a certain diameter and depth. Specifically, the depth of the first hole can be the difference between the depth of a first type of hole and the depth of a second type of hole, that is, the depth of the first hole can be obtained by subtracting the depth of the second type of hole from the depth of the first type of hole.

[0166] Step S1042: Prepare a second hole and a second type of hole. Prepare a second hole at the bottom of the first hole and connect the first hole and the second hole to form a first type of hole.

[0167] In this step, a second hole is prepared directly within the first hole, thereby connecting the first hole and the second hole to form a first type of hole, the depth of which is greater than the depth of the second type of hole.

[0168] In one embodiment, the diameter D1' of the end of the first hole facing the second hole and the diameter D2' of the second hole facing the first hole satisfy: D1' > D2'. The diameter of the bottom end of the first hole is larger than the diameter of the top end of the second hole, forming a step between the first and second holes. When fabricating a metal structure within the first type of hole, this step can be used to support the metal structure, thereby facilitating the attachment of the metal structure to the second hole and improving the reliability of the first type of conductive hole. Furthermore, during the fabrication process, the larger bottom wall area of ​​the first hole facilitates the fabrication of the hole structure of the second hole on the bottom wall of the first hole, making it less likely to damage the sidewalls of the first hole, resulting in a more continuous metal structure on the inner wall of the first conductive hole 1243.

[0169] To improve the connection effect between the conductive hole 124 and the conductive structure connected thereto, a groove 15 is formed in the conductive structure at the bottom of the conductive hole 124 during the fabrication of the conductive hole 124. Specifically, step S1042 includes the second hole portion and the second type of hole extending to the conductive structure, such that the conductive structure includes the groove 15. That is, when fabricating the second hole portion, the actual processing depth is slightly greater than the actual depth of the second hole portion; when fabricating the second type of hole, the actual processing depth is slightly greater than the actual depth of the second type of hole. Therefore, when fabricating the metal structure within the conductive hole 124, the metal structure is attached not only to the inner wall of the conductive hole 124 but also to the groove 15 of the conductive structure. The metal structure within the conductive hole 124 is at least partially located within the groove 15. In this embodiment, the contact area between the metal structure within the conductive hole 124 and the connected conductive structure is large, which is beneficial for improving the reliability of the connection between the metal structure within the conductive hole 124 and the conductive structure, and improving the signal transmission effect.

[0170] Specifically, the inner diameters of the first and second hole portions in the first type of hole increase sequentially away from the substrate 121, resulting in trapezoidal cross-sections when viewed in section. Similarly, the inner diameters of the second type of hole increase sequentially away from the substrate 121, also resulting in trapezoidal cross-sections when viewed in section. In this embodiment, the inner walls of the first and second type of holes each form a certain slope, which facilitates metal adhesion to the inner walls of the first and second type of holes. This is particularly beneficial for the deeper first type of holes, improving the adhesion of metal to the surface of the first type of hole and enhancing the structural stability of the first and second type of conductive holes.

[0171] Step S1043: Prepare a metal structure in the first type of hole and the second type of hole to form a first type of conductive hole and a second type of conductive hole. The first conductive hole 1241 is a first type of conductive hole and the second conductive hole 1242 is a second type of conductive hole.

[0172] In this scheme, the aforementioned metal structure can be prepared using processes such as metal filling, electroplating, or sputtering. This embodiment uses a single process to prepare a metal structure within first and second type holes of different depths to form a conductive hole 124. This simplifies the preparation process of the conductive hole 124 and the light-emitting pixel 12. Specifically, for two sets of connectors with different distances, at least two drilling and metal structure preparation processes are required, making the process more complex. Furthermore, for a set of connectors with relatively large distances, the conductive holes 124 prepared in two separate processes need to be staggered, resulting in a larger area occupied by the conductive holes 124, which is detrimental to improving the integration density of the light-emitting pixel 12. In this embodiment, a second hole is prepared within the first hole to form a complete first type hole. The prepared first type conductive hole extends along the thickness direction of the light-emitting pixel 12, occupying a smaller area, which is beneficial for improving the integration density of the light-emitting pixel 12.

[0173] Step S105: Prepare a metal interconnect layer 125, which connects the first conductive hole 1241 and the second conductive hole 1242.

[0174] Specifically, a metal layer can be prepared first, followed by etching to form a metal pattern, thereby forming a metal interconnect layer 125. At least one metal interconnect layer 125 connects a first conductive via 1241 and a second conductive via 1242. The end of the first conductive via 1241 facing away from the first electrode is connected to the metal interconnect layer, and the end of the second conductive via 1242 facing away from the first electrode is connected to the metal interconnect layer, thereby achieving an electrical connection between the first electrode 1231 and the first electrode 1221. Specifically, the metal interconnect layer 125 can cover the ends of the first conductive via 1241 and the ends of the second conductive via 1242.

[0175] In one embodiment, steps S1043 and S105 can be performed simultaneously or partially overlap. Specifically, the metal structures and metal layers within the first type of hole and the second type of hole can be fabricated simultaneously, followed by etching to form the metal interconnect layer 125. In this embodiment, the metal structure within the conductive hole 124 and the metal interconnect layer 125 are simultaneously fabricated continuous metal layer structures, which can improve the connection reliability between the metal interconnect layer 125 and the conductive hole 124.

[0176] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A light-emitting pixel, characterized in that, It includes a substrate, a light-emitting diode chip, a thin-film transistor, multiple conductive holes, and a first metal interconnect layer, wherein: The light-emitting diode chip is disposed on the substrate, the thin-film transistor is disposed on the side of the light-emitting diode chip facing away from the substrate, and a buffer layer is disposed between the light-emitting diode chip and the thin-film transistor; The light-emitting diode chip includes a first electrode and a second electrode; the thin-film transistor includes a first thin-film transistor, and the first thin-film transistor includes a first electrode. The conductive holes include a first type of conductive holes and a second type of conductive holes. The length of the first type of conductive holes along a first direction is greater than the length of the second type of conductive holes along the first direction. The first direction is perpendicular to the substrate. Wherein, the first metal interconnect layer is located on the side of the first thin film transistor away from the light-emitting diode chip, the first electrode is electrically connected to the first metal interconnect layer through a first conductive hole, and the first electrode is electrically connected to the first metal interconnect layer through a second conductive hole, so that the first electrode is electrically connected to the first electrode, the first conductive hole is a first type of conductive hole, and the second conductive hole is a second type of conductive hole.

2. The light-emitting pixel as described in claim 1, characterized in that, The conductive hole includes a metal structure, and the metal structure of the first type of conductive hole is an integrally formed structure.

3. The light-emitting pixel as described in claim 1 or 2, characterized in that, The first type of conductive hole includes a first conductive hole portion and a second conductive hole portion, the first conductive hole portion and the second conductive hole portion are arranged in a direction toward the substrate, the first conductive hole portion includes a first end facing away from the substrate, and the orthographic projection of the second conductive hole portion on the substrate is completely located within the orthographic projection of the first end on the substrate.

4. The light-emitting pixel as described in claim 3, characterized in that, The diameter D1 of the first conductive hole portion facing the second conductive hole portion and the diameter D2 of the second conductive hole portion facing the first conductive hole portion satisfy: D1 > D2.

5. The light-emitting pixel as described in claim 3 or 4, characterized in that, The length of the second conductive hole portion along the first direction is the same as the length of the second type of conductive hole along the first direction.

6. The light-emitting pixel as described in any one of claims 1 to 5, characterized in that, The conductive hole is connected to a conductive structure at one end facing the substrate. The conductive structure includes a groove, and a metal structure within the conductive hole is at least partially located within the groove.

7. The light-emitting pixel as described in any one of claims 1 to 6, characterized in that, It also includes a first power connector piece, and the second electrode and the first power connector piece are electrically connected through a third conductive hole, wherein the third conductive hole is the first type of conductive hole.

8. The light-emitting pixel as described in any one of claims 1 to 7, characterized in that, It also includes a second power connector, and the first thin-film transistor further includes a second electrode. The second electrode and the second power connector are electrically connected through a fourth conductive hole, which is a second type of conductive hole.

9. The light-emitting pixel as described in any one of claims 1 to 8, characterized in that, The thin-film transistor further includes a second thin-film transistor, the second thin-film transistor including a third electrode, the first thin-film transistor further includes a first active region and a first gate, the first electrode and the second electrode are located in the first active region, the first gate is located on the side of the first active region away from the substrate, the third electrode and the first gate are electrically connected through a fifth conductive hole, the fifth conductive hole being a second type of conductive hole.

10. The light-emitting pixel as described in any one of claims 1 to 9, characterized in that, The orthographic projection of the thin-film transistor on the substrate and the orthographic projection of the light-emitting diode chip on the substrate at least partially overlap.

11. The light-emitting pixel as described in claim 10, characterized in that, The orthogonal projection of the thin-film transistor onto the substrate lies entirely within the orthogonal projection of the light-emitting diode chip onto the substrate.

12. The light-emitting pixel as described in any one of claims 1 to 11, characterized in that, The first conductive hole's orthogonal projection onto the substrate is entirely within the orthogonal projection of the LED chip onto the substrate; the second conductive hole's orthogonal projection onto the substrate is entirely within the orthogonal projection of the LED chip onto the substrate.

13. The light-emitting pixel as described in any one of claims 1 to 12, characterized in that, The first electrode is the anode.

14. The light-emitting pixel as described in any one of claims 1 to 13, characterized in that, The buffer layer covers the top and peripheral surfaces of the light-emitting diode chip.

15. The light-emitting pixel as described in any one of claims 1 to 14, characterized in that, It also includes a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer being arranged in a direction away from the substrate, and the first thin film transistor including a first active region and a first gate, the first active region being located in the first dielectric layer and the first gate being located in the second dielectric layer; The first dielectric layer includes a first groove, and at least a portion of the structure of the light-emitting diode chip is located within the first groove. The second dielectric layer includes a second groove, and at least a portion of the structure of the light-emitting diode chip is located within the second groove.

16. A display panel, characterized in that, It includes a substrate and a plurality of light-emitting pixels as described in any one of claims 1 to 15, wherein the plurality of light-emitting pixels are arranged on the substrate.

17. A display panel, characterized in that, It includes a plurality of light-emitting pixel particles as described in any one of claims 1 to 15, wherein the substrate of the plurality of light-emitting pixel particles is an integral structure.

18. An electronic device, characterized in that, It includes a housing and a display panel as described in claim 16 or 17, wherein the display panel is mounted on the housing.

19. A method for preparing light-emitting pixel particles, characterized in that, include: A light-emitting diode chip is fabricated on a substrate surface, the light-emitting diode chip including a first electrode and a second electrode; A buffer layer is fabricated on the surface of a light-emitting diode chip; A thin-film transistor is fabricated on the surface of the buffer layer. The thin-film transistor includes a first thin-film transistor, and the first thin-film transistor includes a first electrode. A conductive hole is prepared, the conductive hole including a first conductive hole and a second conductive hole, the first conductive hole being electrically connected to the first electrode, and the second conductive hole being electrically connected to the first electrode; A metal interconnect layer is prepared, wherein the metal interconnect layer connects the first conductive via and the second conductive via.

20. The preparation method according to claim 19, characterized in that, The preparation of the conductive hole includes: Prepare the first hole; A second hole portion and a second type of hole are prepared. The second hole portion is prepared at the bottom of the first hole portion, and the first hole portion and the second hole portion are connected to form a first type of hole. Metal structures are fabricated within the first type of hole and the second type of hole to form a first type of conductive hole and a second type of conductive hole, wherein the first conductive hole is a first type of conductive hole and the second conductive hole is a second type of conductive hole.

21. The preparation method according to claim 20, characterized in that, The preparation of the conductive hole further includes: The diameter D1' of the end of the first hole facing the second hole and the diameter D2' of the second hole facing the first hole satisfy: D1' > D2'.

22. The preparation method according to claim 21, characterized in that, The preparation of the second pore and the second type of pore includes: The second hole and the second type of hole extend into the conductive structure, such that the conductive structure includes a groove.

Images