Display device and electronic device

Abstract

A display apparatus and an electronic apparatus are provided. The display device includes: a first pixel and a second pixel disposed adjacent to each other in a first direction; a plurality of first electrodes disposed in each of the first pixels and the second pixels; and a plurality of second electrodes disposed in each of the first pixels and the second pixels and separated from the corresponding plurality of first electrodes. The plurality of first electrodes in the first pixel and the plurality of first electrodes in the second pixel are disposed symmetrically with respect to an imaginary line disposed at a boundary between the first pixel and the second pixel and extending in a second direction different from the first direction. The plurality of second electrodes are asymmetrically disposed with respect to the imaginary line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0124836, filed on September 12, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to display devices and electronic devices. Background Technology

[0004] Among display devices, organic light-emitting diode (OLED) displays are gaining attention as the next generation of displays because they offer advantages such as wide viewing angles, excellent contrast ratios, and fast response times.

[0005] Typically, in organic light-emitting diode (OLED) display devices, thin-film transistors (TFTs) and organic light-emitting diodes (OLEDs) used as display elements are formed on a substrate. OLEDs operate to emit light through themselves. OLED display devices can be used as displays for small products such as mobile phones or large products such as televisions. Summary of the Invention

[0006] One or more embodiments provide display devices and electronic devices with a robust structure even in the face of overlay deviation.

[0007] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0008] According to one or more embodiments, a display device includes: a first pixel and a second pixel disposed adjacent to each other in a first direction; a plurality of first electrodes disposed in each of the first pixel and the second pixel; and a plurality of second electrodes disposed in each of the first pixel and the second pixel and separated from the corresponding plurality of first electrodes, wherein the plurality of first electrodes in the first pixel and the plurality of first electrodes in the second pixel are symmetrically disposed with respect to an imaginary line disposed at the boundary between the first pixel and the second pixel and extending in a second direction different from the first direction, and the plurality of second electrodes are asymmetrically disposed with respect to the imaginary line.

[0009] In an embodiment, the display device may further include a data line disposed at the boundary between the first pixel and the second pixel, extending in the second direction and disposed along the imaginary line.

[0010] In an embodiment, the plurality of first electrodes, the plurality of second electrodes, and the data line may comprise the same conductive material.

[0011] In an embodiment, in each of the first pixel and the second pixel, one of the plurality of first electrodes may be a first capacitor electrode.

[0012] In an embodiment, the first capacitor electrode may have a symmetrical structure relative to the second direction.

[0013] In an embodiment, the display device may further include a first scan signal line extending in the first direction, crossing the first pixel and the second pixel, and electrically connected to one of the plurality of second electrodes of each of the first pixel and the second pixel, wherein at least one of the plurality of second electrodes of each of the first pixel and the second pixel may be disposed between the first scan signal line and the first capacitor electrode.

[0014] In an embodiment, the first scan signal line may include a first-1 scan signal line extending in the first direction and a first-2 scan signal line parallel to the first-1 scan signal line.

[0015] In an embodiment, the display device may further include a lower capacitor electrode that overlaps with the first capacitor electrode, wherein the lower capacitor electrode and the first scan signal line may comprise the same material.

[0016] In an embodiment, the lower capacitor electrode disposed in the first pixel and the lower capacitor electrode disposed in the second pixel can be disposed symmetrically with respect to the imaginary line.

[0017] In one embodiment, the lower capacitor electrode may have a symmetrical structure relative to the second direction.

[0018] In an embodiment, the display device may further include an initialization voltage line extending in the first direction and crossing the first pixel and the second pixel, wherein, in each of the first pixel and the second pixel, at least one of the plurality of first electrodes may be disposed between the first capacitor electrode and the initialization voltage line.

[0019] In an embodiment, the display device may further include a first capacitor disposed in each of the first pixel and the second pixel, wherein the first capacitor may include a first capacitor electrode and a second capacitor electrode overlapping the first capacitor electrode.

[0020] In an embodiment, the display device may further include a second capacitor disposed in each of the first pixel and the second pixel, wherein the second capacitor may include a third capacitor electrode and a fourth capacitor electrode overlapping the third capacitor electrode, and the fourth capacitor electrode may be integrally formed with the first capacitor electrode.

[0021] According to one or more embodiments, a display device includes: a first pixel and a second pixel disposed adjacent to each other in a first direction; a driving transistor disposed in each of the first pixel and the second pixel, the driving transistor including a driving gate electrode; and a switching transistor disposed in each of the first pixel and the second pixel and electrically connected to the corresponding driving transistor, the switching transistor including a switching gate electrode, wherein the driving gate electrode of the first pixel and the driving gate electrode of the second pixel are symmetrically disposed with respect to an imaginary line disposed at the boundary between the first pixel and the second pixel and extending in a second direction different from the first direction, and the switching gate electrode of the first pixel and the switching gate electrode of the second pixel are asymmetrically disposed with respect to the imaginary line.

[0022] In an embodiment, the display device may further include a first electrode disposed in each of the first pixel and the second pixel and overlapping with the corresponding driving gate electrode, wherein the first electrode of the first pixel and the first electrode of the second pixel may be symmetrically disposed with respect to the imaginary line.

[0023] In an embodiment, the first electrode may have a symmetrical structure relative to the second direction.

[0024] In an embodiment, in each of the first pixel and the second pixel, the driving transistor may include a driving semiconductor layer, the switching transistor may include a switching semiconductor layer, and each of the driving semiconductor layer and the switching semiconductor layer may include an oxide semiconductor material.

[0025] In an embodiment, in each of the first pixel and the second pixel, the driving transistor may include a driving semiconductor layer, the switching transistor may include a switching semiconductor layer, and each of the driving semiconductor layer and the switching semiconductor layer may include an N-type semiconductor.

[0026] In an embodiment, the display device may further include an operation control transistor disposed in each of the first pixel and the second pixel and electrically connected to the corresponding driving transistor. The operation control transistor includes an operation control gate electrode, wherein the operation control gate electrode of the first pixel and the operation control gate electrode of the second pixel may be symmetrically arranged with respect to the imaginary line.

[0027] According to one or more embodiments, an electronic device includes: a display device; and wherein the display device includes: a first pixel and a second pixel disposed adjacent to each other in a first direction; a first electrode disposed in each of the first pixel and the second pixel; and a second electrode disposed in each of the first pixel and the second pixel and separated from the corresponding first electrode, wherein the first electrode in the first pixel and the first electrode in the second pixel are symmetrically disposed with respect to an imaginary line disposed at the boundary between the first pixel and the second pixel and extending in a second direction different from the first direction, and the second electrode in the first pixel and the second electrode in the second pixel are asymmetrically disposed with respect to the imaginary line.

[0028] Other aspects, features, and advantages of this disclosure will become better understood through the detailed description, claims, and drawings. Attached Figure Description

[0029] The above and other aspects, features and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 This is a schematic plan view of a display device according to an embodiment;

[0031] Figure 2 This is a schematic diagram illustrating the wiring included in a display device according to an embodiment;

[0032] Figure 3 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment;

[0033] Figure 4 It is shown Figure 1 A schematic layout diagram of a portion of the display area of ​​a display device, including the first pixel and the second pixel;

[0034] Figure 5 This is a schematic layout diagram showing the location of the thin-film transistors in the first pixel;

[0035] Figure 6 It is schematically shown along Figure 4 The line I-I' intercepted Figure 4 A schematic cross-sectional view of the display device;

[0036] Figures 7 to 11 It is shown on the basis of layers Figure 4 The schematic layout diagram of the display device shown includes components such as thin-film transistors, storage capacitors, and holding capacitors.

[0037] Figure 12 This is a schematic layout diagram showing a portion of an area including a first pixel and a second pixel in a display area of ​​a display device according to another embodiment;

[0038] Figure 13 and Figure 14 It is shown on the basis of layers Figure 12 The schematic layout diagram of the display device shown includes components such as thin-film transistors, storage capacitors, and holding capacitors.

[0039] Figure 15 and Figure 16 This is a schematic layout diagram showing a portion of an area including a first pixel and a second pixel in a display area of ​​a display device according to another embodiment;

[0040] Figure 17 This is a schematic block diagram illustrating a display system according to an embodiment; and

[0041] Figure 18 This is a schematic diagram illustrating an example of a smartwatch including a display device according to an embodiment. Detailed Implementation

[0042] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, in which the same reference numerals refer to the same elements throughout. In this respect, present embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below solely by reference to the accompanying drawings to illustrate various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements where a list of elements follows, and do not modify individual elements in the list.

[0043] Because this description allows for various modifications and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure, as well as methods for achieving the effects and features of this disclosure, will be elucidated with reference to the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments and can be implemented in various forms.

[0044] In the following embodiments, the terms "first," "second," etc., are not used in a limiting sense and are used to distinguish one element from another.

[0045] Unless the context clearly indicates otherwise, the singular form used herein is intended to include the plural form as well.

[0046] It will also be understood that the terms “comprising” and / or “including” as used herein indicate the presence of the stated features or elements, but do not exclude the presence or addition of one or more other features or elements.

[0047] In the following embodiments, it will be understood that when a portion, such as a unit, region, or element, is referred to as being "on" another portion, this can include not only the case where the portion is directly on the other portion, but also the case where there may be an intermediary unit, region, or element between the portion and the other portion.

[0048] In the following embodiments, it will be understood that, unless the context clearly indicates otherwise, the terms “connection” or “coupled” do not necessarily mean “direct connection and / or fixed connection or direct coupling and / or fixed coupling” of two components, and this does not preclude the arrangement of other components between the two components.

[0049] Additionally, for ease of illustration, the dimensions and / or thicknesses of elements in the accompanying drawings may be exaggerated or reduced. For example, the dimensions and / or thicknesses of elements in the drawings are arbitrarily shown for ease of illustration, and this disclosure is not limited thereto.

[0050] In the following description, embodiments will be described in detail with reference to the accompanying drawings. When describing embodiments with reference to the accompanying drawings, the same or corresponding elements are indicated by the same reference numerals, and redundant descriptions are omitted.

[0051] It will be understood that when an element, layer, film, region, or plate is referred to as being "on" another element, layer, film, region, or plate, said element, layer, film, region, or plate may be "directly on" the other element, layer, film, region, or plate, and an intermediary element, layer, film, region, or plate may exist between said element, layer, film, region, or plate and said element, layer, film, region, or plate. Furthermore, for ease of illustration, the dimensions and thicknesses of elements in the figures may be enlarged or reduced. For example, the dimensions and thicknesses of elements in the figures are arbitrarily shown for ease of illustration, and this disclosure is not necessarily limited thereto.

[0052] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0053] Figure 1 This is a schematic plan view of the display device 10 according to an embodiment.

[0054] refer to Figure 1 The display device 10 can be applied to various electronic devices, such as small and medium-sized electronic devices like tablet PCs, smartphones, car navigation units, cameras, central information displays (CIDs) provided in automobiles, wristwatches, personal digital assistants (PDAs), portable multimedia players (PMPs), and game consoles, as well as medium and large-sized electronic devices like televisions, billboards, monitors, PCs, and laptops. However, such electronic devices are merely exemplary embodiments, and it is apparent that the display device 10 can be applied to other electronic devices without departing from the concept of this disclosure.

[0055] Display device 10 may include a display panel that provides a display screen. Examples of display panels may include inorganic light-emitting display panels (such as inorganic light-emitting diode display panels), organic light-emitting display panels, quantum dot light-emitting display panels, plasma display panels, and field emission display panels. As an example of a display panel, the application of an inorganic light-emitting display panel has been described, but this disclosure is not limited thereto, and other display panels may be applied as long as the same technical concept is applicable.

[0056] The shape of the display device 10 can be modified in various ways. For example, the display device 10 can have a rectangular shape with a length and width, a rectangular shape with a length and height, a square shape, a rectangular shape with rounded corners (vertices), other polygonal shapes, circular shapes, etc. The shape of the display area DPA in the display device 10 can also be similar to the overall shape of the display device 10. Figure 1 The diagram shows a display device 10 and a display area DPA, each having a rectangular shape with length and width.

[0057] The display device 10 may include two first sides extending in one direction and two second sides extending in another direction intersecting the first direction. The corner where the first and second sides of the display device 10 intersect may be a right angle, but this disclosure is not limited thereto, and the corner may also be curved. In some embodiments, the first side may be shorter than the second side, but this disclosure is not limited thereto. The planar shape of the display device 10 is not limited to the examples described above, and the display device 10 may have a circular shape or other shapes.

[0058] Display device 10 may include a display area DPA and a non-display area NDA. The display area DPA is the area in which an image is displayed, and the non-display area NDA is the area in which no image is displayed. The display area DPA may also be referred to as an active area, and the non-display area NDA may also be referred to as a passive area. The display area DPA may occupy approximately the center of the display device 10.

[0059] The display area (DPA) may include multiple pixels (PX). The multiple pixels (PX) may be arranged in both row and column directions. In a planar view, each pixel (PX) may have a rectangular or square shape, but this disclosure is not limited thereto, and each pixel (PX) may have a rhomboid shape with each side sloping in one direction. The pixels (PX) may be arranged alternately in a striped or five-tile pattern. Each pixel (PX) may include one or more light-emitting elements to emit light of a specific wavelength to display a specific color.

[0060] The non-display area NDA can be disposed around the display area DPA. The non-display area NDA can completely or partially surround the display area DPA. The display area DPA can be rectangular in shape, and the non-display area NDA can be disposed adjacent to the four sides of the display area DPA. The non-display area NDA can form the bezel of the display device 10. Wiring or circuit drivers included in the display device 10 can be disposed in the non-display area NDA, or external devices can be installed in the non-display area NDA.

[0061] Figure 2 This illustrates a display device 10 according to an embodiment (see [link]). Figure 1 The diagram includes a wiring diagram.

[0062] refer to Figure 2 The display device 10 may include multiple wirings. These wirings may include a scan signal line SL, an operation control signal line ECL, and a transmit control signal line (see [link to documentation]). Figure 3 The display device 10 includes the transmit control signal line ECL2, the data line DTL, the initialization voltage line VIL, the first voltage line VDL, and the second voltage line VSL. Although not shown, the display device 10 may also include other wiring. Figure 2 This is only a schematic diagram of the arrangement of multiple cabling lines.

[0063] The scan signal line SL and the operation control signal line ECL can extend along the first direction DR1. The scan signal line SL and the operation control signal line ECL can be electrically connected to the driver SDR. The driver SDR may include scan drive circuitry and transmit signal control circuitry. The driver SDR can be located in the display area DPA (see...). Figure 1 The non-display area NDA on one side of the first direction DR1 (see) Figure 1However, this disclosure is not limited thereto. In some embodiments, the driver SDR may be disposed in the non-display area NDA on both sides of the display area DPA along the first direction DR1, and may include scan driving circuitry and transmit signal control circuitry. Scan signal line SL may be electrically connected to the driver SDR including the scan driving circuitry, and operation control signal line ECL may be electrically connected to the driver SDR including the transmit signal control circuitry. The driver SDR may be electrically connected to signal connection wiring CWL. At least one end of the signal connection wiring CWL may form a pad WPD_CW in the non-display area NDA for electrical connection to an external device.

[0064] The data line DTL can extend in a second direction DR2, intersecting the first direction DR1. The initialization voltage line VIL can extend in the second direction DR2, and may also include a portion branching off from the portion extending in the second direction DR2 in the first direction DR1. The first voltage line VDL and the second voltage line VSL may also include portions extending in the first direction DR1 and portions connected thereto and extending in the second direction DR2. The first voltage line VDL and the second voltage line VSL may each have a mesh structure, but this disclosure is not limited thereto. Although not shown, the pixels PX of the display device 10 (see...) Figure 1 Each of the following can be electrically connected to at least one scan signal line SL, data line DTL, operation control signal line ECL, transmit control signal line ECL2, initialization voltage line VIL, first voltage line VDL, and second voltage line VSL.

[0065] The data line DTL, initialization voltage line VIL, first voltage line VDL, and second voltage line VSL can be electrically connected to at least one wiring pad WPD. At least one wiring pad WPD can be located in the non-display area NDA. In an embodiment, the wiring pad WPD_DT of the data line DTL (hereinafter referred to as "data pad WPD_DT") can be located in the pad area PDA on one side of the display area DPA in the second direction DR2, and the wiring pad WPD_VI of the initialization voltage line VIL (hereinafter referred to as "initialization voltage pad WPD_VI"), the wiring pad WPD_VDD of the first voltage line VDL (hereinafter referred to as "first power pad WPD_VDD"), and the wiring pad WPD_VSS of the second voltage line VSL (hereinafter referred to as "second power pad WPD_VSS") can be located in the pad area PDA on the other side of the display area DPA in the second direction DR2. As another example, the data pad WPD_DT, the initialization voltage pad WPD_VI, the first power pad WPD_VDD, and the second power pad WPD_VSS can all be located in the same area (e.g., the non-display area NDA located above the display area DPA). External devices can be mounted on the wiring pads WPD. External devices can be mounted on the wiring pads WPD via anisotropic conductive films, ultrasonic bonding, etc.

[0066] Each pixel PX of the display device 10 may include a pixel driving circuit. The aforementioned wiring may pass through or around the pixel PX and may apply driving signals to the pixel driving circuit. Each of the pixel driving circuits may include a transistor and a capacitor. The number of transistors and capacitors in each pixel driving circuit may vary. Hereinafter, as an example, a 6T2C structure comprising six transistors and two capacitors is described, but this disclosure is not limited thereto, and the pixel driving circuit may also have various other modified pixel structures, such as a 2T1C structure, a 3T1C structure, or a 7T1C structure.

[0067] Figure 3 This is a schematic diagram of the equivalent circuit of pixel PX according to an embodiment.

[0068] refer to Figure 3 Each of the pixels PX in the display device according to the embodiment may include a pixel circuit PC and an organic light-emitting diode LD electrically connected to the pixel circuit PC.

[0069] like Figure 3As shown, the pixel circuit PC may include multiple thin-film transistors T1 to T6, a storage capacitor Cst, and a holding capacitor Chold. The multiple thin-film transistors T1 to T6, the storage capacitor Cst, and the holding capacitor Chold may be connected to signal lines SL1, SL2, ECL, and DTL, initialization voltage line VIL, reference voltage line RFL, first voltage line VDL, and second voltage line VSL.

[0070] The multiple thin-film transistors T1 to T6 may include a driving transistor T1, a switching transistor T2, a reference voltage transistor T3, an initialization transistor T4, an operation control transistor T5, and an emitter control transistor T6.

[0071] An organic light-emitting diode (OLED) may include a pixel electrode and a counter electrode. The pixel electrode of the OLED may be connected to a driving transistor T1 to receive a driving current, and the counter electrode of the OLED may receive a second power supply voltage ELVSS. The OLED can generate light with a brightness corresponding to the driving current.

[0072] The signal lines may include a first scan signal line SL1 for transmitting the write signal (scan signal) GW, a second scan signal line SL2 for transmitting the reference voltage signal GR, a third scan signal line SL3 for transmitting the initialization signal GI, an operation control signal line ECL for transmitting the operation control signal EM, a transmit control signal line ECL2 for transmitting the transmit control signal EMB, and a data line DTL that crosses the first scan signal line SL1 for transmitting the data signal VDATA.

[0073] The initialization voltage line VIL can transmit the initialization voltage Vint used to initialize the pixel electrode of the organic light-emitting diode LD, the reference voltage line RFL can transmit the reference voltage VREF to the driving gate electrode of the driving transistor T1, and the first voltage line VDL can transmit the first power supply voltage ELVDD as the driving voltage of the driving transistor T1.

[0074] The driving gate electrode of the driving transistor T1 can be connected to the storage capacitor Cst via the first node N1. The drain region of the driving transistor T1 can be connected to the first voltage line VDL via the control transistor T5, and the source region of the driving transistor T1 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED) LD via the second node N2. The driving transistor T1 can receive the data signal VDATA according to the switching operation of the switching transistor T2 and supply driving current to the OLED LD. For example, the driving transistor T1 can control the amount of current flowing to the OLED LD in response to the voltage applied to the first node N1 changing according to the data signal VDATA.

[0075] The switching gate electrode of the switching transistor T2 can be connected to the first scan signal line SL1 for transmitting the write signal GW. One of the source and drain regions of the switching transistor T2 can be connected to the data line DTL, and the other of the source and drain regions of the switching transistor T2 can be connected to the driving gate electrode of the driving transistor T1 via the first node N1. The switching transistor T2 can transmit the data signal VDATA from the data line DTL to the first node N1 in response to a voltage applied to the first scan signal line SL1. For example, the switching transistor T2 can be turned on in response to the write signal GW received via the first scan signal line SL1 and perform a switching operation to transmit the data signal VDATA received via the data line DTL to the driving transistor T1 via the first node N1.

[0076] The reference voltage gate electrode of the reference voltage transistor T3 can be connected to the second scan signal line SL2 for transmitting the reference voltage signal GR. One of the source and drain regions of the reference voltage transistor T3 can be connected to the reference voltage line RFL, and the other of the source and drain regions of the reference voltage transistor T3 can be connected to the drive gate electrode of the drive transistor T1 via the first node N1. The reference voltage transistor T3 can transmit the reference voltage VREF from the reference voltage line RFL to the first node N1 in response to the voltage applied to the second scan signal line SL2. If necessary, the second scan signal line SL2 can be connected to... Figure 3 The pixels PX shown are adjacent to and electrically connected to the first scan signal line SL1 of the pixel belonging to the previous row on the same data line DTL. For example, the reference voltage signal GR can be referred to as the previous write signal (previous scan signal).

[0077] The initialization gate electrode of the initialization transistor T4 can be connected to the third scan signal line SL3. One of the source and drain regions of the initialization transistor T4 can be connected to the pixel electrode of the organic light-emitting diode (OLED), and the other of the source and drain regions of the initialization transistor T4 can be connected to the initialization voltage line VIL to receive the initialization voltage Vint. The initialization transistor T4 can be turned on in response to the initialization signal GI received through the third scan signal line SL3, thus initializing the pixel electrode of the OLED. If necessary, the third scan signal line SL3 can be connected to... Figure 3 The pixels PX shown are adjacent to each other and electrically connected to the write signal lines of the pixels belonging to the next row on the same data line DTL. For example, the initialization signal GI can be referred to as the next write signal (next scan signal).

[0078] The gate electrode of the operation control transistor T5 can be connected to the operation control signal line ECL. One of the source and drain regions of the operation control transistor T5 can be connected to the first voltage line VDL, and the other of the source and drain regions of the operation control transistor T5 can be connected to the drain region of the driving transistor T1. The operation control transistor T5 can be turned on in response to the operation control signal EM received through the operation control signal line ECL, and transmits the first power supply voltage (driving voltage) ELVDD to the organic light-emitting diode LD, causing the driving current to flow to the organic light-emitting diode LD.

[0079] The emitter control gate electrode of emitter control transistor T6 can be connected to emitter control signal line ECL2. One of the source and drain regions of emitter control transistor T6 can be connected to the source region of driving transistor T1 via the second node N2, and the other of the source and drain regions of emitter control transistor T6 can be connected to the pixel electrode of organic light-emitting diode LD. Emitter control transistor T6 can be turned on in response to the emitter control signal EMB received through emitter control signal line ECL2, and transmit the first power supply voltage ELVDD to organic light-emitting diode LD, causing drive current to flow to organic light-emitting diode LD.

[0080] The storage capacitor Cst may include a first capacitor electrode (see...) Figure 4 The first capacitor electrode CE1) and the second capacitor electrode (see Figure 4 The second capacitor electrode CE2). The first capacitor electrode of the storage capacitor Cst (see...) Figure 4 The first capacitor electrode CE1 can be connected to the source region of the driving transistor T1 via the second node N2, and the second capacitor electrode storing the capacitor Cst (see...) Figure 4 The second capacitor electrode (CE2) can be connected to the driving gate electrode of the driving transistor T1 via the first node N1. The storage capacitor Cst can store the charge corresponding to the difference between the voltage at the driving gate electrode of the driving transistor T1 and the initialization voltage Vint. The storage capacitor Cst can be the first capacitor.

[0081] The holding capacitor Chold may include a third capacitor electrode (see [link to capacitor description]). Figure 4 The third capacitor electrode (CE3) and the fourth capacitor electrode (not shown). The third capacitor electrode holding capacitor Chold (see...) Figure 4The third capacitor electrode (CE3) can be connected to the first voltage line VDL, and the fourth capacitor electrode can be connected to the source region of the driving transistor T1 via the second node N2. The fourth capacitor electrode can be connected to the first capacitor electrode CE1 of the storage capacitor Cst. The compensation voltage for compensating the threshold voltage (Vth) of the driving transistor T1 can be stored in the holding capacitor Chold. The holding capacitor Chold can be a second capacitor.

[0082] The detailed operation of each of the pixels PX according to the embodiment is as follows.

[0083] During the initialization period, with the initialization signal GI supplied via the third scan signal line SL3, the initialization transistor T4 can be turned on, and the pixel electrode of the organic light-emitting diode (OLED) LD can be initialized by the initialization voltage Vint supplied from the initialization voltage line VIL. Of course, the source region of the driving transistor T1, which is electrically connected to the pixel electrode of the OLED LD via the second node N2, and the fourth capacitor electrode of the holding capacitor Chold can also be initialized. As described above, the third scan signal line SL3 can be... Figure 3 The pixels PX shown are adjacent to and electrically connected to the first scan signal line SL1 of the pixels belonging to the next row on the same data line DTL. For example, the initialization signal GI can be referred to as the next write signal (next scan signal).

[0084] During the compensation period, when a reference voltage signal GR is supplied via the second scan signal line SL2, the reference voltage transistor T3 can be turned on, and the reference voltage VREF supplied from the reference voltage line RFL can be transferred to the drive gate electrode of the drive transistor T1 to compensate for the threshold voltage (Vth) of the drive transistor T1. The compensation voltage for compensating the threshold voltage (Vth) of the drive transistor T1 can be stored in the holding capacitor Chold. As described above, if necessary, the second scan signal line SL2 can be connected to... Figure 3 The pixels PX shown are adjacent to and electrically connected to the first scan signal line SL1 of the pixel belonging to the previous row on the same data line DTL. For example, the reference voltage signal GR can be referred to as the previous write signal (previous scan signal).

[0085] During the data programming period, when a write signal GW is supplied via the first scan signal line SL1, the switching transistor T2 can be turned on in response to the write signal GW. For example, a voltage corresponding to the data signal VDATA supplied from the data line DTL can be applied to the drive gate electrode of the driving transistor T1. The second capacitor electrode CE2 of the storage capacitor Cst is connected to the drive gate electrode of the driving transistor T1 via the first node N1, and the first capacitor electrode CE1 of the storage capacitor Cst is connected via the second node N2 to the fourth capacitor electrode of the holding capacitor Chold, which stores the compensation voltage (the threshold voltage (Vth) of the driving transistor T1 is compensated by this compensation voltage). Therefore, the data voltage that compensates for the threshold voltage (Vth) of the driving transistor T1 is stored in the storage capacitor Cst.

[0086] During the transmission period, the operation control transistor T5 can be turned on in response to the operation control signal EM supplied from the operation control signal line ECL. The second capacitor electrode CE2 of the storage capacitor Cst is connected to the drive gate electrode of the drive transistor T1 via the first node N1, and the first capacitor electrode CE1 of the storage capacitor Cst is connected to the source region of the drive transistor T1 via the second node N2. Therefore, the drive current corresponding to the data signal VDATA flows to the organic light-emitting diode LD regardless of the threshold voltage (Vth) of the drive transistor T1, through the data voltage (wherein the data voltage is stored in the storage capacitor Cst) compensated for by the threshold voltage (Vth) of the drive transistor T1.

[0087] As described above, each of the plurality of thin-film transistors T1 to T6 may comprise an oxide semiconductor. Because oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is small even with increased driving time. For example, in the case of oxide semiconductors, low-frequency driving is possible because even during low-frequency driving, the color change of the image based on the voltage drop is minimal. Because each of the plurality of transistors T1 to T6 comprises an oxide semiconductor, a display device that prevents leakage current and reduces power consumption can be realized.

[0088] Furthermore, because oxide semiconductors are photosensitive, the amount of current, etc., can change due to external light. Therefore, external light can be absorbed or reflected by placing a metal layer beneath the oxide semiconductor. Thus, as... Figure 3 As shown, the switching transistor T2, reference voltage transistor T3, initialization transistor T4, and operation control transistor T5, each including an oxide semiconductor layer, can have gate electrodes above and below the oxide semiconductor layer. Additionally, in the case of the driving transistor T1, a metal layer can be disposed below the oxide semiconductor layer. For example, when from the substrate (see...) Figure 6When viewed in a direction perpendicular to the upper surface of the substrate (SUB) (e.g., in a plan view perpendicular to the first direction DR1 and the second direction DR2), the metal layer disposed below the oxide semiconductor layer can overlap with the oxide semiconductor layer.

[0089] Figure 4 It is shown Figure 1 A schematic layout diagram of a portion of the display area DPA of the display device 10, including the first pixel PXA and the second pixel PXB. Figure 5 This shows the first pixel PXA (see...) Figure 4 A schematic layout of the positions of thin-film transistors T1 to T6 in the ).

[0090] Figure 6 It is schematically shown along Figure 4 The line I-I' intercepted Figure 4 A schematic cross-sectional view of the display device, and Figures 7 to 11 It is shown on the basis of layers Figure 4 The display device shown includes thin-film transistors T1 to T6 (see...) Figure 5 Storage capacitor Cst (see) Figure 4 ) and holding capacitor Chold (see Figure 4 A schematic layout diagram of the components.

[0091] exist Figures 4 to 11 In the first direction DR1, the two sides can be referred to as the left and right sides, respectively, and the two sides in the second direction DR2 can be referred to as the upper and lower sides, respectively. For ease of explanation, although in Figures 4 to 11 Not shown, but another pixel can be located below the first pixel PXA and the second pixel PXB (or on the other side in the second direction DR2). The first pixel PXA and the second pixel PXB can correspond to Figures 4 to 11 Any of the areas shown are surrounded by alternating long and short dashed lines, and other areas surrounded by alternating long and short dashed lines may correspond to a portion of another pixel PX adjacent to the first pixel PXA and the second pixel PXB in the second direction DR2. In the following, the figures shown to describe each of the pixels PX can be understood in the same manner as described above.

[0092] refer to Figures 4 to 11 The display device 10 according to the embodiment (see Figure 1 It can include multiple pixels (PX) (see Figure 1 Each of the multiple pixels (PX) may include at least one organic light-emitting diode (LD) (see [link]). Figure 3Each pixel PX may include a plurality of thin-film transistors T1 to T6, a storage capacitor Cst, and a holding capacitor Chold as pixel circuit elements. Each pixel PX may be electrically connected to a data line DTL, a scan signal line SL (see [link to data line]). Figure 2 The signal lines are: Operation control signal line ECL, Transmit control signal line ECL2, First voltage line VDL, Second voltage line VSL, Reference voltage line RFL, and Initialization voltage line VIL.

[0093] The display device 10 according to an embodiment may include a plurality of pixels PX, and pixel circuit elements are disposed differently in the plurality of pixels PX. The display device 10 may include a first pixel PXA and a second pixel PXB, and the arrangement of the pixel circuit elements in the first pixel PXA may be different from the arrangement of the pixel circuit elements in the second pixel PXB.

[0094] The first pixel PXA and the second pixel PXB can be arranged adjacent to each other in the first direction DR1, and can include a symmetrical region FA that is symmetrically arranged with respect to the imaginary line L1 pixel circuit element located at the boundary between the first pixel PXA and the second pixel PXB, and an asymmetrical region NFA that is asymmetrically arranged with respect to the imaginary line L1 pixel circuit element located at the boundary between the first pixel PXA and the second pixel PXB.

[0095] First pixel PXA and second pixel PXB can share a data line DTL. The data line DTL can be located at the boundary between the first pixel PXA and the second pixel PXB, can extend in the second direction DR2, and can be positioned along an imaginary line L1. To enable the first pixel PXA and second pixel PXB to share the data line DTL, a symmetrical region FA, which is part of the pixel circuit elements in each of the first pixel PXA and second pixel PXB, can have a symmetrical arrangement structure relative to the data line DTL. An asymmetrical region NFA, which is another part of the pixel circuit elements in each of the first pixel PXA and second pixel PXB, can have an asymmetrical arrangement structure relative to the data line DTL.

[0096] Connect to the second node N2, which is the source node (see...) Figure 3 The first capacitor electrode CE1 can be located in the symmetrical region FA. The asymmetrical region NFA can be a region adjacent to the symmetrical region FA. Connected to the first node N1, which serves as the gate node (see...). Figure 3The switching transistor T2 can be disposed in the asymmetric region NFA. A capacitance Cp can be formed between the first capacitor electrode CE1 and the first switching gate electrode (second-1 gate electrode layer) GP2-1 of the switching transistor T2. Because the pixel circuit elements are asymmetrically arranged adjacent to the source node, the display device 10 according to the embodiment can maintain a constant capacitance Cp even in the event of coverage deviation. The arrangement and structure of the first pixel PXA and the second pixel PXB are described in more detail below.

[0097] First, the cross-sectional structure and layout of each pixel PX are described in detail. The display device 10 may include a substrate SUB, and pixel circuit elements may be disposed on the substrate SUB. The substrate SUB may include an insulating material, such as glass, quartz, or polymer resin. The substrate SUB may be a rigid substrate, or it may be a flexible substrate that is bendable, foldable, or rollable.

[0098] A buffer layer 101 may be disposed on a substrate SUB. The buffer layer 101 may be disposed over the entire surface of the substrate SUB. The buffer layer 101 may be formed on the substrate SUB to protect the thin-film transistors of the pixel PX from moisture (moisture permeates through the moisture-sensitive substrate SUB). The buffer layer 101 may perform a surface planarization function. The buffer layer 101 may comprise multiple inorganic layers stacked alternately. For example, the buffer layer 101 may be formed in which silicon oxide (SiO2) is selected. x ) layer, silicon nitride (SiN) x A multilayer consisting of one or more inorganic layers, including a silicon oxynitride (SiON) layer, stacked alternately.

[0099] like Figure 7 The bottom metal layer BML shown can be disposed on the buffer layer 101. The bottom metal layer BML may include a first down-scan signal line SL11, a reference voltage line RFL, a second scan signal line SL2, a lower capacitor electrode BML1, a first voltage line VDL, a second voltage line VSL, a first initialization voltage line VIL, and a second initialization voltage line VIL2. Among them, the first down-scan signal line SL11, the reference voltage line RFL, the second scan signal line SL2, the first voltage line VDL, the second voltage line VSL, the first initialization voltage line VIL, and the second initialization voltage line VIL2 can extend in a first direction DR1.

[0100] The first up-scan signal line extending in the first direction DR1, as described below (see below) Figure 9 The first upper scan signal line SL12 can be disposed above the first lower scan signal line SL11 and can be electrically connected to the first lower scan signal line SL11 through a contact hole. The group of the first lower scan signal line SL11 and the first upper scan signal line SL12 can correspond to... Figure 3 The first scan signal line SL1.

[0101] The first down-scan signal line SL11 may include a first-1 down-scan signal line SL11-1 and a first-2 down-scan signal line SL11-2 extending separately from each other along the first direction DR1. One of the first-1 down-scan signal line SL11-1 and the first-2 down-scan signal line SL11-2 may be connected to the first-1 connection electrode described below (see [link]). Figure 11 The first-1 connection electrode BE1-1 is electrically connected to the first switch gate electrode GP2-1 of the first pixel PXA, and the other of the first-1 down scan signal line SL11-1 and the first-2 down scan signal line SL11-2 can be connected via the first-2 connection electrode described below (see [link]). Figure 11 The first-2 connection electrode BE1-2 is electrically connected to the second switch gate electrode (second-2 gate electrode layer) GP2-2 of the second pixel PXB.

[0102] The reference voltage line RFL can be accessed via a second connection electrode, which will be described later (see [link to documentation]). Figure 11 The second connecting electrode BE2 is electrically connected to the first semiconductor pattern (see...). Figure 8 The first semiconductor pattern AP1). The reference voltage line RFL can correspond to Figure 3 The reference voltage line RFL.

[0103] The second scan signal line SL2 can be electrically connected to the third gate electrode layer, which serves as the reference voltage gate electrode, via the third connection electrode BE3 (see...). Figure 8 The third gate electrode layer (GP3). For example... Figure 7 As shown, the second scan signal line SL2 may have a protrusion in each of the first pixel PXA and the second pixel PXB, and may be electrically connected to the third-1 gate electrode layer GP3-1 and the third-2 gate electrode layer GP3-2, which serve as reference voltage gate electrodes, via the third-1 connection electrode BE3-1 and the third-2 connection electrode BE3-2. The protrusions of the second scan signal line SL2 in the first pixel PXA and the protrusions of the second scan signal line SL2 in the second pixel PXB may have different shapes from each other. For example, the second scan signal line SL2 may have an asymmetrical structure relative to the imaginary line L1.

[0104] The lower capacitor electrode BML1 can have an isolated shape in each of the pixels PX. The lower capacitor electrode BML1 can be electrically connected to the first capacitor electrode CE1 located above it through a contact hole. The lower capacitor electrode BML1 can have a symmetrical structure relative to the second direction DR2.

[0105] The first voltage line VDL can be electrically connected to the first capacitor electrode CE1 through a contact hole. The first voltage line VDL, the second voltage line VSL, the first initialization voltage line VIL, and the second initialization voltage line VIL2 can have a symmetrical structure with respect to the imaginary line L1.

[0106] The bottom metal layer (BML) can include metals, alloys, conductive metal oxides, or conductive metal nitrides. For example, the bottom metal layer BML can include silver (Ag), Ag-containing alloys, molybdenum (Mo), Mo-containing alloys, aluminum (Al), Al-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). The bottom metal layer BML can have a multilayer structure. For example, the bottom metal layer BML can have approximately... Thick aluminum layer and approximately A two-layer structure with a thick titanium layer.

[0107] A first insulating layer 103 may be disposed on a substrate SUB and cover a bottom metal layer BML. The first insulating layer 103 may include an insulating material. For example, the first insulating layer 103 may be formed in a material selected from silicon oxide (SiO2). x ) layer, silicon nitride (SiN) x A multilayer consisting of one or more inorganic layers, including a silicon oxynitride (SiON) layer and an insulating layer 103, is stacked alternately. The first insulating layer 103 prevents metal atoms or impurities from diffusing from the substrate SUB to the semiconductor layer AP disposed thereon.

[0108] like Figure 8 As shown, the semiconductor layer AP can be disposed on the first insulating layer 103. Figure 8 In the diagram, for convenience, the semiconductor layer AP is shown together with the bottom metal layer BML. As described above, the semiconductor layer AP may comprise an oxide semiconductor material. For example, the semiconductor layer AP may comprise a material having approximately The thickness of the indium tin gallium zinc oxide (ITGZO) layer is [missing information]. The drive transistor T1, switch transistor T2, reference voltage transistor T3, initialization transistor T4, operation control transistor T5, and emitter control transistor T6 can be arranged along the semiconductor layer AP, such as [missing information]. Figure 5 and Figure 8 As shown. Figure 8 As shown, the semiconductor layer AP may include a first semiconductor pattern AP1, a second semiconductor pattern AP2, a third semiconductor pattern AP3, and a fourth semiconductor pattern AP4 that are separated from each other.

[0109] The drain region D2, active region ACT2, and source region S2 of the switching transistor T2, and the drain region D3, active region ACT3, and source region S3 of the reference voltage transistor T3, can be disposed on the first semiconductor pattern AP1. The first semiconductor pattern AP1 can be referred to as the switching semiconductor layer or the reference voltage semiconductor layer.

[0110] The second semiconductor pattern AP2 can be electrically connected to the first voltage line VDL and can correspond to the third capacitor electrode that holds the capacitor Chold (see...). Figure 4 The third capacitor electrode CE3). The drain region D1, active region ACT1, and source region S1 of the driving transistor T1, and the drain region D5, active region ACT5, and source region S5 of the operation control transistor T5 can be disposed on the third semiconductor pattern AP3. The third semiconductor pattern AP3 can be referred to as the driving semiconductor layer or the operation control semiconductor layer.

[0111] The drain region D4, active region ACT4, and source region S4 of the initialization transistor T4, and the drain region D6, active region ACT6, and source region S6 of the emitter control transistor T6 can be disposed on the fourth semiconductor pattern AP4. The fourth semiconductor pattern AP4 can be referred to as the initialization semiconductor layer or the emitter control semiconductor layer.

[0112] The second semiconductor pattern AP2, third semiconductor pattern AP3, and fourth semiconductor pattern AP4 of each of the first pixel PXA and the second pixel PXB can be symmetrically arranged with respect to the imaginary line L1. In contrast, the first-1 semiconductor pattern AP1-1 of the first pixel PXA and the first-2 semiconductor pattern AP1-2 of the second pixel PXB can be asymmetrically arranged with respect to the imaginary line L1. For example, the first-1 semiconductor pattern AP1-1 can be electrically connected to the data line DTL via a contact hole, and the first-2 semiconductor pattern AP1-2 can be connected via a ninth connection electrode (see below)... Figure 11 The ninth connection electrode (BE9) is electrically connected to the data line DTL.

[0113] The second insulating layer 104 may be disposed on the substrate SUB and cover the semiconductor layer AP. The second insulating layer 104 may include an insulating material. For example, the second insulating layer 104 may include an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0114] like Figure 6 As shown, the first conductive layer GP (see Figure 9 It can be disposed on the second insulating layer 104. Figure 9In the diagram, for convenience, the first conductive layer GP is shown together with the bottom metal layer BML and the semiconductor layer AP. The first conductive layer GP may include a first upper scan signal line SL12, a first gate electrode layer GP1, a second gate electrode layer GP2, a third gate electrode layer GP3, an operation control signal line ECL, an emit control signal line ECL2, and a third scan signal line SL3. The first conductive layer GP may also be referred to as the gate layer.

[0115] The first gate electrode layer GP1 can also be referred to as the driving gate electrode layer. The first gate electrode layer GP1 may overlap with the underlying semiconductor layer AP. The portion of the first gate electrode layer GP1 that overlaps with the semiconductor layer AP (e.g., the portion of the semiconductor layer AP that overlaps with the driving active region ACT1) can be the driving gate electrode (see [link to documentation]). Figure 5 The first gate electrode layer GP1 can be used as the gate electrode of the driving transistor T1, and can also be used as the second capacitor electrode CE2 of the storage capacitor Cst by overlapping with the first capacitor electrode CE1, which will be described later. For example, the first gate electrode layer GP1 can electrically connect the storage capacitor Cst, the gate electrode of the driving transistor T1, the switching transistor T2, and the reference voltage transistor T3 to each other. The first gate electrode layer GP1 can be understood as being used as... Figure 3 The first node N1 (which is the gate node).

[0116] A portion of the second gate electrode layer GP2 may also overlap with the underlying semiconductor layer AP. The second gate electrode layer GP2 may also be referred to as the switching gate electrode layer. The portion of the second gate electrode layer GP2 that overlaps with the semiconductor layer AP (e.g., the portion of the semiconductor layer AP that overlaps with the switching active region ACT2) may be the switching gate electrode G2. The second gate electrode layer GP2 may have an isolated shape and may be used as the gate electrode of the switching transistor T2.

[0117] A portion of the third gate electrode layer GP3 may also overlap with the underlying semiconductor layer AP. The third gate electrode layer GP3 may also be referred to as the reference voltage gate electrode layer. The portion of the third gate electrode layer GP3 that overlaps with the semiconductor layer AP (e.g., the portion of the semiconductor layer AP that overlaps with the reference voltage active region ACT3) may be the reference voltage gate electrode G3. The reference voltage gate electrode G3 can be used as the gate electrode of the reference voltage transistor T3.

[0118] A portion of the operation control signal line ECL may overlap with the underlying semiconductor layer AP. The portion of the operation control signal line ECL that overlaps with the semiconductor layer AP (e.g., the portion of the semiconductor layer AP that overlaps with the operation control active region ACT5) may be the operation control gate electrode G5. The operation control gate electrode G5 may be used as the gate electrode of the operation control transistor T5.

[0119] A portion of the emit control signal line ECL2 may overlap with the underlying semiconductor layer AP. The portion of the emit control signal line ECL2 that overlaps with the semiconductor layer AP (e.g., the portion of the semiconductor layer AP that overlaps with the emit control active region ACT6) may be the emit control gate electrode G6. The emit control gate electrode G6 may be used as the gate electrode of the emit control transistor T6.

[0120] A portion of the third scan signal line SL3 may overlap with the underlying semiconductor layer AP. The portion of the third scan signal line SL3 that overlaps with the semiconductor layer AP (e.g., the portion of the semiconductor layer AP that overlaps with the initialization active region ACT4) may be the initialization gate electrode G4. The initialization gate electrode G4 can be used as the gate electrode of the initialization transistor T4.

[0121] The first gate electrode layer GP1, operation control signal line ECL, emission control signal line ECL2, and third scan signal line SL3, disposed in each of the first pixel PXA and the second pixel PXB, can be symmetrically arranged with respect to the imaginary line L1. For example... Figure 9 As shown, the first gate electrode layer GP1 may have an asymmetrical shape relative to the second direction DR2, but the first gate electrode layer GP1 of the first pixel PXA and the second gate electrode layer GP2 of the second pixel PXB may have a symmetrical structure relative to the imaginary line L1.

[0122] In contrast, the second-1 gate electrode layer GP2-1 and the third-1 gate electrode layer GP3-1 of the first pixel PXA and the second-2 gate electrode layer GP2-2 and the third-2 gate electrode layer GP3-2 of the second pixel PXB can be arranged asymmetrically with respect to the imaginary line L1. For example, the arrangement order of the second-1 gate electrode layer GP2-1 and the third-1 gate electrode layer GP3-1 arranged along the first direction DR1 in the first pixel PXA can be the same as the arrangement order of the second-2 gate electrode layer GP2-2 and the third-2 gate electrode layer GP3-2 arranged along the first direction DR1 in the second pixel PXB.

[0123] The first conductive layer GP can include a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive material. For example, the first conductive layer GP can include silver (Ag), Ag-containing alloys, molybdenum (Mo), Mo-containing alloys, aluminum (Al), Al-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first conductive layer GP can have a multilayer structure. For example, the first conductive layer GP can have approximately... Thick titanium layer and approximately A two-layer structure with a thick molybdenum layer.

[0124] The third insulating layer 105 may be disposed on the substrate SUB and cover the first conductive layer GP. The third insulating layer 105 may include an insulating material. For example, the third insulating layer 105 may include an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0125] like Figure 10 As shown, the contact hole CNT can pass through at least one of the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105, and can electrically connect the top metal layer and the bottom metal layer overlapping the contact hole CNT. Figure 10 As shown, it can be confirmed that the contact hole CNT of the first pixel PXA and the contact hole CNT of the second pixel PXB in the symmetrical region FA are symmetrically arranged with respect to the imaginary line L1. In contrast, it can be confirmed that the contact hole CNT of the first pixel PXA and the contact hole CNT of the second pixel PXB in the asymmetrical region NFA are asymmetrically arranged with respect to the imaginary line L1.

[0126] A second conductive layer (not shown in the figures) may be disposed on the third insulating layer 105. The second conductive layer may include a data line DTL, a first capacitor electrode CE1, a first connection electrode BE1, a second connection electrode BE2, a third connection electrode BE3, a fourth connection electrode BE4, a fifth connection electrode BE5, a sixth connection electrode BE6, a seventh connection electrode BE7, an eighth connection electrode BE8, and a ninth connection electrode BE9. The second conductive layer may also be referred to as a source / drain layer.

[0127] The data line DTL can be located at the boundary between the first pixel PXA and the second pixel PXB, and can extend in the second direction DR2. The first pixel PXA and the second pixel PXB can share a single data line DTL.

[0128] The first capacitor electrode CE1 may have an isolated shape and may be disposed above the second capacitor electrode CE2 and the third capacitor electrode CE3. The first capacitor electrode CE1, together with the second capacitor electrode CE2, may constitute a storage capacitor Cst. The first capacitor electrode CE1 may perform the function of the fourth capacitor electrode described above and may, together with the third capacitor electrode CE3, constitute a holding capacitor Chold. For example, the first capacitor electrode CE1 and the fourth capacitor electrode may be as follows: Figure 11 The integrated conductive layer shown.

[0129] The first capacitor electrode CE1 can be electrically connected to the lower capacitor electrode BML1 located at the bottom via a contact hole. For example, the lower capacitor electrode BML1 can be used together with the first capacitor electrode CE1 as a capacitor electrode for storing capacitor Cst and a capacitor electrode for holding capacitor Chold.

[0130] The first capacitor electrode CE1 can be integrally formed with the fourth connection electrode BE4. The fourth connection electrode BE4 can be a protrusion extending from one side of the first capacitor electrode CE1. The first capacitor electrode CE1 can be electrically connected to the first voltage line VDL through the fourth connection electrode BE4. As described above, the first capacitor electrode CE1 can electrically connect the capacitor electrode holding the capacitor Chold, the capacitor electrode storing the capacitor Cst, and the driving transistor T1 to each other. The first capacitor electrode CE1 can be understood as serving as... Figure 3 The second node N2 (which is the source node).

[0131] The first capacitor electrode CE1 can have a symmetrical structure relative to the second direction DR2. For example, the fourth connection electrode BE4 can be offset from the center of the first capacitor electrode CE1, and the fourth connection electrode BE4 of the first pixel PXA and the fourth connection electrode BE4 of the second pixel PXB can be symmetrically arranged with respect to the imaginary line L1. For example, if the fourth connection electrode BE4 of the first pixel PXA is located to the left of the first capacitor electrode CE1, the fourth connection electrode BE4 of the second pixel PXB can be located to the right of the first capacitor electrode CE1.

[0132] The first connecting electrode BE1, the second connecting electrode BE2, the third connecting electrode BE3, the fourth connecting electrode BE4, the fifth connecting electrode BE5, the sixth connecting electrode BE6, the seventh connecting electrode BE7, and the eighth connecting electrode BE8 can be disposed in each of the first pixel PXA and the second pixel PXB. The ninth connecting electrode BE9 can be further disposed in the second pixel PXB.

[0133] One side of the first connection electrode BE1 can be electrically connected to the second gate electrode layer GP2 through a contact hole. The other side of the first connection electrode BE1 can be electrically connected to the first scan signal line SL1 through a contact hole. For example, the first connection electrode BE1 can electrically connect the first scan signal line SL1 to the switching transistor T2.

[0134] As described above, the first scan signal line SL1 can have a dual wiring structure consisting of a first-1 scan signal line SL1-1 and a first-2 scan signal line SL1-2. The first-1 connection electrode BE1-1 of the first pixel PXA can be electrically connected to either the first-1 scan signal line SL1-1 or the first-2 scan signal line SL1-2. The first-2 connection electrode BE1-2 of the second pixel PXB can also be electrically connected to either the first-1 scan signal line SL1-1 or the first-2 scan signal line SL1-2. The first-1 connection electrode BE1-1 and the first-2 connection electrode BE1-2 can be asymmetrically arranged relative to the imaginary line L1 or the data line DTL.

[0135] One side of the second connection electrode BE2 can be electrically connected to the reference voltage line RFL through a contact hole. The other side of the second connection electrode BE2 can be electrically connected to one side of the reference voltage drain region (drain region) D3 of the semiconductor layer AP through a contact hole. For example, the second connection electrode BE2 can electrically connect the reference voltage line RFL to the reference voltage transistor T3. The second-1 connection electrode BE2-1 of the first pixel PXA and the second-2 connection electrode BE2-2 of the second pixel PXB can be asymmetrically arranged relative to the imaginary line L1 or the data line DTL.

[0136] One side of the third connection electrode BE3 can be electrically connected to the second scan signal line SL2 through a contact hole. The other side of the third connection electrode BE3 can be electrically connected to the third gate electrode layer GP3 through a contact hole. For example, the third connection electrode BE3 can electrically connect the second scan signal line SL2 to the gate electrode of the reference voltage transistor T3. The third-1 connection electrode BE3-1 of the first pixel PXA and the third-2 connection electrode BE3-2 of the second pixel PXB can be asymmetrically arranged relative to the imaginary line L1 or the data line DTL.

[0137] The first connecting electrode BE1, the second connecting electrode BE2, and the third connecting electrode BE3 can be disposed in the asymmetric region NFA of the first pixel PXA and the second pixel PXB. The second electrode 210 disposed in the asymmetric region NFA of the first pixel PXA and the second pixel PXB (see...) Figure 14 The second electrode 210 can be asymmetrically arranged relative to the imaginary line L1. The second electrode 210 may include a first connecting electrode BE1, a second connecting electrode BE2, and a third connecting electrode BE3.

[0138] At least one of the second electrodes 210 may be disposed between the first scan signal line SL1 and the first capacitor electrode CE1. For example, the third connecting electrode BE3 of the second electrodes 210 may be disposed between the first scan signal line SL1 and the first capacitor electrode CE1.

[0139] Meanwhile, in order to enable the first pixel PXA and the second pixel PXB to share the data line DTL, the first electrode 110 of the second pixel PXB (see...) Figure 14 It may also include a ninth connection electrode BE9. One side of the ninth connection electrode BE9 can be electrically connected to the data line DTL through a contact hole, and the other side of the ninth connection electrode BE9 can be electrically connected to one side of the switch drain region (drain region) D2 of the semiconductor layer AP through a contact hole. For example, the ninth connection electrode BE9 can electrically connect the data line DTL to the switching transistor T2.

[0140] One side of the fifth connection electrode BE5 can be electrically connected to the first voltage line VDL through a contact hole, and the other side of the fifth connection electrode BE5 can be electrically connected to the operation control drain region (drain region) D5 of the semiconductor layer AP through a contact hole. For example, the fifth connection electrode BE5 can connect the first voltage line VDL to the operation control transistor T5.

[0141] One side of the sixth connecting electrode BE6 can be electrically connected to the second voltage line VSL through a contact hole, and the other side of the sixth connecting electrode BE6 can be connected between the initialization source region (source region) S4 and the emitter control drain region (drain region) D6 of the semiconductor layer AP through a contact hole.

[0142] One side of the seventh connection electrode BE7 can be electrically connected to the first gate electrode layer GP1 through a contact hole, and the other side of the seventh connection electrode BE7 can be connected between the switch source region S2 (source region) and the reference voltage source region S3 through a contact hole.

[0143] One side of the eighth connection electrode BE8 can be electrically connected to the initialization voltage line VIL through a contact hole, and the other side of the eighth connection electrode BE8 can be electrically connected to one side of the initialization drain region (drain region) D4 of the semiconductor layer AP through a contact hole. For example, the eighth connection electrode BE8 can electrically connect the initialization voltage line VIL to the initialization transistor T4.

[0144] The fifth connecting electrode BE5, the sixth connecting electrode BE6, the seventh connecting electrode BE7, and the eighth connecting electrode BE8 can be disposed in the symmetrical region FA of the first pixel PXA and the second pixel PXB. The first electrode 110 disposed in the symmetrical region FA of the first pixel PXA and the second pixel PXB can be symmetrically disposed with respect to the imaginary line L1. The first electrode 110 may include the fifth connecting electrode BE5, the sixth connecting electrode BE6, the seventh connecting electrode BE7, and the eighth connecting electrode BE8.

[0145] At least one of the first electrodes 110 may be disposed between the first capacitor electrode CE1 and the initialization voltage line VIL. For example, the fifth connecting electrode BE5 of the first electrodes 110 may be disposed between the first capacitor electrode CE1 and the initialization voltage line VIL.

[0146] The second conductive layer may include a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive material. For example, the second conductive layer may include silver (Ag), Ag-containing alloys, molybdenum (Mo), Mo-containing alloys, aluminum (Al), Al-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). For example, the second conductive layer may have approximately... Thick titanium layer, approximately Thick aluminum layer and approximately A multilayer structure with a thick titanium layer. The second conductive layer can also be called the source / drain layer.

[0147] Planarization layer 107 may be disposed on third insulating layer 105 and may cover second conductive layer. Planarization layer 107 may include organic insulating material. For example, planarization layer 107 may include photoresist, benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers (such as polyimide), aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or any mixture thereof. For example, planarization layer 107 may include a polyimide layer having a thickness of approximately 1.6 μm.

[0148] An organic light-emitting diode (OLED) can be disposed on a planarization layer 107. The OLED may include a pixel electrode 310, an intermediate layer 320 containing an emission layer, and a counter electrode 330.

[0149] The pixel electrode 310 can be a transmissive (or semi-transmissive) electrode or a reflective electrode. For example, the pixel electrode 310 may include a reflective layer and a transparent or semi-transparent electrode layer disposed on the reflective layer. The reflective layer may include Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or any compound thereof. The transparent or semi-transparent electrode layer may include at least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). For example, the pixel electrode 310 may have a three-layer structure of ITO / Ag / ITO.

[0150] The pixel defining layer 109 can be disposed on the planarization layer 107. The pixel defining layer 109 can prevent electric arcs or the like from occurring at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the opposite electrode 330 on the pixel electrode 310. The pixel defining layer 109 may include at least one organic insulating material selected from polyimide, polyamide, acrylic resin, benzocyclobutene (BCB), and phenolic resin, and can be formed by spin coating or the like.

[0151] At least a portion of the intermediate layer 320 of the organic light-emitting diode (OLED) can be disposed within an opening formed by the pixel defining layer 109. The emission region of the OLED can be defined by the opening.

[0152] The intermediate layer 320 may include an emission layer. The emission layer may include an organic material comprising a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emission layer may include a low-molecular-weight organic material or a high-molecular-weight organic material. Functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may optionally be further disposed below and above the emission layer.

[0153] The emission layer may have a patterned shape corresponding to the patterned shape of each of the pixel electrodes 310. Layers included in the intermediate layer 320 other than the emission layer may be modified differently. For example, these layers may be integrally formed across the pixel electrodes 310.

[0154] The relative electrode 330 can be a transmissive electrode or a reflective electrode. For example, the relative electrode 330 can be a transparent or translucent electrode and can include a metal thin film having a low work function and containing Li, Ca, LiF, Al, Ag, Mg, or any compound thereof. The relative electrode 330 may also include a transparent conductive oxide (TCO) layer (such as an ITO layer, IZO layer, ZnO layer, or In2O3 layer) disposed on the metal thin film. The relative electrode 330 can be integrally formed in the entire display area DPA and disposed above the intermediate layer 320 and the pixel defining layer 109.

[0155] As described above, the driving transistor T1, etc., can be an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET) comprising an oxide semiconductor material. For example, the brightness of an organic light-emitting diode (OLED) can be determined based on the potential difference between the driving gate electrode G1 of the driving transistor T1 and the second node N2, which serves as the source region. The second node N2 may be affected by the capacitance Cp formed between the electrodes in the peripheral region, which may cause brightness deviations in the OLED.

[0156] Simultaneously, the first pixel PXA and the second pixel PXB may include pixel circuit elements symmetrically arranged throughout the region with respect to the imaginary line L1 to share the data line DTL. For example, in the event of a coverage deviation in the gate layer, which serves as the first conductive layer GP, all pixel circuit elements included in the gate layer may shift in one direction. If the gate layer shifts to the left, the distance between the second node N2 in the first pixel PXA and the first conductive layer GP may decrease, and the distance between the second node N2 in the second pixel PXB and the first conductive layer GP may increase. In contrast, if the gate layer shifts to the right, the distance between the second node N2 in the first pixel PXA and the first conductive layer GP may increase, and the distance between the second node N2 in the second pixel PXB and the first conductive layer GP may decrease. For example, if the pixel circuit elements are symmetrically arranged in the first pixel PXA and the second pixel PXB throughout the region, the first pixel PXA and the second pixel PXB may emit light with different brightness due to the coverage deviation, which ultimately leads to a degradation in the quality of the displayed image.

[0157] However, as described above, in the display device 10 according to this embodiment, the first pixel PXA and the second pixel PXB may include a symmetrical region FA and an asymmetrical region NFA. The first electrode 110 disposed in the symmetrical region FA may be symmetrically disposed with respect to the imaginary line L1, and the second electrode 210 disposed in the asymmetrical region NFA may be asymmetrically disposed with respect to the imaginary line L1, thereby preventing or minimizing the brightness deviation between the first pixel PXA and the second pixel PXB. Therefore, the display device 10 according to this embodiment can display high-quality images.

[0158] Figure 12 This is a schematic layout diagram showing a portion of an area including a first pixel PXA and a second pixel PXB in the display area of ​​a display device 10-2 according to another embodiment. Figure 13 and Figure 14 It is shown on the basis of layers Figure 12 The display device 10-2 shown includes thin-film transistors T1 to T6 (see...) Figure 3 Storage capacitor Cst (see) Figure 3 ) and holding capacitor Chold (see Figure 3 A schematic layout diagram of the components. For layout diagrams based on layers, Figure 13 The bottom metal layer BML' is shown, and Figure 14 The second conductive layer is shown. The semiconductor layer AP and the first conductive layer GP are shown in the reference above. Figures 7 to 11 The semiconductor layer AP and the first conductive layer GP are described as being the same, and therefore, their redundant descriptions are omitted.

[0159] exist Figures 12 to 14 In the first direction DR1, the two sides can be referred to as the left and right sides, and the two sides in the second direction DR2 can be referred to as the upper and lower sides. For ease of explanation, Figures 12 to 14 Also shown is a portion of another pixel located below the first pixel PXA and the second pixel PXB (or on the other side in the second direction DR2). The first pixel PXA and the second pixel PXB can correspond to Figures 12 to 14 Any of the areas shown are those surrounded by alternating long and short dashed lines, and the other areas may correspond to a portion of another pixel PX adjacent to the first pixel PXA and the second pixel PXB in the second direction DR2. In the following, the accompanying drawings shown to describe each of the pixels PX can be understood in the same manner as described above.

[0160] refer to Figures 12 to 14 According to another embodiment, the display device 10-2 may include a plurality of pixels PX (see Figure 1 Each of the multiple pixels (PX) may include at least one organic light-emitting diode (LD) (see [link]). Figure 3 ) and pixel circuit elements for driving at least one organic light-emitting diode (LD).

[0161] According to another embodiment, the display device 10-2 may include a plurality of pixels PX in which pixel circuit elements are arranged differently. The display device 10-2 may include a first pixel PXA and a second pixel PXB, and the arrangement of the pixel circuit elements in the first pixel PXA may be different from the arrangement of the pixel circuit elements in the second pixel PXB.

[0162] The first pixel PXA and the second pixel PXB can be arranged adjacent to each other in the first direction DR1, and can include a symmetrical region FA that is symmetrically arranged with respect to the imaginary line L1 pixel circuit element located at the boundary between the first pixel PXA and the second pixel PXB, and an asymmetrical region NFA that is asymmetrically arranged with respect to the imaginary line L1 pixel circuit element located at the boundary between the first pixel PXA and the second pixel PXB.

[0163] First pixel PXA and second pixel PXB can share a data line DTL. The data line DTL can be located at the boundary between the first pixel PXA and the second pixel PXB, can extend in the second direction DR2, and can be positioned along an imaginary line L1. To enable the first pixel PXA and second pixel PXB to share the data line DTL, a symmetrical region FA, which is part of the pixel circuit elements in each of the first pixel PXA and second pixel PXB, can have a symmetrical arrangement structure relative to the data line DTL. An asymmetrical region NFA, which is another part of the pixel circuit elements in each of the first pixel PXA and second pixel PXB, can have an asymmetrical arrangement structure relative to the data line DTL.

[0164] Connect to the second node N2, which is the source node (see...) Figure 3 The first capacitor electrode CE1' can be located in the symmetrical region FA. The asymmetrical region NFA can be a region adjacent to the symmetrical region FA. Connected to the first node N1 (see [link to relevant documentation]) which serves as the gate node. Figure 3 The switching transistor T2 can be disposed in the asymmetric region NFA. A capacitance Cp can be formed between the first capacitor electrode CE1' and the first switching gate electrode GP2-1 of the switching transistor T2. Because the pixel circuit elements are asymmetrically disposed adjacent to the source node, the display device 10-2 according to another embodiment can maintain a constant capacitance Cp even when an overlay deviation occurs.

[0165] A display device 10-2 according to another embodiment may include a first electrode 110 and a second electrode 210 disposed in each of a first pixel PXA and a second pixel PXB. The first electrode 110 may be symmetrically disposed with respect to an imaginary line L1 disposed at the boundary between the first pixel PXA and the second pixel PXB and extending in a second direction DR2 different from the first direction DR1. The second electrode 210 may be asymmetrically disposed with respect to the imaginary line L1. For example, one of the first electrodes 110 of the display device 10-2 according to another embodiment may have a symmetrical shape with respect to the second direction DR2.

[0166] For example, the first capacitor electrode CE1' included in the first electrode 110 may have a symmetrical shape relative to the second direction DR2. As described above, the first capacitor electrode CE1' can electrically connect the capacitor electrode holding the capacitor Chold, the capacitor electrode storing the capacitor Cst, and the driving transistor T1 to each other, and can be used as... Figure 3The second node N2 (which is the source node). The first capacitor electrode CE1' can have a symmetrical shape with respect to a line passing through the center of the first capacitor electrode CE1' and parallel to the second direction DR2. Therefore, the first capacitor electrode CE1' can prevent or minimize the coverage deviation with the electrodes of other layers disposed in the peripheral region.

[0167] like Figure 13 As shown, the bottom metal layer BML' may include a first lower scan signal line SL11, a reference voltage line RFL, a second scan signal line SL2, a lower capacitor electrode BML1', a first voltage line VDL, a second voltage line VSL, a first initialization voltage line VIL, and a second initialization voltage line VIL2. Among these, the lower capacitor electrode BML1' may be disposed below the first capacitor electrode CE1' and may have a structure surrounding the first capacitor electrode CE1'. For example, the lower capacitor electrode BML1' may be larger than the outer side of the first capacitor electrode CE1' (e.g., the lower capacitor electrode BML1' may surround the outer contour of the first capacitor electrode CE1') and may have a symmetrical rectangular shape, such as... Figure 13 As shown in the figure. This disclosure is not limited thereto, and the lower capacitor electrode BML1' may have a structure surrounding the first capacitor electrode CE1' and any structure having a symmetrical shape relative to a line passing through the center of the lower capacitor electrode BML1' and parallel to the second direction DR2.

[0168] like Figure 6 As shown, the first conductive layer GP (see Figure 9 It can be disposed on the second insulating layer 104. Figure 12 In this configuration, the first conductive layer GP may include a first upper scan signal line SL12, a first gate electrode layer GP1, a second gate electrode layer GP2, a third gate electrode layer GP3, an operation control signal line ECL, an emit control signal line ECL2, and a third scan signal line SL3. The first conductive layer GP may also be referred to as the gate layer.

[0169] In the first capacitor electrode CE1' of the first conductive layer GP, the shape of the region adjacent to the fourth connecting electrode BE4 can be different. Figure 11 The shape of the first capacitor electrode CE1. Similar to the lower capacitor electrode BML1', the shape of the first capacitor electrode CE1' is not limited to the shape shown (e.g., a rectangular shape), and the first capacitor electrode CE1' can have any structure with a symmetrical shape relative to the second direction DR2.

[0170] Figure 15 and Figure 16This is a schematic layout diagram illustrating a portion of an area including a first pixel PXA and a second pixel PXB in a display area of ​​a display device according to another embodiment. For convenience, Figure 15 and Figure 16 Only the semiconductor layer AP is shown (see Figure 8 It is a part of the first conductive layer GP and a part of the second conductive layer. Figure 15 and Figure 16 In display devices 10-3 and 10-4, multiple thin-film transistors can be P-channel MOSFETs (PMOS).

[0171] refer to Figure 15 and Figure 16 According to another embodiment, display devices 10-3 and 10-4 may include a plurality of pixels PX (see Figure 1 Each of the plurality of pixels (PX) may include at least one organic light-emitting diode (OLED) and pixel circuitry elements for driving the at least one OLED. Each of the pixels (PX) may include a plurality of thin-film transistors (see [link to relevant documentation]). Figure 3 Multiple thin-film transistors T1 to T6), storage capacitor Cst (see Figure 3 ) and holding capacitor Chold (see Figure 3 ) as pixel circuit elements. Each of the pixels PX can be electrically connected to the data line DTL (see Figure 3 ), scan signal line SL (see Figure 2 ), Operation control signal line ECL (see Figure 3 ), transmit control signal line ECL2 (see Figure 3 ), first voltage line VDL (see Figure 3 ), second voltage line VSL (see Figure 3 ), reference voltage line RFL (see Figure 3 ) and initialization voltage line VIL (see Figure 3 ).

[0172] Display devices 10-3 and 10-4 may include a plurality of pixels PX in which pixel circuit elements are arranged differently. Display devices 10-3 and 10-4 may include a first pixel PXA and a second pixel PXB, and the arrangement of pixel circuit elements in the first pixel PXA may differ from the arrangement of pixel circuit elements in the second pixel PXB.

[0173] The first pixel PXA and the second pixel PXB can be arranged adjacent to each other in the first direction DR1, and can include a symmetrical region FA that is symmetrically arranged with respect to the imaginary line L1 pixel circuit element located at the boundary between the first pixel PXA and the second pixel PXB, and an asymmetrical region NFA that is asymmetrically arranged with respect to the imaginary line L1 pixel circuit element located at the boundary between the first pixel PXA and the second pixel PXB.

[0174] Figure 15 The display device 10-3 illustrates a case where the first pixel PXA and the second pixel PXB do not share a data line DTL with each other; for example, each pixel includes its own separate data line DTL. Figure 16 The display device 10-4 shows a case where the first pixel PXA and the second pixel PXB share the data line DTL.

[0175] When multiple thin-film transistors are PMOS, unlike NMOS, the pixel circuit elements disposed around the first gate electrode layer GP1, which serves as the gate node, can be disposed asymmetrically with respect to the imaginary line L1, and the pixel circuit elements disposed in other regions can be disposed symmetrically. When multiple thin-film transistors are PMOS, the capacitance may vary depending on the coverage deviation between the first gate electrode layer GP1 and the semiconductor layer AP disposed around it. Therefore, display devices 10-3 and 10-4 can asymmetrically dispose of the pixel circuit elements in the asymmetrical region NFA, which is the peripheral region of the first gate electrode layer GP1, and symmetrically dispose of the pixel circuit elements in the symmetrical region FA, which is another region.

[0176] like Figure 15 As shown, the semiconductor layer AP may include a seventh semiconductor pattern AP7, an eighth semiconductor pattern AP8, and a ninth semiconductor pattern AP9 that are separated from each other. For ease of illustration, only the seventh semiconductor pattern AP7, the eighth semiconductor pattern AP8, and the ninth semiconductor pattern AP9 are shown, but other semiconductor patterns may also be included.

[0177] The seventh semiconductor pattern AP7 and the eighth semiconductor pattern AP8 can be disposed asymmetrically in the asymmetric region NFA with respect to the imaginary line L1. The eighth semiconductor pattern AP8 can extend across the first scan signal line SL1 to the symmetric region FA. For example, the eighth-1 semiconductor pattern AP8-1 extending from the first pixel PXA and the eighth-2 semiconductor pattern AP8-2 extending from the second pixel PXB can be electrically connected to the ninth semiconductor pattern AP9 in the symmetric region FA.

[0178] The ninth semiconductor pattern AP9 can be set at a position overlapping with the imaginary line L1, so as to be symmetrically arranged with respect to the imaginary line L1.

[0179] The second conductive layer may include a first electrode 110 and a second electrode 210. The first electrode 110 may be disposed in the first pixel PXA and the second pixel PXB, respectively, and may be symmetrically disposed with respect to the imaginary line L1. The second electrode 210 may be disposed in the first pixel PXA and the second pixel PXB, respectively, and may be asymmetrically disposed with respect to the imaginary line L1. For example, the first electrode 110 may be disposed in the symmetrical region FA, and the second electrode 210 may be disposed in the asymmetrical region NFA. For ease of illustration, only one first electrode 110 and only one second electrode 210 are shown, but it is obvious that other conductive patterns may also be included.

[0180] like Figure 16 As shown, the display device 10-4 is a case where the first pixel PXA and the second pixel PXB share a data line DTL. The data line DTL can be set at the boundary between the first pixel PXA and the second pixel PXB, can extend in the second direction DR2, and can be set along the imaginary line L1.

[0181] The seventh semiconductor pattern AP7 and the eighth semiconductor pattern AP8 can be disposed asymmetrically in the asymmetric region NFA with respect to the imaginary line L1. The eighth semiconductor pattern AP8 can extend across the first scan signal line SL1 to the symmetric region FA. For example, the eighth-1 semiconductor pattern AP8-1 extending from the first pixel PXA and the eighth-2 semiconductor pattern AP8-2 extending from the second pixel PXB can be electrically connected to the ninth semiconductor pattern AP9 in the symmetric region FA.

[0182] For example, the ninth semiconductor pattern AP9 can be separate from the data line DTL. The first pixel PXA and the second pixel PXB can include the ninth semiconductor pattern AP9, which is connected to the eighth-1 semiconductor pattern AP8-1 and the eighth-2 semiconductor pattern AP8-2, respectively. The ninth semiconductor pattern AP9 of the first pixel PXA and the ninth semiconductor pattern AP9 of the second pixel PXB can be positioned symmetrically with respect to the imaginary line L1.

[0183] Figure 17 This is a schematic block diagram illustrating a display system 1000 according to an embodiment. Figure 18 This is a schematic diagram illustrating an example of a smartwatch 2000 including a display device according to an embodiment. Reference Figure 17 The display system 1000 may include a processor 1100 and a display device 1200.

[0184] Processor 1100 can perform various tasks and calculations. Processor 1100 may include application processors, graphics processors, microprocessors, and central processing units (CPUs), etc. Processor 1100 can be electrically connected to other components of display system 1000 via a bus system to control other components.

[0185] Processor 1100 can transmit image data IMG and control signal CTRL to display device 1200. Display device 1200 can display an image based on image data IMG and control signal CTRL. Display device 1200 can be connected to a reference... Figure 1 The described display device 10 is similarly configured.

[0186] Display system 1000 may include computing systems that provide image display capabilities, such as smartwatches, mobile phones, smartphones, portable computers, tablet PCs, watch phones, car displays, smart glasses, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). Display system 1000 may include at least one of head-mounted display (HMD) devices, virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0187] refer to Figure 18 , Figure 17 The display system 1000 can be applied to a smartwatch 2000, which includes a display unit 2100 and a belt unit 2200.

[0188] The smartwatch 2000 can be a wearable electronic device. For example, the smartwatch 2000 can have a structure in which the strap unit 2200 is mounted on the user's wrist. Here, the display system 1000 and / or display device 1200 can be applied to the display unit 2100 and can provide the user with image data including time information.

[0189] In the display device 1200 according to this embodiment, pixel circuit elements may be arranged asymmetrically with respect to the imaginary line in the first pixel PXA (see...). Figure 4 ) and the second pixel PXB (see Figure 4 Around the gate node of the first pixel PXA, the brightness deviation between the first pixel PXA and the second pixel PXB is prevented or minimized. Therefore, the display device 1200 according to this embodiment can display high-quality images.

[0190] Each of the embodiments described above can be implemented independently, but it is obvious that the structure of each of the embodiments can be applied to other embodiments in combination.

[0191] This disclosure has been described with reference to embodiments shown in the accompanying drawings, but these are merely examples. It will be understood by those skilled in the art that various modifications and equivalents can be made thereto. Therefore, the true technical scope of this disclosure should be defined by the technical spirit of the appended claims.

[0192] The specific implementation described in the embodiments is one embodiment and does not limit the scope of the embodiments in any way. Unless specifically mentioned with terms such as "necessary" or "important," it may not be an essential component for the application of this disclosure.

[0193] The use of the term "described" and similar designations in the description of embodiments (especially the claims) should be interpreted to cover both the singular and plural. Where a scope is described in the embodiments, (unless otherwise indicated herein) it includes the individual values ​​within that scope to which the invention applies. This is the same as stating each individual value constituting the above scope in the detailed description. Finally, unless otherwise indicated herein or clearly contradicted by the context, the operations constituting the method according to the embodiments can be performed in any suitable order. The embodiments are not necessarily limited by the order in which the operations are described. Unless otherwise required, any examples provided in the embodiments and all use of example or example terminology are intended only to describe the embodiments in detail, and the scope of the embodiments is not limited by example or example terminology. Furthermore, those skilled in the art will understand that various modifications, combinations, and changes can be made based on the design conditions and factors within the scope of the appended claims or their equivalents.

[0194] A display device according to one or more embodiments includes symmetrical and asymmetrical regions of pixel circuit elements, thereby preventing or minimizing brightness deviation between a first pixel and a second pixel. Therefore, the display device according to this embodiment can display high-quality images.

[0195] However, the effects of this disclosure are not limited to those described above, and can be extended in various ways without departing from the spirit and scope of this disclosure.

[0196] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended to be limiting. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, wherein, The display device includes: The first pixel and the second pixel are set adjacent to each other in a first direction; Multiple first electrodes are disposed in each of the first pixel and the second pixel; and A plurality of second electrodes are disposed in each of the first pixel and the second pixel and are separate from the corresponding plurality of first electrodes. Wherein, the plurality of first electrodes in the first pixel and the plurality of first electrodes in the second pixel are symmetrically arranged with respect to an imaginary line disposed at the boundary between the first pixel and the second pixel and extending in a second direction different from the first direction, and The plurality of second electrodes in the first pixel and the plurality of second electrodes in the second pixel are arranged asymmetrically with respect to the imaginary line.

2. The display device according to claim 1, wherein, The display device further includes a data line disposed at the boundary between the first pixel and the second pixel, extending in the second direction and along the imaginary line.

3. The display device according to claim 2, wherein, The plurality of first electrodes, the plurality of second electrodes, and the data line comprise the same conductive material.

4. The display device according to claim 1, wherein, In each of the first pixel and the second pixel, one of the plurality of first electrodes is a first capacitor electrode.

5. The display device according to claim 4, wherein, The first capacitor electrode has a symmetrical structure with respect to the second direction.

6. The display device according to claim 4, wherein, The display device further includes a first scan signal line extending in the first direction, crossing the first pixel and the second pixel, and electrically connected to one of the plurality of second electrodes of each of the first pixel and the second pixel. In each of the first pixel and the second pixel, at least one of the plurality of second electrodes is disposed between the first scan signal line and the first capacitor electrode.

7. The display device according to claim 6, wherein, The first scan signal line includes a first-1 scan signal line extending in the first direction and a first-2 scan signal line parallel to the first-1 scan signal line.

8. The display device according to claim 6, wherein, The display device further includes a lower capacitor electrode that overlaps with the first capacitor electrode. The lower capacitor electrode and the first scan signal line are made of the same material.

9. The display device according to claim 8, wherein, The lower capacitor electrode disposed in the first pixel and the lower capacitor electrode disposed in the second pixel are symmetrically disposed with respect to the imaginary line.

10. The display device according to claim 8, wherein, The lower capacitor electrode has a symmetrical structure with respect to the second direction.

11. The display device according to claim 4, wherein, The display device further includes an initialization voltage line that extends in the first direction and crosses the first pixel and the second pixel. In each of the first pixel and the second pixel, at least one of the plurality of first electrodes is disposed between the first capacitor electrode and the initialization voltage line.

12. The display device according to claim 4, wherein, The display device further includes a first capacitor disposed in each of the first pixel and the second pixel. The first capacitor includes a first capacitor electrode and a second capacitor electrode that overlaps with the first capacitor electrode.

13. The display device according to claim 12, wherein, The display device further includes a second capacitor disposed in each of the first pixel and the second pixel. The second capacitor includes a third capacitor electrode and a fourth capacitor electrode that overlaps with the third capacitor electrode. The fourth capacitor electrode is integrally formed with the first capacitor electrode.

14. A display device, wherein, The display device includes: The first pixel and the second pixel are set adjacent to each other in a first direction; A driving transistor, disposed in each of the first pixel and the second pixel, the driving transistor including a driving gate electrode; and A switching transistor is disposed in each of the first pixel and the second pixel and electrically connected to the corresponding driving transistor, the switching transistor including a switching gate electrode. Wherein, the driving gate electrode of the first pixel and the driving gate electrode of the second pixel are symmetrically arranged with respect to an imaginary line disposed at the boundary between the first pixel and the second pixel and extending in a second direction different from the first direction, and The switching gate electrode of the first pixel and the switching gate electrode of the second pixel are arranged asymmetrically with respect to the imaginary line.

15. The display device according to claim 14, wherein, The display device further includes a first electrode disposed in each of the first pixel and the second pixel and overlapping with the corresponding driving gate electrode. The first electrode of the first pixel and the first electrode of the second pixel are symmetrically arranged with respect to the imaginary line.

16. The display device according to claim 15, wherein, The first electrode has a symmetrical structure with respect to the second direction.

17. The display device according to claim 14, wherein, In each of the first pixel and the second pixel, the driving transistor includes a driving semiconductor layer. The switching transistor includes a switching semiconductor layer, and Each of the driving semiconductor layer and the switching semiconductor layer comprises an oxide semiconductor material.

18. The display device according to claim 14, wherein, In each of the first pixel and the second pixel, the driving transistor includes a driving semiconductor layer. The switching transistor includes a switching semiconductor layer, and Each of the driving semiconductor layer and the switching semiconductor layer comprises an N-type semiconductor.

19. The display device according to claim 14, wherein, The display device further includes an operation control transistor disposed in each of the first pixel and the second pixel and electrically connected to the corresponding driving transistor. The operation control transistor includes an operation control gate electrode. The operation control gate electrode of the first pixel and the operation control gate electrode of the second pixel are symmetrically arranged with respect to the imaginary line.

20. An electronic device, wherein, The electronic device includes: Display device; and The display device includes: The first pixel and the second pixel are set adjacent to each other in a first direction; A first electrode is disposed in each of the first pixel and the second pixel; and A second electrode is disposed in each of the first pixel and the second pixel and is separate from the corresponding first electrode. The first electrode in the first pixel and the first electrode in the second pixel are symmetrically arranged with respect to an imaginary line disposed at the boundary between the first pixel and the second pixel and extending in a second direction different from the first direction. The second electrode in the first pixel and the second electrode in the second pixel are arranged asymmetrically with respect to the imaginary line.

Images