Display device and electronic device including the same

Abstract

The invention discloses a display device and an electronic device including the same. The display device includes: a substrate including a display area and a peripheral area surrounding the display area; a sub-pixel disposed on the substrate in the display area; a first blocking structure disposed on the substrate in the peripheral region and arranged along an edge of the substrate in a plan view to block crack propagation; a second blocking structure disposed on the substrate in the peripheral area and disposed between the display area and the first blocking structure in a plan view to block moisture; and a crack detection structure disposed on the substrate in the peripheral region and disposed between the display region and the second barrier structure in a plan view, the crack detection structure comprises a lower circuit layer arranged on the substrate, a middle circuit layer arranged on the lower circuit layer and comprising a crack detection line, and an upper circuit layer arranged on the middle circuit layer.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to display devices. More specifically, the embodiments of this disclosure relate to display devices that provide visual information and electronic devices including the display devices. Background Technology

[0002] With the development of information technology, the importance of display devices as the connection medium between users and information has become increasingly prominent. For example, display devices such as liquid crystal displays (LCDs), organic light-emitting diode (OLEDs), plasma display panels (PDPs), or quantum dot displays are widely used in various fields. Summary of the Invention

[0003] Generally, multiple display panels can be formed on a mother substrate, and these panels can be separated into individual display panels through a dicing process. During the dicing of the mother substrate, cracks may appear in the display panels.

[0004] The embodiments provide a display device including a detection structure for detecting cracks.

[0005] The embodiments provide an electronic device including a display device.

[0006] A display device according to an embodiment of the present disclosure includes: a substrate including a display area and a peripheral area surrounding the display area; a plurality of sub-pixels disposed on the substrate and in the display area; a first blocking structure disposed on the substrate and in the peripheral area and arranged along the edge of the substrate in a plan view, wherein the first blocking structure blocks crack propagation; a second blocking structure disposed on the substrate and in the peripheral area and arranged between the display area and the first blocking structure in a plan view, wherein the second blocking structure blocks moisture; and a crack detection structure disposed on the substrate and in the peripheral area and arranged between the display area and the second blocking structure in a plan view, wherein the crack detection structure includes: a lower circuit layer disposed on the substrate; an intermediate circuit layer disposed on the lower circuit layer and including crack detection lines; and an upper circuit layer disposed on the intermediate circuit layer.

[0007] In an embodiment, the crack detection structure may be spaced apart from the first blocking structure and the second blocking structure.

[0008] In one embodiment, the second blocking structure may surround the crack detection structure in a plan view, and the first blocking structure may surround the second blocking structure in a plan view.

[0009] In one embodiment, the display device may further include a crack detection circuit disposed on the substrate in a peripheral region. In such an embodiment, the crack detection line may include: a first crack detection line receiving a test voltage; and a second crack detection line, wherein a first end of the second crack detection line is electrically connected to the first crack detection line, and a second end of the second crack detection line opposite to the first end is electrically connected to the crack detection circuit. In such an embodiment, the second crack detection line may be disposed on the first crack detection line.

[0010] In one embodiment, the crack detection structure may include a first to an eighth circuit layer sequentially stacked on a substrate. In such an embodiment, the lower circuit layer may include the first to fourth circuit layers, the middle circuit layers may include the fifth and sixth circuit layers, and the upper circuit layer may include the seventh and eighth circuit layers.

[0011] In one embodiment, the first crack detection line may be disposed in the same layer as the fifth circuit layer, and the second crack detection line may be disposed in the same layer as the sixth circuit layer.

[0012] In this embodiment, the substrate may include a silicon wafer.

[0013] A display device according to an embodiment of the present disclosure includes: a substrate, including a display area and a peripheral area surrounding the display area; a plurality of sub-pixels disposed on the substrate and in the display area; a blocking structure disposed on the substrate and in the peripheral area, and arranged along the edge of the substrate in a plan view to surround the display area; a crack detection structure disposed on the substrate and in the peripheral area, and arranged between the display area and the blocking structure in a plan view, wherein the crack detection structure includes a lower circuit layer disposed on the substrate, an intermediate circuit layer disposed on the lower circuit layer and including crack detection lines, and an upper circuit layer disposed on the intermediate circuit layer; a plurality of pads disposed on the substrate and in the peripheral area, and adjacent to the edge of the substrate in a plan view; a crack detection circuit disposed on the substrate and in the peripheral area, and arranged between the display area and the plurality of pads in a plan view, and electrically connected to the crack detection lines; and a demultiplexing portion disposed on the substrate and in the peripheral area, and arranged between the display area and the crack detection circuit in a plan view.

[0014] In one embodiment, the crack detection line may include a first crack detection line and a second crack detection line for receiving a test voltage, wherein a first end of the second crack detection line is electrically connected to the first crack detection line, and a second end of the second crack detection line opposite to the first end is electrically connected to a crack detection circuit. In such an embodiment, at least one of a plurality of pads may provide the test voltage to the first crack detection line.

[0015] In one embodiment, the second crack detection line may be set on the first crack detection line.

[0016] In an embodiment, the display device may further include: a plurality of fan-out lines disposed on the substrate, in the peripheral region and arranged below the demultiplexed portion in a plan view; and a plurality of data lines disposed on the substrate and in the display region and connected to a plurality of sub-pixels.

[0017] In one embodiment, the crack detection circuit may include: a constant voltage line to which a test voltage is applied; and a detection switch connected to each of the multiple fan-out lines.

[0018] In one embodiment, at least one of the multiple fan-out lines can be electrically connected to the constant voltage line via a detection switch, and at least another of the multiple fan-out lines can be electrically connected to the second crack detection line via a detection switch.

[0019] In one embodiment, the crack detection structure may include a first to an eighth circuit layer sequentially stacked on a substrate. In such an embodiment, the lower circuit layer may include the first to fourth circuit layers. In such an embodiment, the intermediate circuit layers may include a fifth and a sixth circuit layer. In such an embodiment, the upper circuit layer may include a seventh and an eighth circuit layer. In such an embodiment, the first crack detection line may be disposed in the same layer as the fifth circuit layer, and the second crack detection line may be disposed in the same layer as the sixth circuit layer.

[0020] An electronic device according to an embodiment of the present disclosure includes: a display device including a plurality of sub-pixels; and a processor providing image data signals and input control signals to the display device. In such an embodiment, the display device includes: a substrate including a display area and a peripheral area surrounding the display area; a plurality of sub-pixels disposed on the substrate and in the display area; a first blocking structure disposed on the substrate and in the peripheral area and arranged along the edge of the substrate in a plan view, wherein the first blocking structure blocks crack propagation; a second blocking structure disposed on the substrate and in the peripheral area and arranged between the display area and the first blocking structure in a plan view, wherein the second blocking structure blocks moisture; and a crack detection structure disposed on the substrate and in the peripheral area and arranged between the display area and the second blocking structure in a plan view, wherein the crack detection structure includes: a lower circuit layer disposed on the substrate; an intermediate circuit layer disposed on the lower circuit layer and including crack detection lines; and an upper circuit layer disposed on the intermediate circuit layer.

[0021] A display device according to embodiments of the present disclosure may include: a substrate including a display area and a peripheral area surrounding the display area; a blocking structure disposed on the substrate and in the peripheral area, and arranged along the edge of the substrate in a plan view to surround the display area; and a crack detection structure disposed on the substrate and in the peripheral area, and arranged in a plan view between the display area and the blocking structure. In such an embodiment, the crack detection structure may include: a lower circuit layer disposed on the substrate; an intermediate circuit layer disposed on the lower circuit layer and including crack detection lines; and an upper circuit layer disposed on the intermediate circuit layer.

[0022] In such an embodiment, the barrier structure can prevent cracks from propagating toward the display area during the wafer sawing and packaging processes. Furthermore, the barrier structure can prevent moisture from penetrating toward the display area through the scribing lines during the back-side polishing process of the wafer.

[0023] In such an embodiment, the crack detection line can be disposed in the middle circuit layer of the crack detection structure. Therefore, compared with the case where the crack detection line is disposed in the lower or upper circuit layer of the crack detection structure, the crack detection structure can detect cracks that are not blocked by the blocking structure with appropriate or desired crack detection sensitivity. Attached Figure Description

[0024] The illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0025] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0026] Figure 2 The illustration includes Figure 1 A diagram of the crack detection circuit in the display device.

[0027] Figure 3 yes Figure 1 A magnified plan view of region A.

[0028] Figure 4 It is along Figure 3 The cross-sectional view taken from line II-II'.

[0029] Figure 5 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0030] Figure 6 yes Figure 1 A magnified plan view of region B.

[0031] Figure 7 The illustration includes Figure 1Cross-sectional views of the first blocking structure, the second blocking structure, and the crack detection structure in the display device.

[0032] Figure 8 , Figure 9 , Figure 10 and Figure 11 It is a diagram manufacturing process. Figure 1 A view of an embodiment of a method for displaying a device.

[0033] Figure 12 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0034] Figure 13 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0035] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0036] It will be understood that when an element is referred to as being "on" another element, it can be directly on that other element, or there can be an intermediary element between them. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0037] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings herein.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, reference to “a” element followed by reference to “the” element in the claims includes one element and multiple elements. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” is not to be construed as limited to “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprising” and / or variations thereof, or “including” and / or variations thereof, when used in this specification, indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0039] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to also cover different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” of the other elements will be oriented to be “up” of the other elements. Thus, depending on the specific orientation of the drawing, the term “down” can cover both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will be oriented to be “above” the other elements. Thus, the terms “below” or “under” can cover both “up” and “down” orientations.

[0040] Given the measurements discussed and the errors associated with the measured values ​​of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include stated values ​​and refer to a range of acceptable deviations from that particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0041] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0042] The embodiments described herein are illustrated with reference to schematic cross-sectional views of preferred embodiments. Therefore, variations in the illustrated shapes will be expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape, for example, resulting from manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the present claims.

[0043] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and any repeated detailed descriptions of the same parts will be omitted.

[0044] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0045] In this disclosure, the plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. The direction orthogonal to this plane (i.e., the thickness direction of the display device DD) may be a third direction DR3. In other words, the third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2. As used herein, a “plan view” is a view observed on the third direction DR3.

[0046] refer to Figure 1 The display device DD according to embodiments of the present disclosure may include a substrate SUB, pads PD, driver chip D-IC, crack detection circuit MCDC, first crack detection portions M1a and M1b, second crack detection portions M2a and M2b, demultiplexing portion DEM, first gate driver DV1, second gate driver DV2, test array TA, and sub-pixels SPX.

[0047] The display device DD may have a rectangular planar shape. In an embodiment, for example, the display device DD may have a generally rectangular planar shape comprising a short side extending in a first direction DR1 and a long side extending in a second direction DR2. However, this disclosure is not limited thereto, and the planar shape of the display device DD may be varied according to embodiments.

[0048] The substrate SUB may have edges ED including a first side, a second side, a third side, and a fourth side. The first side of the substrate SUB may extend in a first direction DR1. The second side of the substrate SUB may contact the first side and extend in a second direction DR2. The third side of the substrate SUB may contact the second side and may extend parallel to and opposite to the first side. The fourth side of the substrate SUB may contact the first and third sides and may extend parallel to and opposite to the second side.

[0049] The substrate SUB may include a display area DA and a peripheral area PA. The display area DA can be defined as the area that displays an image by generating light or adjusting the transmittance of light provided from an external light source. Subpixels SPX may be arranged (or configured) in the display area DA. Each of the subpixels SPX can be defined as the smallest light-emitting unit capable of displaying light of various colors. Each of the subpixels SPX can generate light based on a drive signal. In an embodiment, for example, the subpixels SPX may be arranged in a matrix along a first direction DR1 and a second direction DR2.

[0050] The lines connected to the sub-pixel SPX can be arranged in the display area DA. In an embodiment, for example, the lines may include data lines (DL, reference) connected to the sub-pixel SPX to provide data voltage. Figure 2 And gate lines connected to sub-pixels SPX to provide gate signals, etc. Each of the data lines may extend in the second direction DR2, and each of the gate lines may extend in the first direction DR1.

[0051] The peripheral region PA may be located around the display region DA. In a plan view (or when viewed in a third-direction DR3), the peripheral region PA may surround at least a portion of the display region DA. In an embodiment, for example, in a plan view, the peripheral region PA may completely surround the display region DA. The peripheral region PA may not display an image.

[0052] The test array TA can be arranged on the substrate SUB, in the peripheral region PA. In an embodiment, for example, the test array TA can be arranged in the peripheral region PA adjacent to the upper side of the display region DA. The test array TA may include test elements for testing the characteristics of the display device DD. In an embodiment, for example, the test array TA may include test elements for testing the characteristics of transistors or test elements for measuring the surface resistance of a semiconductor layer included in a transistor, etc. However, this disclosure is not limited thereto.

[0053] The first gate driver DV1 and the second gate driver DV2 can be arranged on the substrate SUB in the peripheral region PA. In an embodiment, for example, the first gate driver DV1 can be arranged in the peripheral region PA adjacent to the left side of the display region DA, and the second gate driver DV2 can be arranged in the peripheral region PA adjacent to the right side of the display region DA. The first gate driver DV1 and the second gate driver DV2 can provide gate signals to the sub-pixel SPX via gate lines. In an embodiment, one of the first gate driver DV1 and the second gate driver DV2 can be omitted.

[0054] The demultiplexed portion DEM can be arranged on the substrate SUB, within the peripheral region PA. In an embodiment, for example, the demultiplexed portion DEM can be arranged in the peripheral region PA adjacent to the lower side of the display region DA. In a plan view, in an embodiment, the demultiplexed portion DEM can be arranged between the display region DA and the crack detection circuit MCDC.

[0055] In an embodiment, the demultiplexed portion DEM may include a first demultiplexing control line (MCL1, referenced) Figure 2 ), second demultiplexing control line (MCL2, reference) Figure 2 ( ) and demultiplexing switch. Multiple fan-out lines (FOL, reference) Figure 2 This can be placed below the demultiplexing section DEM, and the demultiplexing section DEM can connect one fan-out line and multiple data lines via a demultiplexing switch. See below for reference. Figure 2 Describe its detailed characteristics.

[0056] The driver chip D-IC and pad PD can be disposed on the substrate SUB in the peripheral area PA. In an embodiment, in a plan view, the driver chip D-IC and pad PD can be disposed below the crack detection circuit MCDC. In a plan view, the driver chip D-IC and pad PD can be adjacent to the edge ED of the substrate SUB. The driver chip D-IC can be connected to the pad PD via an anisotropic conductive film. The driver chip D-IC can provide a drive signal to the sub-pixel SPX. The drive signal can include various signals for driving the sub-pixel SPX, such as drive voltage or data voltage. The drive signal can be transmitted to the sub-pixel SPX via the pad PD. In an embodiment, for example, the driver chip D-IC can be a data driver. In an embodiment, for example, at least one of the plurality of pad PDs can transmit a test voltage (VGH, reference) Figure 2 ).

[0057] First crack detection portions M1a and M1b can be arranged on the substrate SUB in the peripheral region PA. The first crack detection portions M1a and M1b can include a first crack detection portion (hereinafter referred to as "Crack 1-1") M1a and a second crack detection portion (hereinafter referred to as "Crack 1-2") M1b. Crack 1-1 M1a can be arranged in the peripheral region PA adjacent to the left and upper sides of the display region DA. Crack 1-2 M1b can be arranged in the peripheral region PA adjacent to the right and upper sides of the display region DA.

[0058] Each of the first crack detection sections M1a and M1b may include a first crack detection line MCD1a_1 or MCD1b_1 and a second crack detection line MCD1a_2 or MCD1b_2. The first end of the first crack detection line MCD1a_1 (or MCD1b_1) may be electrically connected to the pad PD. The first crack detection line MCD1a_1 (or MCD1b_1) can receive a test voltage (VGH, reference) through the pad PD. Figure 2 The second end of the first crack detection line MCD1a_1 (or MCD1b_1), opposite to the first end, can be electrically connected to the first end of the second crack detection line MCD1a_2 (or MCD1b_2). The second end of the second crack detection line MCD1a_2 (or MCD1b_2), opposite to the first end, can be electrically connected to the crack detection circuit MCDC.

[0059] At least a portion of the first crack detection line MCD1a_1 (or MCD1b_1) and at least a portion of the second crack detection line MCD1a_2 (or MCD1b_2) may extend parallel to each other along the edge ED of the substrate SUB. In an embodiment, for example, in a plan view, the second crack detection line MCD1a_2 (or MCD1b_2) arranged in the peripheral region PA adjacent to the left (or right) of the display region DA may be located between the first crack detection line MCD1a_1 (or MCD1b_1) and the first gate driver DV1 (or the second gate driver DV2).

[0060] The second crack detection portions M2a and M2b can be arranged on the substrate SUB in the peripheral region PA. The second crack detection portions M2a and M2b can include a first second crack detection portion (hereinafter referred to as "the 2-1 crack detection portion") M2a and a second second crack detection portion (hereinafter referred to as "the 2-2 crack detection portion") M2b. The 2-1 crack detection portion M2a can be arranged in the peripheral region PA adjacent to the left and lower sides of the display region DA. The 2-2 crack detection portion M2b can be arranged in the peripheral region PA adjacent to the right and lower sides of the display region DA.

[0061] Each of the second crack detection sections M2a and M2b may include a first crack detection line MCD2a_1 or MCD2b_1 and a second crack detection line MCD2a_2 or MCD2b_2. The first end of the first crack detection line MCD2a_1 (or MCD2b_1) may be electrically connected to the pad PD. The first crack detection line MCD2a_1 (or MCD2b_1) can receive a test voltage (VGH, reference) through the pad PD. Figure 2 The second end of the first crack detection line MCD2a_1 (or MCD2b_1), opposite to the first end, can be electrically connected to the first end of the second crack detection line MCD2a_2 (or MCD2b_2). The second end of the second crack detection line MCD2a_2 (or MCD2b_2), opposite to the first end, can be electrically connected to the crack detection circuit MCDC.

[0062] At least a portion of the first crack detection line MCD2a_1 (or MCD2b_1) and at least a portion of the second crack detection line MCD2a_2 (or MCD2b_2) may extend parallel to each other along the edge ED of the substrate SUB. In an embodiment, for example, in a plan view, the second crack detection line MCD2a_2 (or MCD2b_2) disposed in the peripheral region PA adjacent to the lower side of the display region DA may be located between the first crack detection line MCD2a_1 (or MCD2b_1) and the driver chip D-IC.

[0063] A crack detection circuit MCDC can be disposed on the substrate SUB in the peripheral area PA. In a plan view, the crack detection circuit MCDC can be disposed between the display area DA and the pad PD. In an embodiment, in a plan view, the crack detection circuit MCDC can be disposed between the demultiplexed portion DEM and the pad PD. Furthermore, in a plan view, the crack detection circuit MCDC can be disposed between the demultiplexed portion DEM and the driver chip D-IC. The crack detection circuit MCDC may include a detection switch. The crack detection circuit MCDC can inspect (or detect) crack defects appearing in the peripheral area PA of the substrate SUB.

[0064] In an embodiment, for example, the first crack detection portions M1a and M1b and the crack detection circuit MCDC can inspect (or detect) crack defects appearing in the peripheral regions PA adjacent to the upper, left, and right sides of the display region DA. The second crack detection portions M2a and M2b and the crack detection circuit MCDC can inspect crack defects appearing in the peripheral regions PA adjacent to the lower, left, and right sides of the display region DA. In an embodiment, the second crack detection portions M2a and M2b and the crack detection circuit MCDC can inspect crack defects appearing in the peripheral regions PA adjacent to the driver chip D-IC.

[0065] The first crack detection sections M1a and M1b may differ from the second crack detection sections M2a and M2b in the areas where crack defects are inspected, but the methods used to inspect crack defects in both sections M1a and M1b and the second crack detection sections M2a and M2b can be substantially the same. Therefore, the description of the first crack detection sections M1a and M1b can be applied substantially equally to the second crack detection sections M2a and M2b. Furthermore, the first-first crack detection section M1a and the first-second crack detection section M1b can have substantially the same or symmetrical shapes. Therefore, the following description will focus on the first-first crack detection section M1a. The description of the first-first crack detection section M1a can be applied substantially equally to the first-second crack detection section M1b.

[0066] In an embodiment, for example, the display device DD may be a display device such as an organic light-emitting diode display device, a liquid crystal display device, a silicon-based organic light-emitting diode (OLEDoS) display device, a silicon-based liquid crystal (LCoS) display device, or a silicon-based light-emitting diode (LEDoS) display device. In an embodiment, the display device DD may be a display device such as an OLEDoS display device.

[0067] In embodiments where the display device DD is a display device such as an OLEDoS display device, the display device DD can be configured as a head-mounted display, which is a glasses-type monitor device for virtual reality or augmented reality that is worn in the form of glasses or a helmet and has a focal point at close range in front of the user's eyes. However, this disclosure is not limited thereto, and the display device DD can be configured as various displays.

[0068] The display device DD may further include a first blocking structure (300, reference) disposed on the substrate SUB and arranged along the edge ED of the substrate SUB in a plan view. Figure 6) and a second barrier structure (400, reference) disposed on the substrate SUB and arranged in the plan view between the first barrier structure 300 and the first crack detection lines MCD1a_1, MCD1b_1, MCD2a_1 and MCD2b_1. Figure 6 (The following will refer to...) Figure 6 and Figure 7 Describe its detailed characteristics.

[0069] Figure 2 The illustration includes Figure 1 A diagram of the crack detection circuit in the display device.

[0070] refer to Figure 1 and Figure 2 An embodiment of the display device DD may include a crack detection circuit MCDC, a fan-out line FOL, a demultiplexing section DEM, data lines DL, sub-pixels SPX, and pads PD. The data lines DL may include first to eighth data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, and DL8. Figure 2 For ease of illustration and description, only some of the sub-pixels SPX arranged in the display area DA are shown, and only the first to eighth data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7 and DL8 connected to the sub-pixels SPX are shown.

[0071] The pads (PDs) can be arranged on the substrate (SUB) within the peripheral area (PA). The pads (PDs) can be connected to the driver chip (D-IC). The pads (PDs) can receive various voltages from the driver chip (D-IC). In an embodiment, for example, the pads (PDs) may include first to fourth pads (PD1, PD2, PD3, and PD4).

[0072] In the plan view, fan-out lines (FOLs) can be arranged between the demultiplexed portion (DEM) and the pads (PD). Fan-out lines (FOLs) can be repeatedly arranged along a first direction (DR1). Each of the fan-out lines (FOLs) can extend along a second direction (DR2). In an embodiment, for example, fan-out lines (FOLs) can include first to fourth fan-out lines (FOL1, FOL2, FOL3, and FOL4).

[0073] The first end of the first fan-out line FOL1 can be electrically connected to the first pad PD1, and the second end of the first fan-out line FOL1, opposite to the first end, can be electrically connected to the first data line DL1 and the second data line DL2. The first end of the second fan-out line FOL2 can be electrically connected to the second pad PD2, and the second end of the second fan-out line FOL2, opposite to the first end, can be electrically connected to the third data line DL3 and the fourth data line DL4. The first end of the third fan-out line FOL3 can be electrically connected to the third pad PD3, and the second end of the third fan-out line FOL3, opposite to the first end, can be electrically connected to the fifth data line DL5 and the sixth data line DL6. The first end of the fourth fan-out line FOL4 can be electrically connected to the fourth pad PD4, and the second end of the fourth fan-out line FOL4, opposite to the first end, can be electrically connected to the seventh data line DL7 and the eighth data line DL8.

[0074] In the plan view, the crack detection circuit MCDC can be arranged between the pad PD and the demultiplexed section DEM. The crack detection circuit MCDC may include a constant voltage line VGHL, a second crack detection line MCD1a_2, a detection control line DCL, and detection switches. In an embodiment, for example, the detection switches may include a first detection switch SW11, a second detection switch SW12, a third detection switch SW13, and a fourth detection switch SW14.

[0075] The constant pressure line VGHL, the second crack detection line MCD1a_2, and the detection control line DCL can be spaced apart from each other in the second direction DR2. Each of the constant pressure line VGHL, the second crack detection line MCD1a_2, and the detection control line DCL can extend in the first direction DR1.

[0076] The first detection switch SW11 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the first detection switch SW11 can receive the detection control signal MCD_GATE via the detection control line DCL. The first terminal of the first detection switch SW11 can be connected to the constant voltage line VGHL. The second terminal of the first detection switch SW11 can be connected to the first fan-out line FOL1. When the first detection switch SW11 is turned on in response to the detection control signal MCD_GATE, the first detection switch SW11 can connect the constant voltage line VGHL and the first fan-out line FOL1 to each other.

[0077] The second detection switch SW12 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the second detection switch SW12 can receive the detection control signal MCD_GATE via the detection control line DCL. The first terminal of the second detection switch SW12 can be connected to the constant voltage line VGHL. The second terminal of the second detection switch SW12 can be connected to the second fan-out line FOL2. When the second detection switch SW12 is turned on in response to the detection control signal MCD_GATE, the second detection switch SW12 can connect the constant voltage line VGHL and the second fan-out line FOL2 to each other.

[0078] The third detection switch SW13 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the third detection switch SW13 can receive the detection control signal MCD_GATE via the detection control line DCL. The first terminal of the third detection switch SW13 can be connected to the second crack detection line MCD1a_2. The second terminal of the third detection switch SW13 can be connected to the third fan-out line FOL3. When the third detection switch SW13 is turned on in response to the detection control signal MCD_GATE, the third detection switch SW13 can connect the second crack detection line MCD1a_2 and the third fan-out line FOL3 to each other.

[0079] The fourth detection switch SW14 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the fourth detection switch SW14 can receive the detection control signal MCD_GATE via the detection control line DCL. The first terminal of the fourth detection switch SW14 can be connected to the second crack detection line MCD1a_2. The second terminal of the fourth detection switch SW14 can be connected to the fourth fan-out line FOL4. When the fourth detection switch SW14 is turned on in response to the detection control signal MCD_GATE, the fourth detection switch SW14 can connect the second crack detection line MCD1a_2 and the fourth fan-out line FOL4 to each other.

[0080] In the plan view, the demultiplexed portion DEM can be arranged between the sub-pixel SPX and the crack detection circuit MCDC. The demultiplexed portion DEM may include a first demultiplexing control line MCL1, a second demultiplexing control line MCL2, and a demultiplexing switch. The demultiplexed portion DEM can connect a fan-out line FOL to multiple data lines DL through the demultiplexing switch. In an embodiment, for example, the demultiplexing switch may include first to eighth demultiplexing switches SW21, SW22, SW23, SW24, SW25, SW26, SW27, and SW28.

[0081] The first demultiplexing control line MCL1 and the second demultiplexing control line MCL2 may be spaced apart from each other in the second direction DR2. Each of the first demultiplexing control line MCL1 and the second demultiplexing control line MCL2 may extend in the first direction DR1.

[0082] The first demultiplexing switch SW21 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the first demultiplexing switch SW21 can receive a first demultiplexing control signal CLA via the first demultiplexing control line MCL1. The first terminal of the first demultiplexing switch SW21 can be connected to the first fan-out line FOL1. The second terminal of the first demultiplexing switch SW21 can be connected to the first data line DL1. When the first demultiplexing switch SW21 is turned on in response to the first demultiplexing control signal CLA, the first demultiplexing switch SW21 can connect the first fan-out line FOL1 and the first data line DL1 to each other.

[0083] The second demultiplexing switch SW22 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the second demultiplexing switch SW22 can receive a second demultiplexing control signal CLB via the second demultiplexing control line MCL2. The first terminal of the second demultiplexing switch SW22 can be connected to the first fan-out line FOL1. The second terminal of the second demultiplexing switch SW22 can be connected to the second data line DL2. When the second demultiplexing switch SW22 is turned on in response to the second demultiplexing control signal CLB, the second demultiplexing switch SW22 can connect the first fan-out line FOL1 and the second data line DL2 to each other.

[0084] The third demultiplexing switch SW23 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the third demultiplexing switch SW23 can receive a first demultiplexing control signal CLA via the first demultiplexing control line MCL1. The first terminal of the third demultiplexing switch SW23 can be connected to the second fan-out line FOL2. The second terminal of the third demultiplexing switch SW23 can be connected to the third data line DL3. When the third demultiplexing switch SW23 is turned on in response to the first demultiplexing control signal CLA, the third demultiplexing switch SW23 can connect the second fan-out line FOL2 and the third data line DL3 to each other.

[0085] The fourth demultiplexing switch SW24 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the fourth demultiplexing switch SW24 can receive a second demultiplexing control signal CLB via the second demultiplexing control line MCL2. The first terminal of the fourth demultiplexing switch SW24 can be connected to the second fan-out line FOL2. The second terminal of the fourth demultiplexing switch SW24 can be connected to the fourth data line DL4. When the fourth demultiplexing switch SW24 is turned on in response to the second demultiplexing control signal CLB, the fourth demultiplexing switch SW24 can connect the second fan-out line FOL2 and the fourth data line DL4 to each other.

[0086] The fifth demultiplexer switch SW25 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the fifth demultiplexer switch SW25 can receive a first demultiplexer control signal CLA via the first demultiplexer control line MCL1. The first terminal of the fifth demultiplexer switch SW25 can be connected to the third fan-out line FOL3. The second terminal of the fifth demultiplexer switch SW25 can be connected to the fifth data line DL5. When the fifth demultiplexer switch SW25 is turned on in response to the first demultiplexer control signal CLA, the fifth demultiplexer switch SW25 can connect the third fan-out line FOL3 and the fifth data line DL5 to each other.

[0087] The sixth demultiplexer switch SW26 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the sixth demultiplexer switch SW26 can receive a second demultiplexer control signal CLB via the second demultiplexer control line MCL2. The first terminal of the sixth demultiplexer switch SW26 can be connected to the third fan-out line FOL3. The second terminal of the sixth demultiplexer switch SW26 can be connected to the sixth data line DL6. When the sixth demultiplexer switch SW26 is turned on in response to the second demultiplexer control signal CLB, the sixth demultiplexer switch SW26 can connect the third fan-out line FOL3 and the sixth data line DL6 to each other.

[0088] The seventh demultiplexer switch SW27 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the seventh demultiplexer switch SW27 can receive a first demultiplexing control signal CLA via the first demultiplexing control line MCL1. The first terminal of the seventh demultiplexer switch SW27 can be connected to the fourth fan-out line FOL4. The second terminal of the seventh demultiplexer switch SW27 can be connected to the seventh data line DL7. When the seventh demultiplexer switch SW27 is turned on in response to the first demultiplexing control signal CLA, the seventh demultiplexer switch SW27 can connect the fourth fan-out line FOL4 and the seventh data line DL7 to each other.

[0089] The eighth demultiplexer switch SW28 may include a first terminal, a second terminal, and a gate terminal. The gate terminal of the eighth demultiplexer switch SW28 can receive a second demultiplexer control signal CLB via the second demultiplexer control line MCL2. The first terminal of the eighth demultiplexer switch SW28 can be connected to the fourth fan-out line FOL4. The second terminal of the eighth demultiplexer switch SW28 can be connected to the eighth data line DL8. When the eighth demultiplexer switch SW28 is turned on in response to the second demultiplexer control signal CLB, the eighth demultiplexer switch SW28 can connect the fourth fan-out line FOL4 and the eighth data line DL8 to each other.

[0090] exist Figure 2The illustration shows an example of two demultiplexing switches arranged corresponding to a single fan-out line FOL, but this disclosure is not limited thereto. In another embodiment, for example, three or more demultiplexing switches may be arranged corresponding to a single fan-out line FOL. In such an embodiment, a single fan-out line FOL may be connected to three or more data lines DL.

[0091] When the display device DD is driven in detection mode, a test voltage VGH can be applied to the first crack detection line MCD1a_1. When no crack appears in the peripheral region PA of the substrate SUB, the magnitude of the voltage across (or passing through) the peripheral region PA of the substrate SUB can be constant. Conversely, when a crack appears in the peripheral region PA of the substrate SUB, the magnitude of the voltage across (or passing through) the peripheral region PA of the substrate SUB may decrease.

[0092] When the display device DD is driven in detection mode, the crack detection circuit MCDC can be activated. In an embodiment, for example, a detection control signal MCD_GATE with a low voltage level can be applied to the gate terminals of the first to fourth detection switches SW11, SW12, SW13, and SW14, and the first to fourth detection switches SW11, SW12, SW13, and SW14 can be turned on. Therefore, some of the fan-out lines FOL can be electrically connected to the constant voltage line VGHL through the detection switches, and some of the other fan-out lines FOL can be electrically connected to the second crack detection line MCD1a_2 through the detection switches. In an embodiment, for example, the first fan-out line FOL1 and the second fan-out line FOL2 can be electrically connected to the constant voltage line VGHL through the first detection switch SW11 and the second detection switch SW12, respectively. In an embodiment, for example, the third fan-out line FOL3 and the fourth fan-out line FOL4 can be electrically connected to the second crack detection line MCD1a_2 through the third detection switch SW13 and the fourth detection switch SW14, respectively.

[0093] Furthermore, when the display device DD is driven in detection mode, the demultiplexing section DEM can be activated. In an embodiment, for example, a first demultiplexing control signal CLA with a low voltage level can be applied to the gate terminals of the first demultiplexing switch SW21, the third demultiplexing switch SW23, the fifth demultiplexing switch SW25, and the seventh demultiplexing switch SW27, and a second demultiplexing control signal CLB with a low voltage level can be applied to the gate terminals of the second demultiplexing switch SW22, the fourth demultiplexing switch SW24, the sixth demultiplexing switch SW26, and the eighth demultiplexing switch SW28. Therefore, the first to eighth demultiplexing switches SW21, SW22, SW23, SW24, SW25, SW26, SW27, and SW28 can be turned on. As a result, the first outgoing line FOL1 can be electrically connected to the first data line DL1 and the second data line DL2, the second outgoing line FOL2 can be electrically connected to the third data line DL3 and the fourth data line DL4, the third outgoing line FOL3 can be electrically connected to the fifth data line DL5 and the sixth data line DL6, and the fourth outgoing line FOL4 can be electrically connected to the seventh data line DL7 and the eighth data line DL8.

[0094] When the display device DD is driven in detection mode, a test voltage VGH can be applied to the constant voltage line VGHL. Accordingly, the test voltage VGH can be applied to the first data line DL1 and the second data line DL2 via the first fan-out line FOL1. Additionally, the test voltage VGH can be applied to the third data line DL3 and the fourth data line DL4 via the second fan-out line FOL2. Accordingly, the sub-pixels SPX connected to the first to fourth data lines DL1, DL2, DL3, and DL4 can emit red, green, or blue light. However, this disclosure is not limited thereto.

[0095] When a crack appears in the peripheral region PA of the substrate SUB, a first voltage VGH_MCD, less than the test voltage VGH, can be applied to the second crack detection line MCD1a_2, which passes through the peripheral region PA. The first voltage VGH_MCD can be applied to the fifth data line DL5 and the sixth data line DL6 via the third fan-out line FOL3. Additionally, the first voltage VGH_MCD can be applied to the seventh data line DL7 and the eighth data line DL8 via the fourth fan-out line FOL4. In an embodiment, for example, when the first voltage VGH_MCD, less than the test voltage VGH, is applied to the fifth to eighth data lines DL5, DL6, DL7, and DL8, the sub-pixels SPX connected to the fifth to eighth data lines DL5, DL6, DL7, and DL8 can display black. Thus, crack defects appearing in the peripheral region PA of the substrate SUB can be detected.

[0096] Figure 3 yes Figure 1An enlarged plan view of region A. Specifically, Figure 3 It is a magnified plan view of a portion of the display area DA.

[0097] refer to Figure 3 An embodiment of the display device DD may include a display area DA, and the display area DA may include a first light-emitting area EA1, a second light-emitting area EA2, a third light-emitting area EA3, and a light-shielding area BA.

[0098] In an embodiment, for example, each of the first to third light-emitting regions EA1, EA2, and EA3 may have a rectangular planar shape. However, this disclosure is not limited thereto, and each of the first to third light-emitting regions EA1, EA2, and EA3 may have any one of a triangular planar shape, a circular planar shape, and an elliptical planar shape.

[0099] In an embodiment, for example, the first to third light-emitting regions EA1, EA2, and EA3 may have the same size and / or shape as each other. However, this disclosure is not limited thereto, and the first to third light-emitting regions EA1, EA2, and EA3 may have different sizes.

[0100] Each of the first to third light-emitting regions EA1, EA2, and EA3 may include a light-emitting element LD that emits a first light. In an embodiment, for example, the first light may be white light. However, this disclosure is not limited thereto, and the light-emitting element LD included in the first light-emitting region EA1 may emit red light, the light-emitting element LD included in the second light-emitting region EA2 may emit green light, and the light-emitting element LD included in the third light-emitting region EA3 may emit blue light. In an embodiment, the light-emitting element LD may be a miniature organic light-emitting diode. However, this disclosure is not limited thereto.

[0101] The first light-emitting region EA1 can emit a second light. The first light-emitting region EA1 can convert the first light emitted from the light-emitting element LD into a second light and can emit the second light. In an embodiment, for example, the second light can be red light, but this disclosure is not limited thereto.

[0102] The second light-emitting region EA2 can emit a third light. The second light-emitting region EA2 can convert the first light emitted from the light-emitting element LD into a third light and can emit the third light. In an embodiment, for example, the third light can be green light, but this disclosure is not limited thereto.

[0103] The third light-emitting region EA3 can emit a fourth light. The third light-emitting region EA3 can convert the first light emitted from the light-emitting element LD into a fourth light and can emit the fourth light. In an embodiment, for example, the fourth light can be blue light, but this disclosure is not limited thereto.

[0104] In an embodiment, for example, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be arranged sequentially along the first direction DR1. Alternatively, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be arranged sequentially in the opposite direction to the second direction DR2. However, the arrangement structure of the first to third light-emitting regions EA1, EA2, and EA3 is not limited to this.

[0105] The light-shielding area BA can be arranged between the first to third light-emitting areas EA1, EA2, and EA3. In an embodiment, for example, the light-shielding area BA can surround the first to third light-emitting areas EA1, EA2, and EA3 in a plan view. In an embodiment, for example, the light-shielding area BA can have a grid shape, mesh shape, or lattice shape in a plan view. The light-shielding area BA can be defined as an area that blocks light.

[0106] Figure 4 It is along Figure 3 The cross-sectional view taken from line II-II'.

[0107] refer to Figure 4 An embodiment of the display device DD may include a substrate SUB, a first insulating layer IL1, a connecting electrode CNE, a second insulating layer IL2, a light-emitting element LD, a packaging layer TFE, a color filter layer CFL, a planarization layer OVC, a lens layer LL, a fill layer FIL, and a packaging substrate ENC in the display area DA. Each of the light-emitting elements LD may include a pixel electrode PE, a light-emitting layer EML, and a common electrode CE.

[0108] The substrate SUB may include a base substrate BS and multiple pixel driving circuits CP. The substrate SUB may be a semiconductor circuit board. In an embodiment, the substrate SUB may include a silicon wafer. However, this disclosure is not limited thereto, and the substrate SUB may be a gallium arsenide substrate, a ceramic substrate, a quartz substrate, or a semiconductor-on-insulator (SOI) substrate.

[0109] The recessed groove (GRV) can be defined in the substrate BS. Pixel driving circuits (CP) can be respectively housed in the recessed groove (GRV). Each of the pixel driving circuits (CP) may include at least one transistor and at least one capacitor.

[0110] A first insulating layer IL1 may be disposed on a substrate SUB. The first insulating layer IL1 may define contact holes that expose a portion of the pixel driving circuit CP. The first insulating layer IL1 may comprise an inorganic insulating material and / or an organic insulating material. Examples of inorganic insulating materials that may be used as the first insulating layer IL1 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x Ny Examples of organic insulating materials that can be used as the first insulating layer IL1 include polypropylene resins, polyimide resins, polyamide resins, siloxane resins, acrylic resins, or epoxy resins. These can be used alone or in combination with each other.

[0111] The connection electrode CNE can be disposed on the substrate SUB. The connection electrode CNE can be disposed or disposed in a contact hole defined in the first insulating layer IL1. The connection electrode CNE can be connected to the pixel driving circuit CP. The connection electrode CNE can electrically connect the pixel driving circuit CP and the pixel electrode PE. The connection electrode CNE can include metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides, etc. Examples of materials that can be used as the connection electrode CNE include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used individually or in combination with each other.

[0112] The pixel electrode PE can be disposed on the first insulating layer IL1 and the connecting electrode CNE. The pixel electrode PE can overlap with each of the first to third light-emitting regions EA1, EA2, and EA3. The pixel electrode PE can be electrically connected to the pixel driving circuit CP via the connecting electrode CNE. The pixel electrode PE can include metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides, etc. These can be used individually or in combination with each other. In an embodiment, for example, the pixel electrode PE can act as an anode electrode.

[0113] A second insulating layer IL2 may be disposed on the first insulating layer IL1. The second insulating layer IL2 may cover the edge of the pixel electrode PE and may expose the upper surface of the pixel electrode PE. The second insulating layer IL2 may include an organic insulating material. Examples of organic insulating materials that can be used as the second insulating layer IL2 may include polypropylene resins, polyimide resins, polyamide resins, siloxane resins, acrylic resins, or epoxy resins, etc. These may be used alone or in combination with each other.

[0114] The light-emitting layer EML can be disposed on the pixel electrode PE and the second insulating layer IL2. In an embodiment, the light-emitting layer EML can extend continuously along the first to third light-emitting regions EA1, EA2, and EA3. However, this disclosure is not limited thereto, and the light-emitting layer EML can be disposed independently in each of the first to third light-emitting regions EA1, EA2, and EA3. The light-emitting layer EML may include an organic material that emits light of a certain color (e.g., a predetermined color). In an embodiment, the light-emitting layer EML may include an organic light-emitting material that emits white light, but this disclosure is not limited thereto.

[0115] The common electrode CE can be disposed on the light-emitting layer EML. The common electrode CE can extend continuously along the first to third light-emitting regions EA1, EA2, and EA3. The common electrode CE can include metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides, etc. These can be used individually or in combination with each other. In an embodiment, for example, the common electrode CE can serve as a cathode electrode.

[0116] The TFE encapsulation layer can be disposed on the common electrode CE. The TFE encapsulation layer effectively prevents impurities or moisture from penetrating into the light-emitting element LD from the outside. The TFE encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, for example, the inorganic encapsulation layer may include silicon oxide (SiO₂). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. In an embodiment, for example, the organic encapsulation layer may include a polymer-cured material such as polyacrylate. In an embodiment, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3 stacked sequentially along the third direction DR3.

[0117] The first inorganic encapsulation layer TFE1 can be disposed on the common electrode CE. The first inorganic encapsulation layer TFE1 can cover the common electrode CE and can be disposed along the contour of the common electrode CE with a substantially uniform thickness. The first inorganic encapsulation layer TFE1 can effectively prevent the light-emitting element LD from deteriorating due to the penetration of impurities or moisture. Additionally, the first inorganic encapsulation layer TFE1 can protect the light-emitting element LD from external impacts. In embodiments, for example, the first inorganic encapsulation layer TFE1 may comprise a flexible inorganic material.

[0118] An organic encapsulation layer TFE2 can be disposed on the first inorganic encapsulation layer TFE1. The organic encapsulation layer TFE2 can compensate for any step differences in the first inorganic encapsulation layer TFE1. Accordingly, the organic encapsulation layer TFE2 can have a substantially flat upper surface. The organic encapsulation layer TFE2, together with the first inorganic encapsulation layer TFE1, can protect the light-emitting element (LD) from external impacts. In embodiments, for example, the organic encapsulation layer TFE2 may comprise a flexible organic material.

[0119] The second inorganic encapsulation layer TFE3 can be disposed on the organic encapsulation layer TFE2. The second inorganic encapsulation layer TFE3, together with the first inorganic encapsulation layer TFE1, can effectively prevent the light-emitting element (LD) from deteriorating due to the penetration of impurities or moisture. Furthermore, the second inorganic encapsulation layer TFE3, together with the first inorganic encapsulation layer TFE1 and the organic encapsulation layer TFE2, can protect the light-emitting element (LD) from external impacts. In an embodiment, for example, the second inorganic encapsulation layer TFE3 may comprise a flexible inorganic material.

[0120] The color filter layer (CFL) can be disposed on the encapsulation layer (TFE). The color filter layer (CFL) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) that transmit different colors of light.

[0121] The first color filter CF1 may overlap with the first light-emitting region EA1. The first color filter CF1 may transmit a second light from the first light emitted from the light-emitting layer EML, and may absorb or block a third and a fourth light. In an embodiment, for example, the first color filter CF1 may transmit red light and may absorb or block green and blue light. However, this disclosure is not limited thereto.

[0122] The second color filter CF2 may overlap with the second light-emitting region EA2. The second color filter CF2 may transmit a third light from the first light emitted from the light-emitting layer EML, and may absorb or block the second and fourth light. In an embodiment, for example, the second color filter CF2 may transmit green light and may absorb or block red and blue light. However, this disclosure is not limited thereto.

[0123] The third color filter CF3 may overlap with the third light-emitting region EA3. The third color filter CF3 may transmit a fourth light from the first light emitted from the light-emitting layer EML, and may absorb or block the second and third light. In an embodiment, for example, the third color filter CF3 may transmit blue light and may absorb or block red and green light. However, this disclosure is not limited thereto.

[0124] The first color filter CF1 and the second color filter CF2 can overlap each other in the light-shielding area BA located between the first light-emitting area EA1 and the second light-emitting area EA2. Additionally, the second color filter CF2 and the third color filter CF3 can overlap each other in the light-shielding area BA located between the second light-emitting area EA2 and the third light-emitting area EA3. Furthermore, although not in... Figure 4 As illustrated in the diagram, the first color filter CF1 and the third color filter CF3 can overlap each other in the light-shielding region BA located between the first emitting region EA1 and the third emitting region EA3. That is, in the plan view, the overlapping portions of the different color filters can overlap with the light-shielding region BA. The overlapping portions of the color filter layer CFL can act as a light-shielding pattern blocking light. In an embodiment, the color filter layer CFL may include a black matrix pattern overlapping with the light-shielding region BA in the plan view and comprising an organic material containing a light-shielding material. In an embodiment, for example, the light-shielding material may include black pigment, black dye, or carbon black, etc.

[0125] The planarization layer OVC can be disposed on the color filter layer CFL. The planarization layer OVC can flatten the step difference of the color filter layer CFL (or provide a flat surface on the step difference of the color filter layer CFL). The planarization layer OVC can include inorganic insulating materials or organic insulating materials.

[0126] The lens layer LL can be disposed on the planarization layer OVC. The lens layer LL may include a plurality of microlenses ML. The microlenses ML may overlap with a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3, respectively. Additionally, in a planar view, the microlenses ML may overlap with a first color filter CF1, a second color filter CF2, and a third color filter CF3, respectively. The microlenses ML can improve light extraction efficiency. The microlenses ML may have a refractive index (e.g., a predetermined refractive index). In embodiments, for example, the microlenses ML may have a refractive index greater than or equal to about 1.5 and less than or equal to about 1.7, but this disclosure is not limited thereto.

[0127] A filler layer (FIL) can be disposed on the lens layer (LL). The filler layer (FIL) can flatten the step difference of the lens layer (LL). The filler layer (FIL) can include inorganic insulating materials or organic insulating materials.

[0128] The encapsulation substrate ENC can be disposed on the filler layer FIL. The encapsulation substrate ENC may include a transparent material. In embodiments, for example, the encapsulation substrate ENC may include glass or plastic.

[0129] Figure 5 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0130] refer to Figure 1and Figure 5 An embodiment of the display device DD may include a chip structure CS. The chip structure CS may be disposed in the display area DA and the peripheral area PA adjacent to the display area DA, or on the substrate SUB. The chip structure CS may include a semiconductor chip 100 and a guard ring 200.

[0131] In embodiments, for example, semiconductor chip 100 may be a logic chip or a memory chip, etc. In embodiments where semiconductor chip 100 is a logic chip, the logic chip may be designed in various ways with regard to the operations to be performed. In embodiments where semiconductor chip 100 is a memory chip, the memory chip may be a non-volatile memory chip. In embodiments, the memory chip may be a flash memory chip. In embodiments, for example, the memory chip may be one of NAND flash memory chips and NOR flash memory chips. However, this disclosure is not limited thereto, and the memory chip may also be phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), or resistive random access memory (RRAM).

[0132] Semiconductor chip 100 may include various components. In embodiments, for example, semiconductor chip 100 may include active components and / or passive components. In embodiments, semiconductor chip 100 may include metal-oxide-semiconductor field-effect transistors (MOSFETs) such as complementary metal-oxide-semiconductor (CMOS) transistors, system large-scale integrated circuits (LSIs), image sensors such as CMOS image sensors (CISs), or microelectromechanical systems (MEMSs).

[0133] The guard ring 200 may be arranged adjacent to the semiconductor chip 100. In an embodiment, for example, the guard ring 200 may surround a side surface of the semiconductor chip 100 in a plan view. Figure 5 The illustration shows an embodiment where the protective ring 200 is arranged in the opposite direction to the semiconductor chip 100 in the first direction DR1, but the disclosure is not limited thereto. The protective ring 200 may include metal. In embodiments, for example, the protective ring 200 may include a metal seal.

[0134] You can follow the line (SL, reference) Figure 9 ) will use the chip (WA, reference) Figure 9 The wafer is separated into multiple semiconductor chips 100. During the sawing process that separates the wafer into semiconductor chips 100, cracks may occur in the wafer.

[0135] The guard ring 200 effectively prevents cracks that may occur during the sawing process from propagating to the semiconductor chip 100 or prevents foreign matter (e.g., ionic contaminants) from propagating to the semiconductor chip 100 through cracks. Additionally, the guard ring 200 provides a low-resistance path for inrush current. Here, inrush current can refer to current that may damage components due to heat dissipation (e.g., ...). Figure 4 The current of the light-emitting element (LD). In other words, the guard ring 200 can dissipate abnormal electromagnetic interference (EMI) noise such as surge current to the outside and can effectively prevent the element from being damaged.

[0136] Figure 6 yes Figure 1 A magnified plan view of region B. Specifically, Figure 6 This is an enlarged plan view of the peripheral region PA adjacent to the edge ED of the substrate SUB. Figure 7 The illustration includes Figure 1 Cross-sectional views of the first blocking structure, the second blocking structure, and the crack detection structure in the display device.

[0137] refer to Figure 1 , Figure 6 and Figure 7 An embodiment of the display device DD may include a first blocking structure 300, a second blocking structure 400, and a crack detection structure 500. The crack detection structure 500 may include a first crack detection line MCD1a_1 and a second crack detection line MCD1a_2.

[0138] In an embodiment, such as Figure 6 As shown, the first blocking structure 300, the second blocking structure 400, and the crack detection structure 500 can be sequentially arranged from the edge ED of the substrate SUB along the first direction DR1. Additionally, although not shown in... Figure 1 and Figure 6 As shown in the diagram, the first blocking structure 300, the second blocking structure 400, and the crack detection structure 500 can be arranged sequentially from the edge ED of the substrate SUB along the opposite direction of the first direction DR1, the second direction DR2, and the opposite direction of the second direction DR2. Each of the first blocking structure 300, the second blocking structure 400, and the crack detection structure 500 can surround the display area DA in the plan view. The second blocking structure 400 can surround the crack detection structure 500 in the plan view, and the first blocking structure 300 can surround the second blocking structure 400 in the plan view.

[0139] The first barrier structure 300 can be disposed on the substrate SUB and can be disposed along the edge ED of the substrate SUB in a plan view. The first barrier structure 300 can block the propagation of cracks during sawing and packaging processes.

[0140] In an embodiment, such as Figure 7 As shown, the first barrier structure 300 may include multiple circuit layers, multiple vias 320, and a cover pad 319.

[0141] Multiple circuit layers may include first to eighth circuit layers 311, 312, 313, 314, 315, 316, 317, and 318 stacked sequentially along the third direction DR3. Each of the first to eighth circuit layers 311, 312, 313, 314, 315, 316, 317, and 318 may include a metal. In an embodiment, the first to eighth circuit layers 311, 312, 313, 314, 315, 316, 317, and 318 may include the same metal as each other. In an embodiment, for example, each of the first to eighth circuit layers 311, 312, 313, 314, 315, 316, 317, and 318 may include aluminum (Al) or copper (Cu). These may be used individually or in combination with each other. However, this disclosure is not limited thereto, and the first to eighth circuit layers 311, 312, 313, 314, 315, 316, 317, and 318 may include different materials.

[0142] In an embodiment, such as Figure 7 As shown, the circuit layer of the first barrier structure 300 may include eight metal layers, but this disclosure is not limited thereto. The number of metal layers included in the circuit layer of the first barrier structure 300 may be varied according to embodiments.

[0143] Intermetallic insulating layers can be disposed between multiple circuit layers and cover pad 319. The intermetallic insulating layer can be an intermetallic dielectric (IMD) with a low dielectric constant (i.e., low k). The intermetallic insulating layer can effectively prevent short circuits between the first to eighth circuit layers 311, 312, 313, 314, 315, 316, 317 and 318 and cover pad 319.

[0144] Multiple vias 320 may be defined in the intermetallic insulating layer. Each of the vias 320 can electrically connect the circuit layers. In embodiments, for example, the vias 320 may be arranged between the first circuit layer 311 and the second circuit layer 312, between the second circuit layer 312 and the third circuit layer 313, between the third circuit layer 313 and the fourth circuit layer 314, between the fourth circuit layer 314 and the fifth circuit layer 315, between the fifth circuit layer 315 and the sixth circuit layer 316, between the sixth circuit layer 316 and the seventh circuit layer 317, between the seventh circuit layer 317 and the eighth circuit layer 318, and between the eighth circuit layer 318 and the cover pad 319.

[0145] Each of the through-holes 320 may comprise a chemically resistant metallic material. In an embodiment, for example, each of the through-holes 320 may comprise tungsten (W). However, this disclosure is not limited thereto.

[0146] Cover pad 319 may be disposed on a circuit layer. In an embodiment, for example, cover pad 319 may be disposed on an eighth circuit layer 318. Cover pad 319 can effectively prevent the circuit layer disposed beneath the cover pad 319 of the first barrier structure 300 from being damaged in subsequent processes. In an embodiment, for example, cover pad 319 may include titanium (Ti), tantalum (Ta), or titanium nitride (TiN), etc. However, this disclosure is not limited thereto. In another embodiment, cover pad 319 may be omitted.

[0147] The second barrier structure 400 can be disposed on the substrate SUB and can be located between the display area DA and the first barrier structure 300 in a plan view. In an embodiment, the second barrier structure 400 can be located between the first barrier structure 300 and the crack detection structure 500 in a plan view. In an embodiment, for example, the second barrier structure 400 can be located between the first barrier structure 300 and the first crack detection line MCD1a_1 in a plan view. During the back-side polishing process, the second barrier structure 400 can block moisture from passing through the scribing line (SL, reference). Figure 9 It flows into semiconductor chip 100.

[0148] In an embodiment, such as Figure 7 As shown, the second barrier structure 400 may include multiple circuit layers, multiple vias 420, and a cover pad 419.

[0149] Multiple circuit layers may include first to eighth circuit layers 411, 412, 413, 414, 415, 416, 417, and 418 stacked sequentially along the third direction DR3. Each of the first to eighth circuit layers 411, 412, 413, 414, 415, 416, 417, and 418 may include a metal. In an embodiment, the first to eighth circuit layers 411, 412, 413, 414, 415, 416, 417, and 418 may include the same metal as each other. In an embodiment, for example, each of the first to eighth circuit layers 411, 412, 413, 414, 415, 416, 417, and 418 may include aluminum (Al) or copper (Cu). These may be used individually or in combination with each other. However, this disclosure is not limited thereto, and the first to eighth circuit layers 411, 412, 413, 414, 415, 416, 417, and 418 may include different materials.

[0150] In an embodiment, such as Figure 7 As shown, the circuit layer of the second barrier structure 400 may include eight metal layers, but this disclosure is not limited thereto. The number of metal layers included in the circuit layer of the second barrier structure 400 may be varied according to embodiments.

[0151] An intermetallic insulating layer may be disposed between multiple circuit layers and a cover pad 419. Multiple vias 420 may be defined in the intermetallic insulating layer. Each of the vias 420 can electrically connect the circuit layers. In embodiments, for example, the vias 420 may be disposed between a first circuit layer 411 and a second circuit layer 412, between a second circuit layer 412 and a third circuit layer 413, between a third circuit layer 413 and a fourth circuit layer 414, between a fourth circuit layer 414 and a fifth circuit layer 415, between a fifth circuit layer 415 and a sixth circuit layer 416, between a sixth circuit layer 416 and a seventh circuit layer 417, between a seventh circuit layer 417 and an eighth circuit layer 418, and between an eighth circuit layer 418 and a cover pad 419.

[0152] Each of the through-holes 420 may comprise a chemically resistant metallic material. In an embodiment, for example, each of the through-holes 420 may comprise tungsten (W). However, this disclosure is not limited thereto.

[0153] Cover pad 419 may be disposed on a circuit layer. In an embodiment, for example, cover pad 419 may be disposed on an eighth circuit layer 418. Cover pad 419 can effectively prevent the circuit layer of the second barrier structure 400 disposed beneath cover pad 419 from being damaged in subsequent processes. In an embodiment, for example, cover pad 419 may include titanium (Ti), tantalum (Ta), or titanium nitride (TiN), etc. However, this disclosure is not limited thereto. In an embodiment, cover pad 419 may be omitted.

[0154] The crack detection structure 500 can be disposed on the substrate SUB and, in a plan view, can be located between the display area DA and the second blocking structure 400. The crack detection structure 500 can be spaced apart from the first blocking structure 300 and the second blocking structure 400. In an embodiment, for example, the in-plane separation distance between the crack detection structure 500 and the second blocking structure 400 can be approximately 10 micrometers. However, this disclosure is not limited thereto. The crack detection structure 500 can detect cracks that are not blocked by the first blocking structure 300 and the second blocking structure 400.

[0155] In an embodiment, such as Figure 7 As shown, the crack detection structure 500 may include a lower circuit layer BML, an intermediate circuit layer MML, an upper circuit layer UML, multiple vias 520, a detection line connection electrode MCE, and a cover pad 519. In an embodiment, for example, the lower circuit layer BML may include first to fourth circuit layers 511, 512, 513, and 514, the intermediate circuit layer MML may include a fifth circuit layer 515 and a sixth circuit layer 516, and the upper circuit layer UML may include a seventh circuit layer 517 and an eighth circuit layer 518.

[0156] The first to eighth circuit layers 511, 512, 513, 514, 515, 516, 517, and 518 may be stacked sequentially along the third direction DR3. Each of the first to eighth circuit layers 511, 512, 513, 514, 515, 516, 517, and 518 may include a metal. In an embodiment, the first to eighth circuit layers 511, 512, 513, 514, 515, 516, 517, and 518 may include the same metal as each other. In an embodiment, for example, each of the first to eighth circuit layers 511, 512, 513, 514, 515, 516, 517, and 518 may include aluminum (Al) or copper (Cu). These may be used individually or in combination with each other. However, this disclosure is not limited thereto, and the first to eighth circuit layers 511, 512, 513, 514, 515, 516, 517, and 518 may include different materials.

[0157] In an embodiment, such as Figure 7 As shown, the circuit layer of the crack detection structure 500 may include eight metal layers, but this disclosure is not limited thereto. The number of metal layers included in the circuit layer of the crack detection structure 500 may be varied depending on the embodiment.

[0158] An intermetallic insulating layer may be disposed between multiple circuit layers and a cover pad 519. Multiple vias 520 may be defined in the intermetallic insulating layer. Each of the vias 520 can electrically connect the circuit layers. In an embodiment, the vias 520 may be disposed between a first circuit layer 511 and a second circuit layer 512, between a second circuit layer 512 and a third circuit layer 513, between a third circuit layer 513 and a fourth circuit layer 514, between a fourth circuit layer 514 and a fifth circuit layer 515, between a sixth circuit layer 516 and a seventh circuit layer 517, between a seventh circuit layer 517 and an eighth circuit layer 518, and between an eighth circuit layer 518 and a cover pad 518.

[0159] Each of the through-holes 520 may comprise a chemically resistant metallic material. In an embodiment, for example, each of the through-holes 520 may comprise tungsten (W). However, this disclosure is not limited thereto.

[0160] In an embodiment, the intermediate circuit layer MML may include crack detection lines. In an embodiment, for example, the intermediate circuit layer MML may include a first crack detection line MCD1a_1 and a second crack detection line MCD1a_2. In an embodiment, the second crack detection line MCD1a_2 may be disposed on the first crack detection line MCD1a_1. In an embodiment, for example, the first crack detection line MCD1a_1 may be disposed in the same layer as the fifth circuit layer 515, and the second crack detection line MCD1a_2 may be disposed in the same layer as the sixth circuit layer 516. However, this disclosure is not limited thereto. In an embodiment, the second crack detection line MCD1a_2 may be disposed below the first crack detection line MCD1a_1. In an embodiment, for example, the first crack detection line MCD1a_1 may be disposed in the same layer as the sixth circuit layer 516, and the second crack detection line MCD1a_2 may be disposed in the same layer as the fifth circuit layer 515.

[0161] In an embodiment, the first crack detection line MCD1a_1, the second crack detection line MCD1a_2, the fifth circuit layer 515, and the sixth circuit layer 516 may comprise the same metal as each other. In an embodiment, for example, each of the first crack detection line MCD1a_1, the second crack detection line MCD1a_2, the fifth circuit layer 515, and the sixth circuit layer 516 may comprise aluminum (Al) or copper (Cu). These may be used individually or in combination with each other. However, this disclosure is not limited thereto.

[0162] The detection line connection electrode MCE can be disposed in an intermetallic insulating layer disposed between the fifth circuit layer 515 and the sixth circuit layer 516. The detection line connection electrode MCE can contact the first crack detection line MCD1a_1 and the second crack detection line MCD1a_2. Accordingly, the detection line connection electrode MCE can electrically connect the first crack detection line MCD1a_1 and the second crack detection line MCD1a_2. In an embodiment, the detection line connection electrode MCE can comprise the same metal as the via 520. In an embodiment, for example, each of the detection line connection electrode MCE and the via 520 can comprise tungsten (W). However, this disclosure is not limited thereto.

[0163] Cover pad 519 may be disposed on a circuit layer. In an embodiment, for example, cover pad 519 may be disposed on an eighth circuit layer 518. Cover pad 519 can effectively prevent the circuit layer of the crack detection structure 500 disposed beneath cover pad 519 from being damaged in subsequent processes. In an embodiment, for example, cover pad 519 may include titanium (Ti), tantalum (Ta), or titanium nitride (TiN), etc. However, this disclosure is not limited thereto.

[0164] When crack detection lines are arranged in the lower circuit layer (BML) of the crack detection structure 500, if a crack does not propagate to the lower circuit layer (BML), the crack may go undetected. For example, when the first crack detection line MCD1a_1 is arranged in the same layer as the first circuit layer 511 and the second crack detection line MCD1a_2 is arranged in the same layer as the second circuit layer 512, if a crack does not propagate to the first circuit layer 511 and the second circuit layer 512, the crack may go undetected. In other words, when crack detection lines are arranged in the lower circuit layer (BML) of the crack detection structure 500, the sensitivity for crack detection may be relatively low.

[0165] When crack detection lines are arranged in the upper circuit layer UML of the crack detection structure 500, there is a possibility that even insignificant cracks may be detected. For example, when the first crack detection line MCD1a_1 is arranged in the same layer as the seventh circuit layer 517 and the second crack detection line MCD1a_2 is arranged in the same layer as the eighth circuit layer 518, there is a possibility that even insignificant cracks may be detected. In other words, when crack detection lines are arranged in the upper circuit layer UML of the crack detection structure 500, the sensitivity of crack detection may be relatively high.

[0166] According to embodiments of this disclosure, crack detection lines can be arranged in the intermediate circuit layer MML of the crack detection structure 500. In an embodiment, for example, the first crack detection line MCD1a_1 can be arranged in the same layer as the fifth circuit layer 515, and the second crack detection line MCD1a_2 can be arranged in the same layer as the sixth circuit layer 516. In such an embodiment, because the crack detection lines are arranged in the intermediate circuit layer MML of the crack detection structure 500, the crack detection structure 500 can detect cracks that are not blocked by the first blocking structure 300 and the second blocking structure 400 with appropriate or desired crack detection sensitivity.

[0167] Figure 8 , Figure 9 , Figure 10 and Figure 11 It is a diagram manufacturing process. Figure 1 A view of an embodiment of a method for displaying a device. Figure 10 and Figure 11 It is along Figure 9 The cross-sectional view taken from line III-III'. In the following text, the display device DD may be omitted or simplified in relation to the above reference. Figures 1 to 7 Any repeated detailed descriptions of the same element as described.

[0168] refer to Figure 8 , Figure 9 and Figure 10The substrate can be formed from a wafer WA. In an embodiment, the wafer WA can include silicon. In an embodiment, for example, the wafer WA can be a monocrystalline silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer.

[0169] The wafer WA can have a front surface FRS and a back surface BOS. Semiconductor patterns can be formed on the front surface FRS of the wafer WA. In an embodiment, for example, the substrate can be a silicon semiconductor substrate formed by a CMOS process.

[0170] include Figure 4 The light-emitting elements (LD), encapsulation layers (TFE), or color filter layers (CFL) shown in the diagram can be arranged or sequentially formed on the substrate. In an embodiment, the display device DD can be an OLEDoS display device in which the organic light-emitting elements are arranged on a silicon semiconductor substrate.

[0171] The thickness DE of a wafer WA can be controlled through a back-side grinding process. For example, the thickness DE of a wafer WA can be reduced by removing a portion of the back surface BOS of the wafer WA during the back-side grinding process.

[0172] In an embodiment, such as Figure 9 and Figure 10 As shown, a scribing line SL can be defined or formed on the wafer WA. In the plan view, the scribing line SL can be located between semiconductor chips 10 and 20. The scribing line SL can be formed to a depth of approximately half the thickness DE of the wafer WA.

[0173] A first barrier structure 300 and a second barrier structure 400 can be formed on the wafer WA. The first barrier structure 300 can be formed adjacent to the scribe line SL. During the process of separating individual semiconductor chips 10 and 20 along the scribe line SL, the first barrier structure 300 can prevent cracks from propagating toward the display area DA. The second barrier structure 400 can be formed between the first barrier structure 300 and the display area DA. The second barrier structure 400 can be spaced apart from the scribe line SL by the first barrier structure 300. During the back-side polishing process, the second barrier structure 400 can prevent moisture from penetrating toward the display area DA.

[0174] A crack detection structure 500 can be formed on the wafer WA. The crack detection structure 500 can be formed between the second barrier structure 400 and the display area DA. The crack detection structure 500 can be spaced apart from the first barrier structure 300 and the second barrier structure 400. The intermediate circuit layer (MML, reference) of the crack detection structure 500... Figure 7 It may include a first crack detection line MCD1a_1 and a second crack detection line MCD1a_2.

[0175] refer to Figure 11The wafer WA can be separated into semiconductor chips 10 and 20. In an embodiment, for example, the wafer WA can be separated into semiconductor chips 10 and 20 by a sawing process and a packaging process. When a crack occurs in the wafer WA during the process of dicing the wafer WA, the crack detection structure 500 can detect the crack that is not blocked by the first blocking structure 300 and the second blocking structure 400.

[0176] Figure 12 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0177] refer to Figure 12 The electronic device 1000 according to the embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14. The display device DD according to the embodiment can be applied to various electronic devices. The electronic device 1000 according to the embodiment may include the aforementioned display device DD, and in addition to the display device DD, may further include modules or devices with other additional functions.

[0178] The processor 12 may include at least one selected from a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor, an image signal processor (ISP), and a controller.

[0179] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0180] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 1000. In other words, the power module 14 can provide power to the display device DD according to the above embodiment.

[0181] At least one of the components of the electronic device 1000 described above may be included in the display device DD according to the above embodiment. Additionally, some of the individual modules functionally included in a single module may be included in the display device, while others may be provided separately from the display device. In an embodiment, for example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided in the form of other devices in the electronic device 1000 besides the display device.

[0182] Figure 13 These are schematic diagrams of electronic devices according to various embodiments.

[0183] refer to Figure 13 Various embodiments of electronic devices to which the display device is applied may include image display electronic devices such as smartphones 1000_1a, tablet PCs 1000_1b, laptop computers 1000_1c, televisions 1000_1d, or desktop monitors 1000_1e; wearable electronic devices including display modules such as smart glasses 1000_2a, head-mounted displays 1000_2b, or smartwatches 1000_2c; and vehicle electronic devices 1000_3 including display modules, such as central information displays (CIDs) or interior mirror displays that can be installed on the instrument panel, central dashboard, and dashboard of a car.

[0184] The embodiments disclosed herein can be applied to various display devices, such as display devices for vehicles, ships and aircraft, portable communication devices, display devices for exhibition or information transmission, and medical display devices.

[0185] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, and to fully convey the concept of the invention to those skilled in the art.

[0186] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, comprising: A substrate, including a display area and a peripheral area surrounding the display area; Multiple sub-pixels are disposed on the substrate and in the display area; A first blocking structure is disposed on the substrate, in the peripheral region, and arranged along the edge of the substrate in a plan view, wherein the first blocking structure blocks crack propagation; A second barrier structure is disposed on the substrate, in the peripheral region, and arranged in the plan view between the display area and the first barrier structure, wherein the second barrier structure blocks moisture; and A crack detection structure is disposed on the substrate, in the peripheral region, and arranged in the plan view between the display area and the second blocking structure. The crack detection structure includes: The lower circuit layer is disposed on the substrate; An intermediate circuit layer, disposed on the lower circuit layer and including crack detection lines; and The upper circuit layer is disposed on the intermediate circuit layer.

2. The display device according to claim 1, wherein, In the plan view, the crack detection structure is spaced apart from the first blocking structure and the second blocking structure.

3. The display device according to claim 1, in, In the plan view, the second blocking structure surrounds the crack detection structure, and In the plan view, the first blocking structure surrounds the second blocking structure.

4. The display device according to claim 1, further comprising: A crack detection circuit is disposed on the substrate in the peripheral area. The crack detection line includes: The first crack detection line receives the test voltage; and A second crack detection line, wherein a first end of the second crack detection line is electrically connected to the first crack detection line, and a second end of the second crack detection line, opposite to the first end, is electrically connected to the crack detection circuit. The second crack detection line is set on the first crack detection line.

5. The display device according to claim 4, in, The crack detection structure comprises a first circuit layer, a second circuit layer, a third circuit layer, a fourth circuit layer, a fifth circuit layer, a sixth circuit layer, a seventh circuit layer, and an eighth circuit layer sequentially stacked on the substrate. The lower circuit layer includes the first circuit layer to the fourth circuit layer. The intermediate circuit layer includes the fifth circuit layer and the sixth circuit layer, and The upper line layer includes the seventh line layer and the eighth line layer.

6. The display device according to claim 5, in, The first crack detection line and the fifth circuit layer are disposed in the same layer, and The second crack detection line and the sixth circuit layer are located in the same layer.

7. The display device according to claim 1, wherein, The substrate includes a silicon wafer.

8. A display device, comprising: A substrate, including a display area and a peripheral area surrounding the display area; Multiple sub-pixels are disposed on the substrate and in the display area; A blocking structure is disposed on the substrate, in the peripheral region, and arranged along the edge of the substrate in a plan view to surround the display area; A crack detection structure is disposed on the substrate, in the peripheral region, and arranged in the plan view between the display area and the blocking structure. The crack detection structure includes a lower circuit layer disposed on the substrate, an intermediate circuit layer disposed on the lower circuit layer and including crack detection lines, and an upper circuit layer disposed on the intermediate circuit layer. Multiple pads are disposed on the substrate in the peripheral region, so as to be adjacent to the edge of the substrate in the plan view; A crack detection circuit is disposed on the substrate, in the peripheral region, and arranged in the plan view between the display area and the plurality of pads, and is electrically connected to the crack detection line; and The demultiplexing portion is disposed on the substrate, in the peripheral region, and arranged in the plan view between the display area and the crack detection circuit.

9. The display device according to claim 8, wherein, The crack detection line includes: The first crack detection line receives the test voltage; and A second crack detection line, wherein a first end of the second crack detection line is electrically connected to the first crack detection line, and a second end of the second crack detection line, opposite to the first end, is electrically connected to the crack detection circuit. At least one of the plurality of pads provides the test voltage to the first crack detection line.

10. The display device according to claim 9, wherein, The second crack detection line is set on the first crack detection line.

11. The display device according to claim 9, further comprising: Multiple fan-out lines are disposed on the substrate, in the peripheral region, and arranged below the demultiplexing portion in the plan view; as well as Multiple data lines are disposed on the substrate, in the display area, and connected to the multiple sub-pixels.

12. The display device according to claim 11, wherein, The crack detection circuit includes: A constant voltage line, to which the test voltage is applied; and A detection switch is connected to each of the multiple fan-out lines.

13. The display device according to claim 12, in, At least one of the multiple fan-out lines is electrically connected to the constant voltage line via the detection switch, and At least one of the multiple fan-out lines is electrically connected to the second crack detection line via the detection switch.

14. The display device according to claim 9, in, The crack detection structure comprises a first circuit layer, a second circuit layer, a third circuit layer, a fourth circuit layer, a fifth circuit layer, a sixth circuit layer, a seventh circuit layer, and an eighth circuit layer sequentially stacked on the substrate. The lower circuit layer includes the first circuit layer to the fourth circuit layer. The intermediate circuit layer includes the fifth circuit layer and the sixth circuit layer. The upper circuit layer includes the seventh circuit layer and the eighth circuit layer. The first crack detection line and the fifth circuit layer are disposed in the same layer, and The second crack detection line and the sixth circuit layer are located in the same layer.

15. An electronic device comprising: The display device according to any one of claims 1 to 14; as well as The processor provides image data signals and input control signals to the display device.

Images