Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a display area and a non-display area located on one side of the display area, a substrate, a source and drain electrode layer arranged on one side of the substrate and a plurality of first supporting columns arranged on the side, away from the substrate, of the source and drain electrode layer are arranged in the non-display area, and the source and drain electrode layer comprises a plurality of first signal lines located in the non-display area; the first signal line is used for transmitting a high-potential signal; the orthographic projection of the first supporting column on the substrate is located in the orthographic projection of the source and drain electrode layer on the substrate, and the first supporting column and the first signal line are arranged in a non-overlapping mode, namely, the first supporting column is arranged in the area where the source and drain electrode layer with high flatness is located, and meanwhile the first signal line for transmitting high-potential signals is avoided; the technical problem that the lower film layer is cracked due to the fact that the supporting columns are not well positioned is solved, corrosion of the metal wires is avoided, and the display stability of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] With the development of display devices, the requirements for thin-film transistors in existing display devices are becoming increasingly stringent. Low-temperature polycrystalline silicon thin-film transistors are widely used in liquid crystal display panels and OLED (Organic Light-Emitting Diode) display panels due to their advantages of fast switching speed and low power consumption.

[0003] In current display panels, support pillars are usually required between two substrates to adjust the spacing between them. However, the surface of the current array substrate away from the substrate has poor flatness. The support pillars are poorly positioned, which can cause the lower film layer to crack and lead to metal corrosion, resulting in display abnormalities in the display panel. Summary of the Invention

[0004] This application provides a display panel to solve the technical problem of display abnormalities in existing display panels.

[0005] According to a first aspect of this application, a display panel is provided, comprising a display area and a non-display area located on one side of the display area, wherein the non-display area is provided with: Substrate; A source-drain layer is disposed on one side of the substrate. The source-drain layer includes a plurality of first signal lines located in the non-display area. The first signal lines are used to transmit high-potential signals. A plurality of first support pillars are disposed on the side of the source / drain layer away from the substrate; and Wherein, the orthographic projection of the first support pillar on the substrate is located within the orthographic projection of the source and drain layers on the substrate, and the plurality of first support pillars are arranged in a non-overlapping manner with the plurality of first signal lines.

[0006] According to a second aspect of this application, a display device is provided, the display panel including the display panel as described in any of the above embodiments.

[0007] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0010] Figure 1 This is a perspective view of a contrast display device.

[0011] Figure 2 for Figure 1 The comparison shows a cross-sectional view of the device's cross section AA.

[0012] Figure 3 for Figure 1 The cross-sectional view of the device BB in the comparison display is shown.

[0013] Figure 4 This is a structural diagram of the display device of this application.

[0014] Figure 5 This is a top view of the display panel of this application.

[0015] Figure 6 This is a cross-sectional schematic diagram of the array substrate of this application.

[0016] Figure 7 for Figure 5 Structure diagram of region M in the middle. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0018] In order to illustrate the principle of the technical problem arising in the embodiments of this application, some comparative display devices are provided. It should be understood that these comparative display devices cannot be regarded as prior art in the embodiments of this application. Figure 1 This is a perspective view of a contrast display device. Figure 2 for Figure 1 The comparison display shows the AA cross-sectional view of the device. Figure 3 for Figure 1 The comparison shows the BB cross-sectional view of the device.

[0019] like Figures 1 to 3 As shown, the comparative display device includes a substrate 11, a light-shielding film 12, a first insulating film 13, an active film 14, a second insulating film 15, a gate film 16, a third insulating film 17, a source-drain film 18, a planarization film 191, a bottom electrode film 192, a passivation film 193, and a top electrode film 194. The active film 14 includes a channel region 143, a lightly doped region 142, and a heavily doped region 141.

[0020] from Figure 2 and Figure 3 As can be seen, forming a contrast display device requires nine photomasks: one for forming the light-shielding film 12, one for forming the first insulating film 13 and the active film 14, one for forming the gate film 16, one for forming the vias of the third insulating film 17, one for forming the source / drain film 18, one for forming the vias of the planarization film 191, one for forming the bottom electrode film 192, one for forming the vias of the passivation film 193, and one for forming the top electrode film 194. It is evident that the formation process of a contrast display device requires a large number of photomasks and involves numerous steps, resulting in a complex process, high cost, and low fabrication efficiency. Therefore, existing display devices suffer from the technical problem of complex fabrication processes leading to low fabrication efficiency.

[0021] To reduce the number of photomasks, the planarization layer can be removed, allowing the passivation layer to directly cover the source and drain layers. However, since the passivation layer is usually made of inorganic material, it does not have leveling properties. Furthermore, the source and drain layers are quite thick, resulting in poor flatness on the side of the passivation layer away from the substrate. This leads to a technical problem where the support pillars, due to poor positioning, cause the underlying film layer to crack, resulting in metal corrosion and causing display abnormalities in the display panel.

[0022] This application provides a display panel and a display device to address the aforementioned technical problems.

[0023] Please see Figures 4 to 7 This application provides a display panel 200, which includes a display area AA and a non-display area NA located on one side of the display area AA. The non-display area NA is provided with a substrate 21, a source-drain layer 27 disposed on one side of the substrate 21, and a plurality of first support pillars PS1 disposed on the side of the source-drain layer 27 away from the substrate 21. The orthographic projection of the first support pillars PS on the substrate 21 is located within the orthographic projection of the source-drain layer 27 on the substrate 21, and the plurality of first support pillars PS1 are not overlapped with the plurality of first signal lines 27a.

[0024] This application improves the technical problem of lower film layer cracking due to poor positioning of the support pillars by ensuring that the orthographic projection of the multiple first support pillars PS1 in the display panel 200 onto the substrate 21 is located within the orthographic projection of the source / drain layer 27 onto the substrate 21. This is equivalent to placing the first support pillars in the region where the source / drain layer has high flatness. At the same time, the first support pillars PS1 and the first signal line 27a are not overlapped, which is equivalent to avoiding the first signal line 27a that transmits high-potential signals. This avoids the problem of high voltage in the first signal line 27a aggravating the electrochemical corrosion of metal wires under high temperature and high humidity environment, and improves the display stability of the display panel 200.

[0025] The technical solution of this application is described below with reference to specific embodiments.

[0026] Please see Figure 4 and Figure 5 This application provides a display device 500, including a display panel 200. The display panel 200 includes an array substrate 100, a color filter substrate 300, and a frame adhesive SL disposed between the array substrate 100 and the color filter substrate 300. The frame adhesive SL is arranged in a ring structure. A liquid crystal layer LC is filled in the closed space formed by the array substrate 100, the color filter substrate 300, and the frame adhesive SL.

[0027] Please see Figure 4 The display panel 200 also includes a support structure PS disposed between the array substrate 100 and the color filter substrate 300. One end of the support structure PS contacts the array substrate 100, and the other end of the support structure PS contacts the color filter substrate 300. The support structure PS is used to adjust the spacing between the array substrate 100 and the color filter substrate 300.

[0028] It should be noted that the display panel 200 of this application also includes another support structure with a smaller thickness disposed between the array substrate 100 and the color filter substrate 300, which is disposed in contact with the color filter substrate 300 and spaced apart from the array substrate 100.

[0029] It should be noted that the support structure PS of this application can be directly disposed on the array substrate 100 or disposed on the color filter substrate 300. This application does not make specific limitations. The following description takes the support structure PS disposed on the side of the color filter substrate 300 as an example.

[0030] Please see Figure 6 The array substrate 100 includes a buffer layer 22 disposed on one side of the substrate 21. The buffer layer 22 can be laid on the entire array substrate 100. The buffer layer 22 is in direct contact with the substrate 21, thereby eliminating the need for a light-shielding layer, reducing the number of film layers in the array substrate 100, simplifying the fabrication process of the array substrate 100, and reducing costs.

[0031] In this embodiment, the material of the buffer layer 22 may be a compound composed of nitrogen, silicon and oxygen. For example, the material of the buffer layer 22 may be a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0032] Please see Figure 6 The array substrate 100 also includes an active layer 23 disposed on the side of the buffer layer 22 away from the substrate 21. The active layer 23 may include a channel portion 231 and a first doped portion 232a and a second doped portion 232b disposed on both sides of the channel portion 231.

[0033] In this embodiment, the active layer 23 can be made of silicon semiconductor, such as polycrystalline silicon, low-temperature polycrystalline silicon, etc.

[0034] Please see Figure 6 The array substrate 100 also includes a gate insulating layer 24 disposed on the side of the active layer 23 away from the substrate 21; the material of the gate insulating layer 24 may be a compound composed of nitrogen, silicon and oxygen elements, for example, the material of the gate insulating layer 24 may be a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0035] Please see Figure 6 The array substrate 100 also includes a gate layer 25 disposed on the gate insulating layer 24. The gate layer 25 includes a gate disposed corresponding to the channel portion 231. The doping process of the gate in the active layer 23 serves as a mask.

[0036] In this embodiment, the material of the gate layer 25 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the material of the gate layer 25 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0037] Please see Figure 6 The array substrate 100 also includes an inter-insulating layer 26 disposed on the side of the gate layer 25 away from the substrate 21, and the inter-insulating layer 26 can be laid in an entire layer.

[0038] Please see Figure 6 The array substrate 100 also includes a source / drain layer 27 disposed on the side of the inter-insulating layer 26 away from the substrate 21. The source / drain layer 27 includes a first electrode 271 and a second electrode 272 disposed at intervals. The first electrode 271 passes through a via and is electrically connected to a first doped portion 232a, and the second electrode 272 passes through a via and is electrically connected to a second doped portion 232b.

[0039] In this embodiment, the first electrode 271 is the source and the second electrode 272 is the drain; or, the first electrode 271 is the drain and the second electrode 272 is the source.

[0040] In this embodiment, the material of the source / drain layer 27 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the material of the source / drain layer 27 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0041] It should be noted that the source-drain layer 27 of this application may include signal lines or connecting electrodes such as the source and drain of a thin-film transistor, data lines, clock signal lines, high-potential lines, and stage transmission signal lines. The data lines are used to transmit data signals to the sub-pixels in the display area AA, the clock signal lines are used to transmit clock signals to the gate driving circuit 400 in the non-display area NA, the high-potential lines are used to transmit high-potential signals to the gate driving circuit 400 in the non-display area NA, and the stage transmission signal lines are used to transmit stage transmission signals to the gate driving circuit 400 in the non-display area NA.

[0042] Please see Figure 6 The array substrate 100 also includes a passivation layer 29 disposed on the side of the source / drain layer 27 away from the substrate 21, and the passivation layer 29 can be laid in an entire layer.

[0043] In this embodiment, the materials of the inter-insulating layer 26 and the passivation layer 29 may include compounds composed of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0044] Please see Figure 6 The array substrate 100 also includes a common electrode layer 31 disposed on the side of the passivation layer 29 away from the substrate 21, and the material of the common electrode layer 31 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, etc.

[0045] Please see Figure 6 The array substrate 100 also includes a pixel electrode layer 28 disposed on the side of the inter-insulating layer 26 away from the substrate 21. The pixel electrode layer 28 includes a plurality of pixel electrodes disposed at intervals. The pixel electrodes can be electrically connected to one of the first electrode 271 or the second electrode 272. The material of the pixel electrode layer 28 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, etc.

[0046] Please see Figure 6The array substrate 100 also includes a light-shielding layer LS disposed on one side of the substrate 21. The channel portion 231 of the active layer 23 is orthogonally projected onto the light-shielding layer LS and located within the light-shielding layer LS, thereby preventing the device effect of the thin film transistor from being reduced due to light entering the channel portion 231, that is, preventing the leakage current from increasing.

[0047] In this embodiment, the light-shielding layer LS can be a light-shielding metal or other materials with light-shielding properties, such as molybdenum, aluminum, copper, titanium, or alloys of the above materials or stacks of the above materials.

[0048] It should be noted that the display panel 200 also includes an alignment film disposed on the side of the common electrode layer 31 away from the substrate 21, and the support structure PS is in direct contact with the alignment film.

[0049] Please see Figure 7 The display panel 200 includes a gate drive circuit 400 disposed in the non-display area NA and multiple second signal lines 27b disposed on the side of the gate drive circuit 400 away from the display area AA. The second signal lines 27b can be made of the metal material of the source and drain layer 27.

[0050] Please see Figure 7 The first signal line 27a may include a high-potential line Vgh that transmits a high-potential signal and a forward / reverse scan control line UD. Both the high-potential line Vgh and the forward / reverse scan control line UD are arranged along the first direction X and extend along the second direction Y. Both the high-potential line Vgh and the forward / reverse scan control line UD have overlapping portions with the gate drive circuit 400, that is, both the high-potential line Vgh and the forward / reverse scan control line UD are electrically connected to a certain potential node in the gate drive circuit 400.

[0051] In this embodiment, the forward and reverse scan control lines UD are used to control the scanning direction of the gate driving circuit 400. For example, the display panel is usually provided with two forward and reverse scan control lines UD. When the first forward and reverse scan control line UD outputs a high-level signal, the gate driving circuit 400 is performing forward scanning, that is, transmitting the stage transmission signal from the first stage to the nth stage gate driving circuit 400; when the second forward and reverse scan control line UD outputs a high-level signal, the gate driving circuit 400 is performing reverse scanning, that is, transmitting the stage transmission signal from the nth stage to the first stage gate driving circuit 400.

[0052] In this embodiment, the gate driving circuit 400 includes a signal generation section 410 and a signal output section 420 that are electrically connected. The signal output section 420 is located on the side of the signal generation section 410 near the display area AA. The high potential line Vgh and the forward and reverse scan control line UD are both located in the area where the signal generation section 410 is located.

[0053] It should be noted that when the support structure PS is placed on the signal line that transmits high-potential power signals, the lower film layer may crack due to poor positioning. In the high-voltage and high-humidity environment, the first signal line 27a is prone to electrochemical corrosion, which leads to the failure of the gate drive circuit 400 and causes the display panel 200 to display abnormally.

[0054] This application avoids the first signal line 27a by setting the support structure PS to be non-overlapping with the first signal line 27a, thus avoiding the problem of high voltage in the first signal line 27a aggravating the electrochemical corrosion of the metal wire under high temperature and high humidity environment. It also avoids the technical problem of short circuit or open circuit in the first signal line 27a, improves the stability of the stage transmission signal of the gate drive circuit 400, and improves the display effect of the display panel 200.

[0055] It should be noted that in this application, the first direction X is the row direction and the second direction Y is the column direction.

[0056] Please see Figure 7 The multiple support structures PS include first support pillars PS1, and the orthographic projection of the multiple first support pillars PS1 on the substrate 21 is located within the orthographic projection of the multiple second signal lines 27b on the substrate 21.

[0057] In this embodiment, the voltage transmitted by the second signal line 27b is less than the voltage transmitted by the first signal line 27a. For example, the second signal line 27b can be a clock signal line CK, an initial signal line STV, and a test signal line CT. The clock signal line CK, the initial signal line STV, and the test signal line CT can be arranged at intervals along the first direction X and extended along the second direction Y. The voltage transmitted by the second signal line 27b is generally less than the voltage transmitted by the high potential line Vgh and the forward and reverse scan control line UD.

[0058] Please see Figure 7 In the direction away from the display area AA, the gate drive circuit 400 can be equipped with 6 clock signal lines CK, 2 initial signal lines STV and 8 test signal lines CT.

[0059] In this embodiment, since multiple second signal lines 27b are evenly arranged in the non-display area NA, and the width occupied by multiple second signal lines 27b in the non-display area is large, this application can evenly arrange multiple second support pillars PS2 on the corresponding second signal lines 27b, and the orthographic projection of multiple first support pillars PS1 on the substrate 21 is located within the orthographic projection of multiple second signal lines 27b on the substrate 21.

[0060] In this embodiment, since the surface of the signal line made of the source-drain layer 27 away from the substrate 21 is a relatively flat surface, the passivation layer 29 covering the surface of the source-drain layer 27 and the alignment film also have high flatness. The surface of the support structure PS near the substrate 21 is bonded to the alignment film in this area, which increases the contact area between the support structure PS and the array substrate 100, improves the friction between the support structure PS and the array substrate 100, improves the technical problem of the support structure PS scratching the underlying film layer due to sliding, and improves the stability of the display panel 200.

[0061] Please see Figure 7 Multiple first support pillars PS1 are disposed on the side away from the substrate 21 of one of the two adjacent second signal lines 27b; for example, in 6 clock signal lines CK, 2 initial signal lines STV and 8 test signal lines CT, the first support pillars PS1 can be disposed on the side away from the substrate 21 of one of the two adjacent second signal lines 27b so that the first support pillars PS1 are uniformly disposed in the non-display area NA.

[0062] Please see Figure 7 The multiple support structures PS also include multiple second support pillars PS2, which are located on the side of the multiple second signal lines 27b away from the gate drive circuit 400. Meanwhile, the source and drain layer 27 also includes a spacer pillar 273 located on the side of the multiple second signal lines 27b away from the gate drive circuit 400. A second support pillar PS2 is located on the side of a spacer pillar 273 away from the substrate 21, and the orthographic projection of the second support pillar PS2 on the substrate 21 is located within the orthographic projection of the spacer pillar 273 on the substrate 21.

[0063] It should be noted that, since no structure for improving the strength of the frame adhesive SL is provided within the frame adhesive SL in this application, a certain number of support structures PS need to be provided within the area covered by the frame adhesive SL, so that the support structures PS are embedded within the frame adhesive SL to improve the strength of the frame adhesive SL. Since no signal lines prepared by the source-drain layer 27 are required on the side of the multiple second signal lines 27b away from the gate drive circuit 400, the support structures PS in this area are usually directly provided on the insulating film layer. However, since the first support pillar PS1 is provided on the metal line of the source-drain layer 27, there is a step difference between the first support pillar PS1 and the second support pillar PS2. This results in the second support pillar PS2 having a lower height within the frame adhesive SL than the first support pillar PS1, making the stability of the second support pillar PS2 lower than that of the first support pillar PS1. The second support pillar PS2 is prone to sliding, leading to gaps in the frame adhesive SL and sealing failure.

[0064] In this embodiment, the present application provides a spacer pillar 273 between the second support pillar PS2 and the substrate 21, and the spacer pillar 273 is made of the material of the source-drain layer 27. That is, both the second support pillar PS2 and the first support pillar PS1 are disposed on the material of the source-drain layer 27, eliminating the step difference between the first support pillar PS1 and the second support pillar PS2, thereby increasing the height of the second support pillar PS2 within the frame adhesive SL. This is equivalent to the depth at which multiple second support pillars PS2 and multiple first support pillars PS1 are embedded within the frame adhesive SL, avoiding the technical problem of multiple second support pillars PS2 moving, and improving the technical problem of frame adhesive SL sealing failure caused by the difference in stability of support pillars PS in different areas.

[0065] Please see Figure 7 The frame adhesive SL can cover the first support post PS1, the second support post PS2, and at least part of the gate drive circuit 400; for example, the boundary of the frame adhesive SL near the display area AA is spaced apart from the signal output section 420.

[0066] Please see Figure 7 The first support column PS1 and the second support column PS2 are arranged at intervals along the first direction X and the second direction Y. The first support columns PS1 in adjacent rows are staggered, and the second support columns PS2 in adjacent rows are staggered. The first direction X and the second direction Y intersect, and the second direction Y is parallel to the extension direction of the first signal line 27a.

[0067] At the same time, the distribution density of the first support column PS1 is less than or equal to the distribution density of the second support column PS2; that is, within a unit area, the number of first support columns PS1 is less than or equal to the number of second support columns PS2, and the distance between two adjacent first support columns PS1 is greater than or equal to the distance between two adjacent second support columns PS2.

[0068] Please see Figure 7 The multiple support structures PS also include a third support column PS3, which is located on the side of the second support column PS2 away from the display area AA. The third support column PS3 and the frame adhesive SL are not overlapped.

[0069] In this embodiment, since the frame adhesive SL has a certain coating precision, in order to ensure the strength of the frame adhesive SL at the edge of the display panel 200, this application can provide a sufficient number of third support pillars PS3 at the edge of the array substrate 100 to meet the strength requirements of the frame adhesive SL at the edge of the display panel 200.

[0070] Please see Figure 7The display panel 200 also includes a ground line GND disposed between a plurality of second support pillars PS2 and a plurality of second signal lines 27b. Since the ground line GND of this application is made of the material of the gate layer and two adjacent ground lines GND are electrically connected through the material of the source and drain layers 27, the flatness of the area where the ground line GND is located is less than the flatness of the area where the plurality of second signal lines 27b are located. Therefore, this application does not provide a support structure PS on the ground line GND.

[0071] Please see Figure 7 The display panel 200 also includes a first groove HL1 and a second groove HL2. The first groove HL1 is located between the ground wire GND and a plurality of second signal lines 27b, and the second groove HL2 is located between a plurality of second support pillars PS2 and a plurality of third support pillars PS3. In order to ensure the stability of the connection between the frame adhesive SL and the array substrate 100, the frame adhesive SL can be embedded in the first groove HL1 and the second groove HL2, which increases the contact area between the frame adhesive SL and the array substrate 100 and improves the connection and fixation of the frame adhesive SL and the array substrate 100.

[0072] In this embodiment, the first groove HL1 and the second groove HL2 can be slotted in the passivation layer 29, or in the inter-insulating layer 26 and the passivation layer 29, or in the gate insulating layer 24, the inter-insulating layer 26 and the passivation layer 29, or in the buffer layer 22, the gate insulating layer 24, the inter-insulating layer 26 and the passivation layer 29.

[0073] Please see Figure 7 The display panel 200 also includes at least one barrier DM, which extends in the same direction as the first signal line 27a, and the barrier DM and the signal output section 420 are arranged overlapping each other.

[0074] In this embodiment, the material of the barrier wall DM can be the same as the material of the support PS, and the barrier wall DM can be arranged in a strip shape along the second direction Y; for example, this application can provide two barrier walls DM that are spaced apart, and the two barrier walls DM can be spaced apart on the signal output part 420. The barrier wall DM is used to block the liquid crystal material to prevent the liquid crystal material from flowing too fast and impacting the frame adhesive SL, causing the frame adhesive SL to fail.

[0075] Please see Figure 7 The display panel may also include multiple first buffer pillars BF1, which are located on one side of the retaining wall DM and overlap with the wires located in the source-drain layer 27 of the signal output section 420.

[0076] In this embodiment, the first buffer post BF1 can act as a blocking post to block the flow of liquid crystal material, and work in conjunction with the baffle DM to reduce the flow speed of the liquid crystal material, so as to prevent the liquid crystal material from flowing too fast and impacting the frame adhesive SL, causing the frame adhesive SL to fail.

[0077] In this embodiment, the first buffer post BF1 can be disposed between two spaced-apart barrier walls DM, or disposed on the side of the two spaced-apart barrier walls DM near the display area AA.

[0078] In this embodiment, a plurality of first buffer pillars BF1 are arranged at intervals along the first direction and the second direction, and the first buffer pillars BF1 in adjacent rows correspond one-to-one in the column direction; at the same time, since overlapping source-drain layers 27 and gate layers 25 are provided in the middle region of the signal output section 420, the first buffer pillars BF1 of this application are all disposed on both sides of the signal output section 420 in the second direction.

[0079] Please see Figure 7 In the non-display area NA, there are also multiple second buffer pillars BF2. The second buffer pillars BF2 are located on the side of the barrier wall DM close to the display area, and the second buffer pillars BF2 are not overlapped with the signal output section 420. The second buffer pillars BF2 and the first buffer pillars BF1 can be made of the same material.

[0080] In this embodiment, the distribution density of the second buffer column BF2 is less than that of the first buffer column BF1, which means that the number of second buffer columns BF2 is less than the number of first buffer columns BF1 in a unit area, and the distance between two adjacent second buffer columns BF2 is greater than the distance between two adjacent first buffer columns BF1.

[0081] In this embodiment, since the first buffer pillar BF1 is mainly used to block the flow of liquid crystal, the first buffer pillar BF1 of this application needs to be set with a large area so that the first buffer pillar BF1 has a certain blocking effect. For example, the area of ​​the first buffer pillar BF1 can be larger than the area of ​​the first support pillar PS1.

[0082] Similarly, the area of ​​the second buffer column BF2 in this application can be larger than the area of ​​the first support column PS1.

[0083] It should be noted that the areas of the first support column PS1, the second support column PS2, and the third support column PS3 in this application can be the same.

[0084] It should be noted that, in order to ensure the flatness of the surfaces in contact with the first support pillar PS1 and the second support pillar PS2 in this application, this application may provide only the source and drain layer 27 in the area where the first support pillar PS1 and the second support pillar PS2 are located, that is, no other metal material is provided between the source and drain metal and the substrate 21 in this area.

[0085] For details, please refer to Figure 4 This application provides a display device 500, which includes a display panel 200 as described in the above embodiments.

[0086] Specifically, the display device 500 also includes a backlight module 300.

[0087] It should be noted that the display device in this application can be any product or component with display function, such as an in-vehicle screen, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0088] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0089] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0090] In the above embodiments, the structures shown in the accompanying drawings are only schematic diagrams, and the specific structure of the display panel of this application is based on the description in the specification.

[0091] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0092] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area located on one side of the display area, wherein the non-display area is provided with: Substrate; A source-drain layer is disposed on one side of the substrate. The source-drain layer includes a plurality of first signal lines located in the non-display area. The first signal lines are used to transmit high-potential signals. Multiple first support pillars are disposed on the side of the source / drain layer away from the substrate; as well as Wherein, the orthographic projection of the first support pillar on the substrate is located within the orthographic projection of the source and drain layers on the substrate, and the plurality of first support pillars are arranged in a non-overlapping manner with the plurality of first signal lines.

2. The display panel according to claim 1, characterized in that, The display panel includes a gate driving circuit disposed in the non-display area and a plurality of second signal lines disposed on the side of the gate driving circuit away from the display area, wherein the voltage transmitted by the second signal lines is less than the voltage transmitted by the first signal lines. The orthographic projection of the plurality of first support pillars on the substrate is located within the orthographic projection of the plurality of second signal lines on the substrate.

3. The display panel according to claim 2, characterized in that, The first support post is located on the side of one of the two adjacent second signal lines away from the substrate.

4. The display panel according to claim 2, characterized in that, The non-display area is provided with a plurality of second support pillars, which are located on the side of the plurality of second signal lines away from the gate drive circuit; The source-drain layer further includes spacer pillars disposed on the side of the plurality of second signal lines away from the gate drive circuit, and a second support pillar disposed on the side of the spacer pillar away from the substrate, wherein the orthographic projection of the second support pillar on the substrate is located within the orthographic projection of the spacer pillar on the substrate.

5. The display panel according to claim 4, characterized in that, Both the first support column and the second support column are arranged at intervals along the first direction and the second direction; In this arrangement, the first support columns in two adjacent rows are staggered, the second support columns in two adjacent rows are staggered, the first direction and the second direction intersect, and the second direction is parallel to the extension direction of the first signal line.

6. The display panel according to claim 4, characterized in that, The distribution density of the first support column is less than or equal to the distribution density of the second support column.

7. The display panel according to any one of claims 4 to 6, characterized in that, The display panel also includes a frame adhesive disposed in the non-display area, the frame adhesive covering the first support post, the second support post, and at least a portion of the gate drive circuit.

8. The display panel according to claim 7, characterized in that, The non-display area is provided with a plurality of third support columns, which are located on the side of the second support column away from the display area; The third support column and the frame adhesive are arranged without overlap.

9. The display panel according to claim 7, characterized in that, The gate driving circuit includes a signal generation section and a signal output section electrically connected, with the signal output section located on the side of the signal generation section near the display area. The boundary of the frame adhesive near the display area is spaced apart from the signal output section.

10. The display panel according to claim 9, characterized in that, The display panel further includes at least one baffle, the baffle having the same extension direction as the first signal line; The retaining wall and the signal output unit are arranged overlappingly.

11. The display panel according to claim 10, characterized in that, The non-display area is provided with a plurality of first buffer pillars, which are located on one side of the barrier wall and overlap with the wires in the source-drain layer of the signal output section.

12. The display panel according to claim 11, characterized in that, The non-display area is provided with a plurality of second buffer pillars, which are located on the side of the barrier wall closer to the display area, and the second buffer pillars are not overlapped with the signal output section; The distribution density of the second buffer column is less than that of the first buffer column.

13. The display panel according to claim 11, characterized in that, The projected area of ​​the first buffer post on the substrate is greater than the projected area of ​​the first support post on the substrate.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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