Split pillar architecture for memory devices

Abstract

The invention relates to a partition pillar architecture for a memory device. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternating layers of conductive and insulating material, which may reduce a pitch between the openings while maintaining dielectric thickness for continuous application of a voltage to the array. After etching the material, an insulating material may be deposited in the trench. Portions of the insulating material may be removed to form an opening in which the cell material is deposited. Conductive posts may extend perpendicular to the plane of the conductive material and the substrate, and are coupled to conductive contacts. The conductive pillars may be divided to form first and second pillars.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of Chinese Patent Application No. 202080047945.2, entitled "Segmentation Column Architecture for Memory Devices", filed on June 2, 2020.

[0003] Cross-reference

[0004] This patent application claims priority to PCT application No. PCT / US2020 / 035689, filed June 2, 2020, entitled “SPLIT PILLAR ARCHITECTURES FOR MEMORY DEVICES”, filed by Fantini et al., which claims priority to U.S. Patent Application No. 16 / 460,875, filed July 2, 2019, entitled “SPLIT PILLAR ARCHITECTURES FOR MEMORY DEVICES”, each of which is assigned to the assignee of this application and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field relates to partitioned column architectures for memory devices. Background Technology

[0006] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, typically represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0007] Various types of memory devices exist, including hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), and other chalcogenide-based memories, etc. Memory devices can be volatile or non-volatile.

[0008] Improving memory devices typically includes increasing memory cell density, improving read / write speeds, enhancing reliability, increasing data retention, reducing power consumption, or lowering manufacturing costs, among other metrics. Solutions using a three-dimensional vertical architecture can be expected to save space in memory arrays, increase memory cell density, or reduce the overall power consumption of the memory array. Summary of the Invention

[0009] A method is described. The method may include forming a first opening through an insulating material to expose a first dielectric layer, a conductive layer, and a second dielectric layer. The method may include forming a first chalcogenide assembly and a second chalcogenide assembly separated from the first chalcogenide assembly within the first opening, both the first chalcogenide assembly and the second chalcogenide assembly contacting the conductive layer, the first dielectric layer, and the second dielectric layer. The method may include depositing a conductive material for forming pillars in contact with the first chalcogenide assembly and the second chalcogenide assembly into the first opening. The method may include forming a second opening by etching the conductive material to divide the pillars into a first pillar contacting the first chalcogenide assembly and a second pillar contacting the second chalcogenide assembly.

[0010] Describe a device. The device may include: a word line board; a plurality of memory element pairs, each of the plurality of memory element pairs including a first memory element contacting a first wall of the word line board and a second memory element contacting a second wall of the word line board; a plurality of post pairs configured as digital lines to interact with the word line board, each of the plurality of post pairs including a first post contacting the first memory element and a second post contacting the second memory element; and a dielectric material extending between and in contact with each post of the plurality of post pairs.

[0011] Describe an apparatus. The apparatus may include: a substrate; a plurality of contacts extending through the substrate and configured to couple digital lines and circuitry; a word line board positioned above the substrate; a plurality of pairs of memory elements, each pair including a first memory element contacting a first wall of the word line board and a second memory element opposite to the first memory element contacting a second wall of the word line board; a plurality of pillar pairs coupled to the plurality of contacts and configured as digital lines, each pair including a first pillar contacting the first memory element and a first contact of the plurality of contacts and a second pillar contacting the second memory element and a second contact of the plurality of contacts; and a dielectric material contacting each pillar pair and extending between each pillar pair, the dielectric material being in contact with the substrate.

[0012] Describe an apparatus. The apparatus may include: a first substrate and a second substrate; a first plurality of contacts positioned in the first substrate and a second plurality of contacts positioned in the second substrate; a word line board positioned between the first substrate and the second substrate; a plurality of memory element pairs positioned between the first substrate and the second substrate, each of the plurality of memory element pairs including a first memory element contacting a first wall of the word line board and a second memory element contacting a second wall of the word line board; and a plurality of pillar pairs positioned between the first substrate and the second substrate and configured as digital lines, each of the plurality of pillar pairs including a first pillar contacting the first memory element and a first contact of the first plurality of contacts positioned in the first substrate, and a second pillar contacting the second memory element and a second contact of the second plurality of contacts positioned in the second substrate.

[0013] A method is described. The method may include depositing a first substrate. The method may include forming a first plurality of contacts positioned in the first substrate. The method may include forming pillars in contact with the first substrate, a first chalcogenide assembly, and a second chalcogenide assembly. The method may include dividing the pillars into a first pillar contacting the first chalcogenide assembly and a second pillar contacting the second chalcogenide assembly. The method may include depositing a second substrate over the first pillars and the second pillars. The method may include forming a second plurality of contacts positioned in the second substrate, wherein the first pillar is coupled to a first contact of the first plurality of contacts, and the second pillar is coupled to a second contact of the second plurality of contacts. Attached Figure Description

[0014] Figure 1 This document describes an example of a system that supports a partitioned column architecture for memory devices, based on the examples disclosed herein.

[0015] Figures 2A to 2F This document describes various views of instance memory arrays supporting partitioned column architectures for memory devices, based on the examples disclosed herein.

[0016] Figures 3A to 3H This document describes various views of instance memory arrays supporting partitioned column architectures for memory devices, based on the examples disclosed herein.

[0017] Figure 4A and 4B This document describes various views of instance memory arrays supporting partitioned column architectures for memory devices, based on the examples disclosed herein.

[0018] Figure 5A and 5BThis document describes various views of instance memory arrays supporting partitioned column architectures for memory devices, based on the examples disclosed herein.

[0019] Figure 6A and 6B This document describes various views of instance memory arrays supporting partitioned column architectures for memory devices, based on the examples disclosed herein.

[0020] Figure 7A and 7B This document describes various views of instance memory arrays supporting partitioned column architectures for memory devices, based on the examples disclosed herein.

[0021] Figure 8A and 8B This document describes various views of instance memory arrays supporting partitioned column architectures for memory devices, based on the examples disclosed herein.

[0022] Figures 9 to 11 The flowchart illustrates one or more methods for supporting partitioned column architectures for memory devices, based on the examples disclosed herein. Detailed Implementation

[0023] This disclosure relates to a partitioned pillar architecture for a memory device and a method for processing the same. The memory device may include an arrangement of conductive contacts and openings through alternating layers of conductive and insulating materials, which can reduce the spacing between memory cells while maintaining dielectric thickness to allow voltage to be continuously applied to the memory array of the memory device.

[0024] In some instances, the memory device may include a substrate having a set of contacts arranged in a pattern (e.g., a geometric pattern) and a first insulating material (e.g., a dielectric material) formed on the substrate. A set of planes of conductive material may be separated from each other by a second insulating material (e.g., a dielectric material) and formed on the substrate material. That is, alternating layers of the conductive material and the insulating material may be formed on the substrate. The planes of the conductive material may be examples of word lines.

[0025] During the fabrication of the memory device, one or more trenches can be formed by etching the alternating planes of the conductive and insulating materials. The trenches may extend parallel to each other and expose the substrate. In some instances, the planes of the conductive and dielectric materials may form sidewalls of the trenches. The planes of the conductive material may be etched such that the planes of the dielectric and conductive materials form a set of grooves, wherein each groove may be configured to receive memory element material (e.g., a chalcogenide material). A sacrificial layer (e.g., a conformal material) may be deposited in the trenches, and in some cases, the sacrificial layer fills the grooves. An insulating material may be deposited in the trenches on top of the sacrificial layer.

[0026] The sacrificial layer and portions of the insulating material can be removed to form a first opening. The first opening exposes portions of the substrate, at least some of the set of conductive contacts, and portions of the planes of the conductive material and the dielectric material. Storage element material (e.g., the chalcogenide material) can be deposited in the first opening. The storage element material can fill the recess formed by the planes of the dielectric material and the conductive material. The storage element material can be removed from the first opening portion, leaving the storage element material in the recess. The storage element material positioned in the recess can be a storage element assembly (e.g., a chalcogenide assembly).

[0027] Conductive pillars may be formed in the first opening of the storage component comprising the recess. The conductive pillars may be arranged to extend through the plane of the conductive material (e.g., substantially perpendicular to the plane of the conductive material) and contact the substrate. Each conductive pillar may contact two storage element assemblies, which in turn each contact the same plane of the conductive material. Each conductive pillar may further be coupled to one or two conductive contacts. In some cases, the pillars are formed of both a barrier material and a conductive material.

[0028] A portion of the conductive pillar can be removed to form a second opening. This second opening divides each pillar into a first pillar and a second pillar. The first and second pillars can be examples of digital lines. The first pillar can contact a first memory element assembly coupled to a plane of conductive material, and the second pillar can contact a second memory element assembly coupled to the plane of conductive material. In some cases, each of the first and second pillars can be coupled to different conductive contacts on the substrate. In other cases, each of the first pillars can be coupled to different conductive contacts on the substrate, and each of the second pillars can be coupled to different conductive contacts formed on a second substrate above the first substrate.

[0029] This configuration of the memory array and manufacturing method allows for increased memory cell density compared to previous solutions. Each memory cell (e.g., a memory component) can be recessed within a first or second pillar to ensure cell isolation. This configuration allows for more precise control of unit thickness and size compared to some previous solutions. Each plane of the conductive material intersecting the conductive pillar can form two memory cells addressed by a word line board (e.g., a plane corresponding to the conductive material) and a first digital line of the first memory cell (e.g., corresponding to the first pillar) and a second digital line of the second memory cell (e.g., corresponding to the second pillar). Each pillar can be decoded by a transistor located at the bottom or top of the memory array. The transistor can be an example of a digital line selector formed as a regular matrix.

[0030] Firstly, in reference Figure 1 The features of this disclosure are described in the context of the memory array described. (Referencing...) Figures 2A to 8B The features of this disclosure are described in the context of different views of the instance memory array during the described processing steps. (See reference...) Figures 9 to 11 The flowcharts described herein, relating to the partitioned column architecture for memory devices, are used to further illustrate and describe these and other features of this disclosure, and reference is made to the flowcharts.

[0031] Figure 1 This document describes an example of a memory array 100 (e.g., a three-dimensional (3D) memory array) supporting a partitioned column architecture for a memory device, based on the examples disclosed herein. The memory array 100 may include a first array or layer 105 of memory cells positioned above a substrate 104 and a second array or layer 108 of memory cells on top of the first array or layer 105.

[0032] Memory array 100 may include word lines 110 and number lines 115. Memory cells in the first level 105 and the second level 108 may each have one or more self-selectable memory cells. Although numeric indicators are used for labeling... Figure 1 Some of the elements contained herein are not labeled with other corresponding elements, but they are the same or should be understood as similar.

[0033] The memory cell stack may include a first dielectric material 120, a memory element material 125 (e.g., a chalcogenide material), a second dielectric material 130, a memory element material 135 (e.g., a chalcogenide material), and a third dielectric material 140. In some embodiments, the selectable memory cells of the first layer 105 and the second layer 108 may have a common conductor, such that the corresponding selectable memory cells of each layer 105 and 108 may share a digital line 115 or a word line 110.

[0034] In some instances, a memory cell can be programmed by providing an electrical pulse to it, the memory cell potentially containing a memory storage element. The pulse can be provided via a first access line (e.g., word line 110) or a second access line (e.g., digital line 115) or a combination thereof. In some cases, after the pulse is provided, ions can migrate within the memory storage element, depending on the polarity of the memory cell. Therefore, the ion concentration relative to a first or second side of the memory storage element can be at least partially based on the polarity of the voltage between the first and second access lines. In some cases, asymmetrically shaped memory storage elements can cause ions to accumulate more in portions of the element with a larger area. Certain portions of the memory storage element may have higher resistivity and thus cause a higher threshold voltage than other portions of the memory storage element. This ion migration description represents an example of a mechanism for implementing the results described herein in a self-selecting memory cell. This example of a mechanism should not be considered limiting. This disclosure also includes other examples of mechanisms for implementing the results described herein in a self-selecting memory cell.

[0035] In some cases, the architecture of memory array 100 may be referred to as a cross-point architecture, wherein memory cells are formed at the topological intersection between word line 110 and digital line 115. This cross-point architecture can provide relatively high-density data storage at a lower manufacturing cost than other memory architectures. For example, a cross-point architecture may contain memory cells with a smaller area and therefore a higher memory cell density than other architectures.

[0036] although Figure 1 The examples show two memory layers 105 and 108, but other configurations are possible. In some instances, a single memory layer of self-selecting memory cells can be constructed above substrate 104, which may refer to a two-dimensional memory. In some instances, three or four memory layers of memory cells can be configured in a similar manner as a three-dimensional intersection architecture.

[0037] The memory array 100 may include a substrate 104 having a set of contacts arranged in a grid or staggered pattern. In some cases, the set of contacts may extend through the substrate 104 and couple to the access lines of the memory array 100. The memory array 100 may include an additional substrate 104 (e.g., positioned above two layers 105 and 108). The additional substrate 104 may have a set of contacts (e.g., extending through the substrate 104) and couple to the access lines of the memory array 100.

[0038] The memory array 100 may include a set of planes of conductive material separated from each other by a second insulating material formed on a first insulating material on a substrate material. Each of the planes of the conductive material may include a set of grooves formed therein. A set of planes may be obtained by a replacement process by using a sacrificial layer (e.g., a conformal layer) for etching during a stacking deposition process step, removing the conformal layer after cell definition, and replacing the conformal layer with a more conductive material, such as a word line board corresponding to one or more word lines 110 on the same level (e.g., memory level 105, memory level 108).

[0039] A set of conductive pillars may be formed in the opening and extend substantially perpendicular to a set of planes of the conductive material and the substrate 104. The set of conductive pillars may be divided into a set of pillar pairs. Each pillar in a pillar pair may be coupled to a different conductive contact. In some cases, each pillar in a pillar pair may be coupled to a conductive contact on the substrate 104. Alternatively, pillars in each pillar pair may be coupled to a conductive contact on the substrate 104, and the other pillar in each pillar pair may be coupled to a conductive contact on a different substrate 104 (e.g., positioned above memory layers 105 and 108).

[0040] In some instances, memory layers 105 and 108 may include chalcogenide material configured to store logical states. For example, the memory cells of memory layers 105 and 108 may be instances of self-selecting memory cells. The chalcogenide material may be formed in a set of recesses such that the chalcogenide material in each of the recesses is at least partially in contact with a post in a set of post pairs.

[0041] Figures 2A to 2F Various views of example memory arrays 200-a, 200-b, 200-c, and 200-d are provided, illustrating a series of steps or processes that can be performed to form a stacked memory device according to the examples disclosed herein. Specifically, Figures 2A to 2F The process of forming the word line plane, depositing the sacrificial layer, and insulating material is shown in the image.

[0042] Figure 2A Illustrated side view of example memory array 200-a. Figure 2B illustrate Figure 2A The process steps described herein, during the process steps, Figure 2A A top view of an example memory array 200-b with section line A-A'. Figure 2C Explanation along Figure 2B The memory array 200-b obtained by the cross-section line B-B' (e.g.) Figure 2B The cross-sectional view shown in the figure. Figure 2D illustrate Figure 2B and 2C The process steps described herein, along with the process steps during the process steps described herein Figure 2B The cross-sectional view of memory array 200-c obtained by section line B-B'. Figure 2E illustrate Figure 2D The process steps described herein, along with the process steps during the process steps described herein Figure 2B The cross-sectional view of memory array 200-d obtained by section line B-B'. Figure 2F Explanation along Figure 2E Example memory array 200-d of cross-section line A-A' (e.g.) Figure 2D The top view shown in the image.

[0043] Figure 2A This describes a side view of an example memory array 200-a according to the embodiments disclosed herein. The memory array 200-a may include a set of conductive contacts 235 extending through a substrate 104-a or 104-b. The memory array 200-a may further include alternating layers of material 240 and insulating material 245 (e.g., an insulating layer, a dielectric layer). In some cases, material 240 may be a conductive material (e.g., used to form a conductive layer). In other cases, material 240 may be a sacrificial insulating material (e.g., different from insulating material 245).

[0044] The substrate 104 may be a dielectric material, such as a dielectric film. A single conductive contact of a set of conductive contacts 235 may be configured to couple any single vertical post (e.g., a digital line) to a transistor (e.g., a digital line selector).

[0045] In some instances, conductive contacts 235 may be formed in both substrates 104-a and 104-b. For example, conductive contact 235-a may couple a first pillar (e.g., corresponding to a digital line) of a pillar pair to a transistor. Conductive contact 235-c may couple a second pillar of a pillar pair to a transistor. Conductive contacts 235-b and 235-d may each couple a pillar of the second pillar pair to a transistor. Alternatively or additionally, each of the conductive contacts 235 may extend through substrate 104-b (e.g., conductive contacts 235-c and 235-d may be formed through substrate 104-b). For example, conductive contact 235-a may couple a first pillar of a pillar pair to a transistor, and contact 235-b may couple a second pillar of a pillar pair to a transistor.

[0046] A set of conductive contacts 235 may be arranged in a grid pattern. In some instances, a corresponding contact in a set of conductive contacts 235 may be surrounded by up to eight other conductive contacts 235. Alternatively, a set of conductive contacts 235 may be arranged in an alternating pattern or a hexagonal pattern. For example, a corresponding contact in a set of conductive contacts 235 may be surrounded by up to six other conductive contacts 235.

[0047] The memory array 200-a may also include a set of stacked planes of insulating material 245 and a set of stacked planes of material 240 (e.g., word line planes or word line boards), wherein material 240 may be a conductive material or an insulating material (e.g., in the case of a conductive material). Figure 2A (During process steps described herein, the conductive material replaces the material). The stacked planes of material 240 can be separated from each other in the z-direction (e.g., perpendicularly separated) by a set of planes of insulating material 245. For example, a first plane (e.g., bottom surface) of the second insulating material 245 can be formed (e.g., deposited) on a plane of substrate 104-b, and then a plane of material 240 can be formed on the first plane of the second insulating material 245. In some instances, a layer of the first insulating material 245 can be deposited on substrate 104-b. In some instances, material 240 can be a conductive carbon layer or other conductive layer compatible with the active material. In some instances, material 240 can contain conductive layers separated by the active material through a protective barrier. Each layer of material 240 can be configured to act as at least one word line board. In some instances, material 240 and insulating material 245 form a set of layers, such as alternating layers.

[0048] Alternatively, material 240 may be a sacrificial insulating material. Here, memory array 200-a may include a set of stacked planes of sacrificial insulating material 240 and a set of stacked planes of insulating material 245. The sacrificial insulating material 240 may be a material different from the insulating material 245 (e.g., an oxide material and a nitride material, respectively). Figure 2A During process steps following the process steps described herein, the sacrificial insulating material 240 may be removed and replaced by a conductive material (e.g., a conductive carbon layer or other conductive layer compatible with the active material).

[0049] Additional planes of the second insulating material 245 can be formed on the material 240 in an alternating manner, such as... Figure 2A As described herein, the second insulating material 245 may be a dielectric material, such as a dielectric film or layer. In some instances, the second insulating material 245 and the substrate 104-a may be the same type of insulating material. Examples of insulating materials disclosed herein include (but are not limited to) dielectric materials, such as silicon oxide.

[0050] Each corresponding plane of material 240 may be located at a different level (e.g., forming) the memory array 200-a. Individual planes of the material forming the memory cells may refer to layers of the 3D memory array 200-a. Material 240 (e.g., a conductive material) may include metallic (or semi-metallic) materials or semiconductor materials (e.g., doped polycrystalline silicon, etc.) (e.g., formed from said metallic (or semi-metallic) materials or said semiconductor materials). In some instances, material 240 may be a conductive carbon plane.

[0051] Figure 2A The diagram shows six planes of material 240 and seven planes of the second insulating material 245. The seventh plane of the second insulating material 245 can be the top layer of the memory array 200-a. The number of planes of material 240 and the second insulating material 245 is not limited to... Figure 2A The quantities described herein. Material 240 and second insulating material 245 may be arranged in more than six layers or less than six layers.

[0052] Figure 2B Explanation along Figure 2A Top view of memory array 200-b with section line A-A'. Figure 2B Alternating layers of material 240 (e.g., conductive material, insulating material) and second insulating material 245 are used to form a trench 250 through the memory array 200-b. The trench 250 exposes the substrate 104 and conductive contacts 235 (as previously shown) at its bottom. Figure 2A (As shown in the image). Trench 250 can be etched from top to bottom in a linear shape. In some cases, trench 250 can be formed by a combination of vertical and horizontal etching processes to create recesses within trench 250. Reference Figure 2C To demonstrate and describe additional details about the etching process and the trenches. The trench 250 may form a set of openings extending in substantially parallel directions on each plane of the material 240 (e.g., word line plane, conductive layer).

[0053] Figure 2C Explanation along Figure 2B The image shows a side view of memory array 200-b taken along line B-B'. Memory array 200-b illustrates a set of grooves 215 formed in a material 240 (e.g., conductive material, insulating material) in each plane of memory array 200-b. For example, a selective etching operation can be performed to form a set of grooves 215 isotropically in the sidewalls 290 and 291 of trench 250. In some instances, trench 250 includes a first sidewall 290 spaced apart from a second sidewall 291, wherein a first portion 292 of the first sidewall 290 formed of a first insulating material 245 is spaced apart from a first portion 293 of the second sidewall 291 formed of the first insulating material 245 by a first distance. A second portion 294 of the first sidewall 290 formed of the first material 240 may be spaced apart from a second portion 295 of the second sidewall 291 formed of the first material 240 by a second distance greater than the first distance. In some instances, portions of the sidewalls 290 and 291 of the trench 250 formed by the first material 240 are recessed relative to portions of the sidewalls 290 and 291 of the trench 250 formed by the first insulating material 245.

[0054] The etching operation may include one or more vertical etching processes (e.g., anisotropic etching processes or dry etching processes, or combinations thereof) or horizontal etching processes (e.g., isotropic etching processes, or combinations thereof). For example, a vertical etching process may be performed to vertically etch trench 250 to expose substrate 104-b and one or more conductive contacts 235, and a horizontal etching process may be used to form at least one groove 215 in at least one material 240. Etching parameters may be selected such that material 240 (e.g., a second insulating material 245) is etched faster.

[0055] Figure 2D Explanation along Figure 2B The image shows a side view of memory array 200-b taken along line B-B'. Memory array 200-c illustrates the formation of conformal material 220 (e.g., sacrificial material or sacrificial layer). Conformal material 220 can be deposited into trenches 250 of memory array 200-c. Conformal material 220 can be formed by conformal deposition of conformal material 220. Figure 2C In the groove 215 shown, conformal material 220 contacts the first sidewall 290, the second sidewall 291, and the bottom wall 295 of each groove 250 (e.g., contacting the substrate 104-b and the contact 235). Although Figure 2D A conformal material 220 is shown formed on the sidewall of trench 250 (e.g., on the surface of a second insulating material 245 and material 240 in different layers facing trench 250), but examples are not limited thereto. For example, in some cases, the conformal material 220 may be limited to a set of grooves 215 in the material 240 (e.g., conductive material, insulating material) in different layers. In some cases, the conformal material 220 may refer to a conformal layer or a sacrificial layer.

[0056] In some cases, an etching operation may be performed after the conformal material 220 is formed. In the etching operation, the conformal material 220 may be etched to form an opening or trench 250. The etching operation may result in the surface of the conformal material 220 (e.g., the surface facing the trench 250) being spaced apart from the surface of the second insulating material 245 (e.g., extending into the surface facing the trench 250). In some cases, the etching operation may result in the surface of the conformal material 220 (e.g., the surface facing the trench 250) being substantially coplanar with the surface of the second insulating material 245 (e.g., extending into the surface facing the trench 250), thereby forming continuous sidewalls of the trench. The etching operation may further result in the exposure of the substrate 104-b and the contact 235 (e.g., removal of the conformal material 220 from the bottom wall 295 of the trench 250). The etching operation described herein may be a vertical etching process (e.g., an anisotropic etching process or a dry etching process, or a combination thereof) or a horizontal etching process (e.g., an isotropic etching process). For example, a vertical etching process can be performed to vertically etch trench 250, and a horizontal etching process can be used to form at least one groove in the first material 240 (e.g., first conductive material 240, sacrificial insulating material 240).

[0057] Figure 2E Explanation along Figure 2B The image shows a side view of memory array 200-b taken along line B-B'. Memory array 200-d illustrates the deposition of dielectric material 218 in a trench 250 on top of conformal material 220. Dielectric material 218 may contact conformal material 220. Dielectric material 218 may further contact one or more contacts 235. Dielectric material 218 and conformal material 220 may together fill trench 250. In some cases, dielectric material 218 may be an example of an insulating material. In some instances, conformal material 220 may be selectively etched back to form a surface coplanar with dielectric material 218. The depth of the recess may be defined according to the desired thickness.

[0058] Figure 2F Explanation along Figure 2E A top view of an example memory array 200-d with section line A-A'. Figure 2F This describes a memory array 200-d after dielectric material 218 has been deposited into a set of trenches 250. Each of the trenches 250 in the memory array 200-d is lined with conformal material 220 and filled with dielectric material 218. The trenches 250 may extend through each layer of material 240 (e.g., conductive material 240, sacrificial insulating material 240), such as... Figure 2E As shown in the image.

[0059] Figures 3A to 3HVarious views of example memory arrays 200-e, 200-f, 200-g, and 200-h are provided, illustrating a series of steps or processes executable to form a stacked memory device according to the examples disclosed herein. Specifically, Figures 3A to 3H The diagram shows the formation of a memory array 200-d (e.g. Figure 2D and 2E The process of memory cells (as explained in the document).

[0060] Figure 3A illustrate Figure 2F A top view of the instance memory array 200-e during the process steps described herein. Figure 2F The cross section C-C'. Figure 3B Explanation along Figure 3A A cross-sectional view of an example memory array 200-e with section line B-B'. Figure 3C and 3D illustrate Figure 3A and 3B The instance memory array 200-f during the process steps following the process steps described herein. Figure 3C Explain the top view section CC' of the example memory array 200-f (e.g., Figure 2F (as explained in the text), and Figure 3D Explanation along Figure 3C A cross-sectional view of an instance memory array 200-f with cross-section line B-B'. Figure 3E , 3F and 3G instructions Figure 3C and 3D The instance memory array 200-g during the process steps following the process steps described herein. Figure 3E Explain the top view section CC' of the example memory array 200-g (e.g., Figure 2F (as explained in the text) (e.g., along) Figure 3D (Cross section line A-A'). Figure 3F This illustrates a top view of the example memory array 200-g, and Figure 3G Explanation along Figure 3E A cross-sectional view of an example memory array 200-g with cross-section line B-B'. Figure 3H illustrate Figure 3E , 3F And a top view of the instance memory array 200-h during the process steps following the process steps described in 3G. Figure 3F The cross section C-C'.

[0061] Figure 3A Explaining the top view of instance memory array 200-e Figure 2F The cross section C-C'. Example memory array 200-e can be shown. Figure 2Eand 2F During the process steps described herein, the process steps after the process steps are described herein. Figure 2F The example memory array 200-d shown in the figure has a cross-section C-C'. An opening 360 can be formed in the trench 250 by etching away portions of the dielectric material 218 and / or conformal material 220. The opening 360 can be positioned on one or more of the contacts 235 such that forming the opening 360 exposes at least a portion of one of the contacts 235. Reference Figure 3B To illustrate and describe additional details regarding the relationship between the opening 360 and the contact 235. In some cases, the instance memory array 200-e may include a set of openings 360. For example, a set of openings may be formed at intervals along each of the trenches 250. Each of the openings 360 within the trench 250 may be separated from the other openings in the trench 250 by a dielectric material 218. The etching process used to form the openings 360 may be a vertical etching process. In some instances, the etching operation may not remove all portions of the conformal material 220, for example, at locations where the openings 360 are not formed.

[0062] Figure 3B Explanation along Figure 3A The side view of memory array 200-e obtained by line B-B'. Figure 3B As shown, a set of grooves 215 can be formed in the material 240 in each plane. An opening 360 can be formed (e.g., see reference). Figure 3A During the process (discussed), a set of grooves 215 are formed. For example, a selective etching operation can be performed to form a set of grooves 215 in a fully or partially isotropic manner. The etching chemicals can be selectively applied to the material 240. The contacts 235 can be exposed by forming openings 360 in the trenches 250.

[0063] Figure 3C This describes the instance memory array 200-f based on the examples disclosed herein. Figure 2F The top view of section C-C' as described in the diagram. The top view can be along... Figure 3B The view obtained by section line A-A'. (It can be viewed from...) Figure 3A and 3B Following the processing steps described herein, instance memory array 200-f is formed from instance memory array 200-e. For example... Figure 3C As shown, a storage element material 365 can be formed in the opening 360. In some cases, the storage element material 365 may extend to contact each sidewall of the material 240. The storage element material 365 may further contact the conformal material 220 and the dielectric material 218. Forming the storage element material 365 in the opening 360 (e.g., by depositing the storage element material 365 in the opening 360) can reduce the size of the opening 360.

[0064] The storage element material 365 may be an example of a chalcogenide material (e.g., a chalcogenide alloy and / or glass) that can serve as a self-selecting storage element material (e.g., a material that can serve as both a selection device and a storage element). For example, the storage element material 365 may respond to an applied voltage, such as a programming pulse. For applied voltages less than a threshold voltage, the storage element material 365 may remain in a non-conductive state (e.g., an "off" state). Alternatively, in response to an applied voltage greater than the threshold voltage, the storage element material 365 may enter a conductive state (e.g., an "on" state).

[0065] Figure 3D Explanation along Figure 3C The image shows a side view of the memory array 200-f obtained by line B-B'. The memory element material 365 is formed in a set of trenches 215 by conformally depositing memory element material 365 into trenches 250. The memory element material 365 may be deposited to contact the sidewalls 290 and 291 and the bottom wall 295 of the trenches 250 exposed by etching conformal material 220. When the memory element material 365 contacts the bottom wall 295 of the trenches 250, the memory element material 365 covers the exposed contacts 235. The memory element material 365 may include a top layer 366.

[0066] Figure 3E Explain the top view section CC' of the example memory array 200-g (e.g., Figure 2F (As illustrated in the text) (e.g., along section line A-A'). This can be done for... Figure 3C and 3D The example memory array 200-f described herein undergoes an etching operation to produce example memory array 200-g. The etching operation removes portions of memory element material 365 to produce memory element assemblies (e.g., containing memory element material 365). Each of the memory element assemblies of memory element material 365 may contact a layer of material 240 (e.g., conductive material 240). In some embodiments, portions of conformal material 220 may be positioned on either side of the memory element assembly of memory element material 365. Etching memory element material 365 allows the memory element assembly of memory element material 365 to be separated from the opening 360. The memory element assembly enables memory array 200-g (and memory array 200 formed by subsequent processing steps of memory array 200-g) to store data. That is, the memory element assembly may contain memory element material 365 and may be configured to store logical states (e.g., logical value "0" or logical value "1").

[0067] A memory element assembly can be programmed to a target state by applying a pulse that meets a programming threshold (e.g., a programming pulse). The amplitude, shape, or other characteristics of the programming pulse can be configured to cause the memory element material 365 to exhibit the target state. For example, after applying a programming pulse, ions in the memory element assembly can redistribute throughout the memory element to change the resistance of the memory cell detected when a read pulse is applied. In some cases, the threshold voltage of the memory element assembly can be varied based on the applied programming pulse.

[0068] A state stored by a storage element assembly can be sensed, detected, or read by applying a read pulse to the storage element assembly. The amplitude, shape, or other characteristics of the read pulse can be configured to allow the sensing component to determine what state is stored on the storage element assembly. For example, in some cases, the amplitude of the read pulse is configured to be at a level that would cause the storage element assembly to be in an "on" state for a first state (e.g., current conduction through the material) but in an "off" state for a second state (e.g., almost no current conduction through the material).

[0069] In some cases, the polarity of the pulses applied to a memory element (whether for programming or reading) can affect the outcome of the operation. For example, if the memory element stores a first state, a read pulse of the first polarity may cause the memory element to exhibit an "on" state, while a read pulse of the second polarity may cause the memory element to exhibit an "off" state. This can be due to the asymmetric distribution of ions or other materials within the memory element when it stores a state. Similar principles apply to programming pulses and other pulses or voltages.

[0070] Examples of chalcogenide materials that can serve as components for memory elements include indium (In)-antimony (Sb)-tellurium (Te) (IST) materials (e.g., In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc.) and germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) materials (e.g., Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, etc.) and other chalcogenide materials (including, for example, alloys that do not undergo phase transformation during operation (e.g., selenium-based chalcogenide alloys)). Furthermore, chalcogenide materials may contain low concentrations of other dopant materials. Other examples of chalcogenide materials may include tellurium-arsenic (As)-germanium (OTS) materials, Ge, Sb, Te, silicon (Si), nickel (Ni), gallium (Ga), As, silver (Ag), tin (Sn), gold (Au), lead (Pb), bismuth (Bi), indium (In), selenium (Se), oxygen (O), sulfur (S), nitrogen (N), carbon (C), yttrium (Y), and scandium (Sc) materials, and combinations thereof. The hyphenated chemical composition symbols used herein indicate elements contained in a particular mixture or compound and are intended to represent all stoichiometry involving the indicated element. In some instances, chalcogenide materials may be chalcogenide glasses or amorphous chalcogenide materials. In some instances, chalcogenide materials primarily containing selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. In some instances, SAG alloys may contain silicon (Si), and this chalcogenide material may be referred to as SiSAG alloys. In some instances, chalcogenide glasses may contain additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F). In some instances, conductivity can be controlled by doping with various chemical species. For example, doping may involve incorporating group 3 elements (e.g., boron (B), gallium (Ga), indium (In), aluminum (Al), etc.) or group 4 elements (e.g., tin (Sn), carbon (C), silicon (Si), etc.) into the composition.

[0071] Figure 3F Explanation along Figure 3D A top view of an example memory array 200-g with cross-section line A-A'. Figure 3F Include Figure 3E The cross section C-C' is illustrated in the diagram. Example memory array 200-g shows a set of trenches 250. Each trench 250 contains a set of memory element assemblies of memory element material 365. A set of memory element assemblies is separable from other memory element assemblies by openings 360 and dielectric material 218. The memory element assemblies are in contact with conformal material 220.

[0072] Figure 3G Explanation along Figure 3FA side view of the memory array 200-g obtained by line B-B'. The memory element material 365 (e.g., reference) can be used. Figure 3C and 3D Following the process discussed, an etching operation is performed such that the surface of the memory element material 365 (e.g., the surface extending into the trench 250) is substantially coplanar with the surface of the insulating material 245 layer (e.g., the surface extending into the trench 250). Etching the memory element material 365 can form continuous sidewalls and remove... Figure 3D The top layer 366 of the memory element material 365 shown in the figure. Etching the memory element material 365 also exposes the contacts 235 in the substrate 104-b.

[0073] A portion of the storage element material 365 positioned in a recess may correspond to a storage element assembly. In each recess, each storage element assembly of the storage element material 365 may contact a single conductive material 240 (e.g., a single conductive material 240 positioned adjacent to a cell of the storage element material 365) and at least two dielectric layers (e.g., a top insulating material 245 positioned on the top of the storage element assembly of the storage element material 365 and a bottom insulating material 245 positioned on the bottom of the storage element assembly of the storage element material 365). In some cases, each storage element assembly of the storage element material 365 may contact a single material 240. Here, the material 240 may subsequently (e.g., in…) Figure 3G During the process steps described herein, the material is removed and replaced with conductive material. Etching the memory element material 365 removes the memory element assembly of the memory element material 365. Etching the memory element material 365 also exposes the contacts 235 in the substrate 104-b.

[0074] Figure 3H illustrate Figure 3E , 3F and the top view section CC' of the instance memory array 200-h during the process steps following the process steps described in 3G (as shown in the diagram). Figure 3F (As explained in the text). Figure 3H As shown, conductive material 370 is deposited into opening 360. Conductive material 370 can be formed from a first substrate (e.g., reference slab). Figure 2C The illustrated substrate 104-a) extends to the conductive pillars of the second substrate (e.g., substrate 104-b). In some embodiments, the conductive material 370 contacts at least a portion of the layers of the insulating material 245 and the storage element material 365, such as... Figure 3G As shown in the illustration. In some instances, the conductive material 370 is compatible with the active material. The conductive material 370 may be a uniformly conductive material (e.g., a conformal conductive material) or a barrier layer having an internal material (e.g., where the barrier layer surrounds the conductive material).

[0075] In cases where the conductive material 370 includes a barrier layer and an internal material, the barrier material can be deposited into the opening 360. In some embodiments, the barrier material may contact at least a portion of the insulating material 245 and the storage element material 365, such as Figure 3G As shown in the illustration. In some instances, the barrier material may be compatible with the active material. The barrier material may be a conductive material (e.g., a conformal conductive material) or a barrier layer having a conductive material. For example, the barrier material may include alumina. An internal material may be deposited in the opening 360 (e.g., for contacting the barrier material) to form a conductive pillar. The internal material may be a metallic (or semi-metallic) material or a semiconductor material, such as doped polycrystalline silicon, etc. However, other metallic, semi-metallic, or semiconductor materials (metallic or dielectric materials) may be used.

[0076] The conductive material 370 is accessible to the first and second storage element assemblies formed of the storage element material 365. A post (e.g., a post of the conductive material 370) formed in each of the set of openings 360 may be arranged to extend substantially orthogonally to the alternating planes of the material 240 and the insulating material 245. The storage element material 365 and the conductive post formed in each of the set of openings 360 may be formed in a substantially square shape. Examples of this disclosure are not limited to an exact or precise square shape. For example, the storage element material 365 and the conductive post may be formed in any shape including circular or elliptical shapes.

[0077] Figure 4A and 4B This describes instance memory arrays 200-i and 200-j during a series of steps or processes that can be executed to form a stacked memory device according to the examples disclosed herein. Specifically, Figure 4A and 4B Explanation of the method for dividing conductive pillars to form Figure 3H The process of the digital lines in the memory array 200-h is described in the document.

[0078] Figure 4A This describes a top view of the instance memory array 200-i according to the examples disclosed herein. The second opening 405 in the trench 250 can be formed by etching away portions of the conductive material 370. The etching process may further include etching away portions of other materials. For example, the etching process may etch some (or all) of the dielectric material 218. The etching process may include a vertical etching process occurring substantially orthogonal to the alternating planes of the material 240 and the insulating material 245. For example, the etching process may include a single-gate vertical channel 3D non-AND (SGVC) technique for creating the oval second opening of the instance memory array 200-i. The second opening 405 may extend to the bottom substrate (e.g., 104-b) to expose one or more contacts 235.

[0079] The second opening 405 divides the pillar into a pair of pillars, including the first pillar and the second pillar. Each pillar in the pillar pair may correspond to a digital line. In some cases, the trench 250 may extend and include a set of second openings (e.g., separated by dielectric material 218), each opening dividing the pillar into a pillar pair. The size (e.g., cross-sectional area) of each pillar in the pillar pair does not affect the operation of the memory array 200-i. That is, the height of each pillar in the pillar pair (e.g., extending from the first substrate (e.g., substrate 104-a) to the second substrate (e.g., substrate 104-b)) may be relatively low (e.g., less than 2 micrometers).

[0080] Figure 4B This illustration shows a top view of the example memory array 200-j, based on the examples disclosed herein. Insulating material 410 can be deposited onto the reference... Figure 4A The memory array 200-j is subsequently formed through the opening 405 shown in the described memory array 200-i. The insulating material 410 may be a dielectric material. In some cases, the insulating material 410 may be a material identical to the dielectric material 218. The insulating material 410 may contact the pillars formed of the conductive material 370. The insulating material 410 may be from the top substrate (e.g., Figure 2A The substrate 104-a shown in the figure extends to the bottom substrate (e.g., Figure 2A The substrate 104-b shown in the diagram isolates each pillar in a pillar pair. The insulating material 410 may further extend to contact the insulating material 218. Here, the insulating material (e.g., a combination of insulating material 410 and insulating material 218) may extend the length of the trench 250.

[0081] The insulating material 410 isolates the pillars of a pair from each other. This reduces the impact of accessing the first storage element assembly on the second storage element assembly when the first and second storage element assemblies are positioned in the same recess. The insulating material 410 separates the storage element materials 365 on both sides of the trench 250. That is, the insulating material 410 isolates (e.g., electrically isolates) the memory cells (e.g., formed of storage element materials 365) on the first sidewall of the contact trench 250 from the memory cells on the second sidewall of the contact trench 250.

[0082] Figure 5A and 5B This describes the instance memory arrays 200-k and 200-l during a series of steps or processes that can be executed to form a stacked memory device according to the examples disclosed herein. Specifically, Figure 5A and 5B Explanation of the method for dividing conductive pillars to form Figure 3H Other processes of the digital lines in the memory array 200-h as described herein.

[0083] Figure 5A This describes a top view of the instance memory array 200-k based on the examples disclosed herein. Figure 5A This can explain the difference from Figure 4A The embodiments described herein are examples of embodiments. In some other cases, the embodiments may be used. Figure 4A and Figure 5A The combination of these processes. The second opening 505 in the trench 250 can be formed by etching away portions of the conductive material 370. The etching process may further include etching away portions of other materials. For example, the etching process may etch some (or all) of the dielectric material 218. The etching process may include a vertical etching process occurring substantially orthogonal to the alternating planes of the material 240 and the insulating material 245. The etching process can produce a dog-bone shaped second opening 505. In some cases, the etching process used to produce the second opening 505 may differ from that used to produce different types of openings (e.g., see reference). Figure 4A The etching process of the opening 405 discussed.

[0084] The second opening 505 can divide the pillar into a pair of pillars, including the first pillar and the second pillar. Each pillar in the pillar pair may correspond to a digital line. In some cases, the trench 250 may extend and include a set of second openings (e.g., separated by dielectric material 218), where each opening divides the pillar into a pillar pair. The size (e.g., cross-sectional area) of each pillar in the pillar pair does not affect the operation of the memory array 200-k. That is, the height of each pillar in the pillar pair (e.g., extending from the first substrate (e.g., substrate 104-a) to the second substrate (e.g., substrate 104-b)) may be relatively low (e.g., less than 2 micrometers).

[0085] Figure 5B This illustration shows a top view of an example memory array 200-l based on the examples disclosed herein. Insulating material 510 can be deposited onto a reference... Figure 5A The memory array 200-1 is subsequently formed through the opening 505 shown in the described memory array 200-k. The insulating material 510 may be a dielectric material. In some cases, the insulating material 510 may be a material identical to the dielectric material 218. The insulating material 510 may contact pillars formed of conductive material 370. The insulating material 510 may be from a top substrate (e.g., Figure 2A The substrate 104-a shown in the figure extends to the bottom substrate (e.g., Figure 2A The substrate 104-b shown in the figure isolates each pillar in a pillar pair. The insulating material 510 may extend further to contact the insulating material 218. Here, the insulating material (e.g., a combination of insulating material 510 and insulating material 218) may extend the length of the trench 250.

[0086] The insulating material 510 isolates the pillars of a pair from each other. This reduces the impact of accessing the first storage element assembly on the second storage element assembly when the first and second storage element assemblies are positioned in the same recess. The insulating material 510 separates the storage element materials 365 on both sides of the trench 250. That is, the insulating material 510 isolates (e.g., electrically isolates) the memory cells (e.g., formed of storage element materials 365) on the first sidewall of the contact trench 250 from the memory cells on the second sidewall of the contact trench 250.

[0087] Figure 6A and 6B This describes the instance memory arrays 200-m and 200-n during a series of steps or processes that can be executed to form a stacked memory device according to the examples disclosed herein. Specifically, Figure 6A and 6B Explanation of the method for dividing conductive pillars to form Figure 3H Other processes of the digital lines in the memory array 200-h as described herein.

[0088] Figure 6A This describes a top view of an instance memory array 200-m based on the examples disclosed herein. Figure 6A This can explain the difference from Figures 4A to 5B The embodiments described herein are examples of embodiments. In some other cases, the embodiments may be used. Figures 4A to 5B The combination of conductive material 370 and dielectric material 218. A second opening 605 in the trench 250 can be formed by etching away portions of the conductive material 370 and dielectric material 218. The etching process may include a vertical etching process occurring substantially orthogonal to alternating planes of material 240 and insulating material 245. The etching process can produce a second opening 605 that extends the length of the trench 250. For example, the trench 250 may include a set of conductive materials 370 separated by dielectric material 218. The second opening can be formed by etching a continuous opening through the set of conductive materials 370 and dielectric material 218. The second opening 605 may extend to the bottom substrate (e.g., Figure 2A The substrate 104-b shown is used to expose one or more contacts 235. In some cases, the etching process used to create the second opening 605 may differ from that used to create different types of openings (e.g., see reference 104-b). Figure 4A The opening discussed is 405, see reference. Figure 5A The etching process of the opening 505 discussed.

[0089] The second opening 605 divides the pillar into a pair of pillars, including the first pillar and the second pillar. Each pillar in the pillar pair may correspond to a digital line. In some cases, the trench 250 may extend and include a set of second openings (e.g., separated by dielectric material 218), each opening dividing the pillar into a pillar pair. The size (e.g., cross-sectional area) of each pillar in the pillar pair does not affect the operation of the memory array 200-m. That is, the height of each pillar in the pillar pair (e.g., extending from the first substrate (e.g., substrate 104-a) to the second substrate (e.g., substrate 104-b)) may be relatively low (e.g., less than 2 micrometers).

[0090] Figure 6B This illustration shows a top view of an example memory array 200-n based on the examples disclosed herein. Insulating material 610 can be deposited onto a reference... Figure 6A The memory array 200-n is subsequently formed through the opening 605 shown in the described memory array 200-m. The insulating material 610 may be a dielectric material. In some cases, the insulating material 610 may be a material identical to the dielectric material 218. The insulating material 610 may contact pillars formed of conductive material 370. The insulating material 610 may be from a top substrate (e.g., Figure 2A The substrate 104-a shown in the figure extends to the bottom substrate (e.g., Figure 2A The substrate 104-b shown in the diagram isolates each pillar in a pillar pair. The insulating material 610 may further extend to contact the insulating material 218. Here, the insulating material (e.g., a combination of insulating material 610 and insulating material 218) may extend the length of the trench 250.

[0091] The insulating material 610 isolates the pillars of a pair from each other. This reduces the impact of accessing the first storage element assembly on the second storage element assembly when the first and second storage element assemblies are positioned in the same recess. The insulating material 610 separates the storage element materials 365 on both sides of the trench 250. That is, the insulating material 610 isolates (e.g., electrically isolates) the memory cells (e.g., formed of storage element materials 365) on the first sidewall of the contact trench 250 from the memory cells on the second sidewall of the contact trench 250.

[0092] Figure 7A and 7B This describes the instance memory arrays 200-o and 200-p during a series of steps or processes that can be executed to form a stacked memory device according to the examples disclosed herein. Specifically, Figure 7A and 7B Explanation of the method for dividing conductive pillars to form Figure 3E , 3F And other processes of the digital lines in the memory array 200-g as described in 3G.

[0093] Figure 7A This describes a top view of the instance memory array 200-o, based on the examples disclosed herein. Figure 7A This can explain the difference from Figures 3H to 5B The embodiments described herein are examples. Alternatively or alternatively, the embodiments described herein may be used. Figures 3H to 5B The combination of memory array 200 described herein. Figure 7A It can be explained that it is possible to... Figure 3G The instance memory array 200-o during the subsequent series of steps or processes.

[0094] Conductive material 370 may be deposited into opening 360 to form a conductive pillar. In some cases, the pillar may be partially filled with conductive material 370 and subsequently filled with dielectric material 705. In some cases, dielectric material 705 may be the same as dielectric material 218. The pillar may extend from a first substrate (e.g., substrate 104-a) to a second substrate (e.g., substrate 104-b).

[0095] The conductive material 370 can contact the first and second storage element assemblies formed of the storage element material 365. The pillars (e.g., pillars of the conductive material 370 and the dielectric material 705) formed in each of the set of openings 360 can be arranged to extend substantially orthogonally to the alternating planes of the material 240 and the insulating material 245.

[0096] Figure 7B This illustration shows a top view of an example memory array 200-p according to the embodiments disclosed herein. The memory array 200-p may be formed after a second opening is formed and subsequently filled with insulating material 710. In some cases, dielectric material 705 and insulating material 710 are examples of the same material. (See reference...) Figure 4A , 5A The second opening may be formed using the methods discussed in 6A. The second opening may divide the pillar (e.g., comprising conductive material 370 and dielectric material 705) into a pair of pillars comprising the first pillar and the second pillar. Each pillar in the pillar pair may correspond to a digital line. The size (e.g., cross-sectional area) of each pillar in the pillar pair does not affect the operation of the memory array 200-p. That is, the height of each pillar in the pillar pair (e.g., extending from the first substrate (e.g., substrate 104-a) to the second substrate (e.g., substrate 104-b)) may be relatively low (e.g., less than 2 micrometers).

[0097] In some cases, trench 250 may extend and include a set of second openings (e.g., separated by dielectric material 218), wherein each opening divides the pillars into pillar pairs. Insulating material 710 may be a dielectric material. In some cases, insulating material 710 may be a material identical to dielectric material 218. Insulating material 710 may contact the pillars formed of conductive material 370. Insulating material 710 may be separated from a top substrate (e.g., Figure 2A The substrate 104-a shown in the figure extends to the bottom substrate (e.g., Figure 2A The substrate 104-b shown in the diagram isolates each of the pair of pillars. The insulating material 710 may further extend to contact the insulating material 218. Here, the insulating material (e.g., a combination of insulating material 710 and insulating material 218) may extend the length of the trench 250.

[0098] The insulating material 710 isolates the pillars of a pair from each other. This reduces the impact of accessing the first storage element assembly on the second storage element assembly when the first and second storage element assemblies are positioned in the same recess. The insulating material 710 separates the storage element materials 365 on both sides of the trench 250. That is, the insulating material 710 isolates (e.g., electrically isolates) the memory cells (e.g., formed of storage element materials 365) on the first sidewall of the contact trench 250 from the memory cells on the second sidewall of the contact trench 250.

[0099] Figure 8A and 8B This document describes example memory arrays 200-q and 200-r that support partitioned column architectures for memory devices, based on the examples disclosed herein. Specifically, Figure 8A and 8B This describes the various configurations used to couple digital lines to a digital line selector.

[0100] Figure 8A This illustrates a cross-sectional view of the memory array 200-q. The cross-sectional view can be viewed along... Figure 4B , 5B The section line B-B' shown in any of 6B and 7B. Figure 8A The configuration of the memory device is illustrated, wherein each pillar (e.g., each of a pair of pillars) in the conductive material 370 contacts a contact 235 on the same substrate 104. Substrate 104-b is shown positioned below the pillars of the conductive material 370, but in some other cases, the contact 235 may be formed through substrate 104-a positioned above the pillars of the conductive material 370.

[0101] The memory array 200-q may include a first pillar formed of conductive material 370-a in contact with contacts 235-a of substrate 104-b. Contacts 235-a may couple the pillar formed of conductive material 370-a to other circuitry, such as sensing components, decoders, or other circuitry. For example, contacts 235-a may couple a pillar (e.g., a digital line) to transistor 805-a. Transistor 805-a may be an example of a digital line selector formed as a regular matrix. Transistor 805-a may be positioned to selectively couple or isolate pillars (e.g., digital lines) at various times during access operations (e.g., read operations, write operations, refresh operations). Activating transistor 805-a may trigger an access operation on one of the memory element assemblies formed of memory element material 365. For example, activating transistor 805-a and applying a voltage to material 240-a or 240-b (e.g., by a word line driver applying voltage to a conductive material) may access the memory element assembly formed of memory element material 365-a or 365-b. Material 240-a may be an example of conductive material 240. In some cases, material 240-a may have been deposited as a conductive material onto the stack (e.g., in...). Figure 2A (During the process steps described above). In some other cases, material 240-a may have been deposited onto the stack as a sacrificial insulating material. During subsequent process steps, material 240-a may have been removed and replaced by conductive material 240-a.

[0102] The memory array 200-q may further include a second pillar formed of conductive material 370-b in contact with contacts 235-b of substrate 104-b. The pillar formed of conductive material 370-a and the pillar formed of conductive material 370-b may be a pair of pillars. That is, the pillar formed of conductive material 370-a and the pillar formed of conductive material 370-b may be formed during the etching process that divides the conductive pillars. Contact 235-b may couple the second pillar formed of conductive material 370-b to transistor 805-b, which may be an example of a digital line selector formed as a regular matrix. In some cases, transistor 805-b may be at the same level as transistor 805-a (e.g., a portion of the same matrix). In other cases, transistor 805-b may be offset from transistor 805-a. For example, transistor 805-b may be positioned below transistor 805-a.

[0103] Figure 8B This illustrates a cross-sectional view of the memory array 200-r. The cross-sectional view can be viewed along... Figure 4B , 5B The section line B-B' shown in any of 6B and 7B. Figure 8BThe configuration of the memory device is illustrated, wherein a first pillar (e.g., the first pillar of a pair of pillars) of conductive material 370 contacts a contact 235 on a first substrate 104, and a second pillar (e.g., the second pillar of a pair of pillars) of conductive material 370 contacts a contact 235 on a second substrate 104 different from the first substrate 104. Substrate 104-b is shown positioned below the pillars of conductive material 370, but in some other cases, the contact 235 may be formed through substrate 104-a positioned above the pillars of conductive material 370.

[0104] The memory array 200-r may include a first pillar formed of a conductive material 370-a in contact with contacts 235-c of a substrate 104-b. Contacts 235-c may couple the pillar formed of the conductive material 370-a to other circuitry, such as sensing components, decoders, or other circuitry. For example, contacts 235-c may couple a pillar (e.g., a digital line) to a transistor 805-c. Transistor 805-c may be an example of a digital line selector formed as a regular matrix. Transistor 805-c may be positioned to selectively couple or isolate pillars (e.g., digital lines) at various times during access operations (e.g., read operations, write operations, refresh operations). Activating transistor 805-c may trigger an access operation on one of the memory element assemblies formed of memory element material 365. For example, activating transistor 805-c and applying a voltage to material 240-a or 240-b (e.g., by a word line driver applying voltage to a conductive material) may access the memory element assembly formed of memory element material 365-a or 365-b. Material 240-a may be an example of conductive material 240-a. In some cases, material 240-a may have been deposited as a conductive material on the stack (e.g., in...). Figure 2A (During the process steps described above). In some other cases, material 240-a may have been deposited onto the stack as a sacrificial insulating material. During subsequent process steps, material 240-a may have been removed and replaced by conductive material 240-a.

[0105] The memory array 200-r may further include a second pillar formed of conductive material 370-b in contact with contacts 235-d of the substrate 104-a. The pillar formed of conductive material 370-a and the pillar formed of conductive material 370-b may be a pair of pillars. That is, the pillars formed of conductive material 370-a and conductive material 370-b may be formed during the etching process that divides the conductive pillars. Contact 235-d may couple the second pillar formed of conductive material 370-b to transistor 805-d, which may be an example of a digital line selector formed as a regular matrix.

[0106] Figure 9The flowchart illustrates one or more methods 900 supporting a partitioned column architecture for a memory device, based on examples disclosed herein. Operation of method 900 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Alternatively, one or more controllers may use dedicated hardware to perform portions of the described functions.

[0107] In method 905, method 900 may include forming a first opening through the insulating material to expose a first dielectric layer, a conductive layer, and a second dielectric layer. Operation 905 may be performed according to the method described herein.

[0108] In 910, method 900 may include forming a first chalcogenide component and a second chalcogenide component separate from the first chalcogenide component in a first opening, both the first chalcogenide component and the second chalcogenide component contacting a conductive layer, a first dielectric layer and a second dielectric layer. Operation 910 may be performed according to the method described herein.

[0109] In 915, method 900 may include depositing conductive material for forming pillars in contact with the first chalcogenide assembly and the second chalcogenide assembly into the first opening. Operation 915 may be performed according to the method described herein.

[0110] In 920, method 900 may include forming a second opening by etching a conductive material to divide the pillar into a first pillar contacting a first chalcogenide assembly and a second pillar contacting a second chalcogenide assembly. Operation 920 may be performed according to the method described herein.

[0111] In some instances, the device described herein may perform one or more methods, such as method 900. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: forming a first opening through an insulating material to expose a first dielectric layer, a conductive layer, and a second dielectric layer; and forming a first chalcogenide assembly and a second chalcogenide assembly separate from the first chalcogenide assembly in the first opening, both the first chalcogenide assembly and the second chalcogenide assembly contacting the conductive layer, the first dielectric layer, and the second dielectric layer. The device may further include components, features, or instructions for: depositing conductive material for forming pillars in contact with the first chalcogenide assembly and the second chalcogenide assembly into the first opening; and forming a second opening by etching the conductive material to divide the pillars into a first pillar contacting the first chalcogenide assembly and a second pillar contacting the second chalcogenide assembly.

[0112] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for depositing a second insulating material contacting the insulating material, the first post, and the second post into a second opening. In some cases of the method 900 and apparatus described herein, forming the first chalcogenide assembly and the second chalcogenide assembly may include operations, features, components, or instructions for depositing chalcogenide material into the first opening, the chalcogenide material contacting the insulating material; and etching the chalcogenide material to form the first chalcogenide assembly and the second chalcogenide assembly.

[0113] Examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for forming a set of contacts extending through a substrate in contact with a conductive layer, the set of contacts being associated with a set of digital lines, wherein a first opening through an insulating material exposes a first contact in the set of contacts. In some instances of the method 900 and apparatus described herein, a first post may be formed on one of the contacts in the set, and a second post may be formed on a second contact in the set of contacts.

[0114] In some instances of the method 900 and apparatus described herein, the operation, feature, component, or instruction may further include: depositing a second substrate on a second dielectric layer, the second substrate contacting the first pillar and the second pillar. The second substrate may include a second contact extending through the second substrate and contacting the second pillar, and the first pillar may contact a first contact of a set of contacts on the substrate. In some examples of the method 900 and apparatus described herein, depositing conductive material to form the pillar may further include: filling a first opening with the conductive material.

[0115] In some instances of the method 900 and apparatus described herein, depositing conductive material to form a pillar may further include operations, features, components, or instructions for partially filling a first opening using a conformal layer of conductive material. In some cases of the method 900 and apparatus described herein, may further include operations, features, components, or instructions for forming trenches through a first dielectric layer, a conductive layer, and a second dielectric layer; and depositing conformal layers to contact the first and second sidewalls of the trench. Both the first chalcogenide assembly and the second chalcogenide assembly may contact the conformal layers.

[0116] Examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for depositing insulating material in contact with the conformal layer, the first dielectric layer, and the second dielectric layer into a trench. Forming a first opening through the insulating material may be based on depositing the insulating material. In some instances of the method 900 and apparatus described herein, forming a trench through the first dielectric layer, the conductive layer, and the second dielectric layer may include operations, features, components, or instructions for performing a vertical etching process to vertically etch the trench; and performing a horizontal etching process after the vertical etching process to form at least one groove in the conductive layer.

[0117] Some embodiments of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: allowing a portion of the sidewall of a trench formed by the conductive layer to be recessed relative to a portion of the sidewall of a trench formed by the first dielectric layer. Examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: forming a set of contacts extending through a substrate, the set of contacts being associated with a set of digital lines; forming a first dielectric layer on the substrate; forming a conductive layer on the first dielectric layer, the conductive layer being configured as a word line board; and forming a second dielectric layer on the conductive layer. Forming a first opening may be based on forming a second dielectric layer.

[0118] In some instances of the method 900 and apparatus described herein, a first chalcogenide assembly includes a first storage element for a self-selecting memory cell, and a second chalcogenide assembly includes a second storage element for a self-selecting memory cell. Some instances of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: forming a second conductive layer on a second dielectric layer, the second conductive layer being configured as a word line board; and forming a third conductive layer on the second conductive layer, wherein forming the first opening may be based on forming the third conductive layer. In some instances of the method 900 and apparatus described herein, the memory cell array associated with the conductive layer and the second conductive layer comprises a three-dimensional memory cell array.

[0119] Figure 10 The flowchart illustrates one or more methods 1000 supporting a partitioned column architecture for a memory device, based on the examples disclosed herein. Operation of method 1000 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Alternatively, one or more controllers may use dedicated hardware to perform portions of the described functions.

[0120] In 1005, method 1000 may include forming a first opening through the insulating material to expose a first dielectric layer, a conductive layer, and a second dielectric layer. Operation 1005 may be performed according to the method described herein.

[0121] In 1010, method 1000 may include forming a first chalcogenide component and a second chalcogenide component separate from the first chalcogenide component in a first opening, both the first chalcogenide component and the second chalcogenide component contacting a conductive layer, a first dielectric layer and a second dielectric layer. Operation 1010 may be performed according to the method described herein.

[0122] In step 1015, method 1000 may include depositing conductive material for forming pillars in contact with the first chalcogenide assembly and the second chalcogenide assembly into the first opening. Step 1015 may be performed according to the methods described herein.

[0123] In 1020, method 1000 may include forming a second opening by etching a conductive material to divide the pillar into a first pillar contacting a first chalcogenide assembly and a second pillar contacting a second chalcogenide assembly. Operation 1020 may be performed according to the method described herein.

[0124] In step 1025, method 1000 may include depositing a second insulating material, contact insulating material, a first post, and a second post, into the second opening. Step 1025 may be performed according to the method described herein.

[0125] Figure 11 The flowchart illustrates one or more methods 1100 supporting a partitioned column architecture for a memory device, based on the examples disclosed herein. Operation of method 1100 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Alternatively, one or more controllers may use dedicated hardware to perform portions of the described functions.

[0126] In 1105, method 1100 may include depositing a first substrate. Operation 1105 may be performed according to the methods described herein.

[0127] In 1110, method 1100 may include forming a first set of contacts positioned in a first substrate. Operation 1110 may be performed according to the methods described herein.

[0128] In 1115, method 1100 may include forming pillars in contact with the first substrate, the first chalcogenide assembly, and the second chalcogenide assembly. Operation 1115 may be performed according to the methods described herein.

[0129] In 1120, method 1100 may include dividing the column into a first column contacting a first chalcogenide assembly and a second column contacting a second chalcogenide assembly. Operation 1120 may be performed according to the methods described herein.

[0130] In 1125, method 1100 may include depositing a second substrate over the first pillar and the second pillar. Operation 1125 may be performed according to the methods described herein.

[0131] In 1130, method 1100 may include forming a second set of contacts positioned in a second substrate, wherein a first post is coupled to a first contact in the first set of contacts and a second post is coupled to a second contact in the second set of contacts. Operation 1130 may be performed according to the method described herein.

[0132] In some instances, the device described herein may perform one or more methods, such as method 1100. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: depositing a first substrate; forming a first set of contacts positioned in the first substrate; forming pillars in contact with the first substrate, a first chalcogenide assembly, and a second chalcogenide assembly; dividing the pillars into a first pillar contacting the first chalcogenide assembly and a second pillar contacting the second chalcogenide assembly; depositing a second substrate over the first and second pillars; and forming a second set of contacts positioned in the second substrate, wherein the first pillar is coupled to a first contact in the first set of contacts and the second pillar is coupled to a second contact in the second set of contacts.

[0133] Some aspects of the method 1100 and apparatus described herein may further include operations, features, components, or instructions for depositing an insulating material between a first pillar and a second pillar, the insulating material contacting a first substrate and a second substrate, wherein the deposition of the second substrate may be based on the deposition of the insulating material.

[0134] It should be noted that the above methods describe feasible implementation schemes, and the operations and procedures can be rearranged or modified in other ways, and other implementation schemes are feasible. Furthermore, parts from two or more methods can be combined.

[0135] Describe a device. The device may include a word line board, a set of memory element pairs, each pair of the set of memory element pairs including a first memory element contacting a first wall of the word line board and a second memory element contacting a second wall of the word line board. The device may further include a set of post pairs configured as digital lines to interact with the word line board, each pair of the set of post pairs including a first post contacting the first memory element and a second post contacting the second memory element. The device may further include a dielectric material extending between and in contact with each post of the set of post pairs.

[0136] Some examples of the device may include a set of contacts associated with a set of digital lines and extending through a substrate, wherein each first post of a set of post pairs may contact one of the contacts in the set. In some cases, each second post of a set of post pairs may contact one of the contacts in the set. Some examples of the device may include a second set of contacts associated with a second set of digital lines and extending through a second substrate, wherein each second post of a set of post pairs may contact one of the contacts in the second set. In some cases, the set of contacts may be arranged in a grid.

[0137] Some examples of the device may include conformal material that contacts the word line plate and extends between a first memory element in a first memory element pair and a first memory element in a second memory element pair. In some cases, the memory elements in the set of memory element pairs may be positioned in recesses formed by the word line plate and the posts in the post pairs.

[0138] Some examples of the device may include a dielectric layer positioned above the word line board and in contact with the set of memory element pairs and the set of pillar pairs, wherein the set of pillar pairs extends through the dielectric layer. Some examples of the device may include: a second word line board positioned above the dielectric layer, wherein the set of pillar pairs extends through the second word line board; and a second set of memory element pairs, wherein each pair in the second set of memory element pairs includes a third memory element and a fourth memory element.

[0139] In some cases, the device may include a substrate positioned beneath the word line board, wherein the set of pillar pairs and the dielectric material contact the substrate. In some examples, the word line board comprises a conductive material. Some examples may further include memory elements in the set of memory element pairs comprising a chalcogenide material.

[0140] Describe a device. The device may include: a substrate; a set of contacts extending through the substrate and configured to couple digital lines and circuitry; a word line board positioned above the substrate; and a set of pairs of memory elements. Each pair of the set of memory element pairs may include a first memory element contacting a first wall of the word line board and a second memory element opposite the first memory element contacting a second wall of the word line board. The device may further include a set of pillar pairs coupled to the set of contacts and configured as digital lines, each pair of pillar pairs including a first pillar contacting the first memory element and the first contact of the set of contacts, and a second pillar contacting the second memory element and the second contact of the set of contacts. The device may further include a dielectric material contacting each pair of pillar pairs and extending between each pair of pillar pairs, the dielectric material being in contact with the substrate.

[0141] Some examples of the device may include conformal material that contacts the word line board and extends between the first memory element in the first memory element pair and the first memory element in the second memory element pair.

[0142] A device is described. The device may include: a first substrate and a second substrate; a first set of contacts positioned in the first substrate and a second set of contacts positioned in the second substrate; and a word line board positioned between the first substrate and the second substrate. The device may further include a set of pairs of memory elements positioned between the first substrate and the second substrate, each pair of the set of memory element pairs including a first memory element contacting a first wall of the word line board and a second memory element contacting a second wall of the word line board. The device may further include a set of pillar pairs positioned between the first substrate and the second substrate and configured as digital lines. Each pair of pillar pairs may include a first pillar contacting the first memory element and a first contact of the first set of contacts positioned in the first substrate, and a second pillar contacting the second memory element and a second contact of the second set of contacts positioned in the second substrate.

[0143] Some examples of the device may include a dielectric material extending between each of the set of pillar pairs, the dielectric material being in contact with the first substrate, the second substrate, and each of the pillar pairs.

[0144] The information and signals described herein can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips mentioned above can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, wherein the bus can have various bit widths.

[0145] As used herein, the term "virtual ground" refers to a node in a circuit that maintains a voltage of approximately zero volts (0 V) but is not directly coupled to ground. Therefore, the voltage of a virtual ground may fluctuate temporarily and recover to approximately 0 V in a steady state. Virtual grounding can be implemented using various electronic circuit elements, such as voltage dividers consisting of operational amplifiers and resistors. Other implementation methods are also possible. "Virtual ground" or "virtual ground connection" implies a connection to approximately 0 V.

[0146] The terms “electronic communication,” “conductive contact,” “connection,” and “coupling” refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) with each other if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) may be open or closed based on the operation of the device containing the connecting component. The conductive path between connecting components may be a direct conductive path between components or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some cases, the signal flow between connecting components may be interrupted for a period of time, for example, by using one or more intermediate components (e.g., switches or transistors).

[0147] The term "coupling" refers to a change from an open-circuit relationship between components where signals cannot currently be transmitted through conductive paths to a closed-circuit relationship where signals can be transmitted through conductive paths between components. When one component (e.g., a controller) couples other components together, the component triggers a change that allows signals to flow between the other components through conductive paths that were previously not permitted.

[0148] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it uses the previously permitted conductive path to influence changes that prevent signal flow between the components.

[0149] As used herein, the term "layer" refers to a hierarchical or sheet-like geometric structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer may contain different elements, components, and / or materials. In some cases, a layer may consist of two or more sublayers. In some figures, two dimensions of a three-dimensional layer are depicted for illustrative purposes.

[0150] As used in this article, the term “substantially” means that the modifying characteristic (e.g., a verb or adjective modified by the term “substantially”) does not need to be absolute, but is close enough to achieving the advantage of the characteristic.

[0151] As used herein, the term "electrode" can refer to an electrical conductor and, in some cases, can be used as an electrical contact to a memory cell or other component of a memory array. An electrode may comprise a trace, wire, conductor, conductive layer, or the like that providing a conductive path between elements or components of the memory array.

[0152] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or any other doping method.

[0153] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices having a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are signals), then the FET may refer to an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may refer to a p-type FET. The channel may be covered by an insulating gate oxide cap. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. The transistor can be “turned on” or “activated” when a voltage greater than or equal to the transistor’s threshold voltage is applied to the transistor’s gate. The transistor can be “turned off” or “deactivated” when a voltage less than the transistor’s threshold voltage is applied to the transistor’s gate.

[0154] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" rather than "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0155] In the accompanying drawings, similar components or features may have the same element symbol. Furthermore, various components of the same type can be distinguished by following the element symbol with a dash and a second symbol to differentiate similar components. If only the first element symbol is used in the specification, then regardless of the second element symbol, the description applies to any similar components having the same first element symbol.

[0156] The various illustrative blocks and modules described herein can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0157] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or program code. Other examples and embodiments are within the scope of the disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, with their inclusion distributed such that portions of the functions are implemented at different physical locations. Furthermore, as used herein (and contained in the claims), the word "or" used in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on..." should not be construed as relating to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on..." should be interpreted in the same way as the phrase "at least partially based on...".

[0158] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure will be made, and that the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Multiple letter plates; Insulating material located between the plurality of word line boards; Multiple storage element pairs, which include at least: The first storage element pair of the plurality of storage element pairs, located at a first level associated with a first word line board of the plurality of word line boards, comprises a first storage element and a second storage element; and The second storage element pair of the plurality of storage element pairs, located at a second level associated with the second word line board of the plurality of word line boards, includes a third storage element and a fourth storage element; and Multiple column pairs, which include at least: A first pillar pair includes a first pillar coupled to the first storage element at the first level and the third storage element at the second level, and a second pillar coupled to the second storage element at the first level and the fourth storage element at the second level; and A dielectric material is located between the first pillar and the second pillar.

2. The device of claim 1, wherein the dielectric material extends orthogonally to the first layer and the second layer.

3. The device according to claim 2, wherein the dielectric material has an oval cross-section in a direction perpendicular to the plurality of pillar pairs.

4. The device of claim 2, wherein the dielectric material has a dog-bone shaped cross-section in a direction perpendicular to the plurality of pillar pairs.

5. The device of claim 2, wherein the dielectric material spans the length of the trench of the memory array associated with the plurality of memory element pairs.

6. The device of claim 1, wherein the first pair of posts partially surrounds the dielectric material, and wherein the dielectric material equally divides the conductive material of the first pair of posts.

7. The device of claim 1, wherein the plurality of column pairs are configured as digital lines to interact with the plurality of word line boards.

8. The device according to claim 1, further comprising: Multiple contacts, associated with multiple digital lines and extending through a first insulating substrate, wherein each first post of the multiple post pairs is coupled to one of the multiple contacts.

9. The device of claim 8, wherein each second post of the plurality of post pairs is coupled to one of the plurality of contacts.

10. The device according to claim 8, further comprising: The second plurality of contacts are associated with and extend through the second plurality of digital lines, wherein each of the plurality of pillar pairs has a second pillar in contact with one of the second plurality of contacts.

11. The device according to claim 1, further comprising: A conformal material that contacts the first word line plate and the second word line plate and extends between the first storage element and the third storage element.

12. The device according to claim 1, wherein: The storage elements in the plurality of storage element pairs are placed in the recess formed by the first word line plate and the pillars in the first pillar pair.

13. An apparatus comprising: Alternating layers of lettering board and insulating material; A first storage element pair, located at a first level of the alternating layer, the first level being associated with a first word board, the first storage element pair comprising a first storage element and a second storage element; A second pair of memory elements is located at a second level of the alternating layer, the second level being associated with a second word board, the second pair of memory elements comprising a third memory element and a fourth memory element; The first pillar pair includes a first pillar coupled to the first storage element at the first level and the third storage element at the second level, and a second pillar coupled to the second storage element at the first level and the fourth storage element at the second level. and A dielectric material is located between the first pillar and the second pillar.

14. The device of claim 13, wherein the first pair of posts partially surrounds the dielectric material, and wherein the dielectric material equally divides the conductive material of the first pair of posts.

15. The device of claim 13, wherein the first column pair is configured as digital lines to interact with the word line board.

16. The device according to claim 13, further comprising: An insulating substrate is located beneath the alternating layers; and Multiple contacts extending through the insulating substrate, wherein a first post is coupled to one of the multiple contacts and a second post is coupled to a different one of the multiple contacts.

17. An apparatus comprising: The first character line plate is located at the first level; The second character line plate is located at the second level; An insulating material is placed between the first layer and the second layer, between the first letter plate and the second letter plate; A first storage element pair, located at the first level, the first storage element pair includes a first storage element and a second storage element; The second storage element pair, located at the second level, includes a third storage element and a fourth storage element; and The first column pair includes: The first pillar is coupled to the first storage element at the first level and the third storage element at the second level. The second pillar is coupled to the second storage element in the first level and the fourth storage element in the second level, and A dielectric material is located between the first pillar and the second pillar.

18. The device of claim 17, wherein the first post and the second post partially surround the dielectric material, and wherein the dielectric material equally divides the first post and the second post.

19. The device of claim 17, wherein the first post and the second post are configured as digital lines to interact with the first word line board and the second word line board.

20. The apparatus of claim 17, further comprising: Insulating substrate; A first contact point extends through the insulating substrate and is coupled to the first pillar; and The second contact extends through the insulating substrate and is coupled to the second post.

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