Semiconductor manufacturing apparatus and parameter adjusting method thereof
By integrating measurement and control devices into semiconductor manufacturing equipment, alignment and stacking recipe parameters can be corrected in real time, solving the problem of parameter inapplicability caused by process changes, improving stacking accuracy, and ensuring semiconductor process yield and capacity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2026-03-13
AI Technical Summary
In semiconductor manufacturing, process changes can render alignment and stacking parameters inapplicable, affecting semiconductor yield and throughput.
By integrating measurement and control devices into semiconductor manufacturing equipment, the alignment marks on the wafer are measured in real time and the alignment and stacking formula parameters are automatically corrected, ensuring real-time adjustment of process parameters.
This improves the stacking accuracy and avoids a decrease in semiconductor process yield and production capacity.
Smart Images
Figure CN121666027A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device, and more particularly to a semiconductor manufacturing apparatus and a method for adjusting its parameters. Background Technology
[0002] In semiconductor manufacturing, alignment marks can be formed on the wafer to check the alignment between the front and back layers. However, changes in the process may render optimized alignment and overlay formulation parameters unsuitable, thereby affecting semiconductor yield and throughput. Summary of the Invention
[0003] This invention relates to a semiconductor manufacturing apparatus and its parameter adjustment method, which can automatically and in real time correct alignment and overlay parameters to improve overlay accuracy and avoid a decrease in semiconductor process yield and production capacity.
[0004] According to an embodiment of the present invention, a semiconductor manufacturing apparatus includes a process apparatus, a measurement apparatus, and a control apparatus. Before the process apparatus performs a patterning process, the measurement apparatus measures alignment marks on a wafer to generate position data and quality data for the alignment marks. The control apparatus is coupled to the process apparatus and the measurement apparatus, and the control apparatus corrects the alignment recipe parameters used by the process apparatus during the patterning process and wafer bonding, as well as the overlay recipe parameters used by the measurement apparatus when measuring the relative positions of the alignment marks on the wafer, based on the position data and the quality data.
[0005] This invention also provides a method for adjusting parameters of a semiconductor manufacturing apparatus. The semiconductor manufacturing apparatus includes a process apparatus and a measuring apparatus. The method for adjusting parameters of the semiconductor manufacturing apparatus includes the following steps: Before the process apparatus performs a patterning process, the alignment marks on the wafer are measured to generate position data and quality data of the alignment marks. Based on the position data and quality data, the alignment recipe parameters used by the process apparatus when performing the patterning process and wafer bonding, and the overlay recipe parameters used by the measuring apparatus when measuring the relative positions of the alignment marks on the wafer are corrected.
[0006] Based on the above, embodiments of the present invention can measure the alignment marks on the wafer before performing the patterning process to generate position data and quality data of the alignment marks. The alignment recipe parameters used during the patterning process and wafer bonding, as well as the overlay recipe parameters used when measuring the relative position of the alignment marks on the wafer, are corrected based on the position data and quality data. The alignment recipe parameters and overlay recipe parameters are automatically and in real time modified to adapt to changes in the process, thereby improving the overlay accuracy and avoiding a decrease in the yield and capacity of the semiconductor process. Attached Figure Description
[0007] Figure 1This is a schematic diagram of a semiconductor manufacturing apparatus according to an embodiment of the present invention;
[0008] Figure 2 as well as Figure 3 This is a flowchart illustrating a parameter adjustment method for a semiconductor manufacturing apparatus according to an embodiment of the present invention. Detailed Implementation
[0009] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.
[0010] Reference Figure 1 The semiconductor manufacturing apparatus may include a control device 102, an engineering data analysis system 104, a manufacturing execution system 106, an advanced process control system 108, a lithography integrated automation system 110, a measurement device 112, and a process apparatus 114. The control device 102 is coupled to the engineering data analysis system 104, the manufacturing execution system 106, the advanced process control system 108, the lithography integrated automation system 110, the measurement device 112, and the process apparatus 114.
[0011] The control device 102 may be, for example, a host computer, but is not limited thereto. The control device 102 includes a central processing unit (CPU) 116, a read-only memory (ROM) 118, a random access memory (RAM) 120, a display unit 122, and an input unit 124. The CPU 116, ROM 118, RAM 120, display unit 122, and input unit 124 may be connected via a bus.
[0012] The central processing unit 116 can execute a patterning support program to support patterning on the wafer, such as supporting the position correction of multiple patterns. The patterning support program is a computer-executable computer program having a computer-readable recording medium, which may include multiple instructions for calculating position correction parameters required for pattern position correction. The instructions of the patterning support program enable the computer to perform position correction parameter calculation processing. The patterning support program can be stored in read-only memory 118 and loaded into random access memory 120 via a bus.
[0013] The input unit 124 may include, for example, a mouse and / or a keyboard, to receive instruction information input from the user and transmit the instruction information to the central processing unit 116.
[0014] The central processing unit 116 can read the pattern forming support program from the read-only memory 118 according to the instructions input by the user from the input unit 124, and expand the pattern forming support program in the program storage area of the random access memory 120 to perform various types of processing. The central processing unit 116 temporarily stores various data generated in various types of processing in the data storage area formed in the random access memory 120.
[0015] The display unit 122 may be a display device such as a liquid crystal display, and displays the status of the semiconductor manufacturing apparatus, measurement data, etc., based on instructions from the central processing unit 116.
[0016] The engineering data analysis system 104, manufacturing execution system 106, advanced process control system 108, and lithography integrated automation system 110 can be executed by and controlled by the control device 102. The engineering data analysis system 104 analyzes process data to identify the causes of process parameter variations or output losses. The manufacturing execution system 106 manages the manufacturing process and operations of the semiconductor manufacturing equipment. The advanced process control system 108 performs fault detection and classification (FDC) and run-to-run (R2R) control. The lithography integrated automation system 110 performs automated control of the lithography process. This computer-integrated manufacturing system, comprising the engineering data analysis system 104, manufacturing execution system 106, advanced process control system 108, and lithography integrated automation system 110, integrates and manages activities within the semiconductor process.
[0017] Process apparatus 114 may include, for example, a patterning tool, such as an exposure machine, and a wafer bonder, but is not limited thereto. Measurement apparatus 112 may include, for example, a stand-alone pre-aligner and an overlay metrology equipment, but is not limited thereto. Measurement apparatus 112 may measure the alignment marks on the wafer before the patterning process is performed in process apparatus 114 to generate position data and quality data of the alignment marks. The position data may include, for example, the absolute position of the alignment marks (e.g., coordinate position), and the quality data may include, for example, the contrast of the image obtained by the measurement apparatus 112 measuring the reflected light generated by the incident light beam reflected from the alignment marks, but is not limited thereto. For example, the quality data may also include the normalized image log slope, correlation coefficient, etc., but is not limited thereto.
[0018] like Figure 2 As shown, the measuring device 112 can measure the alignment marks of the wafer before step S202 to generate position data and quality data of the alignment marks. In step S204, the control device 102 can automatically perform calculations to correct the formulation parameters, such as correcting the alignment formulation parameters and the overlay formulation parameters based on the position data and quality data of the alignment marks. The alignment formulation parameters are the alignment formulation parameters used by the process device 114 when performing the patterning process and wafer bonding, and the overlay formulation parameters are the overlay formulation parameters used by the measuring device 112 when measuring the relative position of the alignment marks of the wafer. Then, the corrected alignment formulation parameters and overlay formulation parameters are fed forward in real time to the patterning and wafer bonding steps S206 and the overlay error measurement step S208, so that the patterning process and wafer bonding are performed using the corrected alignment formulation parameters, and the overlay error measurement is performed using the corrected overlay formulation parameters. After step S208, it can be determined whether the alignment error is less than the default value. If the alignment error is less than the default value, the adjustment of the alignment formula parameters and the alignment formula parameters can be stopped. If the alignment error is not less than the default value, the alignment formula parameters and the alignment formula parameters can be corrected again in step S204.
[0019] Furthermore, the method by which the control device 102 calibrates and aligns the formula parameters and the method of overlapping the formula parameters can be as follows: Figure 3As shown. First, the position data and quality data generated by the measuring device 112 measuring the alignment mark are received (step S302), for example, position data and quality data provided by a stand-alone pre-aligner are received. Then, the position data is subtracted from the reference position data (for example, subtracting the absolute position coordinates from the default position coordinates, but not limited thereto) to produce a first subtraction result, and the quality data is subtracted from the reference quality data (for example, subtracting the contrast of the alignment mark image from the default contrast, but not limited thereto) to produce a second subtraction result (step S304), wherein the reference position data and reference quality data may be, for example, reference position data and reference quality data of the current batch (lot) or previous batch in an engineering data analysis system.
[0020] The control device 102 determines whether the first subtraction result is less than a first threshold and whether the second subtraction result is less than a second threshold (step S306). When the first subtraction result is less than the first threshold and the second subtraction result is less than the second threshold, the calculation of the formula parameters can be terminated. When the first subtraction result is not less than the first threshold or the second subtraction result is not less than the second threshold, the control device 102 can correct and align the formula parameters and overlay the formula parameters based on the first subtraction result and the second subtraction result. For example, the k-means clustering algorithm can be used to cluster the first and second subtraction results to generate multiple clusters (step S308). Then, optimized alignment formula parameters or overlay formula parameters can be quickly derived for each cluster to generate predicted alignment formula parameters and predicted overlay formula parameters (step S310). For example, the alignment formula parameters (e.g., pattern position compensation value or alignment correction model) can be corrected by subtracting the absolute position coordinates from the default position coordinates, and the overlay formula parameters (e.g., wavelength of the measurement beam) can be corrected by subtracting the contrast of the alignment mark image from the default contrast. However, this is not a limitation. In some embodiments, position data, quality data, reference position data, and reference quality data can also be input into a machine learning model to determine the type of alignment mark, optimized wavelength or color, measurement focus, and measurement position, etc., and modify the alignment formula parameters and overlay formula parameters accordingly to generate predicted alignment formula parameters and predicted overlay formula parameters.
[0021] The control device 102 can register the predicted alignment recipe parameters and the predicted stacking recipe parameters to the lithography integration automation system 110 (step S312), and control the lithography integration automation system 110 and the manufacturing execution system 106 to replace the alignment recipe parameters used by the process apparatus 114 and the stacking recipe parameters used by the measurement device 112 with the predicted alignment recipe parameters and the predicted stacking recipe parameters in real time (step S314), so that the process apparatus 114 and the measurement device 112 can use the predicted alignment recipe parameters and the predicted stacking recipe parameters to perform patterning processes, wafer bonding and stacking error measurement more accurately, thereby improving stacking accuracy and avoiding a decrease in semiconductor process yield and capacity.
[0022] Furthermore, the control device 102 can also modify the cache contents and model of the process apparatus 114 in the advanced process control system 108 for each group based on the first subtraction result (step S316), for example, modifying the pattern position compensation value stored in the advanced process control system 108, but not limited thereto. In addition, the control device 102 can also control the manufacturing execution system 106 to provide automatic chip dicing instructions and batch customization instructions before the coating step (step S318).
[0023] In summary, embodiments of the present invention can measure the alignment marks on the wafer before performing the patterning process to generate position data and quality data of the alignment marks. Based on the position data and quality data, the alignment recipe parameters used during the patterning process and wafer bonding, as well as the overlay recipe parameters used when measuring the relative position of the alignment marks on the wafer, are corrected. The alignment recipe parameters and overlay recipe parameters are automatically and in real time modified to adapt to changes in the process, thereby improving the overlay accuracy and avoiding a decrease in semiconductor process yield and throughput.
[0024] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A semiconductor manufacturing apparatus, characterized in that, include: Process equipment; The measuring device measures the alignment marks on the wafer before the patterning process is performed by the process apparatus, thereby generating position data and quality data of the alignment marks. as well as A control device, coupled to the process apparatus and the measuring device, corrects the alignment recipe parameters used by the process apparatus when performing the patterning process and wafer bonding, and the overlay recipe parameters used by the measuring device when measuring the relative positions of the alignment marks on the wafer, based on the position data and the quality data.
2. The semiconductor manufacturing apparatus according to claim 1, characterized in that, The control device also subtracts the position data from the reference position data to generate a first subtraction result, subtracts the mass data from the reference mass data to generate a second subtraction result, and reflects whether the first subtraction result is less than a first threshold or the second subtraction result is less than a second threshold. Based on the first subtraction result and the second subtraction result, the alignment formula parameters and the stacking formula parameters are calculated.
3. The semiconductor manufacturing apparatus according to claim 2, characterized in that, It also includes a manufacturing execution system and a lithography integration automation system coupled to the control device. The control device uses a clustering algorithm to group the first subtraction result and the second subtraction result into multiple groups, optimizes the alignment recipe parameters or overlay recipe parameters corresponding to each group, generates predicted alignment recipe parameters and predicted overlay recipe parameters, and controls the lithography integration automation system and the manufacturing execution system to replace the alignment recipe parameters used by the process apparatus and the overlay recipe parameters used by the measurement device with the predicted alignment recipe parameters and the predicted overlay recipe parameters.
4. The semiconductor manufacturing apparatus according to claim 2, characterized in that, It also includes an advanced process control system coupled to the control device, wherein the control device modifies the cache contents and model of the process device in the advanced process control system based on the first subtraction result.
5. The semiconductor manufacturing apparatus according to claim 4, characterized in that, The control device also modifies the pattern position compensation value stored in the advanced process control system.
6. The semiconductor manufacturing apparatus according to claim 1, characterized in that, It also includes a manufacturing execution system coupled to the control device, wherein the control device further controls the manufacturing execution system to provide automatic chip dicing instructions and batch customization instructions.
7. A method for adjusting parameters of a semiconductor manufacturing apparatus, characterized in that, The semiconductor manufacturing apparatus includes a process unit and a measuring unit, and the parameter adjustment method of the semiconductor manufacturing apparatus includes: Before the patterning process is performed in the aforementioned process apparatus, alignment marks on the wafer are measured to generate position data and quality data for the alignment marks; and The alignment formula parameters used by the process apparatus to perform the patterning process and wafer bonding, and the stacking formula parameters used by the measuring device to measure the relative position of the alignment marks on the wafer, are corrected based on the position data and the quality data.
8. The parameter adjustment method for a semiconductor manufacturing apparatus according to claim 7, characterized in that, include: The location data is subtracted from the reference location data to produce a first subtraction result, and the mass data is subtracted from the reference mass data to produce a second subtraction result; as well as If the first subtraction result is not less than a first threshold or the second subtraction result is not less than a second threshold, the alignment formulation parameters and the stacking formulation parameters are calculated based on the first subtraction result and the second subtraction result.
9. The parameter adjustment method for a semiconductor manufacturing apparatus according to claim 8, characterized in that, The semiconductor manufacturing apparatus further includes a photolithography integration automation system and a manufacturing execution system, and the parameter adjustment method of the semiconductor manufacturing apparatus includes: The first subtraction result and the second subtraction result are divided into multiple groups using a clustering algorithm; Optimize the alignment formulation parameters or stacking formulation parameters corresponding to each group to generate predicted alignment formulation parameters and predicted stacking formulation parameters; and The lithography integration automation system and the manufacturing execution system are controlled to replace the alignment recipe parameters used by the process apparatus and the overlay recipe parameters used by the measurement device with the predicted alignment recipe parameters and the predicted overlay recipe parameters.
10. The parameter adjustment method for a semiconductor manufacturing apparatus according to claim 8, characterized in that, The semiconductor manufacturing apparatus further includes an advanced process control system, and the parameter adjustment method of the semiconductor manufacturing apparatus includes: Based on the first subtraction result, modify the cache contents and model used for the process unit in the advanced process control system.
11. The parameter adjustment method for a semiconductor manufacturing apparatus according to claim 7, characterized in that, The semiconductor manufacturing apparatus further includes an advanced process control system, and the parameter adjustment method of the semiconductor manufacturing apparatus includes: Modify the pattern position compensation value stored in the advanced process control system.
12. The parameter adjustment method for a semiconductor manufacturing apparatus according to claim 7, characterized in that, The semiconductor manufacturing apparatus further includes a manufacturing execution system, and the parameter adjustment method of the semiconductor manufacturing apparatus includes: The manufacturing execution system is controlled to provide automatic chip segmentation instructions and batch customization instructions.