Preparation method of porous array interconnection line

Abstract

The invention provides a preparation method of a porous array interconnection line, which comprises the following steps of: firstly, pre-determining a quantitative relationship among a side wall inclination angle, a dielectric layer thickness and a through hole pitch through a geometrical relationship in a structural design stage, and providing a guarantee for forming a stable trapezoidal or triangular support structure; secondly, in the process, an ideal inclined side wall of about 60 degrees or smaller is formed in the through hole array by adopting ashing based on oxygen plasma and a low-selection-ratio etching technology and accurately controlling plasma parameters. According to the method, the coverage uniformity and compactness of the metal conducting layer in the through hole are finally and remarkably improved, so that the over-etching resistance and the electromigration reliability of the interconnection structure are synchronously enhanced, the product yield is improved, the service life of an MEMS device is greatly prolonged, and the maintenance cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and specifically relates to a method for preparing a porous array interconnect. Background Technology

[0002] In semiconductor manufacturing, vias play a crucial role in connecting different metal layers. Traditional logic chips commonly use tungsten as the via filling material due to its excellent high aspect ratio filling capability, forming a standard "Metal / Ti / W / Ti / Metal" stacked structure. However, in MEMS devices that require both electrical and mechanical properties, the high brittleness and low ductility of tungsten metal make it difficult to meet the demands of mechanical stress environments, easily leading to structural fracture. Therefore, AlCu alloys, with their good ductility, have become an ideal choice for MEMS devices, driving the widespread application of multi-hole array via structures.

[0003] However, using aluminum-copper alloys in porous array structures still faces significant challenges: 1) AlCu is typically deposited using physical vapor deposition, resulting in poor step coverage and a tendency for a "shadowing effect" in vias with high aspect ratios, leading to thinner deposition at the bottom and sidewalls of the vias and creating structural weaknesses. 2) The already very thin metal layer at the bottom of the vias can cause multiple microvias to open simultaneously during subsequent over-etching, leading to electrical connection failures. 3) The inherent electromigration phenomenon of aluminum-copper is exacerbated in arrays with uneven current distribution, potentially triggering cascading failures and severely impacting product lifespan.

[0004] In summary, the aforementioned defects severely limit the electrical and mechanical performance of MEMS devices. Therefore, how to address this issue has become a pressing technical challenge in this field.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating porous array interconnects, which solves the problems of insufficient mechanical strength, easy breakage and short service life of the interconnect structure caused by uneven step coverage, poor resistance to over-etching and low electromigration reliability of existing porous arrays.

[0007] To achieve the above objectives, the present invention provides a method for fabricating a porous array interconnect, comprising the following steps:

[0008] S1, a substrate is provided, and a dielectric layer is formed on the surface of the substrate;

[0009] S2, using photoresist as a mask, a first plasma etching is performed on the dielectric layer using a mixed gas containing a first F gas, O2, and Ar to form a porous array consisting of multiple through-holes penetrating the dielectric layer; wherein, by controlling the proportion of O2, the lateral ashing rate of the photoresist is adjusted, thereby controlling the sidewall tilt angle θ of the through-holes within a target range; wherein, the thickness H of the dielectric layer, the shortest horizontal distance A between adjacent through-hole sidewalls, the over-etching coefficient OE, and the geometric factor k related to the sidewall tilt angle θ satisfy H(1+OE)≤k×A;

[0010] S3, Remove the photoresist;

[0011] S4, a metal conductive layer is formed in the porous array.

[0012] Optionally, the geometric factor k and the sidewall inclination angle θ satisfy the relationship k=(1 / 2)×tanθ, and the sidewall inclination angle θ≤60°.

[0013] Optionally, after step S3 and before step S4, the via is further subjected to physical etching using a process gas mainly composed of Ar to flatten the protrusions of the dielectric layer between adjacent vias, forming a flat platform.

[0014] Optionally, the flow rate of O2 accounts for more than 20% of the total flow rate of O2 and the first F-containing gas.

[0015] Optionally, in the first plasma etching process, the etching selectivity ratio of the dielectric layer to the photoresist is maintained between 2:1 and 3:1.

[0016] Optionally, in step S2, the parameters of the first plasma etching process include: a power range of 600~1200W, a pressure range of 20~200mTorr, an O2 flow rate range of 20~80sccm, a first F-containing gas flow rate range of 20~100sccm, and an Ar flow rate range of 100~300sccm.

[0017] Optionally, the first F-containing gas includes one or a combination of CH3F, CF4, and C4F8; the material of the dielectric layer includes one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.

[0018] Optionally, the photoresist is removed by an oxygen ashing process.

[0019] Optionally, before performing step S2, a pre-processing step of the dielectric layer is included. If the thickness of the deposited dielectric layer is greater than the maximum value allowed by the relation H(1+OE)≤k×A, then the dielectric layer is globally etched until the relation is satisfied.

[0020] Optionally, the dielectric layer pretreatment includes: performing a second plasma etching on the dielectric layer using a second F-containing gas and an Ar-containing mixed gas under conditions without a photoresist mask; the second F-containing gas includes one or a combination of CH3F, CF4, or C4F8.

[0021] As described above, this invention provides a method for fabricating a via array interconnect. First, in the structural design stage, by establishing strict geometric relationships, the quantitative matching of via tilt angle, dielectric layer thickness, and via spacing is predetermined, providing a theoretical guarantee for forming a stable trapezoidal or triangular support structure. Second, in terms of process, a low selectivity etching technique based on oxygen plasma is employed. This technique utilizes the ashing and etching effects of oxygen plasma to simultaneously remove the photoresist and the underlying dielectric layer at similar rates. By precisely controlling the plasma parameters, ideal tilted sidewalls of approximately 60° or less are formed inside the via array. This method ultimately significantly improves the uniformity and density of the metal conductive layer coverage within the vias, thereby simultaneously enhancing the over-etching resistance and electromigration reliability of the interconnect structure. While improving product yield, it also significantly extends the lifespan of MEMS devices and reduces maintenance costs. Attached Figure Description

[0022] Figure 1 The diagram shows a flowchart illustrating the fabrication process of the porous array interconnect of the present invention.

[0023] Figure 2 The diagram shown is a schematic representation of the structure after providing a substrate in an embodiment of the present invention.

[0024] Figures 3a-3b The diagram shows the structure after O2 lateral etching and mixed gas longitudinal etching in an embodiment of the present invention.

[0025] Figures 4a-4b The diagram shown is a structural schematic of the through hole after the inclined sidewall is formed in an embodiment of the present invention.

[0026] Figure 5 The diagram shown is a schematic representation of the structure after removing the photoresist according to an embodiment of the present invention.

[0027] Figure 6 The diagram shown is a structural schematic of an embodiment of the present invention after a metal conductive layer has been provided.

[0028] Explanation of reference numerals in the attached figures

[0029] 100 substrate 110 Bottom metal layer 120 Dielectric layer 130 Photoresist 140 Metal conductive layer Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0032] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0033] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0034] Example

[0035] This embodiment provides a method for fabricating a porous array interconnect. Figure 1 The flowcharts for each step are illustrated. (See attached diagram.) Figures 2-6 The fabrication methods of porous array interconnects are introduced.

[0036] First, refer to Figure 1 and Figure 2 Step S1 is performed, providing a substrate 100, on the surface of which a dielectric layer 120 is formed.

[0037] Specifically, this application emphasizes that the material selection of the dielectric layer 120 is crucial for achieving the subsequent geometric model (H(1+OE)≤k×A) and ultimately obtaining a precisely tilted sidewall. To achieve the core process of controlling the lateral ashing rate by adjusting the O2 ratio, the material of the dielectric layer 120 must be able to work synergistically with the photoresist 130 in the specific plasma environment to obtain the target via.

[0038] As an example, the material of the dielectric layer 120 includes one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.

[0039] Specifically, the value of this application lies in the fact that the material of the dielectric layer 120, through its interaction with the subsequent mixed gas, can stably maintain the etching selectivity ratio of the dielectric layer 120 and the photoresist 130 within an optimized range. This ensures that the dielectric layer 120 is efficiently etched through in the vertical direction, and that the photoresist 130 mask can be laterally retreated at a controllable rate in the horizontal direction. Together, these factors translate the theoretical tilt angle θ in the design model into a physical guarantee of uniform, smooth, tilted sidewalls in the subsequent product. The material of the dielectric layer 120 can be used alone or in combination as needed, and its flexibility allows those skilled in the art to precisely adapt the low selectivity etching process window while meeting insulation and mechanical performance requirements.

[0040] Next, refer to Figure 1 , Figures 3a-5 Step S2 is executed, using photoresist 130 as a mask, and employing a mixed gas containing a first F-containing gas, O2, and Ar to perform a first plasma etching on the dielectric layer 120 to form a porous array composed of multiple through-holes penetrating the dielectric layer; wherein, by controlling the proportion of O2 to regulate the lateral ashing rate of the photoresist 130, the sidewall tilt angle θ of the through-hole is controlled within a target range; wherein, the thickness H of the dielectric layer 120, the shortest horizontal distance A between adjacent through-hole sidewalls, the over-etching coefficient OE, and the geometric factor k related to the sidewall tilt angle θ satisfy H(1+OE)≤k×A.

[0041] Specifically, in some embodiments, the number of through holes is greater than 2*2 (4), and of course, it can also be two adjacent through holes. Step S2 is the key to realizing the through hole structure with inclined sidewalls, and its core lies in using the ashing effect of O2 to achieve active control of the etching morphology. The first F-containing gas is used as the main etching agent, which dissociates in the plasma to generate active species such as F* free radicals, and reacts chemically with the dielectric layer 120 to generate volatile products, thereby achieving longitudinal etching. Wherein, see Figure 3a and Figure 3bIn the plasma, O2 generates oxygen free radicals, which continuously and isotropically ash the photoresist 130, causing the mask opening size to gradually increase over time during etching. Furthermore, O2 competes with the first F-containing gas, affecting the etching rate, and participates in the formation of weak protective polymers on the sidewalls, aiding in morphology control. Ar, as an inert dilution gas and physical bombardment source, primarily maintains plasma stability, promotes the desorption of reaction products, and assists in anisotropic etching.

[0042] Furthermore, the formation of the inclined sidewalls of the via is a dynamic morphological change process. At the start of etching, the mask opening is small. Vertically, the dielectric layer 120 is rapidly etched. Horizontally, the lateral ashing effect of O2 on the photoresist 130 causes the mask sidewalls to continuously recede, and the opening to continuously expand. Therefore, the later-exposed areas of the dielectric layer 120 are etched in a shorter time than the earlier-exposed areas. Thus, the gradient distribution of etching time from top to bottom naturally transforms into the tilt angle of the sidewalls from top to bottom. In this embodiment, refer to... Figure 4a The dielectric layer 120 between adjacent vias has a trapezoidal morphology. In another embodiment, see [reference needed]. Figure 4b The dielectric layer 120 between adjacent vias has a triangular shape, wherein the photoresist 130 on the surface of the protrusion of the dielectric layer 120 is completely removed during the etching process (the sidewall tilt angle θ is 60 degrees).

[0043] For further details, please refer to [link / reference]. Figure 6 In the thickness specification of the dielectric layer 120, OE, as the over-etching factor, is a coefficient greater than 0, used to address situations of uneven etching rates or film thickness fluctuations. The range of OE is 20% to 100%, for example, 20%, 40%, 60%, 80%, and 100%. A represents the shortest horizontal distance between the inclined sidewalls of adjacent vias within the via array defined in the chip layout design. This is a critical dimension defined in the chip layout to ensure electrical isolation. This relationship enables coordinated control of the morphology and reliability of the inclined sidewalls. It not only ensures sufficient material to form the desired morphology of the inclined sidewalls through lateral ashing, but also ensures that even if process fluctuations occur during the formation of the inclined sidewall morphology, it prevents adjacent vias from penetrating through to the bottom, thereby fundamentally guaranteeing the electrical reliability of the interconnects.

[0044] As an example, the geometric factor k and the sidewall inclination angle θ satisfy the relationship k=(1 / 2)×tanθ.

[0045] Specifically, the relationship relates the sidewall tilt angle θ, controlled by adjusting the O2 ratio in this step, to the geometric constraint H(1+OE)≤k×A; this geometric constraint serves as a critical condition to ensure that the dielectric layer 120 between adjacent vias is not broken down during the over-etching stage. Therefore, by actively controlling the sidewall tilt angle θ to meet the critical condition, a clear process window is set for adjusting the O2 ratio in this step, thereby simultaneously achieving precise control of the etching morphology and ensuring the integrity of the interconnect structure.

[0046] As an example, the sidewall inclination angle θ ≤ 60°.

[0047] Specifically, the sidewall tilt angle θ design provides ideal metal coverage conditions for the physical vapor deposition process, significantly reducing the "shadowing effect" and ensuring integration density while providing ample process windows for subsequent etching processes. This facilitates the smooth removal of etching byproducts and ensures etching uniformity.

[0048] Furthermore, by setting a wider sidewall angle (i.e., θ ≤ 60°), this embodiment can retain a wider platform structure between adjacent vias in the dielectric layer 120. This enhanced platform structure brings dual benefits: firstly, it significantly improves the structural strength and integrity of the porous array, reducing the risk of mechanical damage in subsequent processes; secondly, the wider platform provides a flatter deposition surface for subsequent metal filling processes, helping to improve the step coverage capability of the metal conductive layer 140, reducing open-circuit defects in interconnects caused by excessively thin or broken metal, thereby further improving the yield and reliability of the device.

[0049] As an example, the flow rate of O2 accounts for more than 20% of the total flow rate of O2 and the first F-containing gas.

[0050] Specifically, the flow control of the O2 ratio can affect the lateral ashing rate of the photoresist 130. The higher the O2 ratio, the faster the ashing rate, the more significant the lateral mask retreat, and the smaller the final sidewall tilt angle. Conversely, the tilt angle is larger and steeper, thus enabling the process to have efficient control over the tilt angle.

[0051] As an example, the first F-containing gas includes one or a combination of CH3F, CF4, and C4F8.

[0052] Specifically, CF4 offers high etching rates and anisotropy, making it suitable for deep etching of via structures. C4F8 decomposes in plasma to generate numerous CF2 groups, facilitating the formation of protective polymers on the sidewalls and enhancing morphology control. CH3F has a moderate etching selectivity, beneficial for controlling critical dimensions and sidewall tilt angles. Ultimately, the optimal gas or combination is selected based on the required dielectric layer thickness (120mm) and via aspect ratio. Simultaneously, O2 flow rate control balances etching rate and morphology control requirements, while Ar gas proportions optimize plasma stability and etching uniformity.

[0053] As an example, in the first plasma etching process, the etching selectivity ratio of the dielectric layer 120 to the photoresist 130 is maintained between 2:1 and 3:1.

[0054] Specifically, by precisely controlling the composition of the mixed gas and the plasma process parameters, the etching selectivity ratio of the dielectric layer 120 to the photoresist 130 is maintained between 2:1 and 3:1, for example, any etching selectivity ratio among 2:1, 2.2:1, 2.5:1, 2.8:1, and 3:1. This means that the removal rate of the dielectric layer 120 is 2 to 3 times the consumption rate of the photoresist 130. This range ensures that while the dielectric layer 120 is completely etched through, a sufficient thickness of the photoresist 130 is retained to continuously and effectively perform lateral ashing and opening expansion, thereby stably forming tilted vias with controllable sidewall morphology and avoiding etching stoppage or bottom damage caused by premature depletion of the photoresist 130. In this embodiment, by adjusting the parameters, the etching rate of the dielectric layer 120 is maintained at 4000 A / min and the etching rate of the photoresist is maintained at 2000 A / min, so as to achieve a selectivity ratio of 2:1. Then, under the current thickness of the dielectric layer 120 and a certain OE, the etching time is set to complete the final etching.

[0055] As an example, in step S2, the parameters of the first plasma etching process include: a power range of 600~1200W, a pressure range of 20~200mTorr, an O2 flow rate range of 20~80sccm, a flow rate range of the first F-containing gas of 20~100sccm, and an Ar flow rate range of 100~300sccm.

[0056] Specifically, to achieve through-holes with tilted sidewalls, the first plasma etching parameters in step S2 are used to control plasma characteristics through a combination of high power and a wide intracavity pressure range, achieving a balance between longitudinal etching and lateral ashing. Simultaneously, morphology control is achieved by adjusting the gas ratio, where the ratio of O2 to the first F-containing gas flow rate directly dominates the lateral retraction of the mask and the sidewall tilt angle, while high-flow Ar plays a role in stabilizing the plasma, suppressing polymer buildup, and clarifying the contours. These parameters collectively define a broad process window, allowing technicians to flexibly adjust the sidewall morphology by regulating the O2 flow rate and pressure, thereby ensuring that the target structure is obtained under efficient and repeatable conditions.

[0057] As an example, before performing step S2, a pre-processing step is included for the dielectric layer 120. If the thickness of the deposited dielectric layer 120 is greater than the maximum value allowed by the relation H(1+OE)≤k×A, then the dielectric layer 120 is globally etched until the relation is satisfied.

[0058] Specifically, during the deposition of the dielectric layer, the thickness of the dielectric layer is effectively monitored and processed. The preprocessing steps include the following: First, thickness measurement is performed using online metrology tools such as an elliptic transducer or optical interferometer to measure the thickness of the dielectric layer 120 on the surface of the substrate 100 over the entire area to obtain an accurate initial thickness. Next, the measured initial thickness is compared with the maximum thickness threshold allowed by the relational expression. If the initial thickness > the maximum thickness, the dielectric layer 120 is determined to be too thick, and a global etching correction is required. Then, a maskless, global etching process is performed on the overly thick dielectric layer 120 to uniformly reduce its thickness. This process requires real-time or stepwise thickness monitoring until the final thickness of the dielectric layer stably meets the critical specification requirements.

[0059] In one specific embodiment, the dielectric layer 120 is preprocessed to ensure it meets the geometric constraint model. The initial thickness of the dielectric layer 120 is measured to be 600 nm using an elliptic apparatus. Based on the design objectives: sidewall tilt angle θ = 60°, shortest horizontal distance A between via sidewalls = 800 nm, and over-etching factor OE = 50%, the geometric factor k = (1 / 2) × tanθ ≈ 0.866 is calculated. According to the relationship H(1+OE) ≤ k × A, the allowable final thickness of the dielectric layer 120 must satisfy H ≤ (0.866 × 800 nm) / (1 + 0.5) ≈ 462 nm. Since the initial thickness of 600 nm is greater than 462 nm, the dielectric layer 120 is determined to be too thick and requires global etching correction. Subsequently, maskless global etching is used to uniformly thin the dielectric layer 120 to 450 nm. The technical effect of this operation is that setting the final thickness to 450nm (slightly less than the critical value of 462nm) ensures that the dielectric material can be fully utilized in subsequent etching, making the sidewall tilt angle θ accurately approach the target value of 60°, while also providing a small safety margin. This fundamentally eliminates the risk of bottom penetration caused by over-etching, ensuring the robustness of the process and the reliability of the device.

[0060] As an example, the pretreatment of the dielectric layer 120 includes: performing a second plasma etching on the dielectric layer 120 using a second mixed gas containing F gas and Ar under conditions without a photoresist mask 130; the second F gas includes one or a combination of CH3F, CF4 or C4F8.

[0061] Specifically, as a concrete example of process implementation, the pretreatment step of the dielectric layer 120 is achieved through global etching. The second plasma etching uses the second F-containing gas, supplemented by Ar as a carrier gas and plasma stabilizer. This etching is an isotropic global etching, which aims to achieve uniform and controllable thinning of the dielectric layer 120. By real-time thickness monitoring or timed etching, the amount of dielectric layer 120 removed is precisely controlled until its thickness meets the specifications, ensuring the uniformity of the entire substrate 100 and preventing the introduction of additional topographic irregularities.

[0062] Furthermore, in one embodiment, the second F-containing gas is a combination of CH3F, CF4, or C4F8, with a flow rate ranging from 10 to 80 sccm. The Ar flow rate ranges from 10 to 100 sccm. The etching pressure ranges from 10 to 200 mTorr, and the power ranges from 600 to 1800 W. This allows for full-surface etching of the dielectric layer 120 at an etching rate of 2000 to 4000 A / min, thereby obtaining a dielectric layer 120 with a thickness conforming to specifications. Of course, the specific process parameters are set based on the actual selection and thickness design of the dielectric layer 120, as well as the via spacing design; no specific limitations are imposed here.

[0063] Next, refer to Figure 1 and Figure 5 Then, perform step S3 to remove the photoresist 130.

[0064] As an example, the removal of the photoresist 130 is achieved through an oxygen ashing process.

[0065] Specifically, after the etching is completed, the dielectric layer 120 between adjacent vias exhibits a trapezoidal or triangular shape. When the dielectric layer 120 has a trapezoidal structure, photoresist 130 remains on its surface. When the dielectric layer 120 has a triangular structure, although the photoresist 130 between the vias has been removed, there may still be residues of photoresist 130 at non-via locations or other peripheral locations. Therefore, placing the structure in an oxygen plasma environment allows the photoresist 130 to be completely decomposed and volatilized by reactive oxygen free radicals, thereby obtaining a clean surface of the dielectric layer 120 structure for subsequent processes. In this embodiment, the O2 flow rate is in the range of 50~100 sccm, and no bias power is applied. Under these conditions, because the physical bombardment of high-energy ions is avoided, etching occurs uniformly in all directions, thereby achieving uniform and non-selective removal of the photoresist 130 from both the front and side surfaces. Of course, using pure oxygen ashing is only one implementation method. In actual production, wet etching or other dry etching processes can also be used to remove the photoresist 130.

[0066] Through the above steps, through-holes with a gentle slope morphology (sidewall inclination angle θ≤60°) are formed inside the porous array. The key technology lies in the use of a low selectivity etching process with the photoresist 130 as a mask. This process dynamically expands the mask opening by laterally ashing the photoresist 130 while etching the dielectric layer 120, thereby naturally forming the inclined sidewalls.

[0067] The key to this invention lies in achieving precise feedforward design through the quantitative relationship H(1+OE)≤(A / 2)×tanθ. For example, with a target tilt angle of θ=60 degrees, when the over-etching coefficient OE=20% and the aperture spacing A=100nm, the maximum allowable thickness H of the dielectric layer 120 can be directly calculated to be ≤72nm. This provides a rigid constraint on the process and design, requiring the selection of a thinner dielectric film or the design of a larger aperture spacing, thereby ensuring the realization of the target morphology from the source and eliminating the risk of through-hole penetration.

[0068] Under this design, the morphology brings two core advantages: First, it can ensure that the dielectric layer 120 structure is naturally formed between adjacent vias, which can greatly buffer the covering stress generated during subsequent metal conductive film deposition, effectively improving the filling quality and connection reliability of the metal layer; Second, in the internal region of the array, thanks to the uniform plasma loading environment and the symmetric morphology co-evolution, it is possible to stably and repeatedly obtain via morphology with a sidewall tilt angle θ that is highly consistent with the design target.

[0069] It should be noted that for the outermost vias of the porous array, due to the lack of a symmetrical etching environment and morphological synergy on their outer sides, the sidewall tilt angle may deviate from the typical value (approximately 60°) of the interior. This phenomenon is a known effect in the art, inherent to the asymmetry of physical boundary conditions. Its existence precisely demonstrates the controllability and superiority of the process of the present invention within the array body, and does not affect the core advantage of the present invention in achieving a stable and uniform via morphology within the array.

[0070] As an example, after step S3 and before step S4, the via is further subjected to physical etching using a process gas mainly composed of Ar to flatten the protrusions of the dielectric layer 120 between adjacent vias, forming a flat platform.

[0071] Specifically, after forming the vias, a subsequent morphology control step is included, which involves physical etching of the via structure using a process gas primarily composed of inert gas Ar. This aims to selectively flatten the protrusions of the dielectric layer 120 formed between adjacent vias due to the initial etching by utilizing the directional bombardment effect of Ar ions under a bias electric field, thereby forming a flat-topped platform structure in the porous array. This planarization process provides a more uniform and abrupt surface morphology for the subsequent deposition of the metal conductive layer 140, effectively preventing premature breakdown or migration of metal at protrusions due to electric field concentration, reducing the risk of short circuits, and further improving the long-term electrical reliability of the interconnect.

[0072] Next, refer to Figure 1 and Figure 6 Step S4 is executed to form a metal conductive layer 140 in the porous array.

[0073] Specifically, in one embodiment, a bottom metal layer 110 is further disposed above the substrate 100 and between the dielectric layer 120. This step first involves plasma cleaning to enhance the adhesion of subsequent deposits. Then, a continuous metal film is formed on the inner surface of the porous structure using physical vapor deposition (PVD) or atomic layer deposition (ALD) techniques. The formed conductive metal layer 140 forms an electrical contact with the bottom metal layer, thereby transforming the porous array into a functional three-dimensional conductive network. Of course, the bottom structure of the porous array is not limited to this, and will not be described in detail here.

[0074] As an example, the material of the metal conductive layer 140 includes one or a combination of Ti, Ta, Au, Cu, and Al.

[0075] Specifically, Ti / Ta can be used as an adhesion or diffusion barrier layer to form a stacked structure with Cu or Al as the main conductive layer; or Au or Al can be used directly as a single material to form a conductive channel.

[0076] In summary, this invention provides a method for fabricating multi-hole array interconnects. First, during the structural design stage, by establishing strict geometric relationships, the sidewall tilt angle, the dielectric layer thickness, and the via spacing are pre-determined to provide a theoretical guarantee for forming a stable trapezoidal or triangular support structure. Second, in terms of process, oxygen plasma-based ashing and low selectivity etching techniques are employed. By precisely controlling plasma parameters, ideal tilted sidewalls of approximately 60° or less are formed within the via array. This method ultimately significantly improves the uniformity and density of the metal conductive layer coverage within the vias, thereby simultaneously enhancing the over-etching resistance and electromigration reliability of the interconnect structure. While improving product yield, it also significantly extends the lifespan of MEMS devices and reduces maintenance costs. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a porous array interconnect, characterized in that... Includes the following steps: S1, a substrate is provided, and a dielectric layer is formed on the surface of the substrate; S2, using photoresist as a mask, a first plasma etching is performed on the dielectric layer using a mixed gas containing a first F gas, O2, and Ar to form a porous array consisting of multiple through-holes penetrating the dielectric layer; wherein, by controlling the proportion of O2, the lateral ashing rate of the photoresist is adjusted, thereby controlling the sidewall tilt angle θ of the through-hole within a target range; wherein, the thickness H of the dielectric layer, the shortest horizontal distance A between adjacent sidewalls of the through-hole, the over-etching coefficient OE, and the geometric factor k related to the sidewall tilt angle θ satisfy H(1+OE)≤k×A; S3, Remove the photoresist; S4, a metal conductive layer is formed in the porous array.

2. The method for fabricating a porous array interconnect according to claim 1, characterized in that: The geometric factor k and the sidewall inclination angle θ satisfy the relationship k=(1 / 2)×tanθ, and the sidewall inclination angle θ≤60°.

3. The method for fabricating a porous array interconnect according to claim 1, characterized in that: After step S3 and before step S4, the process further includes using an Ar-based process gas to physically etch the vias to flatten the protrusions of the dielectric layer between adjacent vias, forming a flat platform.

4. The method for fabricating a porous array interconnect according to claim 1, characterized in that: The flow rate of O2 accounts for more than 20% of the total flow rate of O2 and the first F-containing gas.

5. The method for fabricating a porous array interconnect according to claim 1 or 4, characterized in that: In the first plasma etching process, the etching selectivity ratio of the dielectric layer to the photoresist is maintained between 2:1 and 3:

1.

6. The method for fabricating a porous array interconnect according to claim 1, characterized in that: In step S2, the parameters of the first plasma etching process include: a power range of 600~1200W, a pressure range of 20~200mTorr, an O2 flow rate range of 20~80sccm, a flow rate range of the first F-containing gas of 20~100sccm, and an Ar flow rate range of 100~300sccm.

7. The method for fabricating a porous array interconnect according to claim 1, characterized in that: The first F-containing gas includes one or a combination of CH3F, CF4, and C4F8; the material of the dielectric layer includes one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.

8. The method for fabricating a porous array interconnect according to claim 1, characterized in that: The photoresist is removed using an oxygen ashing process.

9. The method for fabricating a porous array interconnect according to claim 1, characterized in that: Before performing step S2, a pre-processing step is also included. When the thickness of the deposited dielectric layer is greater than the maximum value allowed by the relation H(1+OE)≤k×A, the dielectric layer is globally etched until the relation is satisfied.

10. The method for fabricating a porous array interconnect according to claim 9, characterized in that: The dielectric layer pretreatment includes: performing a second plasma etching on the dielectric layer using a mixed gas containing a second F gas and Ar under conditions without a photoresist mask; the second F gas includes one or a combination of CH3F, CF4, or C4F8.

Images